An IGBT structure with an internal insulation structure and its manufacturing process

Abstract

The present invention provides an IGBT structure with an internal insulation structure and its manufacturing process, including a collector, a p-type buffer layer is disposed above the collector, an n-type buffer layer is disposed above the p-type buffer layer, an n+-type drift layer is disposed above the n-type buffer layer, a p-type block is disposed inside the n+-type drift layer, an etching trench is disposed at the top of the n+-type drift layer, an amphoteric doping region is disposed inside the etching trench, and a first doping region is disposed below the inside of the amphoteric doping region. By providing an amphoteric doping region in the n+-type drift layer, the number of parasitic triodes is reduced. At the same time, with the provided first doping region and second doping region, while reducing the number of parasitic triodes, the base region resistance of the parasitic triodes is further reduced to further suppress the parasitic triode effect, achieving the effect of avoiding leakage current inside the IGBT and preventing damage to the IGBT.

Description

Technical Field

[0001] The present invention relates to the technical field of IGBTs, and particularly relates to an IGBT structure with an internal insulation structure. Background Art

[0002] At present, the new power electronic devices in our country mainly include VDMOS and IGBT devices. IGBT has the functions of MOS input and bipolar output, and combines the advantages of large current density, high breakdown voltage, small drive power of power MOSFET, fast switching speed, high input impedance, and good thermal stability. Since its appearance, it has quickly developed into the mainstream power switching device in the medium and high power power electronics field. Due to the existence of parasitic triodes in IGBTs, when the IGBT is turned on, the parasitic triodes have a certain probability of conduction. After the parasitic triodes are turned on, the leakage current of the IGBT will be greatly increased, thereby damaging the IGBT. Summary of the Invention

[0003] An embodiment of the present invention provides an IGBT structure with an internal insulation structure. By setting amphoteric doping regions in the n+-type drift layer, the number of parasitic triodes is reduced. At the same time, the first doping region and the second doping region are set, which not only reduce the number of parasitic triodes but also reduce the base resistance of the parasitic triodes to further suppress the parasitic triode effect, achieving the effect of avoiding internal leakage current in the IGBT and avoiding damage to the IGBT.

[0004] In view of the above problems, the technical solution proposed by the present invention is:

[0005] An IGBT structure with an internal insulation structure, including a collector, a p-type buffer layer is arranged above the collector, an n-type buffer layer is arranged above the p-type buffer layer, an n+-type drift layer is arranged above the n-type buffer layer, a p-type block is arranged inside the n+-type drift layer, an etching trench is arranged at the top of the n+-type drift layer, an amphoteric doping region is arranged inside the etching trench, a first doping region is arranged below the amphoteric doping region, a second doping region is arranged outside the upper part of the first doping region in the amphoteric doping region, an n-type block and a p-type block are sequentially arranged above the amphoteric doping region, an emitter is arranged on one side of the top of the amphoteric doping region, an oxide layer is arranged on the top of the n+-type drift and the other side of the top of the amphoteric doping region, and a gate is arranged on the top of the oxide layer.

[0006] As a preferred technical solution of the present invention, the amphoteric doping regions are arranged on both sides inside the n+-type drift.

[0007] As a preferred technical solution of the present invention, the first doping region is an n-type doping region, and the second doping region is a p-type doping region.

[0008] As a preferred technical solution of the present invention, it is characterized in that the first doped region is arranged around the second doped region.

[0009] The embodiment of the present invention also provides a process for an IGBT structure with an internal insulation structure, including the following steps:

[0010] S1, growing a p-type buffer layer on the surface of a semiconductor substrate by chemical vapor deposition; growing an n-type buffer layer on the surface of the p-type buffer layer by chemical vapor deposition; growing an n+-type drift layer on the surface of the n-type buffer layer by chemical vapor deposition;

[0011] S2, etching a first trench at the top of the n+-type drift layer through an ion etching process;

[0012] S3, growing an amphoteric doped region inside the first trench by chemical vapor deposition and then etching a second trench in the amphoteric doped region through an ion etching process, and growing a first doped region inside the second trench by chemical vapor deposition;

[0013] S4, etching a third trench on the outer side of the upper part of the first doped region in the amphoteric doped region through an ion etching process, and growing a second doped region inside the third trench by chemical vapor deposition;

[0014] S5, continuously growing an amphoteric doped region above the first doped region and the second doped region by chemical vapor deposition to make the surface of the amphoteric doped region flush with the surface of the n+-type drift layer, etching a fourth trench on the surface of the amphoteric doped region through an ion etching process, growing a p-type block inside the fourth trench by chemical vapor deposition, growing an n-type block on the surface of the p-type block by chemical vapor deposition, etching on one side of the surface of the n-type block through an ion etching process to obtain a fourth trench, and growing an amphoteric doped region inside the fourth trench by chemical vapor deposition until it is flush with the surface of the n-type buffer layer;

[0015] S6, adopting a chemical mechanical polishing process to remove the semiconductor substrate and annealing in a nitrogen atmosphere at a temperature of 1100°C for 12 minutes;

[0016] S7, removing the semiconductor substrate and setting a metal material layer on the back to form a collector; respectively setting a metal layer and an oxide layer on the top of the completed part of the structure and setting a metal layer on the oxide layer to form an emitter and a gate respectively.

[0017] Compared with the prior art, the beneficial effects of the present invention are as follows: By arranging an amphoteric doped region in the n+-type drift layer, the number of parasitic triodes is reduced. At the same time, the first doped region and the second doped region are arranged, which not only reduce the number of parasitic triodes but also reduce the base region resistance of the parasitic triodes to further suppress the parasitic triode effect, achieving the effect of avoiding leakage current inside the IGBT and preventing damage to the IGBT.

[0018] The above description is only an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention, it can be implemented according to the content of the specification. And in order to make the above and other objects, features and advantages of the present invention more obvious and understandable, the specific embodiments of the present invention are specifically exemplified below. Brief Description of the Drawings

[0019] Figure 1 It is a schematic structural diagram of step S1 disclosed in an embodiment of the present invention;

[0020] Figure 2 It is a schematic structural diagram of step S2 disclosed in an embodiment of the present invention;

[0021] Figure 3 It is a schematic structural diagram of steps S3 - S6 disclosed in an embodiment of the present invention;

[0022] Figure 4 It is a schematic structural diagram of step S7 disclosed in an embodiment of the present invention;

[0023] Figure 5 It is a schematic flow diagram of the IGBT structure process of the internal insulation structure disclosed in an embodiment of the present invention.

[0024] Reference Signs:

[0025] 1. Collector; 2. Semiconductor substrate; 3. p-type buffer layer; 4. n-type buffer layer; 5. Amphoteric doping region; 6. First doping region; 7. Second doping region; 8. p-type block; 9. n-type block; 10. Emitter; 11. Gate; 12. Oxide layer; 13. n+-type drift layer; 14. First trench; 15. Second trench; 16. Third trench; 17. Fourth trench; 18. Fifth trench. Detailed Embodiments

[0026] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0027] Refer to the attached Figures 1-4As shown in the figure, an IGBT structure with an internal insulation structure includes a collector 1. Above the collector 1, a p-type buffer layer 3 is provided. Above the p-type buffer layer 3, an n-type buffer layer 4 is provided. Above the n-type buffer layer 4, an n+-type drift layer 13 is provided. Inside the n+-type drift layer 13, a p-type block 8 is provided. At the top of the n+-type drift layer 13, an etching trench is provided. Inside the etching trench, an amphoteric doping region 5 is provided. The amphoteric doping region 5 uses N-type and P-type impurities to play a semi-insulating role in the n+-type drift layer 13. The amphoteric doping region 5 is provided on both inner sides of the n+-type drift. Below the inside of the amphoteric doping region 5, a first doping region 6 is provided. A second doping region 7 is provided outside the upper part of the first doping region 6 inside the amphoteric doping region 5. The first doping region 6 is an n-type doping region, and the second doping region 7 is a p-type doping region, and the first doping region 6 surrounds the second doping region 7. Above the inside of the amphoteric doping region 5, an n-type block 9 and a p-type block 8 are sequentially provided. On one side of the top of the amphoteric doping region 5, an emitter 10 is provided. On the top of the n+-type drift and on the other side of the top of the amphoteric doping region 5, an oxide layer 12 is provided. On the top of the oxide layer 12, a gate 11 is provided. By providing the amphoteric doping region 5 in the n+-type drift layer 13, a semi-insulating region is formed to reduce the number of parasitic triodes inside the IGBT. At the same time, the first doping region 6 and the second doping region 7 provided inside the n+-type drift layer 13 connect the semi-insulating region formed by the amphoteric doping region 5 to the n-type buffer layer 4 and the p-type buffer layer 3 respectively, reducing the number of parasitic triodes and further suppressing the parasitic triode effect by reducing the base region resistance of the parasitic triode. Through the above design, an internal insulation structure inside the IGBT is formed, achieving the effect of avoiding leakage current inside the IGBT and preventing damage to the IGBT. At the same time, when the IGBT has a breakdown voltage, it can also reduce the leakage current of the IGBT and prevent damage to the IGBT.

[0028] Refer to the attached Figures 1-5 As shown in the figure, a process for an IGBT structure with an internal insulation structure is characterized by including the following steps:

[0029] S1, grow a p-type buffer layer 3 on the surface of the semiconductor substrate 2 by chemical vapor deposition; grow an n-type buffer layer 4 on the surface of the p-type buffer layer 3 by chemical vapor deposition; grow an n+-type drift layer 13 on the surface of the n-type buffer layer 4 by chemical vapor deposition;

[0030] S2, etch a first trench 14 at the top of the n+-type drift layer 13 through an ion etching process;

[0031] S3. After growing the amphoteric doping region 5 inside the first trench 14 by chemical vapor deposition, an ion etching process is used to etch out the second trench 15 in the amphoteric doping region 5, and the first doping region 6 is grown inside the second trench 15 by chemical vapor deposition;

[0032] S4. An ion etching process is used to etch out the third trench 16 on the outer side of the upper part of the first doping region 6 in the amphoteric doping region 5, and the second doping region 7 is grown inside the third trench 16 by chemical vapor deposition;

[0033] S5. The amphoteric doping region 5 is continuously grown above the first doping region 6 and the second doping region 7 by chemical vapor deposition so that the surface of the amphoteric doping region 5 is flush with the surface of the n+-type drift layer 13. An ion etching process is used to etch out the fourth trench 17 on the surface of the amphoteric doping region 5, and the p-type block 8 is grown inside the fourth trench 17 by chemical vapor deposition. The n-type block 9 is grown on the surface of the p-type block 8 by chemical vapor deposition. An ion etching process is used to etch one side of the surface of the n-type block 9 to obtain the fourth trench 17, and the amphoteric doping region 5 is grown inside the fourth trench 17 by chemical vapor deposition until it is flush with the surface of the n-type buffer layer 4;

[0034] S6. A chemical mechanical polishing process is used to remove the semiconductor substrate 2 and anneal for 12 minutes in a nitrogen atmosphere at a temperature of 1100 °C;

[0035] S7. A metal material layer is provided on the back surface of the semiconductor substrate 2 to form the collector 1; a metal layer and an oxide layer 12 are respectively provided on the top of the completed part of the structure, and a metal layer is provided on the oxide layer 12 to form the emitter and the gate 11 respectively.

[0036] Specifically, the working principle is as follows: By providing the amphoteric doping region 5 in the n+-type drift layer 13, a semi-insulating region is formed to reduce the number of parasitic triodes inside the IGBT. At the same time, the first doping region 6 and the second doping region 7 provided inside the n+-type drift layer 13 connect the semi-insulating regions formed by the amphoteric doping region 5 to the n-type buffer layer 4 and the p-type buffer layer 3 respectively. While reducing the number of parasitic triodes, the base region resistance of the parasitic triodes is further reduced to further suppress the parasitic triode effect, achieving the effect of avoiding leakage current inside the IGBT and preventing damage to the IGBT.

[0037] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these changes and modifications.

Claims

1. An IGBT structure with an internal insulation structure, characterized in that It includes a collector, with a p-type buffer layer disposed above the collector, an n-type buffer layer disposed above the p-type buffer layer, an n+-type drift layer disposed above the n-type buffer layer, a p-type block disposed inside the n+-type drift layer, an etching trench disposed at the top of the n+-type drift layer, an amphoteric doping region disposed inside the etching trench. The amphoteric doping region uses N-type and P-type impurities and is used to play a semi-insulating role in the n+-type drift layer. A first doping region is disposed below the interior of the amphoteric doping region, and a second doping region is disposed outside the upper part of the first doping region inside the amphoteric doping region. An n-type block and a p-type block are sequentially disposed above the interior of the amphoteric doping region. An emitter is disposed on one side of the top of the amphoteric doping region. An oxide layer is disposed on the top of the n+-type drift and on the other side of the top of the amphoteric doping region, and a gate is disposed on the top of the oxide layer.

2. The IGBT structure with an internal insulation structure according to claim 1, characterized in that: The amphoteric doping region is disposed on both sides inside the n+-type drift.

3. An IGBT structure with an internal insulation structure according to claim 1, characterized in that: The first doping region is an n-type doping region, and the second doping region is a p-type doping region.

4. The IGBT structure with an internal insulation structure according to claim 3, characterized in that: The first doping region surrounds the second doping region.

5. A process for an IGBT structure with an internal insulation structure, applying an IGBT structure with an internal insulation structure as described in any one of claims 1-4, characterized in that: It includes the following steps: S1, growing a p-type buffer layer on the surface of a semiconductor substrate by chemical vapor deposition; growing an n-type buffer layer on the surface of the p-type buffer layer by chemical vapor deposition; growing an n+-type drift layer on the surface of the n-type buffer layer by chemical vapor deposition; S2, etching a first trench at the top of the n+-type drift layer by an ion etching process; S3, growing an amphoteric doping region inside the first trench by chemical vapor deposition and then etching a second trench in the amphoteric doping region by an ion etching process, and growing a first doping region inside the second trench by chemical vapor deposition; S4, etching a third trench outside the upper part of the first doping region inside the amphoteric doping region by an ion etching process, and growing a second doping region inside the third trench by chemical vapor deposition; S5, continuously growing an amphoteric doping region above the first doping region and the second doping region by chemical vapor deposition to make the surface of the amphoteric doping region flush with the surface of the n+-type drift layer, etching a fourth trench on the surface of the amphoteric doping region by an ion etching process, growing a p-type block inside the fourth trench by chemical vapor deposition, growing an n-type block on the surface of the p-type block by chemical vapor deposition, etching one side of the surface of the n-type block by an ion etching process to obtain a fourth trench, and growing an amphoteric doping region inside the fourth trench by chemical vapor deposition until it is flush with the surface of the n-type buffer layer; S6, using a chemical mechanical polishing process to remove the semiconductor substrate and annealing in a nitrogen atmosphere at a temperature of 1100 °C for 12 minutes; S7, removing the back surface of the semiconductor substrate and setting a metal material layer to form a collector; Setting a metal layer and an oxide layer on the top of the completed part of the structure respectively and setting a metal layer on the oxide layer to form an emitter and a gate respectively.

Images