Semiconductor structure and method for forming the same

Abstract

A semiconductor structure and a method for forming the same include: providing a substrate comprising a carrier substrate, an insulating buried layer, and a device substrate stacked in sequence; the insulating buried layer comprising a bottom insulating layer, a support portion protruding from the bottom insulating layer in the device region, and a sacrificial layer located on the bottom insulating layer and covering the sidewalls of the support portion, the sacrificial layer being located in the isolation region and also extending into a portion of the device region; removing at least the device substrate in the isolation region to form a trench, exposing the sacrificial layer; removing the sacrificial layer to form a cavity surrounded by the bottom insulating layer, the support portion, and the device substrate; and forming a liner oxide layer on the device substrate at the bottom surface of the device substrate exposed in the cavity and at the sidewalls of the trench. The cavity provides space for the liner oxide layer to form and expand below the device substrate, thereby preventing stress on the device substrate caused by the formation and expansion of the liner oxide layer on the bottom surface of the device substrate and reducing the risk of warping of the device substrate near the edge of the device region.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] SOI (silicon-on-insulator) typically refers to silicon on an insulating layer. It consists of three layers: silicon film, insulating layer, and silicon substrate. The top silicon film (referred to as silicon film) is used to make semiconductor devices such as CMOS. The middle insulating buried layer (usually silicon dioxide, also referred to as buried oxide layer or BOX layer) isolates the device from the silicon substrate.

[0003] Compared with bulk silicon devices, SOI devices have the advantages of smaller parasitic capacitance, lower leakage current and lower probability of soft errors, so they are increasingly used in the semiconductor field.

[0004] However, the performance of SOI devices still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby reducing the risk of warping of a device substrate near the edge of the device region and optimizing the performance of the semiconductor structure.

[0006] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, comprising: a substrate, comprising a plurality of discrete device regions and an isolation region located between the device regions; the substrate comprising: a carrying substrate; a bottom insulating layer located on the carrying substrate; a supporting portion protruding from the bottom insulating layer of the device region, the bottom insulating layer exposed by the supporting portion being located on the top surface of the isolation region and a portion of the device region; a device substrate, located above the bottom insulating layer of the device region and in contact with the supporting portion, the device substrate, the bottom insulating layer and the supporting portion forming a cavity; a liner oxide layer, located on the bottom surface of the device substrate exposed in the cavity and on the sidewalls of the device substrate; an isolation layer filling the cavity and between adjacent device substrates, and the isolation layer covering the liner oxide layer; a gate structure, located on the device substrate of the device region; and source / drain doping regions, located in the device substrate on both sides of the gate structure.

[0007] Accordingly, an embodiment of the present invention further provides a method for forming a semiconductor structure, comprising: providing a substrate, comprising a plurality of discrete device regions and an isolation region located between the device regions; the substrate comprising: a carrier substrate; an insulating buried layer located on the carrier substrate, the insulating buried layer comprising a bottom insulating layer, a support portion protruding from the bottom insulating layer of the device region, and a sacrificial layer located on the bottom insulating layer and covering the sidewall of the support portion, the sacrificial layer being located in the isolation region and also extending to a portion of the device region; a device substrate located on the insulating buried layer; removing at least the device substrate located in the isolation region to form a trench, the trench The sacrificial layer is exposed; after the groove is formed, the sacrificial layer is removed to form a cavity surrounded by the bottom insulating layer, the support portion and the device substrate, the cavity is connected to the groove, and the cavity exposes a portion of the bottom surface of the device substrate close to the edge of the device area; a pad oxide layer is formed on the bottom surface of the device substrate exposed in the cavity and on the device substrate on the sidewall of the groove; after the pad oxide layer is formed, an isolation layer is filled in the cavity and the trench; after the isolation layer is formed, a gate structure located on the device substrate and a source-drain doped region located in the device substrate on both sides of the gate structure are formed.

[0008] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0009] In the semiconductor structure provided by an embodiment of the present invention, the substrate includes: a carrier substrate; a bottom insulating layer located on the carrier substrate; a support portion protruding from the bottom insulating layer of the device area, the bottom insulating layer exposed by the support portion being located on the top surface of the isolation area and part of the device area; a device substrate located above the bottom insulating layer of the device area and in contact with the support portion, the device substrate, the bottom insulating layer and the support portion forming a cavity; by setting the cavity, the cavity can provide a formation space and an expansion space for the pad oxide layer below the device substrate, thereby preventing stress on the device substrate due to the formation and expansion of the pad oxide layer below the device substrate, and correspondingly reducing the risk of warping of the device substrate near the edge of the device area, thereby optimizing the performance of the semiconductor structure.

[0010] In the method for forming a semiconductor structure provided by an embodiment of the present invention, in the step of providing a substrate, the buried insulating layer includes a bottom insulating layer, a support portion protruding from the bottom insulating layer in the device region, and a sacrificial layer located on the bottom insulating layer and covering the sidewalls of the support portion, the sacrificial layer being located in the isolation region and also extending into a portion of the device region; the sacrificial layer is then removed through a trench to form a cavity surrounded by the bottom insulating layer, the support portion, and the device substrate, the cavity correspondingly exposing a portion of the bottom surface of the device substrate near the edge of the device region; accordingly, in the process of forming a pad oxide layer, the pad oxide layer can be formed on the bottom surface of the device substrate exposed by the cavity, and since the cavity is formed at the bottom of the device substrate, the cavity can provide a formation space and an expansion space for the pad oxide layer below the device substrate, thereby facilitating the prevention of stress on the device substrate due to the formation and expansion of the pad oxide layer at the bottom of the device substrate, and correspondingly facilitating the reduction of the risk of warping of the device substrate near the edge of the device region, thereby optimizing the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figures 1 to 5 It is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure;

[0012] Figure 6 and Figure 7 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0013] Figures 8 to 24 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0014] As can be seen from the background art, the performance of SOI devices currently needs to be improved. The reasons why the performance of SOI devices needs to be improved are analyzed in conjunction with a method for forming a semiconductor structure. Figures 1 to 5 The present invention is a schematic structural diagram corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1 , providing a substrate, including a carrier substrate 1, an insulating buried layer 2 located on the carrier substrate 1, and a device substrate 3 located on the insulating buried layer 2, wherein the substrate includes a plurality of discrete device regions i and isolation regions ii located between the device regions i.

[0016] refer to Figure 2 , etching the device substrate 3 of the isolation region ii to form a trench 4 in the device substrate 3 .

[0017] refer to Figure 3, a pad oxide layer 5 is formed on the bottom and sidewalls of the trench 4 .

[0018] refer to Figure 4 An isolation layer 6 filling the trench 4 is formed on the liner oxide layer 5 , and the liner oxide layer 5 and the isolation layer 6 located in the trench 4 are used to constitute an isolation structure.

[0019] refer to Figure 5 , forming a gate structure 7 located on the device substrate 3 and source / drain doped regions 8 located in the device substrate 3 on both sides of the gate structure 7 .

[0020] In the formation method, in the step of providing a substrate, the substrate is an SOI substrate, the device substrate 3 is used to form a semiconductor device, and after the trench 4 is formed, the remaining device substrate 3 is an active region substrate.

[0021] However, in the formation method, after the trench 4, the substrate oxide layer 5 and the isolation layer 6 are formed, the remaining device substrate 3 is easily subjected to the compressive stress of the isolation structure.

[0022] Specifically, in the process of forming the liner oxide layer 5, an oxygen-containing gas is usually introduced, and the oxygen-containing gas easily contacts the bottom edge of the device substrate 3, thereby causing the bottom edge of the device substrate 3 to be oxidized to form an oxide layer material during the formation of the liner oxide layer 5 and the subsequent heat treatment process. Compared with the density of the device substrate 3 material, the density of the oxide layer material is usually smaller, and the oxide layer located at the bottom edge of the device substrate 3 will expand. For example, Figure 4 As shown in the dotted circle position, a bird beak effect is generated at the bottom edge of the device substrate 3, causing the device substrate 3 to be subjected to compressive stress. The device substrate 3 is prone to warpage, which in turn easily reduces the performance of the device.

[0023] One method is to remove only a portion of the device substrate in the isolation region during trench formation, leaving a portion of the device substrate at the bottom of the trench. This prevents oxidation of the bottom edge of the device substrate in the device region during formation of the liner oxide layer and subsequent heat treatment. However, etching only a portion of the device substrate in the isolation region presents significant process control challenges.

[0024] Another method is to form a semiconductor spacer layer on the sidewalls of the trench after forming the trench and before forming the liner oxide layer. The semiconductor spacer layer can react with oxygen during the formation of the liner oxide layer and prevent oxygen from reacting with the device substrate at the edge of the device area, thereby reducing the probability of oxidation at the bottom edge of the device substrate in the device area. However, this approach forms the semiconductor spacer layer directly on the sidewalls of the trench, resulting in the liner oxide layer not being formed on the device substrate at the sidewalls of the trench. As a result, etching damage caused to the device substrate sidewalls during the etching process to form the trench is difficult to repair. In addition, since the semiconductor spacer layer is also formed in the trench, the isolation effect between adjacent devices is also reduced.

[0025] Another method is to increase the distance between the gate structure and the edge of the device region to reduce the impact of the device substrate warping at the edge of the device region on device performance. However, this will result in an increase in the device area occupied.

[0026] In order to solve the technical problem, in the semiconductor structure provided by an embodiment of the present invention, the substrate includes: a carrier substrate; a bottom insulating layer located on the carrier substrate; a support portion protruding from the bottom insulating layer of the device area, the bottom insulating layer exposed by the support portion is located on the top surface of the isolation area and part of the device area; a device substrate, located above the bottom insulating layer of the device area and in contact with the support portion, the device substrate, the bottom insulating layer and the support portion form a cavity; by setting the cavity, the cavity can provide a formation space and expansion space for the pad oxide layer below the device substrate, which is beneficial to prevent the device substrate from being subjected to stress due to the formation and expansion of the pad oxide layer below the device substrate, and correspondingly helps to reduce the risk of warping of the device substrate near the edge of the device area, thereby optimizing the performance of the semiconductor structure.

[0027] In order to make the above-mentioned objects, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figure 6 and Figure 7 , showing a structural schematic diagram of an embodiment of a semiconductor structure of the present invention. Figure 6 is a cross-sectional view, Figure 7 for Figure 6 A top view of the bottom insulating layer and the supporting portion corresponding to FIG.

[0028] like Figure 6 and Figure 7As shown, in this embodiment, the semiconductor structure includes: a substrate, including a plurality of discrete device regions I and an isolation region II located between the device regions I; the substrate includes: a carrier substrate 100; a bottom insulating layer 10 located on the carrier substrate 100; a support portion 20 protruding from the bottom insulating layer 10 of the device region I, wherein the bottom insulating layer 10 exposed by the support portion 20 is located on the top surface of the isolation region II and a portion of the device region I; a device substrate 120, located above the bottom insulating layer 10 of the device region I and in contact with the support portion 20, wherein the device substrate 120, the bottom insulating layer 10 and the support portion 20 enclose a cavity 200 (combined with reference to FIG. Figure 18 ); a pad oxide layer 150, located on the bottom surface of the device substrate 120 exposed by the cavity 200, and the sidewalls of the device substrate 120; an isolation layer 210, filling the cavity 200 and between adjacent device substrates 120, and the isolation layer 210 covering the pad oxide layer 150; a gate structure 230, located on the device substrate 120 of the device region I; and source-drain doped regions 250, located in the device substrate 120 on both sides of the gate structure 230.

[0029] The substrate is used to provide a platform for forming a semiconductor structure.

[0030] The device region I is used to form a semiconductor device. Specifically, the semiconductor device may include any one or both of an NMOS device and a PMOS device.

[0031] In this embodiment, the substrate is a semiconductor-on-insulator substrate.

[0032] The carrier substrate 100 is used to support the buried insulating layer 110 and the device substrate 120 .

[0033] As an example, the material of the carrier substrate 100 includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. In this embodiment, the material of the carrier substrate 100 is silicon.

[0034] The bottom insulating layer 10, the supporting portion 20, and the isolation layer 210 located in the cavity 200 constitute an insulating base. The insulating base is used to isolate the carrier substrate 100 and the device substrate 120, so that each semiconductor device located on the device substrate 120 is surrounded by an isolation material to be isolated from the surrounding devices, which is conducive to eliminating the latch effect; and since there is no PN junction formed by the source, drain region and substrate, the parasitic capacitance of the MOS transistor is reduced; at the same time, the insulating base also increases the thickness of the insulating layer between the interconnection line and the substrate (i.e., the carrier substrate), greatly reducing the parasitic capacitance of the interconnection line.

[0035] The bottom insulating layer 10 is used to protect the carrier substrate 100 during the formation of the semiconductor structure. In one embodiment, the bottom insulating layer 10 is made of silicon oxide. The bottom insulating layer 10 may also be made of other insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0036] During the formation of the semiconductor structure, the support portion 20 is used to support the device substrate 120. The support portion 20 is used to enclose a cavity 200 with the bottom insulating layer 10 and the device substrate 120.

[0037] As an embodiment, the material of the support portion 20 is the same as that of the bottom insulating layer 10, which is conducive to improving process compatibility. In other embodiments, the material of the support portion can also be other suitable insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0038] Along a direction parallel to the surface of the device substrate 120, a gap is formed between the sidewall of the support portion 20 and the edge of the device region I, so that the cavity 200 can extend to a portion of the device region I, so that the cavity 200 can expose a portion of the bottom surface of the device substrate 120 near the edge of the device region I. The edge of the device region I refers to the boundary between the device region I and the isolation region II.

[0039] Along a direction parallel to the substrate surface, the distance between the sidewalls of the support portion 20 and the sidewalls of the device substrate 120 should be neither too small nor too large. If the distance is too small, the bottom surface area of the device substrate 120 in the device region I exposed by the cavity 200 is too small, which can easily result in insufficient space for the material at the bottom of the device substrate 120 exposed by the cavity 200 to expand after oxidation, increasing the risk of warping and compressive stress in the device substrate 120. If the distance is too large, the support portion 20 cannot effectively support the entire bottom of the device substrate 120. To this end, in this embodiment, along a direction parallel to the substrate surface, the distance between the sidewalls of the support portion 20 and the sidewalls of the device substrate 120 is at least 500 nanometers.

[0040] As an example, the support portion 20 is a columnar structure, that is, the support portion 20 is a support column. In other embodiments, the support portion can also be a structure of other shapes, as long as the support portion can support the device substrate.

[0041] It should be noted that the width of the support portion 20 along a direction parallel to the surface of the device substrate 120 should not be too small or too large. If the width of the support portion 20 is too small, the support effect of the support portion 20 on the device substrate 120 will be reduced; if the width of the support portion 20 is too large, the space between the support portions 20 will be too small, which is not conducive to the filling of the liner oxide layer in the cavity 200. Therefore, in this embodiment, the width of the support portion 20 along a direction parallel to the surface of the device substrate 120 is 50 nanometers to 1000 nanometers.

[0042] Specifically, in this embodiment, the support portion 20 is a columnar structure, and the width of the support portion 20 refers to the diameter of the support portion 20 .

[0043] Combined with reference Figure 7 In this embodiment, the support parts 20 are arranged in a matrix on the bottom insulating layer 10. In other embodiments, the support parts can be arranged in other ways on the bottom insulating layer.

[0044] Specifically, based on the actual size of the support portion 20 and the area size of the device area I, the number of the support portion 20 in each device area I can be one or more, as long as the support portion 20 can provide sufficient support for the device substrate 120.

[0045] In this embodiment, in each device region I, there are a plurality of support portions 20, and the plurality of support portions 20 are spaced apart. Accordingly, the cavity 200 is also located in the region between adjacent support portions 20 in the device region I, that is, the cavity 200 is also located in the middle region of the device region I. This helps to improve the uniformity of the distribution of the cavity 200 at the bottom of the device substrate 120, thereby helping to improve the uniformity of the position distribution of the liner oxide layer 150 at the bottom of the device substrate 120, and further helps to reduce the probability of stress generated in the device substrate 120 due to oxidation of the bottom of the device substrate 120.

[0046] As an embodiment, in each of the device regions I, the number of the supporting portions 20 is four.

[0047] The cavity 200 exposes a portion of the bottom surface of the device substrate 120 near the edge of the device region I. The cavity 200 can provide a formation space and an expansion space for the pad oxide layer 150 below the device substrate 120, thereby preventing stress from being generated on the bottom of the device substrate 120 due to the formation and expansion of the pad oxide layer 150 at the bottom of the device substrate 120. This is correspondingly beneficial to reducing the risk of warping of the device substrate 120 near the edge of the device region I, thereby optimizing the performance of the semiconductor structure.

[0048] Among them, when forming an NMOS device, it is beneficial to prevent compressive stress from being generated on the device substrate 120 due to the formation and expansion of the oxide material at the bottom of the device substrate 120, that is, it is beneficial to reduce the probability of compressive stress being generated on the channel of the NMOS device, and thus it is beneficial to significantly improve the performance of the NMOS device.

[0049] The thickness of the liner oxide layer 150 is a target thickness. Compared to the target thickness, the height of the cavity 200, along a direction perpendicular to the substrate surface, should not be too small or too large. If the height of the cavity 200 is too small, the vertical space of the cavity 200 is too small, making it difficult to provide sufficient space for the liner oxide layer 150 to form and expand at the bottom of the device substrate 120 exposed in the cavity. Furthermore, during the formation of the semiconductor structure, the cavity 200 is formed by removing a sacrificial layer. A too small height of the cavity 200 can easily make the sacrificial layer removal more difficult and slow the removal efficiency, further making the formation of the cavity 200 more difficult. If the height of the cavity 200 is too large, the thickness of the formed device is likely to be too large, and it is also likely to cause unnecessary waste of material and space. To this end, in this embodiment, the height of the cavity 200, along a direction perpendicular to the substrate surface, is 5 to 10 times the target thickness.

[0050] The device substrate 120 is used to provide a process platform for forming a semiconductor device, and the device substrate 120 is also used as an active area (AA).

[0051] In this embodiment, the substrate is a silicon-on-insulator (SOI) substrate, and accordingly, the material of the device substrate 120 is silicon. The device substrate 120 may also be other types of semiconductor substrates, for example, the material of the device substrate 120 may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0052] The pad oxide layer 150 is used to repair etching damage on the surface of the device substrate 120 , including etching damage caused to the device substrate 120 during the process of forming the trench 130 .

[0053] In this embodiment, the pad oxide layer 150 is formed by oxidizing a portion of material exposed from the device substrate 120 .

[0054] Accordingly, in this embodiment, the material of the pad oxide layer 150 is the oxide of the material of the device substrate 120. In this embodiment, the material of the device substrate 120 is silicon, and the material of the pad oxide layer 150 is silicon oxide.

[0055] The isolation layer 210 is used to isolate adjacent device regions I. The isolation layer 210 also fills the cavity 200 so that the isolation layer 210 and the support portion 20 together support the device substrate 120, thereby improving the support strength of the device substrate 120.

[0056] The isolation layer 210 is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride. The isolation layer 210 may be made of the same material as the bottom insulating layer 10, or may be made of a different material than the bottom insulating layer 10.

[0057] As an embodiment, the material of the isolation layer 210 is the same as that of the bottom insulating layer 10 , and the material of the isolation layer 210 is silicon oxide.

[0058] In this embodiment, the isolation layer 210 is formed by filling between the cavity 200 and the adjacent device substrate 120 in the same step. Accordingly, the isolation layer 210 is an integrated structure.

[0059] The gate structure 230 is used to control the opening and closing of the conductive channel.

[0060] In this embodiment, the gate structure 230 is a polysilicon gate structure or an amorphous silicon gate structure, and the gate structure 230 includes a gate layer, and the material of the gate layer is polysilicon or amorphous silicon. In other embodiments, the gate structure can also be other types of gate structures, such as a metal gate structure.

[0061] The source / drain doping regions 250 are used as source or drain regions of a field-effect transistor. Specifically, when forming an NMOS transistor, the source / drain doping regions 150 are doped with N-type ions, such as P ions, As ions, or Sb ions. When forming a PMOS transistor, the source / drain doping regions 150 are doped with P-type ions, such as B ions, Ga ions, or In ions.

[0062] In this embodiment, the semiconductor structure further includes a gate dielectric layer 220 located between the device substrate 120 and the gate structure 230 , and on the isolation layer 210 .

[0063] The gate dielectric layer 220 is used to isolate the gate structure 230 from the device substrate 120 .

[0064] In this embodiment, the gate dielectric layer 220 is a gate oxide layer, and the material of the gate oxide layer is silicon oxide. In other embodiments, the material of the gate oxide layer can also be nitrogen-doped silicon oxide or other insulating materials. In other embodiments, the gate dielectric layer can also include a high-k gate dielectric layer, and the material of the high-k gate dielectric layer is a high-k gate dielectric material.

[0065] In this embodiment, the semiconductor structure further includes a gate spacer 240 located on the sidewall of the gate structure 230 .

[0066] The gate spacer 240 is used to protect the sidewalls of the gate structure 230 and is also used to define the formation area of the source and drain doped regions 250 .

[0067] The gate spacer 240 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, and boron carbonitride. The gate spacer 240 may have a single-layer structure or a stacked-layer structure. In this embodiment, the gate spacer 240 is a single-layer structure made of silicon nitride.

[0068] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 24 1 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0069] The method for forming the semiconductor structure of this embodiment will be described in detail below with reference to the accompanying drawings.

[0070] refer to Figures 8 to 16 , providing a substrate, including a plurality of discrete device areas I and an isolation area II located between the device areas I; the substrate includes: a carrier substrate 100; an insulating buried layer 110, located on the carrier substrate 100, the insulating buried layer 110 including a bottom insulating layer 10, a support portion 20 protruding from the bottom insulating layer 10 of the device area I, and a sacrificial layer 30 located on the bottom insulating layer 10 and covering the sidewall of the support portion 20, the sacrificial layer 30 being located in the isolation area II and also extending to a portion of the device area I; a device substrate 120, located on the insulating buried layer 110.

[0071] The substrate is used to provide a platform for subsequent process steps.

[0072] The device region I is used to form a semiconductor device. Specifically, the semiconductor device may include any one or both of an NMOS device and a PMOS device.

[0073] In this embodiment, the substrate is a semiconductor-on-insulator substrate, and the substrate includes a carrier substrate 100 , an insulating buried layer 110 located on the carrier substrate 100 , and a device substrate 120 located on the insulating buried layer 110 .

[0074] The carrier substrate 100 is used to support the buried insulating layer 110 and the device substrate 120 .

[0075] The material of the carrier substrate 100 includes one or more of single crystal silicon, germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium. In this embodiment, the material of the carrier substrate 100 is silicon.

[0076] The insulating buried layer 110 is used to isolate the carrier substrate 100 and the device substrate 120, so that after a semiconductor device is subsequently formed on the device substrate 120, each semiconductor device is surrounded by an insulating material to be isolated from surrounding devices, which is conducive to eliminating the latch-up effect; and since there is no PN junction formed by the source, drain region and substrate, the parasitic capacitance of the MOS transistor is reduced; at the same time, the insulating buried layer 110 also increases the thickness of the insulating layer between the interconnection line and the substrate (i.e., the carrier substrate 100), greatly reducing the parasitic capacitance of the interconnection line.

[0077] The material of the insulating buried layer 110 is an insulating material, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride. As an example, the material of the insulating buried layer 110 is silicon oxide.

[0078] The device substrate 120 is used to provide a process platform for forming a semiconductor device, and the device substrate 120 is also used to form an active region.

[0079] In this embodiment, the substrate is a silicon-on-insulator (SOI) substrate, and accordingly, the material of the device substrate 120 is silicon. The device substrate 120 may also be other types of semiconductor substrates, for example, the material of the device substrate 120 may also be one or more of germanium, silicon germanium, silicon carbide, gallium nitride, gallium arsenide, and indium gallium.

[0080] The steps of providing a substrate in this embodiment are described in detail below with reference to the accompanying drawings.

[0081] like Figure 8 As shown, a carrier substrate 100 is provided.

[0082] like Figures 8 to 13 As shown, the insulating buried layer 110 is formed on the top surface of the carrier substrate 100 .

[0083] In this embodiment, the buried insulating layer 110 includes a bottom insulating layer 10, a supporting portion 20 protruding from the bottom insulating layer 10 of the device region I, and a sacrificial layer 30 located on the bottom insulating layer 10 and covering the side wall of the supporting portion 20. The sacrificial layer 30 is located in the isolation region II and also extends to a portion of the device region I.

[0084] The bottom insulating layer 10 is used to protect the carrier substrate 100 in subsequent manufacturing processes. As an embodiment, the material of the bottom insulating layer 10 is silicon oxide.

[0085] The sacrificial layer 30 is used to occupy a space for the subsequent formation of a cavity, and the cavity is used to provide a formation space and an expansion space for forming a liner oxide layer at the bottom of the device substrate 120 exposed in the cavity.

[0086] The sacrificial layer 30 is located in the isolation region II, so that at least the device substrate 120 located in the isolation region II is subsequently removed. The formed trench can expose the sacrificial layer 30 , facilitating the subsequent removal of the sacrificial layer 30 .

[0087] Moreover, the sacrificial layer 30 is located in the isolation region II and also extends to a portion of the device region I, so that after the sacrificial layer 30 is subsequently removed, the cavity formed can expose a portion of the bottom surface of the device substrate 120 near the edge of the device region I. Accordingly, in the subsequent step of forming a pad oxide layer, the cavity can provide a formation space for the pad oxide layer on the portion of the bottom surface of the device substrate 120 near the edge of the device region I, which is beneficial to prevent stress from being generated on the device substrate 120 due to the formation and expansion of the pad oxide layer at the bottom of the device substrate 120, and is beneficial to reducing the risk of warping of the device substrate 120 near the edge of the device region I.

[0088] The thickness of the liner oxide layer is the target thickness. Compared to the target thickness, the thickness of the sacrificial layer 30 should not be too small or too large. If the thickness of the sacrificial layer 30 is too small, then after the sacrificial layer 30 is subsequently removed to form a cavity, the vertical space of the cavity is too small, making it difficult to provide sufficient space for the liner oxide layer to form and expand at the bottom of the device substrate 120 exposed in the cavity. Moreover, a too small thickness of the sacrificial layer 30 can easily make the subsequent removal of the sacrificial layer 30 more difficult and the removal efficiency of the sacrificial layer 30 too slow. If the thickness of the sacrificial layer 30 is too large, it can easily lead to an excessive thickness of the insulating buried layer 110, which in turn can easily lead to an excessive thickness of the formed device, which is not conducive to device miniaturization and can also easily result in unnecessary waste of material and space. To this end, in this embodiment, the thickness of the sacrificial layer 30 is 5 to 10 times the target thickness.

[0089] In the step of providing the substrate, the material of the sacrificial layer 30 is different from the materials of the bottom insulating layer 10 and the supporting portion 20, so that in the subsequent process of removing the sacrificial layer 30, there is a selectivity between the sacrificial layer 30 and the bottom insulating layer 10 and the supporting portion 20, which is beneficial to reduce the probability of damaging the bottom insulating layer 10 and the supporting portion 20 in the subsequent process of removing the sacrificial layer 30.

[0090] As an embodiment, the material of the sacrificial layer 30 includes silicon nitride. In other embodiments, based on the actual materials of the bottom insulating layer and the support portion, the material of the sacrificial layer can also be one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0091] The support portion 20 is used to support the device substrate 120 during the subsequent formation of the cavity, liner oxide layer, and isolation layer. After the sacrificial layer is removed, the support portion 20, the bottom insulating layer 10, and the device substrate 120 form a cavity.

[0092] In one embodiment, the material of the support portion 20 is the same as that of the bottom insulating layer 10. Specifically, the material of the support portion 20 is silicon oxide, which is beneficial for improving process compatibility. In other embodiments, the material of the support portion may also be other suitable insulating materials, such as one or more of silicon oxide, silicon oxynitride, silicon nitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride.

[0093] Along a direction parallel to the surface of the device substrate 120, a gap is formed between the sidewall of the support portion 20 and the edge of the device region I, so that the sacrificial layer 30 can extend to a portion of the device region I. The edge of the device region I refers to the boundary between the device region I and the isolation region II.

[0094] Along the direction parallel to the substrate surface, the distance d between the sidewall of the support portion 20 and the boundary between the device region I and the isolation region II is Figure 16 The distance d should not be too small or too large. If the distance d is too small, the bottom surface area of the device substrate 120 in the device region I covered by the sacrificial layer 30 will be too small. This may result in the material at the bottom of the device substrate 120 being exposed after oxidation and expansion after the sacrificial layer 30 is subsequently removed. This may increase the risk of warping of the device substrate 120 and the formation of compressive stress. If the distance d is too large, the support portion 20 may not be able to effectively support the entire bottom of the device substrate 120. To this end, in this embodiment, the distance d between the sidewall of the support portion 20 and the boundary between the device region I and the isolation region II, along a direction parallel to the substrate surface, is at least 500 nanometers.

[0095] As an example, the support portion 20 is a columnar structure, that is, the support portion 20 is a support column. In other embodiments, the support portion can also be a structure of other shapes, as long as the support portion can support the device substrate.

[0096] It should be noted that the width of the support portion 20 in a direction parallel to the surface of the device substrate 120 should not be too small or too large. If the width of the support portion 20 is too small, the support effect of the support portion 20 on the device substrate 120 will be reduced; if the width of the support portion 20 is too large, the space between the support portions 20 will be too small, which is not conducive to the subsequent filling of the liner oxide layer in the cavity. To this end, in this embodiment, the width of the support portion 20 in a direction parallel to the surface of the device substrate 120 is 50 nanometers to 1000 nanometers.

[0097] Specifically, in this embodiment, the support portion 20 is a columnar structure, and the width of the support portion 20 refers to the diameter of the support portion 20 .

[0098] In this embodiment, in the step of providing a substrate, in each device region I, there are a plurality of support portions 20, and the plurality of support portions 20 are spaced apart from each other. The sacrificial layer 30 is also filled between adjacent support portions 20. Accordingly, after the sacrificial layer 30 is subsequently removed to form a cavity, the cavity is still located in the region between adjacent support portions 20 in the device region I, that is, the cavity is still located in the middle region of the device region I. This helps to improve the uniformity of the distribution of the cavity at the bottom of the device substrate 120, thereby helping to improve the uniformity of the position distribution of the subsequent liner oxide layer at the bottom of the device substrate 120, and further helps to reduce the probability of stress generated in the device substrate 120 due to oxidation of the bottom of the device substrate 120.

[0099] In this embodiment, the steps of forming the buried insulating layer 110 include:

[0100] like Figure 8 As shown, the bottom insulating layer 10 is formed on the top surface of the carrier substrate 100 .

[0101] In this embodiment, an oxidation process is used to form the bottom insulating layer 10. Specifically, an oxidation process is performed on the top surface of the carrier substrate 100 to oxidize a portion of the thickness of the top surface of the carrier substrate 100 into the bottom insulating layer 10.

[0102] like Figure 9 As shown, a sacrificial material layer 40 is formed on the bottom insulating layer 10 .

[0103] The sacrificial material layer 40 is used to form a sacrificial layer later.

[0104] In this embodiment, a deposition process (eg, chemical vapor deposition process) is used to form the sacrificial material layer 40 .

[0105] like Figure 10 and Figure 11 As shown, Figure 10 is a cross-sectional view, Figure 11 for Figure 10 In the corresponding top view, a through hole 50 is formed in the sacrificial material layer 40 in the device region I, and the remaining sacrificial material layer 40 is used as the sacrificial layer 30 .

[0106] The through hole 50 is used to provide a space for forming the support portion. The sacrificial layer 30 is used to provide support for forming the support portion, and the sacrificial layer 30 is also used to occupy a space for subsequently forming a cavity.

[0107] In this embodiment, an anisotropic etching process is adopted to etch the sacrificial material layer 40 to form the through hole 50 , thereby precisely controlling the opening size, position and sidewall morphology of the through hole 50 .

[0108] In this embodiment, the through holes 50 are arranged in a matrix on the bottom insulating layer 10. In other embodiments, the through holes can be arranged in other ways on the bottom insulating layer.

[0109] Specifically, based on the actual size of the through hole 50 and the area size of the device area I, the number of the through holes 50 in each device area I can be one or more, as long as the support portion subsequently formed in the through hole 50 can provide sufficient support for the device substrate 120.

[0110] As an embodiment, in each of the device regions I, the number of the through holes 50 is 4.

[0111] In this embodiment, in order to ensure that the sacrificial material layer 40 in the isolation region II can be completely removed, the sacrificial material layer 40 is usually over-etched during the process of forming the through hole 50 .

[0112] Therefore, in this embodiment, during the process of forming the through hole 50 , a portion of the bottom insulating layer 10 is also etched.

[0113] like Figures 12 to 13 As shown, the support portion 20 is filled in the through hole 50 , and the bottom insulating layer 10 , the support portion 20 and the sacrificial layer 30 constitute the buried insulating layer 110 .

[0114] In this embodiment, the step of filling the support portion 20 in the through hole 50 includes: Figure 12As shown, a support material layer 60 is filled in the through hole 50, and the support material layer 60 is also formed on the top surface of the sacrificial layer 30; Figure 13 As shown, the support material layer 60 located on the top surface of the sacrificial layer 30 is removed.

[0115] In this embodiment, a process with strong filling capability is selected to fill the support material layer 60 in the through hole 50 to improve the filling capability and filling quality of the support material layer 60 in the through hole 50 and reduce the probability of defects such as voids in the support material layer 60 .

[0116] As an example, the process of filling the support material layer 60 in the through hole 50 includes one or more of a chemical vapor deposition process, a plasma enhanced chemical vapor deposition process, and an atomic layer deposition process.

[0117] In this embodiment, a planarization process is used to remove the support material layer 60 on the top surface of the sacrificial layer 30. The planarization process is beneficial to improving the top surface height consistency and top surface flatness of the support portion 20 and the sacrificial layer 30.

[0118] Specifically, the process of removing the support material layer 60 located on the top surface of the sacrificial layer 30 includes a chemical mechanical planarization (CMP) process. The chemical mechanical planarization process is beneficial for improving the flatness and height consistency of the top surfaces of the support portion 20 and the sacrificial layer 30, thereby providing a highly flat film surface for subsequent processes.

[0119] like Figure 14 As shown, an initial device substrate 70 is provided. The initial device substrate 70 includes a first surface 701 and a second surface 702 that are opposite to each other.

[0120] The first surface 701 is used as a bonding surface for bonding the initial device substrate 70 to the insulating buried layer 110 .

[0121] like Figure 15 As shown, the first surface 701 of the initial device substrate 70 is bonded to the insulating buried layer 110 .

[0122] like Figure 16 As shown, a portion of the thickness of the material on the second surface 702 of the initial device substrate 70 is removed, and the remaining initial device substrate 70 serves as the device substrate 120 .

[0123] Part of the thickness of the material on the second surface 702 of the initial device substrate 70 is removed, thereby reducing the thickness of the initial device substrate 70 .

[0124] In this embodiment, removing part of the thickness of material on the second surface 702 of the initial device substrate 70 includes: using an etch back process to remove part of the thickness of material on the second surface 702 of the initial device substrate 70; or using a grinding process to remove part of the thickness of material on the second surface 702 of the initial device substrate 70; or using a smart cut process to remove part of the thickness of material on the second surface 702 of the initial device substrate 70.

[0125] In which, when the intelligent stripping process is used to remove part of the thickness of the material on the second surface 702 of the initial device substrate 70, the method for forming the semiconductor structure also includes: after providing the initial device substrate 70 and before bonding the first surface 701 of the initial device substrate 70 to the insulating buried layer 110, ion implantation of part of the depth of the material on the second surface 702 of the initial device substrate 70 is performed to form a microcavity layer in the initial device substrate 70 having a distance between the second surface 702.

[0126] Specifically, the ions implanted into the material at a portion of the depth of the second surface 702 of the initial device substrate 70 include H ions.

[0127] Accordingly, the step of removing a portion of the thickness of the material from the second surface 702 of the initial device substrate 70 using the smart peeling process includes: performing a heat treatment on the initial device substrate 70 to generate internal pressure in the micro-cavity layer to cause foaming, thereby causing the initial device substrate 70 to peel at the location of the micro-cavity layer. Specifically, performing the heat treatment on the initial device substrate 70 includes annealing.

[0128] refer to Figure 17 , at least the device substrate 120 located in the isolation region II is removed to form a trench 130 , wherein the trench 130 exposes the sacrificial layer 30 .

[0129] The trench 130 in the device substrate 120 is used to provide a space for subsequently forming an isolation layer, so as to isolate adjacent device regions I. In addition, the trench 130 exposes the sacrificial layer 30, and facilitates the subsequent removal of the sacrificial layer 30 through the exposed sacrificial layer 30.

[0130] In this embodiment, in the step of removing at least the device substrate 120 located in the isolation region II, the groove 130 penetrates the device substrate 120 of the isolation region II, or the groove 130 penetrates the device substrate 120 of the isolation region II and a partial thickness or full thickness of the sacrificial layer 30.

[0131] Among them, when the groove 130 penetrates the device substrate 120 of the isolation region II and the sacrificial layer 30 of partial thickness or full thickness, it is beneficial to increase the exposed area of the sacrificial layer 30, which is beneficial to improve the efficiency of subsequent removal of the sacrificial layer 30 and reduce the difficulty of removing the sacrificial layer 30, so as to facilitate the clean removal of the sacrificial layer 30.

[0132] As an embodiment, the groove 130 penetrates the device substrate 120 of the isolation region II and the entire thickness of the sacrificial layer 30, so that the sidewall of the groove 130 exposes the entire thickness of the sacrificial layer 30, which is beneficial to further increase the exposed area of the sacrificial layer 30. Accordingly, in the subsequent process of removing the sacrificial layer 30, the contact area between the etching solution or etching gas and the sacrificial layer 30 can be increased, so as to remove the sacrificial layer 30 with higher efficiency, and at the same time, it is beneficial to remove the sacrificial layer 30 cleanly.

[0133] In this embodiment, the method for forming the semiconductor structure further includes: forming a capping layer 140 on the device substrate 120 after providing the substrate and before forming the trench 130 .

[0134] The cover layer 140 is used to protect the top surface of the device substrate 120 .

[0135] As an embodiment, the material of the cover layer 140 is silicon oxide. In other embodiments, the cover layer can also be made of other materials suitable for protecting the top surface of the device substrate.

[0136] Accordingly, in this embodiment, the step of forming the trench 130 includes: sequentially removing the cover layer 130 , the device substrate 120 , and the sacrificial layer 30 located in the isolation region II to form the trench 130 .

[0137] In this embodiment, an anisotropic etching process (eg, an anisotropic dry etching process) is used to form the trench 130. The anisotropic etching process has the characteristic of anisotropic etching, which is conducive to precise control of the etching profile.

[0138] refer to Figure 18 After forming the groove 130, the sacrificial layer 30 is removed to form a cavity 200 surrounded by the bottom insulating layer 10, the support portion 20 and the device substrate 120. The cavity 200 is connected to the groove 130, and the cavity 200 exposes a portion of the bottom surface of the device substrate 120 near the edge of the device region I.

[0139] In the aforementioned process of forming the sacrificial layer 30, the sacrificial layer 30 is located in the isolation region II and also extends to a portion of the device region I. Accordingly, after removing the sacrificial layer 30, the formed cavity 200 can expose a portion of the bottom surface of the device substrate 120 near the edge of the device region I. The cavity 200 can provide a formation space and expansion space for the subsequent pad oxide layer under the device substrate 120, thereby preventing stress from being generated on the bottom of the device substrate 120 due to the formation and expansion of the pad oxide layer at the bottom of the device substrate 120, and correspondingly reducing the risk of warping of the device substrate 120 near the edge of the device region I, thereby optimizing the performance of the semiconductor structure.

[0140] As an example, an isotropic etching process is used to remove the sacrificial layer 30 . The isotropic etching process has the characteristic of isotropic etching, so as to remove the sacrificial layer 30 located below the device substrate 120 .

[0141] In one embodiment, the process for removing the sacrificial layer 30 includes a wet etching process. The wet etching process has the characteristic of isotropic etching, which facilitates the clean removal of the sacrificial layer 30. The wet etching process is also simple to operate and low in cost. Specifically, in this embodiment, the material of the sacrificial layer 30 is silicon nitride, and the etching solution of the wet etching process includes a hot phosphoric acid solution.

[0142] In other embodiments, the sacrificial layer may be removed by using an isotropic dry etching process.

[0143] In this embodiment, in the step of providing a substrate, in each of the device areas I, there are multiple support parts 20, and the multiple support parts 20 are spaced apart, and the sacrificial layer 30 is also filled between adjacent support parts 20. Accordingly, after removing the sacrificial layer 30 to form the cavity 200, the cavity 200 is also located in the area between the adjacent support parts 20 of the device area I, that is, the cavity 200 is also located in the middle area of the device area I, which is beneficial to improving the distribution uniformity of the cavity 200 at the bottom of the device substrate 120, and further beneficial to improving the position distribution uniformity of the subsequent liner oxide layer at the bottom of the device substrate 120, and beneficial to further reduce the probability of stress on the device substrate 120 due to bottom oxidation of the device substrate 120.

[0144] refer to Figure 19 A pad oxide layer 150 is formed on the bottom surface of the device substrate 120 exposed in the cavity 200 and the device substrate 120 on the sidewalls of the trench 130 .

[0145] The pad oxide layer 150 is used to repair etching damage on the surface of the device substrate 120 , including etching damage caused to the device substrate 120 during the process of forming the trench 130 .

[0146] In this embodiment, the cavity 200 exposes a portion of the bottom surface of the device substrate 120 near the edge of the device region I. In the process of forming the pad oxide layer 150, the pad oxide layer 150 can be formed on the bottom surface of the device substrate 120 exposed by the cavity 200. Since the cavity 200 is formed at the bottom of the device substrate 120, the cavity 200 can provide a formation space and expansion space for the pad oxide layer 150 below the device substrate 120, thereby preventing the device substrate 120 from being subjected to stress due to the formation and expansion of the pad oxide layer 150 at the bottom of the device substrate 120, and correspondingly reducing the risk of warping of the device substrate 120 near the edge of the device region I, thereby optimizing the performance of the semiconductor structure.

[0147] When forming an NMOS device, it is beneficial to prevent compressive stress on the device substrate 120 due to the formation and expansion of the oxide material at the bottom of the device substrate 120, thereby significantly improving the performance of the NMOS device.

[0148] In this embodiment, the process for forming the pad oxide layer 150 includes an oxidation process. By using the oxidation process to form the pad oxide layer 150, the exposed portion of the device substrate 120 is oxidized to form the pad oxide layer 150. Furthermore, the exposed portion of the device substrate 120 that may have etching damage is oxidized to form the pad oxide layer 150, thereby repairing the etching damage to the device substrate 120.

[0149] Accordingly, in this embodiment, the material of the pad oxide layer 150 is the oxide of the material of the device substrate 120. In this embodiment, the material of the device substrate 120 is silicon, and the material of the pad oxide layer 150 is silicon oxide.

[0150] As an embodiment, the process for forming the liner oxide layer 150 includes a furnace dry oxygen oxidation process or an in-situ steam generation (ISSG) oxidation process. The process for forming the liner oxide layer 150 may also be other oxidation processes.

[0151] Specifically, in this embodiment, the pad oxide layer 150 may be formed in a nitrogen-containing gas atmosphere.

[0152] By forming the pad oxide layer 150 in a nitrogen-containing gas atmosphere, it is beneficial to make the surface of the device substrate 120 contain nitrogen atoms or the pad oxide layer 150 contain nitrogen atoms. Since nitrogen atoms can inhibit oxidation in the subsequent heat treatment process, it is beneficial to reduce the consumption of the device substrate 120 in the subsequent process, and it is also beneficial to reduce the oxidation of the bottom of the device substrate 120, which is beneficial to further reduce the problem of stress caused by oxidation of the bottom of the device substrate 120.

[0153] The nitrogen-containing gas may include nitrogen, ammonia, etc.

[0154] Alternatively, refer to Figure 20 In this embodiment, the method for forming the semiconductor structure further includes: after forming the liner oxide layer 150 , heat treating the liner oxide layer 150 and the device substrate 120 in a nitrogen-containing gas atmosphere.

[0155] After forming the pad oxide layer 150, heat-treating the pad oxide layer 150 and the device substrate 120 in a nitrogen-containing gas atmosphere helps to diffuse nitrogen atoms into the pad oxide layer 150 and at the interface between the pad oxide layer 150 and the device substrate 120, which in turn helps to enable the nitrogen atoms to inhibit oxidation in the subsequent heat treatment process, thereby helping to reduce the consumption of the device substrate 120 in the subsequent process, and also helps to reduce the oxidation of the bottom of the device substrate 120, which helps to further reduce the problem of stress caused by the oxidation of the bottom of the device substrate 120.

[0156] The nitrogen-containing gas may include nitrogen, ammonia, etc. The heat treatment of the pad oxide layer 150 and the device substrate 120 may include an annealing process.

[0157] refer to Figures 21 to 23 After forming the liner oxide layer 150 , an isolation layer 210 is filled in the cavity 200 and the trench 130 .

[0158] The isolation layer 210 is used to isolate adjacent device regions I. The isolation layer 210 also fills the cavity 200 so as to support the device substrate 120 together with the support portion 20 , thereby improving the support strength of the device substrate 120 .

[0159] The isolation layer 210 is made of an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, and silicon boron carbide nitride. The isolation layer 210 may be made of the same material as the bottom insulating layer 10, or may be made of a different material than the bottom insulating layer 10.

[0160] As an embodiment, the material of the isolation layer 210 is the same as that of the bottom insulating layer 10 . The material of the isolation layer 210 is silicon oxide, which is beneficial to improving process compatibility.

[0161] In this embodiment, in the same step, the isolation layer 210 is filled in the cavity 200 and the trench 130 . Accordingly, the isolation layer 210 is an integrated structure.

[0162] In this embodiment, the step of filling the cavity 200 and the trench 130 with the isolation layer 210 includes:

[0163] like Figure 21 As shown, an isolation material layer 180 is filled in the cavity 200 and the trench 130 , and the isolation material layer 180 is also formed on the device substrate 120 .

[0164] Specifically, in this embodiment, the isolation material layer 180 is also formed on the cover layer 140 .

[0165] In this embodiment, the process of forming the isolation material layer 180 includes one or more of a chemical vapor deposition process, a flow chemical vapor deposition process, and an atomic layer deposition process.

[0166] The process of forming the isolation material layer 180 has a high gap filling capability, thereby improving the filling capability and filling quality of the isolation material layer 180 in the cavity 200 and the groove 130 , and reducing the probability of defects such as voids being generated in the isolation material layer 180 located in the cavity 200 and the groove 130 .

[0167] The process for forming the isolation material layer 180 is not limited to the above-mentioned deposition process, and may also be other processes with strong gap-filling capabilities.

[0168] like Figure 22 and Figure 23 As shown, the isolation material layer 170 above the top surface of the device substrate 120 is removed.

[0169] In this embodiment, during the step of forming the isolation layer 210 , the cover layer 140 is removed.

[0170] Specifically, in the step of removing the isolation material layer 170 that is higher than the top surface of the device substrate 120 , the cover layer 140 is removed.

[0171] In this embodiment, the step of removing the isolation material layer 170 above the top surface of the device substrate 120 includes: Figure 22 As shown, the isolation material layer 170 and the cover layer 140 are planarized; Figure 23 As shown, the remaining isolation material layer 170 and cover layer 140 are removed.

[0172] In this embodiment, the process of planarizing the isolation material layer 170 and the cover layer 140 includes a chemical mechanical planarization process.

[0173] In this embodiment, the process of removing the remaining isolation material layer 170 and the cover layer 140 includes an etching process.

[0174] refer to Figure 24 After forming the isolation layer 210 , a gate structure 230 located on the device substrate 120 and source / drain doped regions 250 located in the device substrate 120 on both sides of the gate structure 230 are formed.

[0175] The gate structure 230 is used to control the on and off of the conductive channel.

[0176] In this embodiment, the gate structure 230 is a polysilicon gate structure or an amorphous silicon gate structure, and the gate structure 230 includes a gate layer, and the material of the gate layer is polysilicon or amorphous silicon. In other embodiments, the gate structure can also be other types of gate structures, such as a metal gate structure.

[0177] The source / drain doped regions 250 are used as source or drain regions of a field-effect transistor. Specifically, when forming an NMOS transistor, the source / drain doped regions 250 are doped with N-type ions, such as P ions, As ions, or Sb ions. When forming a PMOS transistor, the source / drain doped regions 250 are doped with P-type ions, such as B ions, Ga ions, or In ions.

[0178] In this embodiment, before forming the gate structure 230 and the source-drain doped regions 250 , the method for forming the semiconductor structure further includes: forming a gate dielectric layer 220 on the device substrate 120 and the isolation layer 210 .

[0179] The gate dielectric layer 220 is used to isolate the gate structure 230 from the device substrate 120 .

[0180] In this embodiment, the gate dielectric layer 220 is a gate oxide layer made of silicon oxide. In other embodiments, the gate oxide layer may be made of nitrogen-doped silicon oxide or other insulating materials. In still other embodiments, the gate dielectric layer may include a high-k gate dielectric layer made of a high-k dielectric material.

[0181] The specific steps of forming the gate structure 230 and the source-drain doped regions 250 in this embodiment will be described in detail below with reference to the accompanying drawings.

[0182] like Figure 24 As shown, a gate structure 230 is formed on the device substrate 120 .

[0183] like Figure 24 As shown, a gate spacer 240 is formed on the sidewall of the gate structure 230 .

[0184] The gate spacer 240 is used to protect the sidewalls of the gate structure 230 and is also used to define the formation area of the source and drain doped regions 250 .

[0185] The gate spacer 240 may be made of one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxycarbide, silicon oxycarbonitride, boron nitride, and boron carbonitride. The gate spacer 240 may have a single-layer structure or a stacked-layer structure. In this embodiment, the gate spacer 240 is a single-layer structure made of silicon nitride.

[0186] like Figure 24 As shown, after the gate spacer 240 is formed, the source and drain doped regions 250 are formed in the device substrate 120 on both sides of the gate structure 230 and the gate spacer 240 .

[0187] Specifically, ion doping is performed on the device substrate 120 on both sides of the gate structure 230 and the gate spacer 240 to form the source and drain doping regions 250 .

[0188] In this embodiment, an ion implantation process is used to perform ion doping on the device substrate 120 on both sides of the gate structure 230 and the gate spacer 240 .

[0189] Subsequent processes generally further include: forming a silicide layer on the top surfaces of the gate structure 230 and the source / drain doped regions 250. The subsequent process steps will not be described in detail in this embodiment.

[0190] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that include: A substrate comprising a plurality of discrete device regions and isolation regions between the device regions; The substrate comprises: a carrier substrate; a bottom insulating layer located on the carrier substrate; a support portion protruding from the bottom insulating layer in the device region, wherein the bottom insulating layer exposed by the support portion is located on the top surface of the isolation region and a portion of the device region; a device substrate located above the bottom insulating layer in the device region and in contact with the support portion, wherein the device substrate, the bottom insulating layer and the support portion enclose a cavity; a liner oxide layer, located on the bottom surface of the device substrate exposed by the cavity and the sidewalls of the device substrate; an isolation layer, filling the cavity and between adjacent device substrates, and covering the liner oxide layer; a gate structure, located on the device substrate in the device region; The source and drain doping regions are located in the device substrate on both sides of the gate structure.

2. The semiconductor structure according to claim 1, wherein Along a direction parallel to the substrate surface, a distance between a sidewall of the support portion and a sidewall of the device substrate is at least 500 nanometers.

3. The semiconductor structure according to claim 1, wherein: The thickness of the liner oxide layer located on the bottom surface of the device substrate is a target thickness; along a direction perpendicular to the surface of the substrate, the height of the cavity is 5 to 10 times the target thickness.

4. The semiconductor structure according to claim 1, wherein: The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon boron carbide nitride.

5. The semiconductor structure according to claim 1 or 4, wherein: The isolation layer is made of the same material as the bottom insulating layer, or the isolation layer is made of a different material than the bottom insulating layer.

6. The semiconductor structure according to claim 1, wherein The isolation layer is an integrated structure.

7. The semiconductor structure according to claim 1, wherein: The supporting portion is a columnar structure.

8. The semiconductor structure according to claim 1 or 3, wherein: In each of the device regions, there are a plurality of support portions, and the plurality of support portions are spaced apart from each other.

9. The semiconductor structure according to claim 1, wherein: Along a direction parallel to the surface of the device substrate, the width of the support portion is 50 nanometers to 1000 nanometers.

10. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate comprising a plurality of discrete device regions and isolation regions between the device regions; the substrate comprising: a carrier substrate; an insulating buried layer located on the carrier substrate, the insulating buried layer comprising a bottom insulating layer, a support portion protruding from the bottom insulating layer in the device region, and a sacrificial layer located on the bottom insulating layer and covering a sidewall of the support portion, the sacrificial layer being located in the isolation region and also extending into a portion of the device region; A device substrate, located on the insulating buried layer; removing at least the device substrate located in the isolation region to form a trench, wherein the trench exposes the sacrificial layer; After forming the trench, removing the sacrificial layer to form a cavity surrounded by the bottom insulating layer, the support portion, and the device substrate, wherein the cavity is connected to the trench and exposes a portion of the bottom surface of the device substrate near the edge of the device region; forming a liner oxide layer on the bottom surface of the device substrate exposed in the cavity and on the device substrate at the sidewalls of the trench; After forming the liner oxide layer, filling the cavity and the trench with an isolation layer; After forming the isolation layer, a gate structure located on the device substrate and source / drain doped regions located in the device substrate on both sides of the gate structure are formed.

11. The method for forming a semiconductor structure according to claim 10, wherein: The step of providing a substrate comprises: providing a carrier substrate; forming the insulating buried layer on the top surface of the carrier substrate; Providing an initial device substrate, the initial device substrate comprising a first side and a second side opposite to each other; bonding the first side of the initial device substrate to the insulating buried layer; Part of the thickness of the material on the second surface of the initial device substrate is removed, and the remaining initial device substrate serves as the device substrate.

12. The method for forming a semiconductor structure according to claim 11, wherein: The step of forming the buried insulating layer on the top surface of the carrier substrate comprises: forming the bottom insulating layer on the top surface of the carrier substrate; forming a sacrificial material layer on the bottom insulating layer; forming a through hole in the sacrificial material layer in the device region, with the remaining sacrificial material layer being used as the sacrificial layer; The supporting portion is filled in the through hole, and the bottom insulating layer, the supporting portion and the sacrificial layer constitute the buried insulating layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: The step of filling the support portion in the through hole includes: filling the through hole with a support material layer, wherein the support material layer is also formed on the top surface of the sacrificial layer; and removing the support material layer on the top surface of the sacrificial layer.

14. The method for forming a semiconductor structure according to claim 13, wherein: The process of filling the support material layer in the through hole includes one or more of a chemical vapor deposition process and an atomic layer deposition process; The process of removing the support material layer on the top surface of the sacrificial layer includes a chemical mechanical planarization process.

15. The method for forming a semiconductor structure according to claim 11, wherein: Removing part of the thickness of material on the second surface of the initial device substrate includes: using an etching process to remove part of the thickness of material on the second surface of the initial device substrate; or using a grinding process to remove part of the thickness of material on the second surface of the initial device substrate; or using an intelligent stripping process to remove part of the thickness of material on the second surface of the initial device substrate.

16. The method for forming a semiconductor structure according to claim 10, wherein: forming the pad oxide layer in a nitrogen-containing gas atmosphere; Alternatively, the method for forming the semiconductor structure further comprises: after forming the liner oxide layer and before forming the isolation layer, performing a heat treatment on the liner oxide layer and the device substrate in a nitrogen-containing gas atmosphere.

17. The method for forming a semiconductor structure according to claim 10, wherein: In the step of removing at least the device substrate located in the isolation region, the trench penetrates the device substrate in the isolation region, or the trench penetrates the device substrate in the isolation region and a partial thickness or the entire thickness of the sacrificial layer.

18. The method for forming a semiconductor structure according to claim 10, wherein: The supporting portion is a columnar structure.

19. The method for forming a semiconductor structure according to claim 10 or 18, wherein: In the step of providing a substrate, in each of the device regions, there are a plurality of support portions, and the plurality of support portions are spaced apart from each other, and the sacrificial layer is also filled between adjacent support portions.

20. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing the substrate, the material of the sacrificial layer is different from the materials of the bottom insulating layer and the supporting portion; The material of the sacrificial layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride and silicon boron carbide nitride.

21. The method for forming a semiconductor structure according to claim 10, wherein: The process of removing the sacrificial layer includes a wet etching process.

22. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the liner oxide layer includes a furnace tube dry oxygen oxidation process or an in-situ steam generation oxidation process.

23. The method for forming a semiconductor structure according to claim 10, wherein: In the step of providing a substrate, the sacrificial layer is used to occupy a space for forming a cavity, and the cavity is used to provide a formation space for forming a pad oxide layer; The thickness of the liner oxide layer is a target thickness, and the thickness of the sacrificial layer is 5 to 10 times the target thickness.

24. The method for forming a semiconductor structure according to claim 10, wherein: The step of filling the cavity and the trench with an isolation layer includes: filling the cavity and the trench with an isolation material layer, the isolation material layer also being formed on the device substrate; and removing the isolation material layer above the top surface of the device substrate.

25. The method for forming a semiconductor structure according to claim 10, wherein: The process of forming the isolation layer includes one or more of a chemical vapor deposition process and an atomic layer deposition process.

26. The method for forming a semiconductor structure according to claim 10, wherein: The method for forming a semiconductor structure further includes: forming a covering layer on the device substrate after providing the substrate and before forming the trench; In the step of forming the isolation layer, the cover layer is removed.

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