Semi-floating gate device

Abstract

The application discloses a kind of semi-floating gate devices, floating gate structure covers the selected area of first well region and is used to form conductive channel.Floating gate structure also covers the surface of lightly doped drain region and contacts between floating gate material layer and lightly doped drain region at dielectric layer window and forms PN structure.Source region and the first side of floating gate structure are self-aligned.First control gate is superimposed on the top of floating gate structure, and first control gate is superimposed by first gate dielectric layer and first gate conductive material layer.Second control gate is arranged on the surface of lightly doped drain region between drain region and the second side of floating gate structure;Second control gate is superimposed by second gate dielectric layer and second gate conductive material layer.Gate dielectric layer is isolated between first control gate and second control gate.First control gate is used to control the reading operation of semi-floating gate device;Second control gate is used to control the erasing operation of semi-floating gate device.The application can realize simultaneous read and write and obtain better signal retention characteristics.

Description

Technical Field

[0001] This invention relates to a semiconductor integrated circuit, and more particularly to a semi-floating gate transistor. Background Technology

[0002] Semi-floating gate devices have great potential to replace DRAM, offering fast read / write speeds and eliminating the need for capacitors. Unlike conventional floating gate devices, semi-floating gate devices utilize an embedded tunneling transistor and a PN junction for charging and discharging. Writing is performed through the channel of the embedded tunneling transistor, while erasing is done through the PN junction. For example... Figure 1 The diagram shown is a schematic of an existing semi-floating gate device; the existing semi-floating gate device includes:

[0003] A first well region 101 doped with a second conductivity type and a lightly doped source region 1021 and a lightly doped drain region 1022, both composed of a second well region 102 doped with a second conductivity type, are formed in a semiconductor substrate.

[0004] The floating gate structure includes a gate trench, a floating gate dielectric layer 103, a dielectric layer window, and a floating gate material layer 104.

[0005] The gate trench passes through the second well region 102 and its bottom surface enters the first well region 101. The floating gate dielectric layer 103 covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region 1022 outside the gate trench.

[0006] The floating gate material layer 104 completely fills the gate trench on which the floating gate dielectric layer 103 is formed and extends to the floating gate dielectric layer 103 and the dielectric layer window outside the gate trench. The dielectric layer window is located on the surface of the lightly doped drain region 1022 in the region described by dashed box 111, and the floating gate material layer 104 and the lightly doped drain region 1022 are in contact at the dielectric layer window to form a PN structure.

[0007] The material of the floating gate dielectric layer 103 includes an oxide layer.

[0008] The floating gate material layer 104 is a polycrystalline silicon layer doped with a second conductivity type.

[0009] The bottom of the floating gate structure covers the first well region 101, and the surface of the first well region 101 covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region 1021 and the lightly doped drain region 1022.

[0010] A source region 109 heavily doped with a first conductivity type is formed in a selected area on the surface of the lightly doped source region 1021.

[0011] A heavily doped drain region 110 of a first conductivity type is formed in a selected area on the surface of the lightly doped drain region 1022.

[0012] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0013] The source region 109 and the first side of the floating grid structure are self-aligned.

[0014] A control gate covers the top of the floating gate structure and the surface of the lightly doped drain region 1022 between the drain region 110 and the second side of the floating gate structure. The control gate includes a gate conductive material layer 107, a gate dielectric layer 105, and an inter-gate dielectric layer 106. The gate dielectric layer 105 provides isolation between the gate conductive material layer 107 and the lightly doped drain region 1022, and the inter-gate dielectric layer 106 provides isolation between the gate conductive material layer 107 and the floating gate material layer 104.

[0015] The leak area 110 and the second side of the second control gate 105 are self-aligned.

[0016] Sidewalls 108 are formed on both sides of the control gate.

[0017] Figure 1 The existing device shown has only a single control gate, which overlays the floating gate and partially covers the substrate. During write and erase operations, charge tunnels through the PN junction at the location indicated by the dashed box 111 under the control of the control gate. Read operations also require the control gate to be controlled. This structure requires the same control gate for both reading and writing, and simultaneous reading and writing are not possible. Summary of the Invention

[0018] The technical problem to be solved by the present invention is to provide a semi-floating gate device that can achieve simultaneous read and write and obtain better signal retention characteristics.

[0019] To solve the above-mentioned technical problems, the semi-floating gate device provided by the present invention includes:

[0020] A lightly doped source region of a first conductivity type, a lightly doped drain region of a first conductivity type, and a first well region of a second conductivity type are formed in a semiconductor substrate.

[0021] A floating gate structure covers a selected area of ​​the first well region, and the surface of the first well region covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region and the lightly doped drain region.

[0022] The floating grid structure includes a floating grid dielectric layer, a dielectric layer window, and a floating grid material layer.

[0023] The floating gate structure also covers the surface of the lightly doped drain region, and the dielectric layer window is located on the surface of the lightly doped drain region. At the dielectric layer window, the floating gate material layer and the lightly doped drain region are in contact and form a PN structure.

[0024] A heavily doped source region of the first conductivity type is formed in a selected area on the surface of the lightly doped source region.

[0025] A heavily doped drain region of the first conductivity type is formed in a selected area on the surface of the lightly doped drain region.

[0026] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0027] The source region and the first side of the floating grid structure are self-aligned.

[0028] The first control gate is superimposed on top of the floating gate structure, and the first control gate is composed of a first gate dielectric layer and a first gate conductive material layer.

[0029] The second control gate is disposed on the surface of the lightly doped drain region between the drain region and the second side of the floating gate structure; the second control gate is formed by stacking a second gate dielectric layer and a second gate conductive material layer.

[0030] An inter-gate dielectric layer isolates the first control gate and the second control gate.

[0031] The first control gate is used to control the readout operation of the semi-floating gate device;

[0032] The second control gate is used to control the erase and write operations of the semi-floating gate device.

[0033] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0034] A further improvement is that the floating gate structure further includes a gate trench, the bottom surface of which enters the first well region, the lightly doped source region is located above the first well region and contacts the first side surface of the gate trench; the lightly doped drain region is located above the first well region and contacts the second side surface of the gate trench.

[0035] The floating gate dielectric layer covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region outside the gate trench.

[0036] The floating gate material layer completely fills the gate trench on which the floating gate dielectric layer is formed and extends to the floating gate dielectric layer and the dielectric layer window outside the gate trench.

[0037] A further improvement is that the material of the floating gate dielectric layer includes an oxide layer.

[0038] The floating gate material layer is a polycrystalline silicon layer doped with a second conductivity type.

[0039] A further improvement is that the first gate dielectric layer is an oxide layer, and the first gate conductive material layer is a polysilicon layer.

[0040] Alternatively, the first gate dielectric layer may be a high dielectric constant material layer, and the first gate conductive material layer may be a metal gate.

[0041] A further improvement is that the second gate dielectric layer is an oxide layer, and the second gate conductive material layer is a polysilicon layer.

[0042] Alternatively, the second gate dielectric layer may be a high dielectric constant material layer, and the second gate conductive material layer may be a metal gate.

[0043] A further improvement is that the first side and the second side of the first control gate are aligned with the first side and the second side of the floating gate structure, respectively.

[0044] A further improvement is that the first side of the second control gate and the second side of the first control gate are spaced apart by the inter-gate dielectric layer.

[0045] The leak area and the second side of the second control gate are self-aligned.

[0046] A further improvement is that sidewalls are formed on the first side of the first control gate and the second side of the second control gate.

[0047] A further improvement is that the top surface of the first control gate and the top surface of the second control gate are flush.

[0048] A further improvement is that both the lightly doped source region and the lightly doped drain region are composed of a second well region doped with a first conductivity type formed on the surface of the first well region, and the gate trench passes through the second well region to divide the second well region into the lightly doped source region and the lightly doped drain region.

[0049] A further improvement is that the ion implantation dose for the second conductivity type doped in the first well region is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 220keV.

[0050] A further improvement is that the doping concentration of the first well region decreases in a gradient from top to bottom.

[0051] A further improvement is that the ion implantation dose for the first conductivity type doped in the second well region is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

[0052] A further improvement is that the ion implantation dose for the second conductivity type doped in the floating gate material layer is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

[0053] Based on the read and erase / write characteristics of semi-floating gate devices, this invention features a specially designed control gate, primarily by splitting it into a first control gate and a second control gate. The first control gate is located at the top of the floating gate structure and enables control of the read operation of the semi-floating gate device. The second control gate is disposed on the surface of the lightly doped drain region between the drain region and the second side of the floating gate structure, enabling control of the erase / write operation of the semi-floating gate device. By applying different voltages to the first and second control gates, simultaneous read and write operations can be achieved, and the independent operation of each control gate provides better signal retention characteristics.

[0054] The first and second control gates of the present invention have simple structures and are flush in height, which enables diverse preparation methods and simple processes. Attached Figure Description

[0055] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0056] Figure 1 This is a schematic diagram of the structure of an existing semi-floating gate device;

[0057] Figure 2 This is a schematic diagram of the structure of the semi-floating gate device according to the first embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of the structure of the semi-floating gate device according to the second embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of the structure of the semi-floating gate device according to the third embodiment of the present invention;

[0060] Figure 5 This is a schematic diagram of the structure of the semi-floating gate device according to the fifth embodiment of the present invention. Detailed Implementation

[0061] The first embodiment of the present invention is a semi-floating gate device:

[0062] like Figure 2 The diagram shown is a structural schematic of a semi-floating gate device according to a first embodiment of the present invention; the semi-floating gate device according to the first embodiment of the present invention includes:

[0063] A lightly doped source region 2021 of a first conductivity type, a lightly doped drain region 2022 of a first conductivity type, and a first well region 201 of a second conductivity type are formed in a semiconductor substrate.

[0064] In the first embodiment of the present invention, the semiconductor substrate is a silicon substrate.

[0065] A floating gate structure covers a selected area of ​​the first well region 201, and the surface of the first well region 201 covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region 2021 and the lightly doped drain region 2022.

[0066] The floating grid structure includes a floating grid dielectric layer 203, a dielectric layer window, and a floating grid material layer 204.

[0067] The floating gate structure also covers the surface of the lightly doped drain region 2022, and the dielectric layer window is located on the surface of the lightly doped drain region 2022. At the dielectric layer window, the floating gate material layer 204 and the lightly doped drain region 2022 are in contact and form a PN structure.

[0068] A source region 209 of a first conductivity type is formed in a selected area on the surface of the lightly doped source region 2021.

[0069] A heavily doped drain region 210 of a first conductivity type is formed in a selected area on the surface of the lightly doped drain region 2022.

[0070] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0071] The source region 209 and the first side of the floating grid structure are self-aligned.

[0072] The first control gate 206 is superimposed on the top of the floating gate structure. The first control gate 206 is formed by superimposing a first gate dielectric layer 2061 and a first gate conductive material layer 2062.

[0073] The second control gate 205 is disposed on the surface of the lightly doped drain region 2022 between the drain region 210 and the second side of the floating gate structure; the second control gate 205 is formed by stacking a second gate dielectric layer 2051 and a second gate conductive material layer 2052.

[0074] An inter-gate dielectric layer 207 is provided between the first control gate 206 and the second control gate 205.

[0075] The first control gate 206 is used to control the read operation of the semi-floating gate device;

[0076] The second control gate 205 is used to control the erase and write operations of the semi-floating gate device.

[0077] In a first embodiment of the present invention, the floating gate structure further includes a gate trench, the bottom surface of which extends into the first well region 201. The lightly doped source region 2021 is located above the first well region 201 and contacts a first side surface of the gate trench; the lightly doped drain region 2022 is located above the first well region 201 and contacts a second side surface of the gate trench. In other embodiments, the floating gate structure can also be a planar gate, in which case the gate junction trench is not required.

[0078] The floating gate dielectric layer 203 covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region 2022 outside the gate trench.

[0079] The floating gate material layer 204 completely fills the gate trench on which the floating gate dielectric layer 203 is formed and extends to the floating gate dielectric layer 203 and the dielectric layer window outside the gate trench.

[0080] The material of the floating gate dielectric layer 203 includes an oxide layer.

[0081] The floating gate material layer 204 is a polycrystalline silicon layer doped with a second conductivity type.

[0082] In the first embodiment of the present invention, the first gate dielectric layer 2061 is an oxide layer, and the first gate conductive material layer 2062 is a polysilicon layer.

[0083] The second gate dielectric layer 2051 is an oxide layer, and the second gate conductive material layer 2052 is a polysilicon layer.

[0084] The first side and the second side of the first control gate 206 are aligned with the first side and the second side of the floating gate structure, respectively.

[0085] The first side of the second control gate 205 and the second side of the first control gate 206 are spaced apart by the inter-gate dielectric layer 207.

[0086] The leak area 210 and the second side of the second control gate 205 are self-aligned.

[0087] Sidewalls 208 are formed on the first side of the first control gate 206 and the second side of the second control gate 205.

[0088] The top surface of the first control gate 206 is flush with the top surface of the second control gate 205.

[0089] The lightly doped source region 2021 and the lightly doped drain region 2022 are both composed of a second well region 202 formed on the surface of the first well region 201 and doped with a first conductivity type. The gate trench passes through the second well region 202 and divides the second well region 202 into the lightly doped source region 2021 and the lightly doped drain region 2022.

[0090] The ion implantation dose for the second conductivity type doped in the first well region 201 is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 220keV.

[0091] From top to bottom, the doping concentration of the first well region 201 decreases in a gradient.

[0092] The ion implantation dose for the first conductivity type doped in the second well region 202 is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

[0093] The second conductivity type doped ion implantation dose of the floating gate material layer 204 is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

[0094] In the first embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0095] In the first embodiment of the present invention, the control gate is specially configured according to the read and erase / write characteristics of the semi-floating gate device. Specifically, the control gate is divided into a first control gate 206 and a second control gate 205. The first control gate 206 is located at the top of the floating gate structure and can control the read operation of the semi-floating gate device. The second control gate 205 is disposed on the surface of the lightly doped drain region 2022 between the drain region 210 and the second side of the floating gate structure, and can control the erase / write operation of the semi-floating gate device. By applying different voltages to the first control gate 206 and the second control gate 205, simultaneous read and write operations can be achieved, and the two control gates can independently obtain better signal retention characteristics.

[0096] The first control gate 206 and the second control gate 205 in the first embodiment of the present invention have simple structures and the two control gates are at the same height, which enables diverse preparation methods and simple processes.

[0097] The second embodiment of the present invention is a semi-floating gate device:

[0098] like Figure 3 The diagram shown is a structural schematic of a semi-floating gate device according to a second embodiment of the present invention; the semi-floating gate device according to the second embodiment of the present invention includes:

[0099] A lightly doped source region 3021 of the first conductivity type, a lightly doped drain region 3022 of the first conductivity type, and a first well region 301 of the second conductivity type are formed in a semiconductor substrate.

[0100] In the second embodiment of the present invention, the semiconductor substrate is a silicon substrate.

[0101] A floating gate structure covers a selected area of ​​the first well region 301, and the surface of the first well region 301 covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region 3021 and the lightly doped drain region 3022.

[0102] The floating grid structure includes a floating grid dielectric layer 303, a dielectric layer window, and a floating grid material layer 304.

[0103] The floating gate structure also covers the surface of the lightly doped drain region 3022, and the dielectric layer window is located on the surface of the lightly doped drain region 3022. At the dielectric layer window, the floating gate material layer 304 and the lightly doped drain region 3022 are in contact and form a PN structure.

[0104] A source region 309 of a first conductivity type is formed in a selected area on the surface of the lightly doped source region 3021.

[0105] A heavily doped drain region 310 of a first conductivity type is formed in a selected area on the surface of the lightly doped drain region 3022.

[0106] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0107] The source region 309 and the first side of the floating grid structure are self-aligned.

[0108] The first control gate 306 is superimposed on the top of the floating gate structure. The first control gate 306 is formed by superimposing a first gate dielectric layer 3061 and a first gate conductive material layer 3062.

[0109] The second control gate 305 is disposed on the surface of the lightly doped drain region 3022 between the drain region 310 and the second side of the floating gate structure; the second control gate 305 is formed by stacking a second gate dielectric layer 3051 and a second gate conductive material layer 3052.

[0110] An inter-gate dielectric layer 307 is provided between the first control gate 306 and the second control gate 305.

[0111] The first control gate 306 is used to control the read operation of the semi-floating gate device;

[0112] The second control gate 305 is used to control the erase and write operations of the semi-floating gate device.

[0113] In a second embodiment of the present invention, the floating gate structure further includes a gate trench, the bottom surface of which extends into the first well region 301. The lightly doped source region 3021 is located above the first well region 301 and contacts a first side surface of the gate trench; the lightly doped drain region 3022 is located above the first well region 301 and contacts a second side surface of the gate trench. In other embodiments, the floating gate structure can also be a planar gate, in which case the gate junction trench is not required.

[0114] The floating gate dielectric layer 303 covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region 3022 outside the gate trench.

[0115] The floating gate material layer 304 completely fills the gate trench on which the floating gate dielectric layer 303 is formed and extends to the floating gate dielectric layer 303 and the dielectric layer window outside the gate trench.

[0116] The material of the floating gate dielectric layer 303 includes an oxide layer.

[0117] The floating gate material layer 304 is a polycrystalline silicon layer doped with a second conductivity type.

[0118] In the second embodiment of the present invention, the first gate dielectric layer 3061 is an oxide layer, and the first gate conductive material layer 3062 is a polysilicon layer.

[0119] The second gate dielectric layer 3051 is made of a high dielectric constant material layer, and the second gate conductive material layer 3052 is made of a metal gate. Compared with the first embodiment of the present invention, the second control gate 305 of the second embodiment of the present invention is a high dielectric constant metal gate (HKMG), and the use of HKMG can reduce the gate leakage current of the second control gate 302.

[0120] The first side and the second side of the first control gate 306 are aligned with the first side and the second side of the floating gate structure, respectively.

[0121] The first side of the second control gate 305 and the second side of the first control gate 306 are spaced apart by the inter-gate dielectric layer 307.

[0122] The leak area 310 and the second side of the second control gate 305 are self-aligned.

[0123] Sidewalls 308 are formed on the first side of the first control gate 306 and the second side of the second control gate 305.

[0124] The top surface of the first control gate 306 is flush with the top surface of the second control gate 305.

[0125] The lightly doped source region 3021 and the lightly doped drain region 3022 are both composed of a second well region 302 formed on the surface of the first well region 301 and doped with a first conductivity type. The gate trench passes through the second well region 302 and divides the second well region 302 into the lightly doped source region 3021 and the lightly doped drain region 3022.

[0126] The ion implantation dose for the second conductivity type doped in the first well region 301 is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 230keV.

[0127] From top to bottom, the doping concentration of the first well region 301 decreases in a gradient.

[0128] The ion implantation dose for the first conductivity type doped in the second well region 302 is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

[0129] The second conductivity type doped ion implantation dose of the floating gate material layer 304 is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

[0130] In the second embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0131] The third embodiment of the present invention is a semi-floating gate device:

[0132] like Figure 4 The diagram shown is a structural schematic of a semi-floating gate device according to a third embodiment of the present invention; the semi-floating gate device according to the third embodiment of the present invention includes:

[0133] A lightly doped source region 4021 of a first conductivity type, a lightly doped drain region 4022 of a first conductivity type, and a first well region 401 of a second conductivity type are formed in a semiconductor substrate.

[0134] In the third embodiment of the present invention, the semiconductor substrate is a silicon substrate.

[0135] A floating gate structure covers a selected area of ​​the first well region 401, and the surface of the first well region 401 covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region 4021 and the lightly doped drain region 4022.

[0136] The floating grid structure includes a floating grid dielectric layer 403, a dielectric layer window, and a floating grid material layer 404.

[0137] The floating gate structure also covers the surface of the lightly doped drain region 4022, and the dielectric layer window is located on the surface of the lightly doped drain region 4022. At the dielectric layer window, the floating gate material layer 404 and the lightly doped drain region 4022 are in contact and form a PN structure.

[0138] A source region 409 of a first conductivity type is formed in a selected area on the surface of the lightly doped source region 4021.

[0139] A heavily doped drain region 410 of a first conductivity type is formed in a selected area on the surface of the lightly doped drain region 4022.

[0140] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0141] The source region 409 and the first side of the floating grid structure are self-aligned.

[0142] The first control gate 406 is superimposed on the top of the floating gate structure. The first control gate 406 is formed by superimposing a first gate dielectric layer 4061 and a first gate conductive material layer 4062.

[0143] The second control gate 405 is disposed on the surface of the lightly doped drain region 4022 between the drain region 410 and the second side of the floating gate structure; the second control gate 405 is formed by stacking a second gate dielectric layer 4051 and a second gate conductive material layer 4052.

[0144] An inter-gate dielectric layer 407 is provided between the first control gate 406 and the second control gate 405.

[0145] The first control gate 406 is used to control the read operation of the semi-floating gate device;

[0146] The second control gate 405 is used to control the erase and write operations of the semi-floating gate device.

[0147] In a third embodiment of the present invention, the floating gate structure further includes a gate trench, the bottom surface of which extends into the first well region 401. The lightly doped source region 4021 is located above the first well region 401 and contacts a first side surface of the gate trench; the lightly doped drain region 4022 is located above the first well region 401 and contacts a second side surface of the gate trench. In other embodiments, the floating gate structure can also be a planar gate, in which case the gate junction trench is not required.

[0148] The floating gate dielectric layer 403 covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region 4022 outside the gate trench.

[0149] The floating gate material layer 404 completely fills the gate trench on which the floating gate dielectric layer 403 is formed and extends to the floating gate dielectric layer 403 and the dielectric layer window outside the gate trench.

[0150] The material of the floating gate dielectric layer 403 includes an oxide layer.

[0151] The floating gate material layer 404 is a polycrystalline silicon layer doped with a second conductivity type.

[0152] In the third embodiment of the present invention, the first gate dielectric layer 4061 is a high dielectric constant material layer, and the first gate conductive material layer 4062 is a metal gate. Compared with the first embodiment of the present invention, the first control gate 405 in the third embodiment of the present invention is an HKMG, which can increase the charge storage capacity of the floating gate structure.

[0153] The first gate dielectric layer 4061 is an oxide layer, and the first gate conductive material layer 4062 is a polysilicon layer.

[0154] The first side and the second side of the first control gate 406 are aligned with the first side and the second side of the floating gate structure, respectively.

[0155] The first side of the second control gate 405 and the second side of the first control gate 406 are spaced apart by the inter-gate dielectric layer 407.

[0156] The leak area 410 and the second side of the second control gate 405 are self-aligned.

[0157] Sidewalls 408 are formed on the first side of the first control gate 406 and the second side of the second control gate 405.

[0158] The top surface of the first control gate 406 and the top surface of the second control gate 405 are flush.

[0159] The lightly doped source region 4021 and the lightly doped drain region 4022 are both composed of a second well region 402 formed on the surface of the first well region 401 and doped with a first conductivity type. The gate trench passes through the second well region 402 and divides the second well region 402 into the lightly doped source region 4021 and the lightly doped drain region 4022.

[0160] The ion implantation dose for the second conductivity type doped in the first well region 401 is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 240keV.

[0161] From top to bottom, the doping concentration of the first well region 401 decreases in a gradient.

[0162] The ion implantation dose for the first conductivity type doped in the second well region 402 is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

[0163] The second conductivity type doped ion implantation dose of the floating gate material layer 404 is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

[0164] In the third embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0165] The fourth embodiment of the present invention is a semi-floating gate device:

[0166] like Figure 5 The diagram shown is a structural schematic of a semi-floating gate device according to a fourth embodiment of the present invention; the semi-floating gate device according to the fourth embodiment of the present invention includes:

[0167] A lightly doped source region 5021 of the first conductivity type, a lightly doped drain region 5022 of the first conductivity type, and a first well region 501 of the second conductivity type are formed in a semiconductor substrate.

[0168] In the fourth embodiment of the present invention, the semiconductor substrate is a silicon substrate.

[0169] A floating gate structure covers a selected area of ​​the first well region 501, and the surface of the first well region 501 covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region 5021 and the lightly doped drain region 5022.

[0170] The floating grid structure includes a floating grid dielectric layer 503, a dielectric layer window, and a floating grid material layer 504.

[0171] The floating gate structure also covers the surface of the lightly doped drain region 5022, and the dielectric layer window is located on the surface of the lightly doped drain region 5022. At the dielectric layer window, the floating gate material layer 504 and the lightly doped drain region 5022 are in contact and form a PN structure.

[0172] A source region 509 heavily doped with a first conductivity type is formed in a selected area on the surface of the lightly doped source region 5021.

[0173] A heavily doped drain region 510 of a first conductivity type is formed in a selected area on the surface of the lightly doped drain region 5022.

[0174] The floating gate structure has a first side and a second side on the surface of the semiconductor substrate.

[0175] The source region 509 and the first side of the floating grid structure are self-aligned.

[0176] The first control gate 506 is superimposed on the top of the floating gate structure. The first control gate 506 is formed by superimposing a first gate dielectric layer 5061 and a first gate conductive material layer 5062.

[0177] The second control gate 505 is disposed on the surface of the lightly doped drain region 5022 between the drain region 510 and the second side of the floating gate structure; the second control gate 505 is formed by stacking a second gate dielectric layer 5051 and a second gate conductive material layer 5052.

[0178] An inter-gate dielectric layer 507 is provided between the first control gate 506 and the second control gate 505.

[0179] The first control gate 506 is used to control the read operation of the semi-floating gate device;

[0180] The second control gate 505 is used to control the erase and write operations of the semi-floating gate device.

[0181] In the fourth embodiment of the present invention, the floating gate structure further includes a gate trench, the bottom surface of which enters the first well region 501. The lightly doped source region 5021 is located above the first well region 501 and contacts the first side surface of the gate trench; the lightly doped drain region 5022 is located above the first well region 501 and contacts the second side surface of the gate trench. In other embodiments, the floating gate structure can also be a planar gate, in which case the gate junction trench is not required.

[0182] The floating gate dielectric layer 503 covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region 5022 outside the gate trench.

[0183] The floating gate material layer 504 completely fills the gate trench on which the floating gate dielectric layer 503 is formed and extends to the floating gate dielectric layer 503 and the dielectric layer window outside the gate trench.

[0184] The material of the floating gate dielectric layer 503 includes an oxide layer.

[0185] The floating gate material layer 504 is a polycrystalline silicon layer doped with a second conductivity type.

[0186] In the fourth embodiment of the present invention, the first gate dielectric layer 5061 is a high dielectric constant material layer, and the first gate conductive material layer 5062 is a metal gate. Compared with the first embodiment of the present invention, the first control gate 505 in the fourth embodiment of the present invention is an HKMG, which can increase the charge storage capacity of the floating gate structure.

[0187] The second gate dielectric layer 5051 is made of a high dielectric constant material layer, and the second gate conductive material layer 5052 is made of a metal gate. Compared with the first embodiment of the present invention, the second control gate 505 of the fourth embodiment of the present invention is a high dielectric constant metal gate (HKMG), and the use of HKMG can reduce the gate leakage current of the second control gate 502.

[0188] The first side and the second side of the first control gate 506 are aligned with the first side and the second side of the floating gate structure, respectively.

[0189] The first side of the second control gate 505 and the second side of the first control gate 506 are spaced apart by the inter-gate dielectric layer 507.

[0190] The leak area 510 and the second side of the second control gate 505 are self-aligned.

[0191] Sidewalls 508 are formed on the first side of the first control gate 506 and the second side of the second control gate 505.

[0192] The top surface of the first control gate 506 is flush with the top surface of the second control gate 505.

[0193] The lightly doped source region 5021 and the lightly doped drain region 5022 are both composed of a second well region 502 formed on the surface of the first well region 501 and doped with a first conductivity type. The gate trench passes through the second well region 502 and divides the second well region 502 into the lightly doped source region 5021 and the lightly doped drain region 5022.

[0194] The ion implantation dose for the second conductivity type doped in the first well region 501 is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 250keV.

[0195] From top to bottom, the doping concentration of the first well region 501 decreases in a gradient.

[0196] The ion implantation dose for the first conductivity type doped in the second well region 502 is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

[0197] The second conductivity type doped ion implantation dose of the floating gate material layer 504 is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

[0198] In the fourth embodiment of the present invention, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type can also be P-type and the second conductivity type can be N-type.

[0199] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A semi-floating gate device, characterized in that, include: A lightly doped source region of the first conductivity type, a lightly doped drain region of the first conductivity type, and a first well region of the second conductivity type are formed in a semiconductor substrate. A floating gate structure covers a selected area of ​​the first well region, and the surface of the first well region covered by the floating gate structure is used to form a conductive channel for electrically connecting the lightly doped source region and the lightly doped drain region; The floating grid structure includes a floating grid dielectric layer, a dielectric layer window, and a floating grid material layer; The floating gate structure also covers the surface of the lightly doped drain region, the dielectric layer window is located on the surface of the lightly doped drain region, and the floating gate material layer and the lightly doped drain region are in contact at the dielectric layer window to form a PN structure; A heavily doped source region of the first conductivity type is formed in a selected region on the surface of the lightly doped source region; A heavily doped drain region of the first conductivity type is formed in a selected region on the surface of the lightly doped drain region; The floating gate structure has a first side and a second side on the surface of the semiconductor substrate. The source region and the first side of the floating grid structure are self-aligned; The first control gate is superimposed on the top of the floating gate structure, and the first control gate is composed of a first gate dielectric layer and a first gate conductive material layer. The second control gate is disposed on the surface of the lightly doped drain region between the drain region and the second side of the floating gate structure; the second control gate is formed by stacking a second gate dielectric layer and a second gate conductive material layer. An inter-gate dielectric layer isolates the first control gate and the second control gate; The first control gate is used to control the readout operation of the semi-floating gate device; The second control gate is used to control the erase and write operations of the semi-floating gate device.

2. The semi-floating gate device as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

3. The semi-floating gate device as described in claim 1, characterized in that: The floating gate structure also includes a gate trench, the bottom surface of which enters the first well region, and the lightly doped source region is located above the first well region and in contact with the first side surface of the gate trench. The lightly doped drain region is located above the first well region and contacts the second side of the gate trench; The floating gate dielectric layer covers the bottom surface and sides of the gate trench and extends to the surface of the lightly doped drain region outside the gate trench; The floating gate material layer completely fills the gate trench on which the floating gate dielectric layer is formed and extends to the floating gate dielectric layer and the dielectric layer window outside the gate trench.

4. The semi-floating gate device as described in claim 3, characterized in that: The material of the floating gate dielectric layer includes an oxide layer; The floating gate material layer is a polycrystalline silicon layer doped with a second conductivity type.

5. The semi-floating gate device as described in claim 1 or 4, characterized in that: The first gate dielectric layer is an oxide layer, and the first gate conductive material layer is a polysilicon layer; Alternatively, the first gate dielectric layer may be a high dielectric constant material layer, and the first gate conductive material layer may be a metal gate.

6. The semi-floating gate device as described in claim 1 or 4, characterized in that: The second gate dielectric layer is an oxide layer, and the second gate conductive material layer is a polysilicon layer; Alternatively, the second gate dielectric layer may be a high dielectric constant material layer, and the second gate conductive material layer may be a metal gate.

7. The semi-floating gate device as claimed in claim 1, characterized in that: The first side and the second side of the first control gate are aligned with the first side and the second side of the floating gate structure, respectively.

8. The semi-floating gate device as claimed in claim 7, characterized in that: The first side of the second control gate and the second side of the first control gate are separated by the inter-gate dielectric layer; The leak area and the second side of the second control gate are self-aligned.

9. The semi-floating gate device as claimed in claim 8, characterized in that: Sidewalls are formed on the first side of the first control gate and the second side of the second control gate.

10. The semi-floating gate device as claimed in claim 8, characterized in that: The top surface of the first control gate and the top surface of the second control gate are flush.

11. The semi-floating gate device as claimed in claim 4, characterized in that: Both the lightly doped source region and the lightly doped drain region are composed of a second well region doped with a first conductivity type formed on the surface of the first well region. The gate trench passes through the second well region, dividing the second well region into the lightly doped source region and the lightly doped drain region.

12. The semi-floating gate device as claimed in claim 11, characterized in that: The ion implantation dose for the second conductivity type doped in the first well region is 0.25e14cm. -2 ~2.50e14cm -2 The ion implantation energy is 55keV to 220keV.

13. The semi-floating gate device as claimed in claim 12, characterized in that: From top to bottom, the doping concentration of the first well region decreases in a gradient.

14. The semi-floating gate device as claimed in claim 11, characterized in that: The ion implantation dose for the first conductivity type doped in the second well region is 4.5e12cm. -2 ~2.50e13cm -2 The ion implantation energy is 45keV to 85keV.

15. The semi-floating gate device as claimed in claim 11, characterized in that: The second conductivity type doping ion implantation dose of the floating gate material layer is 5.00e12cm. -2 ~3.60e13cm -2 The ion implantation energy is 2keV to 12keV.

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