Superconducting Circuit, Quantum Chip and Preparation Method of Superconducting Circuit

Abstract

The present application discloses a superconducting circuit, a quantum chip and a preparation method of the superconducting circuit, belonging to the technical field of quantum computing. The superconducting circuit includes: a first superconductor located on a substrate; a barrier layer located on one side surface of the first superconductor, the side surface being perpendicular to the substrate; and a second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor. In the structure of the present application, since the barrier layer is located on a side surface of the first superconductor perpendicular to the substrate, the size of the barrier layer can be adjusted by adjusting the thickness of the first superconductor, overcoming the problem in the prior art that the size of the barrier layer can only be adjusted by the line widths of the first superconductor and / or the second superconductor, thereby reducing the requirement for line width accuracy.

Description

Technical Field

[0001] This application belongs to the field of quantum information, especially the field of quantum computing technology. In particular, this application relates to a superconducting circuit, a quantum chip, and a method for preparing a superconducting circuit. Background Art

[0002] The core part of a quantum chip is a superconducting circuit with the Josephson effect, also known as a Josephson junction. A common structural form of this superconducting circuit is a three-layer stack structure of a superconducting layer - barrier layer - superconducting layer formed in sequence on a substrate, as shown in Figure 1 shown. In order to obtain a relatively ideal qubit frequency, the line width of this superconducting circuit must be controlled to the nanometer level. However, the nanometer-level line width requires a high line width accuracy for process equipment. For example, the line width accuracy of the exposure equipment needs to reach the nanometer level to prepare an ideal mask pattern, and then prepare a superconducting circuit with this line width. Therefore, it is urgent to propose a structure of a superconducting circuit that is easy to prepare to reduce the requirement for the line width accuracy of process equipment. Summary of the Invention

[0003] The purpose of this application is to provide a superconducting circuit, a quantum chip, and a method for preparing a superconducting circuit to solve the deficiencies in the prior art.

[0004] One aspect of this application provides a superconducting circuit, which includes:

[0005] A first superconductor located on a substrate; a barrier layer on one side of the first superconductor, the side being perpendicular to the substrate; and a second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer, and the first superconductor.

[0006] The superconducting circuit as described above further includes an insulating isolation layer on the first superconductor, the insulating isolation layer being adjacent to the barrier layer, and the second superconductor covering the insulating isolation layer.

[0007] The superconducting circuit as described above, wherein both the barrier layer and the insulating isolation are oxide layers formed on the first superconductor.

[0008] The superconducting circuit as described above forms at least two of the second superconductors.

[0009] The superconducting circuit as described above, wherein each of the second superconductors has a different line width.

[0010] The superconducting circuit according to any one of the above, wherein the line width of the second superconductor is 1.5 μm or more, and the thickness of the first superconductor in the direction perpendicular to the substrate is 10 nm to 30 nm.

[0011] The superconducting circuit described in any of the above, wherein the thickness of the barrier layer is 1 nm to 3 nm, and the thickness of the insulating isolation is 4 nm to 6 nm.

[0012] The second aspect of the present application provides a quantum chip, including the superconducting circuit described above.

[0013] The quantum chip described above further includes: a capacitor plate, the capacitor plate is connected to the first superconductor; and a ground plate, the ground plate is connected to the second superconductor.

[0014] The quantum chip described above further includes: a first capacitor plate, the first capacitor plate is connected to the first superconductor; and a second capacitor plate, the second capacitor plate is connected to the second superconductor.

[0015] The quantum chip described in any of the above further includes a signal transmission line located on another substrate, and the signal transmission line is coupled to the superconducting circuit.

[0016] The third aspect of the present application provides a method for manufacturing a superconducting circuit, the manufacturing method including:

[0017] Forming a first superconductor on a substrate; forming a barrier layer on one side surface of the first superconductor, the side surface being perpendicular to the substrate; and forming a second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor.

[0018] The manufacturing method described above, wherein, before the step of forming the barrier layer on one side surface of the first superconductor, further includes: removing the natural oxide film on one side surface of the first superconductor.

[0019] The manufacturing method described above further includes: forming an insulating isolation layer on the first superconductor, the insulating isolation layer is adjacent to the barrier layer, and the second superconductor covers the insulating isolation layer.

[0020] The manufacturing method described above, the step of forming the insulating isolation layer on the first superconductor includes: repeating the coating and oxidation steps multiple times to generate the insulating isolation layer, and the coating and oxidation steps include: forming a superconducting metal material with a thickness of 0.1 nm to 1 nm on the first superconductor and oxidizing the superconducting metal material.

[0021] The manufacturing method described above, wherein at least two second superconductors are formed.

[0022] The manufacturing method described above, wherein each of the second superconductors has a different line width.

[0023] The preparation method described in any one of the above, wherein the line width of the second superconductor is 1.5 μm or more, and the thickness of the first superconductor in the direction perpendicular to the substrate is 10 nm to 30 nm.

[0024] The preparation method described in any one of the above, wherein the thickness of the barrier layer is 1 nm to 3 nm, and the thickness of the insulating isolation is 4 nm to 6 nm.

[0025] Compared with the prior art, a superconducting circuit provided by the present application includes: a first superconductor located on a substrate; a barrier layer located on one side surface of the first superconductor, the side surface being perpendicular to the substrate; and a second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor. In the structure of this solution, since the barrier layer is located on one side surface of the first superconductor perpendicular to the substrate, the area of the barrier layer can be adjusted by adjusting the thickness of the first superconductor, overcoming the problem in the prior art that the area of the barrier layer can only be adjusted according to the line width of the first superconductor and / or the second superconductor, thereby reducing the requirement for line width accuracy.

[0026] Compared with the prior art, a preparation method of a superconducting circuit provided by the present application includes: forming a first superconductor on a substrate; forming a barrier layer on one side surface of the first superconductor, the side surface being perpendicular to the substrate; and forming a second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor. In the solution of the present application, since the barrier layer is formed on one side surface of the first superconductor, the area of the barrier layer can be adjusted by adjusting the thickness of the first superconductor, overcoming the problem in the prior art that the area of the barrier layer can only be adjusted according to the line width of the first superconductor and / or the second superconductor, thereby reducing the requirement for line width accuracy. Description of the Drawings

[0027] Figure 1 It is a schematic structural diagram of a Josephson junction in the related art;

[0028] Figure 2 It is a schematic diagram of a partial structure of a superconducting circuit provided by an embodiment of the present application;

[0029] Figure 3 It is a schematic diagram of a partial structure of a quantum chip provided by an embodiment of the present application;

[0030] Figure 4 It is a schematic structural diagram of another quantum chip provided by an embodiment of the present application;

[0031] Figure 5 It is a flowchart of a preparation method of a superconducting circuit provided by an embodiment of the present application.

[0032] Description of reference numerals:

[0033] 1-superconducting circuit, 11-first superconductor, 12-barrier layer, 13-second superconductor, 14-insulating isolation layer, 2-capacitor plate, 3-grounding plate, 4-first capacitor plate, 5-second capacitor plate. DETAILED DESCRIPTION

[0034] The following detailed description is illustrative only and is not intended to limit the application or use of the embodiments and / or embodiments. In addition, it is not intended to be bound by any explicit or implicit information presented in the previous "background technology" or "invention content" section or "specific implementation" section.

[0035] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, one or more embodiments are now described with reference to the accompanying drawings, wherein similar reference numerals throughout the text are used to refer to similar components. In the following description, for the purpose of explanation, many specific details are set forth in order to provide a more thorough understanding of one or more embodiments. However, it is clear that in various cases, one or more embodiments can be practiced without these specific details, and the various embodiments can be combined and referenced to each other without contradiction.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] In addition, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can also be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can also be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0038] According to different physical systems used to construct qubits, the physical implementation of qubits includes superconducting quantum circuits, semiconductor quantum dots, ion traps, diamond vacancies, topological qubits, photons, etc.

[0039] Superconducting quantum computing is currently the fastest and best-developed method for realizing solid-state quantum computing. Since the energy level structure of superconducting quantum circuits can be regulated by applying external electromagnetic signals, the controllability of circuit design and customization is strong. At the same time, thanks to the existing mature integrated circuit technology, superconducting quantum circuits have scalability that is difficult to match by many quantum physical systems.

[0040] In the superconducting quantum computing system, the core part of the quantum chip is a superconducting circuit with the Josephson effect, also called a Josephson junction. Figure 1 For the structural schematic diagram of the Josephson junction in related technologies, see Figure 1 As shown, a common structural form of this superconducting circuit is a three-layer stacked structure of superconducting layer - barrier layer - superconducting layer formed on a substrate. The thickness of the barrier layer is generally on the nanometer scale and plays a role of weak connection between the two superconducting layers. When the temperature is low enough, the superconducting layer can exchange paired electrons through the barrier layer at a very fast speed. The normal temperature resistance of this superconducting circuit affects the frequency of the qubit, and the size of the superconducting circuit determines the normal temperature resistance. Therefore, in order to obtain a relatively ideal qubit frequency (for example, 4 - 8 GHz), the line width of the superconducting circuit of this structure must be controlled to the nanometer level. However, the nanometer-level line width requires a high line width accuracy for process equipment. For example, the line width accuracy of the exposure equipment reaches the nanometer level to prepare an ideal mask pattern, and then prepare a superconducting circuit with this line width. Specifically, currently, the main method for preparing this three-layer stacked structure in a quantum chip is to prepare a mask pattern by electron beam exposure and then perform oblique evaporation coating. However, the rate of electron beam exposure is slow. But if common optical exposure means are used, since the exposure accuracy is generally at the micron level, the prepared pattern size is at the micron level, and the normal temperature resistance of the superconducting circuit in the micron-level junction area is too small, which causes the performance parameters such as the frequency of the qubit to deviate seriously.

[0041] Therefore, the present application provides a superconducting circuit, a quantum chip, and a preparation method of the superconducting circuit to solve the deficiencies in the prior art. The structure of the superconducting circuit proposed in the present application has a lower requirement for the line width accuracy of process equipment and is convenient for process preparation.

[0042] Figure 2 FIG. is a structural schematic diagram of a superconducting circuit provided by an embodiment of the present application.

[0043] Combined with Figure 2 and with reference for comparison to Figure 1As shown in the figure, a superconducting circuit 1 provided by an embodiment of the present application includes: a first superconductor 11 located on a substrate; a barrier layer 12 located on one side surface of the first superconductor 11, the side surface being perpendicular to the substrate, and the thickness of the barrier layer 12 ≤ the coherence length of Cooper electron pairs; and a second superconductor 13 covering the barrier layer 12, and a structure with Josephson effect is formed among the second superconductor 13, the barrier layer 12, and the first superconductor 11.

[0044] Compared with the prior art, in the structure of a superconducting circuit 1 provided by the present application, the barrier layer 12 is located on a side surface of the first superconductor 11 perpendicular to the substrate. Therefore, the area size of the barrier layer 12 is not limited by the linewidth accuracy. This structure can adjust the area of the barrier layer 12 by adjusting the thickness of the first superconductor 11, thereby overcoming the problem in the prior art that the area size of the barrier layer 12 can only be adjusted by designing the linewidths of the first superconductor 11 and / or the second superconductor 13, and further reducing the requirement for linewidth accuracy. During the process implementation, a mask pattern can be prepared by using a micron-level exposure device (for example, laser direct writing), and then a first superconductor 11 with a certain thickness is deposited by using the mask pattern. After forming the barrier layer 12 on the side surface of the first superconductor 11, a second superconductor 13 is deposited to cover the barrier layer 12. In this way, a superconducting circuit 1 with relevant performance parameters (for example, normal temperature resistance) meeting the design requirements can be obtained, and the long electron beam exposure process can be avoided, and the requirement for the linewidth accuracy of the prepared mask pattern is not high.

[0045] In some embodiments of the present application, the superconducting circuit 1 further includes an insulating isolation layer 14 located on the first superconductor 11. The insulating isolation layer 14 is adjacent to the barrier layer 12, and the second superconductor 13 covers the insulating isolation layer 14. The insulating isolation layer 14 can be formed on other surfaces of the first superconductor 11. For example, it can be formed on a surface parallel to the substrate and another side surface perpendicular to the substrate. This facilitates the preparation of the overlapping second superconductor 13 by oblique evaporation. Due to the isolation effect of the insulating isolation layer 14, unnecessary contact between the second superconductor 13 and the first superconductor 11 is avoided, which affects the performance of the superconducting circuit 1, such as the normal temperature resistance.

[0046] In some embodiments of the present application, both the barrier layer 12 and the insulating isolation layer 14 are oxide layers formed on the first superconductor 11. The oxide layer can be a metal oxide layer or a non-metal oxide layer, as long as it can play an insulating isolation role. Exemplarily, it can be an oxide of a superconducting metal. For example, it can be an oxide of aluminum (Al), that is, an aluminum oxide layer (Al2O3).

[0047] In some other embodiments of the present application, at least two of the second superconductors 13 are formed in the superconducting circuit 1. The two second superconductors 13 are parallel to each other and form corresponding Josephson-effect structures with the first superconductor 11 and the barrier layer 12 located on one side of the first superconductor 11. In one embodiment, each of the second superconductors 13 has a different line width to obtain an asymmetric structure, and the asymmetric structure has at least two magnetic flux insensitive points during quantum computing. Exemplarily, the requirements for the line widths of the first superconductor 11 and the second superconductor can be reduced by controlling the thickness of the first superconductor 11. The line widths of the first superconductor 11 and the second superconductor 13 can be 1.5 μm or more, and the thickness of the first superconductor 11 in the direction perpendicular to the substrate can be 10 nm to 30 nm. Exemplarily, it can be 10 nm, 11 nm, 13 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 27 nm, 30 nm.

[0048] In still some other embodiments of the present application, the thickness of the barrier layer 12 can be 1 nm to 3 nm. The thickness of the barrier layer 12 is the dimension in the direction perpendicular to the side surface, and the thickness of the barrier layer 12 defines the spacing between the first superconductor 11 and the second superconductor 12. Exemplarily, it can be 1 nm, 2 nm, 3 nm. The thickness of the insulating isolation layer 14 can be 4 nm to 6 nm. Exemplarily, it can be 4 nm, 5 nm, 6 nm.

[0049] The second aspect of the embodiments of the present application provides a quantum chip, including the superconducting circuit 1 as described above.

[0050] Figure 3 It is a schematic diagram of a partial structure of a quantum chip provided by the embodiments of the present application.

[0051] In some embodiments of the present application, the quantum chip further includes: a capacitor plate 4, which is connected to the first superconductor 11; and a ground plate 5, which is connected to the second superconductor 13.

[0052] Figure 4 It is a schematic diagram of a partial structure of another quantum chip provided by the embodiments of the present application.

[0053] In some embodiments of the present application, the quantum chip further includes: a first capacitor plate 4, which is connected to the first superconductor 11; and a second capacitor plate 5, which is connected to the second superconductor 13.

[0054] In some embodiments of the present application, the quantum chip further includes a signal transmission line located on another substrate, and the signal transmission line is coupled to the superconducting circuit 1.

[0055] In the embodiments of the present application, the first capacitor plate 4, the second capacitor plate 5, and the ground plate (GND) may be formed of a superconductor material that exhibits superconducting characteristics at a temperature equal to or lower than the critical temperature, such as aluminum, niobium, titanium nitride, etc. Specifically, in implementation, it is not limited to these several types. Any material that exhibits superconducting characteristics at a temperature equal to or lower than the critical temperature can be used to form the first capacitor plate, the second capacitor plate, and the ground plate (GND).

[0056] It should be noted here that: the superconducting circuit in the above quantum chip is similar to the above structure and has the same beneficial effects as the above superconducting circuit embodiments, so it will not be elaborated here. For the technical details not disclosed in the quantum chip embodiments of the present application, those skilled in the art can refer to the description of the above superconducting circuit for understanding. To save space, it will not be elaborated here.

[0057] It should be noted that Figure 3 and Figure 4 schematically shows some components or structures on the quantum chip. For example, the positions and shape configurations of the first capacitor plate 4, the second capacitor plate 5, and the ground plate (GND), etc. Other components or structures are not shown.

[0058] Figure 5 It is a flowchart of a preparation method of a superconducting circuit provided by an embodiment of the present application.

[0059] In the third aspect of the embodiments of the present application, a preparation method of a superconducting circuit is provided. The preparation method includes steps S501 to S503, where:

[0060] Step S501: Form a first superconductor 11 on a substrate;

[0061] Step S502: Form a barrier layer 12 on one side surface of the first superconductor 11, the side surface being perpendicular to the substrate, and the thickness of the barrier layer 12 ≤ the coherence length of Cooper electron pairs; and

[0062] Step S503: Form a second superconductor 13 covering the barrier layer 12, and a structure with Josephson effect is formed among the second superconductor 13, the barrier layer 12, and the first superconductor 11.

[0063] Compared with the prior art, the preparation method of the superconducting circuit 1 provided by the present application forms the barrier layer 12 on one side of the first superconductor 11. According to the thickness of the first superconductor 11 and the width of the second superconductor 13, the area size of the barrier layer 12 is defined, thereby defining the size of the weakly connected region between the first superconductor 11 and the second superconductor 13. Therefore, the area of the barrier layer 12 can be adjusted by adjusting the thickness of the first superconductor 11, overcoming the problem in the prior art that the area of the barrier layer 12 can only be adjusted by the line widths of the first superconductor 11 and / or the second superconductor 13, thus reducing the requirement for line width accuracy. For example, a mask pattern can be prepared by a micron-level optical exposure device, and then a material is deposited under the mask pattern to form the first superconductor 11, and the formation thickness of the first superconductor 11 is controlled according to the line width of the mask pattern. Then, a barrier layer 12 is formed on one side of the first superconductor 11, and a material is deposited again to form the second superconductor 13 to cover the barrier layer, so that the first superconductor 11, the barrier layer 12, and the second superconductor 13 form a structure with the Josephson effect. In this process, the requirement for the line width of the prepared mask pattern is reduced by regulating the thickness of the first superconductor 11.

[0064] In some embodiments of the present application, before the step of forming the barrier layer 12 on one side of the first superconductor 11, it further includes: removing the natural oxide film on one side of the first superconductor 11 to prevent the natural oxide film from affecting the formation quality of the barrier layer 12 and thus affecting the performance parameters of the obtained superconducting circuit 1. The step of forming the barrier layer 12 on one side of the first superconductor 11 includes: oxidizing the first superconductor 11 in an oxygen pressure atmosphere of 0.5 torr for 20 minutes.

[0065] In some embodiments of the present application, the preparation method further includes: forming an insulating isolation layer 14 on the first superconductor 11, the insulating isolation layer 14 being adjacent to the barrier layer 12, and the second superconductor 13 covering the insulating isolation layer 14. The insulating isolation layer 14 can be formed on other surfaces of the first superconductor 11.

[0066] In some embodiments of the present application, the step of forming the insulating isolation layer 14 on the first superconductor 11 includes: repeatedly performing a coating and oxidation step to generate the insulating isolation layer 14, and the coating and oxidation step includes: forming a superconducting metal material with a thickness of 0.1 to 1 nm on the first superconductor, and oxidizing the superconducting metal material to generate an oxide of the superconducting metal material. Exemplarily, the coating and oxidation step is repeated six times. In each coating and oxidation step, first, 0.5 nm of aluminum (Al) is formed on one surface of the first superconductor 11 parallel to the substrate and on the other side surface of the first superconductor 11 perpendicular to the substrate, and then it is oxidized in an oxygen pressure atmosphere of 0.9 torr for 20 minutes. After repeatedly performing the coating and oxidation step, the thickness of the oxide is preferably accumulated, ensuring that the thickness of the obtained insulating isolation layer 14 is greater than the coherence length of Cooper electron pairs, so as to play an insulating and isolating role, and no tunneling effect will occur between the first superconductor 11, the insulating isolation layer 14, and the second superconductor 13. Therefore, the tunneling effect only occurs through the side barrier layer 12. If only one coating and oxidation step is performed, no matter how thick the formed aluminum is or how long the oxidation time is, the thickness of the oxide is not conducive to accumulation and cannot achieve a good insulating and isolating effect. This is mainly because when the surface of the formed aluminum is oxidized, it will have a certain hindrance to the oxidation process of the internal aluminum. It should be noted that in order to avoid the influence of the coating and oxidation step on the barrier layer 12, when forming a superconducting metal material with a thickness of 0.1 to 1 nm on the first superconductor, directional coating can be used to avoid the formation of superconducting metal material on the barrier layer 12 during this process, thereby avoiding the increase in the thickness of the oxide on the barrier layer 12 and affecting the tunneling effect.

[0067] In some embodiments of the present application, at least two second superconductors 13 are formed. In one embodiment, each of the second superconductors 13 has a different line width to obtain an asymmetric structure, and the asymmetric structure has at least two magnetic flux insensitive points during quantum computing. Exemplarily, the line width of the second superconductor 13 can be 1.5 μm or more, and the thickness of the first superconductor 11 in the direction perpendicular to the substrate can be 10 nm to 30 nm. Exemplarily, it can be 10 nm, 11 nm, 13 nm, 15 nm, 18 nm, 20 nm, 22 nm, 25 nm, 27 nm, 30 nm.

[0068] In still some embodiments of the present application, the thickness of the barrier layer 12 is 1 nm to 3 nm. Exemplarily, it can be 1 nm, 2 nm, 3 nm, and the thickness of the insulating isolation layer 14 is 4 nm to 6 nm. Exemplarily, it can be 4 nm, 5 nm, 6 nm.

[0069] The preparation method of the superconducting circuit provided by this application may first form a mask on a substrate, and then form crossed first deposition windows and second deposition windows on the mask. The first deposition window exposes a first area on the substrate, and the second deposition window exposes a second area on the substrate. The first area and the second area cross each other. Among them, the first area is used to deposit a first superconductor 11, and the second area is used to deposit a second superconductor 13. Then, after directionally depositing a coating in one direction to form the first superconductor 11 in the first area, the natural oxide film on the first superconductor 11 is removed by IBE, and then oxidation is immediately carried out in an atmosphere of a certain oxygen pressure to obtain a barrier layer 12 on one side surface of the first superconductor 11. Immediately afterwards, the coating oxidation steps are repeated on the other side surface of the first superconductor 11 and on the surface parallel to the substrate. Then, directionally depositing a coating in another direction to form the second superconductor 13 in the second area. Since the first deposition window and the second deposition window cross each other, the formed second superconductor covers the barrier layer. Finally, a Josephson effect exists between the obtained second superconductor 13, the barrier layer 12, and the first superconductor 11. The insulating isolation layer 14 formed by the oxides accumulated multiple times on the other side surface of the first superconductor 11 and on the surface parallel to the substrate during the coating oxidation steps can block the quantum tunneling effect. In addition, it should be noted that directional deposition can deposit materials in the required position areas and prevent other areas from being deposited with materials.

[0070] In the embodiments of this application, the preparation of the superconducting circuit may require depositing one or more materials, such as superconductors, dielectrics, and / or metals. Depending on the materials selected, these materials can be deposited using deposition processes such as chemical vapor deposition, physical vapor deposition (e.g., evaporation or sputtering), or epitaxial techniques, as well as other deposition processes. The preparation process of a quantum chip described in the embodiments of this application may require removing one or more materials from the device during the manufacturing process. Depending on the materials to be removed, the removal process may include, for example, wet etching techniques, dry etching techniques, or lift-off processes. Known lithographic techniques (e.g., photolithography or electron beam lithography) can be used to pattern the materials forming the circuit elements described herein.

[0071] The structure, features, and effects of this application have been described in detail based on the embodiments shown in the drawings. The above are only the preferred embodiments of this application, but this application is not limited to the scope defined by the drawings. Any changes made according to the concept of this application, or equivalent embodiments modified into equivalent changes, should still be within the protection scope of this application as long as they do not exceed the spirit covered by the description and the drawings.

Claims

1. A superconducting circuit, characterized in that, Comprising: A first superconductor located on a substrate; A barrier layer located on one side surface of the first superconductor, the side surface being perpendicular to the substrate, the barrier layer being an oxide layer formed by oxidizing the first superconductor, and the thickness of the barrier layer being less than the coherence length of Cooper electron pairs; And A second superconductor covering the barrier layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor; An insulating isolation layer located on the first superconductor, the insulating isolation layer being adjacent to the barrier layer, and the second superconductor covering the insulating isolation layer, the insulating isolation layer being an oxide layer formed by repeatedly performing a coating and oxidation step on the surface of the oxidized first superconductor parallel to the substrate, the coating and oxidation step including: directionally coating to form a superconducting metal material with a thickness of 0.1 - 1 nm on a surface of the first superconductor parallel to the substrate, and oxidizing the superconducting metal material to generate an oxide of the superconducting metal material, and the thickness of the insulating isolation layer being greater than the coherence length of Cooper electron pairs.

2. The superconducting circuit according to claim 1, characterized in that, At least two of the second superconductors are formed.

3. The superconducting circuit according to claim 2, characterized in that, Each of the second superconductors has a different line width.

4. The superconducting circuit according to any one of claims 1 to 3, characterized in that, The line width of the second superconductor is 1.5 μm or more, and the thickness of the first superconductor in the direction perpendicular to the substrate is 10 nm - 30 nm.

5. The superconducting circuit according to any one of claims 1 to 3, characterized in that, The thickness of the barrier layer is 1 nm - 3 nm, and the thickness of the insulating isolation layer is 4 nm - 6 nm.

6. A quantum chip, characterized in that, Including the superconducting circuit according to claim 2 or 3.

7. The quantum chip according to claim 6, characterized in that, The quantum chip further comprises: A capacitor plate, the capacitor plate being connected to the first superconductor; and A ground plate, the ground plate being connected to the second superconductor.

8. The quantum chip according to claim 6, characterized in that, The quantum chip further comprises: A first capacitor plate, the first capacitor plate being connected to the first superconductor; and A second capacitor plate, the second capacitor plate being connected to the second superconductor.

9. The quantum chip according to any one of claims 7 to 8, characterized in that, The quantum chip further comprises a signal transmission line located on another substrate, the signal transmission line being coupled to the superconducting circuit.

10. A method for preparing a superconducting circuit, characterized in that, Comprising: Forming a first superconductor on a substrate; Oxidizing the first superconductor to form a barrier layer on one side surface of the first superconductor, the side surface being perpendicular to the substrate, and the thickness of the barrier layer being less than the coherence length of Cooper electron pairs; And Repeatedly performing a coating and oxidation step on the surface of the oxidized first superconductor parallel to the substrate to form an insulating isolation layer located on the first superconductor, the insulating isolation layer being adjacent to the barrier layer, and the thickness of the insulating isolation layer being greater than the coherence length of Cooper electron pairs, the coating and oxidation step including: directionally coating to form a superconducting metal material with a thickness of 0.1 - 1 nm on a surface of the first superconductor parallel to the substrate, and oxidizing the superconducting metal material; Forming a second superconductor covering the barrier layer and the insulating isolation layer, and there is a Josephson effect between the second superconductor, the barrier layer and the first superconductor.

11. The preparation method according to claim 10, characterized in that, Before the step of oxidizing the first superconductor to form a barrier layer on one side surface of the first superconductor, further comprising: Removing the natural oxide film on one side surface of the first superconductor.

12. The preparation method according to claim 10, characterized in that, At least two of the second superconductors are formed.

13. The preparation method according to claim 12, characterized in that, Each of the second superconductors has a different line width.

14. The preparation method according to any one of claims 10 to 13, characterized in that, The line width of the second superconductor is 1.5 μm or more, and the thickness of the first superconductor in the direction perpendicular to the substrate is 10 nm to 30 nm.

15. The preparation method according to any one of claims 10 to 13, characterized in that, The thickness of the barrier layer is 1 nm to 3 nm, and the thickness of the insulating isolation is 4 nm to 6 nm.

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