Method for manufacturing non-volatile memory cells

Abstract

The application discloses a manufacturing method of a non-volatile memory cell, comprising: forming a first dielectric layer on a first metal line; etching a first via hole directly to the first metal line; forming a bottom electrode in the first via hole; forming a resistance layer, a top electrode and a second dielectric layer on the bottom electrode and the first dielectric layer; oxidizing the resistance layer and the top electrode to form a side surface part covering the top electrode and the resistance layer; forming a side wall layer covering the second dielectric layer and the side surface part; forming a second via hole directly to the top electrode through the side wall layer and the second dielectric layer; and forming a contact lead in the second via hole, the width of the contact lead being less than the width between the outer side surfaces of the side surface part.

Description

[0001] This application is a divisional application of patent application No. 202080012917.7, filed on June 9, 2020, entitled "Non-volatile memory cell, non-volatile memory cell array and manufacturing method thereof".

[0002] Cross-references to related applications

[0003] This application claims priority to U.S. Application No. 16 / 669391, filed October 30, 2019, entitled "Non-volatile memory cell, non-volatile memory cell array, and method of manufacturing thereof," and U.S. Provisional Application No. 62 / 862307, filed June 17, 2019, entitled "Non-volatile memory cell, non-volatile memory cell array, and method of manufacturing thereof." U.S. Application No. 16 / 669391 claims priority and benefit to U.S. Provisional Application No. 62 / 862307. The disclosures of both applications are incorporated herein by reference in their entirety. Technical Field

[0004] This invention relates generally to a method for manufacturing a memory cell, and more particularly to a method for manufacturing a non-volatile memory cell. Background Technology

[0005] Many electronic devices, such as mobile phones, computers, automobiles, and monitors, contain storage devices. These devices store data for various purposes. Depending on whether the data is retained or erased after power is off, storage devices generally fall into two categories. For volatile storage devices, the data is erased whenever the power is turned off. However, for non-volatile storage devices, the data stored within is retained even when the power is off.

[0006] Non-volatile storage devices typically include storage arrays with tens of thousands of storage cells. Figure 1 This is a schematic diagram of a memory cell 100 in a conventional non-volatile memory device. The memory cell 100 includes a bottom electrode 102, a top electrode 104, a dielectric layer 106 disposed between the bottom electrode 102 and the top electrode 104, and metal lines 108 connected to the top electrode 104. The bottom electrode 102 and the top electrode 104 typically comprise conductive materials, while the dielectric layer 106 typically contains oxides. This conventional memory cell 100 has several disadvantages. For example, due to structural reasons, short circuits may occur between the metal lines 108 and the dielectric layer 106, or between the metal lines 108 and the bottom electrode 102. Short circuits will damage the memory cell 100 or prevent it from functioning properly. Furthermore, oxygen within the dielectric layer 106 may escape to other parts of the memory cell 100, thereby degrading the functionality of the memory cell 100.

[0007] Figure 2 This is a schematic diagram of a memory cell 200 in a conventional non-volatile memory device. The memory cell 200 includes a bottom electrode 202, a top electrode 204, a dielectric layer 206 disposed between the bottom electrode 202 and the top electrode 204, a top metal line 208 connected to the top electrode 204, a bottom metal line 210 connected to the bottom electrode 202, and an insulating layer 212 disposed between the bottom metal line 210 and the dielectric layer 206. The insulating layer 212 insulates the bottom electrode 202, thereby reducing the possibility of a short circuit between the top metal line 208 and the bottom electrode 202. However, the possibility of a short circuit still exists between the top metal line 208 and the dielectric layer 206. Furthermore, oxygen within the dielectric layer 206 may still escape to other parts of the memory cell 200, thereby reducing the reliability of the memory cell 200. Summary of the Invention

[0008] This invention relates to a method for manufacturing a non-volatile memory cell. After forming a first dielectric layer on a first metal line, the first dielectric layer is etched to form a first via extending to the first metal line. After forming a bottom electrode within the first via, a resistive layer, a top electrode, and a second dielectric layer are formed on the bottom electrode and the first dielectric layer. Subsequently, the resistive layer and the top electrode are oxidized to form a side portion covering the top electrode and the resistive layer. After forming a sidewall layer covering the second dielectric layer and the side portion, a second via is formed, penetrating the sidewall layer and the second dielectric layer to reach the top electrode. Then, a contact wire is formed within the second via, the width of which is smaller than the width between the outer surfaces of the side portion.

[0009] The above and other features of the various devices, systems, and methods disclosed herein, as well as the functions of their operating methods and related structural elements, will become more apparent when viewed in conjunction with the accompanying drawings, all of which form part of this specification. However, it should be clearly understood that the drawings are for illustrative and descriptive purposes only and are not intended to define the scope of the invention. It should be understood that both the foregoing summary and the following detailed description are illustrative and explanatory in nature and do not limit the scope of the claimed invention. Attached Figure Description

[0010] The non-limiting embodiments of the present invention can be more easily understood by referring to the following figures.

[0011] Figure 1 This is a schematic diagram of a storage cell in an existing non-volatile storage device.

[0012] Figure 2 This is a schematic diagram of another existing non-volatile storage device.

[0013] Figure 3A This is a schematic cross-sectional view of a storage cell along the X direction according to an exemplary embodiment.

[0014] Figure 3B According to an exemplary embodiment Figure 3A A schematic diagram of a cross-section of a storage cell along the Y direction.

[0015] Figure 4A This is a schematic cross-sectional view of another storage cell along the X direction according to an exemplary embodiment.

[0016] Figure 4B According to an exemplary embodiment Figure 4A A schematic diagram of a cross-section of a storage cell along the Y direction.

[0017] Figure 5A This is a schematic cross-sectional view of another storage cell along the X direction according to an exemplary embodiment.

[0018] Figure 5B According to an exemplary embodiment Figure 5A A schematic diagram of a cross-section of a storage cell along the Y direction.

[0019] Figure 6 The image shows a portion of a storage array containing the storage cells of the present invention according to an exemplary embodiment.

[0020] Figure 7 This is a flowchart of a method for manufacturing a memory cell according to one embodiment.

[0021] Figures 8A to 8W This is a schematic diagram of a method for manufacturing a memory cell according to various exemplary embodiments. Detailed Implementation

[0022] Hereinafter, non-limiting embodiments of the invention are described with reference to the accompanying drawings. It should be understood that any specific features and aspects of any embodiment disclosed herein may be used and / or combined with any other specific features and aspects of embodiments disclosed herein. It should also be understood that such embodiments are exemplary and only a small subset of embodiments within the scope of the invention are illustrated. Various changes and modifications readily understood by those skilled in the art to which this invention pertains are considered to fall within the spirit, scope, and concept of the invention as further defined by the appended claims.

[0023] The technology disclosed herein provides a memory cell that overcomes the shortcomings of existing memory cells. The solutions provided by the following embodiments simplify the manufacturing process and are compatible with logic circuit technology. Memory devices employing the memory cells of this invention have stable storage performance, thereby improving device reliability.

[0024] Hereinafter, various embodiments will be described with reference to the accompanying drawings. First, referring to... Figure 3A and Figure 3B ,in, Figure 3A This is a schematic cross-sectional view along the X direction of a storage cell 300 according to an exemplary embodiment. Figure 3B This is a schematic cross-sectional view along the Y direction of a storage cell 300 according to an exemplary embodiment. The storage cell 300 includes a bottom electrode 302, a top electrode 304, a dielectric layer 306 disposed between the bottom electrode 302 and the top electrode 304, a top contact wire 308 connected to the top electrode 304, and a bottom contact wire 310 connected to the bottom electrode 302. The sides of the bottom electrode 302, the top electrode 304, and the dielectric layer 306 are covered by side portions 312. An insulating layer 314 is disposed on the side portions 312. Sidewalls 316 cover the outer surfaces of the side portions 312 and the insulating layer 314. A bottom insulating layer 318 is disposed below the bottom electrode 302 to insulate the bottom contact wire 310. A top insulating layer 320 is disposed on the sidewalls 316 to insulate the top contact wire 308. Figure 3B As shown, two adjacent stacked structures consisting of a bottom electrode 302, a top electrode 304, and a dielectric layer 306 are separated in the Y direction by a sidewall 316 and a top insulating layer 320.

[0025] In some embodiments, the bottom electrode 302 contains at least one of TiN, TaN, W, or other suitable conductive materials. In some embodiments, the top electrode 304 contains at least one of TiN, TaN, Ru, Pt, Ir, W, and other suitable conductive materials. The dielectric layer 306 can be a resistive layer containing a resistive material. The dielectric layer 306 may, for example, include Ta2O5, TaO, etc. x WO x TiO x ZrO x One or more resistive metal oxides are used. In some embodiments, the resistive layer 306 comprises one or more thin films. The resistive layer 306 may, for example, have a first thin film and a second thin film disposed on the first thin film. The second thin film is different from the first thin film. In some embodiments, the first thin film contains a first metal oxide, and the second thin film contains a second metal oxide.

[0026] The top contact wire 308 and the bottom contact wire 310 may contain conductive materials such as metals. Each contact wire may contain, for example, Cu, Al, Au, Pt, W, etc. The side portion 312 contains at least an oxide of the conductive material contained in the top electrode 304. In some embodiments, the side portion 312 may further contain an oxide of the resistive layer 306. In some embodiments, the side portion 312 may further contain an oxide of the bottom electrode 302.

[0027] Insulating layer 314 may contain SiON, SiN, or SiO. x The insulating material may be CSiNH, CSiOH, or other insulating materials. The sidewall 316 may contain SiO2, Si3N4, TEOS, CSiNH, etc. The sidewall 316 extends to the top surface of the insulating layer 314 and the top surface of the bottom insulating layer 318. The width d1 of the top contact wire 308 is less than the width d2 between the outer surfaces of the side portion 312. The width d1 of the top contact wire 308 is greater than the width d3 of the top electrode 304. A portion of the bottom surface and a portion of the side surface of the top contact wire 308 are in contact with the side portion 312. Furthermore, the side surface of the top contact wire 308 is in contact with the insulating layer 314 and the sidewall 316.

[0028] In the illustrated embodiment, the sides of the bottom electrode 302, top electrode 304, and resistive layer 306 are covered by insulating side portions 312, thereby significantly reducing the possibility of short circuits between the top contact wire 308 and the resistive layer 306, and between the top contact wire 308 and the bottom electrode 302. Furthermore, the side portions 312 covering the sides of the resistive layer 306 effectively prevent oxygen from diffusing from the resistive layer 306 to other parts of the memory cell 300. This structure improves the performance and reliability of the memory cell 300, and particularly enhances its retention capability.

[0029] Figure 4A This is a schematic cross-sectional view along the X direction of a storage cell 400 according to an exemplary embodiment. Figure 4B This is a schematic cross-sectional view along the Y direction of a memory cell 400 according to an exemplary embodiment. The memory cell 400 includes a bottom electrode 402, a top electrode 404, a dielectric / resistive layer 406 disposed between the bottom electrode 402 and the top electrode 404, a top contact wire 408 connected to the top electrode 404, and a bottom contact wire 410 connected to the bottom electrode 402. The sides of the top electrode 404 and the dielectric layer 406 are covered by side portions 412. An insulating layer 414 is provided on the side portions 412. Sidewalls 416 cover the outer surfaces of the side portions 412 and the insulating layer 414. A bottom insulating layer 418 is provided on the bottom contact wire 410 for insulating the bottom electrode 402. A top insulating layer 420 is provided on the sidewalls 416 for insulating the top contact wire 408. Figure 4B As shown, two adjacent stacked structures consisting of a bottom electrode 402, a top electrode 404, and a dielectric layer 406 are separated in the Y direction by a sidewall 416 and a top insulating layer 420.

[0030] Storage unit 400 and Figure 3A and Figure 3BThe illustrated memory cell 300 is similar, except that the bottom electrode 402 is disposed in a via within the bottom insulating layer 418 and connected to the bottom contact wire 410. In the memory cell 400, the side portion 412 at least contains an oxide of the conductive material contained in the top electrode 404. In some embodiments, the side portion 412 may further contain an oxide of the resistive layer 406. In the illustrated embodiment, the side portion 412 may not contain the oxide of the bottom electrode 402.

[0031] The width d4 of the top contact wire 408 is less than the width d5 ​​between the outer surfaces of the side portion 412. The width d4 of the top contact wire 408 is greater than the width d6 of the top electrode 404. The width d7 of the bottom electrode 402 is less than the width d6 of the top electrode 404 or the resistive layer 406.

[0032] The top electrode 404 and the sides of the resistive layer 406 are covered by insulating side portions 412, thereby reducing the possibility of a short circuit between the top contact wire 408 and the resistive layer 406. Furthermore, the bottom electrode 402, embedded in a via within the bottom insulating layer 418, reduces the possibility of a short circuit between the top contact wire 408 and the bottom electrode 402. Additionally, the side portions 412 covering the sides of the resistive layer 406 effectively prevent oxygen from diffusing from the resistive layer 406 to other parts of the memory cell 400. This structure improves the performance and reliability of the memory cell 400.

[0033] Figure 5A This is a schematic cross-sectional view along the X direction of a storage cell 500 according to an exemplary embodiment. Figure 5B This is a schematic cross-sectional view along the Y direction of a memory cell 500 according to an exemplary embodiment. The memory cell 500 includes a bottom electrode 502, a top electrode 504, a dielectric / resistive layer 506 disposed between the bottom electrode 502 and the top electrode 504, a top contact wire 508 connected to the top electrode 504, and a bottom contact wire 510 connected to the bottom electrode 502. The sides of the top electrode 504 and the dielectric layer 506 are covered by side portions 512. An insulating layer 514 is disposed on the side portions 512. Sidewalls 516 cover the outer surfaces of the side portions 512 and the insulating layer 514. A bottom insulating layer 518 is disposed on the bottom contact wire 510 for insulating the bottom electrode 502. A top insulating layer 520 is disposed on the sidewalls 516 for insulating the top contact wire 508.

[0034] like Figure 5B As shown, the resistive layer 506 and the top electrode 504 are formed into a linear structure connecting multiple memory cells 500 along the Y direction. Each bottom electrode 502 is separated by a bottom insulating layer 518.

[0035] and Figure 4A and Figure 4BSimilar to the storage cell 400 shown, in the X direction, the width d8 of the top contact wire 508 is smaller than the width d9 between the outer surfaces of the side portion 512. The width d8 of the top contact wire 508 is larger than the width d10 of the top electrode 504. The width d11 of the bottom electrode 502 is smaller than the width d10 of the top electrode 504 or the resistive layer 506.

[0036] The top electrode 504 and the sides of the resistive layer 506 are covered by insulating side portions 512, thereby reducing the possibility of a short circuit between the top contact wire 508 and the resistive layer 506. Furthermore, the bottom electrode 502, embedded in a via within the bottom insulating layer 518, reduces the possibility of a short circuit between the top contact wire 508 and the bottom electrode 502. Additionally, the side portions 512 covering the sides of the resistive layer 506 effectively prevent oxygen from diffusing from the resistive layer 506 to other parts of the memory cell 500. This structure improves the performance and reliability of the memory cell 500.

[0037] The storage cells disclosed herein can be used to form storage arrays of storage devices. Figure 6 The diagram shows a portion of a memory array 600 incorporating memory cells of the present invention according to an exemplary embodiment. The memory array 600 includes a plurality of memory cells 602. Each memory cell may include a resistive element 604 and a transistor 606. The memory array 600 employs an intersection structure including word lines 610 and bit lines 620. The extension directions of the word lines 610 and bit lines 620 are orthogonal to each other. A resistive memory cell 602 is disposed at each intersection of the word line 610 and the bit line 620. The word line 610 is connected to a word line decoder 615, which selects a word line connected to a corresponding row of resistive memory cells 602. The bit line 620 is connected to a bit line decoder 625, which selects a bit line connected to a corresponding column of resistive memory cells 602. The memory array 600 also includes a plurality of source lines 630 extending parallel to the word lines 610. In some embodiments, the source lines 630 may also extend parallel to the bit lines 620.

[0038] The gate of transistor 606 is connected to word line 610. The source of transistor 606 is connected to source line 630, and the drain of transistor 606 is connected to one end of resistor element 604. The other end of resistor element 604 is connected to bit line 620. Depending on the duration, magnitude, and polarity of the corresponding voltage pulse applied to the resistive memory cell 602 at the intersection of selected word line 610 and selected bit line 620, the resistive memory cell 102 undergoes read, reset, or set operations.

[0039] The memory array employing the aforementioned memory cells can be applied to various electronic devices and systems. For example, the memory array can be used as a component in microcontroller units, radio frequency identification systems, etc.

[0040] The following is for reference. Figure 7 The manufacturing method of the storage unit in the above-described embodiments will be explained. Figure 7 This is a flowchart of a memory cell manufacturing method 700 according to one embodiment. In 702, a first dielectric layer is formed on a first metal line. In 704, a first via extending to the first metal line is formed by etching the first dielectric layer. In 706, a bottom electrode is formed within the first via. In 708, a resistive layer, a top electrode, and a second dielectric layer are formed on the bottom electrode and the first dielectric layer. In 710, a side portion covering the top electrode and the resistive layer is formed by oxidizing the resistive layer and the top electrode. In 712, a sidewall layer covering the second dielectric layer and the side portion is formed. In 714, a second via extending through the sidewall layer and the second dielectric layer and reaching the top electrode is formed. In 716, a contact wire is formed in the second via such that the width of the contact wire is less than the width between the outer sides of the side portion.

[0041] The following is for reference. Figures 8A to 8W Another method for manufacturing the storage unit of the above-described embodiment will be described. Figures 8A to 8W This is a schematic diagram of a memory cell manufacturing method according to various exemplary embodiments. First, refer to... Figure 8A Multiple bottom metal lines 802, including metal lines 802a and 802b, are formed on the substrate 800. Although Figure 8A Not shown, but substrate 800 may include other circuitry for controlling memory cells. Subsequently, a first dielectric layer 804 is deposited on the bottom metal lines 802 and substrate 800. The first dielectric layer 804 may contain silicon oxide, silicon nitride, silicon oxynitride, or other insulating materials. The first dielectric layer 804 may be deposited using physical vapor deposition or chemical vapor deposition.

[0042] refer to Figure 8B A photoresist 806 is deposited on the first dielectric layer 804, and a photolithography process is performed on the photoresist 806 to form an opening 810 in the photoresist 806 that exposes the surface of the first dielectric layer 804. (Reference) Figure 8C The first dielectric layer 804 is etched through the aperture 810 to reach the surface of the bottom metal line 802, and the photoresist 806 on the top surface of the first dielectric layer 804 is removed to form the first via 810. Figure 8D Subsequently, a conductive layer 812 is deposited on the first dielectric layer 804 and within the first via 810. Figure 8E The conductive layer 812 on the surface of the first dielectric layer 804 is removed using chemical mechanical polishing (CMP), leaving the conductive layer 812 inside the first via 810. Figure 8F The conductive layer 812 within the via forms the bottom electrode 814 of the non-volatile memory cell.

[0043] Subsequently, reference Figure 8G ,exist Figure 8F The structure shown is deposited with one or more metal oxides (MO). x The resistive layer 816. In some embodiments, the resistive layer 816 may contain Ta2O5, TaO x One or more resistive metal oxides are used. In some embodiments, the resistive layer 816 may comprise one or more thin films. The resistive layer 816 may, for example, have a first thin film and a second thin film disposed on the first thin film. The second thin film is different from the first thin film. In some embodiments, the first thin film contains a first metal oxide, and the second thin film contains a second metal oxide. For example, a first Ta2O5 thin film is first deposited on the bottom electrode 814 and the first dielectric layer 804, and then TaO is deposited on the first thin film. x Second thin film. Subsequently, conductive layer 818 is deposited on resistive layer 816. Figure 8H Then, a second dielectric layer 820 is deposited on the conductive layer 818. Figure 8I Subsequently, photoresist is applied to the second dielectric layer 820, and then a photoresist pattern 822 is formed by patterning the photoresist. Figure 8J In some embodiments, during the photoresist patterning process, the metal line 802a can be used as a mask so that the photoresist pattern 822 is aligned with the metal line 802a along the width direction.

[0044] Following this, the second dielectric layer 820 is etched using the photoresist pattern 822 to form a residual second dielectric layer 824. Figure 8K Subsequently, the second dielectric layer 824 is exposed by stripping away the photoresist pattern 822. Figure 8L In some embodiments, the photoresist pattern 822 is removed by photoresist ashing. For example, an active material such as oxygen or fluorine can be generated using a plasma source. The active material reacts with the photoresist pattern 822 to ashing it, and the resulting ash is removed by a vacuum pump. Subsequently, using the second dielectric layer 824 as a mask, the conductive layer 818 is etched to form the top electrode 826 of the memory cell. Figure 8M Then, using the second dielectric layer 824 as a mask, the resistive layer 816 is etched to form the residual resistive layer 828. Figure 8N ).

[0045] refer to Figure 8O An oxidation process is performed on the top electrode 826 and the resistive layer 828 to form a side portion 830 covering the sides of the top electrode 830 and the resistive layer 828. The side portion 830 contains at least an oxide of the conductive material of the top electrode 830. In some embodiments, the side portion 830 may also contain an oxide of the resistive layer 828.

[0046] Following the oxidation process, a sidewall layer 832 covering the second dielectric layer 824, the side portion 830, and the first dielectric layer 804 is deposited on the substrate 800. Figure 8P In some embodiments, the sidewall layer 832 contains, for example, silicon oxide. The sidewall layer 832 may be formed, for example, by tetraethoxysilane (TEOS). In some embodiments, a thick insulating layer 834 is subsequently deposited on the sidewall layer 832. Figure 8Q In some embodiments, the insulating layer 834 can be formed using TEOS or other suitable insulating materials. Subsequently, a CMP process is performed to planarize the uneven surface of the insulating layer 834. Figure 8R ).

[0047] Following this, photoresist 836 is applied to the planarized surface of the insulating layer 834, and through patterning of the photoresist, openings 838 corresponding to the metal lines 802b are formed in the insulating layer 834. Figure 8S Subsequently, through the openings 838 in the photoresist 836, the insulating layer 834, the sidewall layer 832, and the first dielectric layer 804 are patterned to form trenches 840 that expose the surface of the metal line 802b. Then, the remaining photoresist 836 is stripped away. Figure 8T Next, photoresist 842 is applied to the substrate 800 and patterned to form two openings 844 and 846 corresponding to the top electrode 826 and the trench 840, respectively. Figure 8U ).

[0048] refer to Figure 8V A second via 848 is formed using openings 844 in the photoresist 842. This second via 848 penetrates the insulating layer 834, the sidewall layer 932 on the second dielectric layer 824, and the second dielectric layer 824, extending to the surface of the top electrode 826. Furthermore, a third via 850 is formed using openings 846 in the photoresist 842. The third via 850 overlaps with the trench 840 and has a wider width than the trench 840. Afterwards, the photoresist 842 on the substrate 800 is stripped. (Refer to...) Figure 8W A metal layer is deposited on the substrate 800, which fills the second via 848, the third via 850, and the trench 840. Subsequently, the excess metal layer on the insulating layer 834 is removed by a CMP process to form the top contact line 852 of the memory cell 854 and the contact wiring structure 856 that contacts the metal line 802b.

[0049] like Figure 8WAs shown, a top contact line 852 is formed, and the width d20 of the top contact line 852 is smaller than the width d21 between the outer sides of the side portion 830. The width d20 of the top contact line 852 is larger than the width d22 of the top electrode 826. The top electrode 826 and the sides of the resistive layer 828 are covered by the insulating side portion 830, thereby reducing the possibility of a short circuit between the top contact line 852 and the resistive layer 828. In addition, the bottom electrode 814 embedded in the first via 810 within the first dielectric layer 804 reduces the possibility of a short circuit between the top contact line 852 and the bottom electrode 814. Furthermore, the side portion 830 covering the sides of the resistive layer 828 effectively prevents oxygen from diffusing from the resistive layer 828 to other parts of the memory cell 854. This structure can improve the performance and reliability of the memory cell 854.

[0050] It should be understood that, Figures 8A to 8W The embodiments shown are for illustrative purposes only. Those skilled in the art will understand that the above methods, processes, and steps can be modified to varying degrees without departing from the spirit of the invention.

[0051] While examples and features of the principles of this disclosure have been described herein, modifications and alterations may be made without departing from the spirit and scope of embodiments of this disclosure, and other implementations exist. Furthermore, the words “comprising,” “having,” “including,” “containing,” and other similar forms are intended to be synonymous in meaning and are open-ended terms, meaning that one or more items following any of these words are not intended to be an exhaustive list of these items, nor are they intended to be limited to only the listed one or more items. It must be noted that in this document and in the appended claims, unless the context clearly indicates otherwise, the unspecified number includes both singular and plural meanings.

[0052] The detailed descriptions of the embodiments given herein are sufficient to enable those skilled in the art to practice the disclosed technical solutions. In addition, other embodiments may be used, or other embodiments may be derived therefrom; therefore, structural and logical substitutions and changes may be made without departing from the scope of the invention. Therefore, this "Detailed Description" section should not be construed as limiting, and the scope of the various embodiments is defined only by the appended claims and all their equivalents.

Claims

1. A method for manufacturing a non-volatile memory cell, characterized in that, The method includes: A first dielectric layer is formed on the first metal line; Etching forms a first via that directly reaches the first metal line; A bottom electrode is formed within the first via; A resistive layer, a top electrode, and a second dielectric layer are formed on the bottom electrode and the first dielectric layer; Oxidize the resistive layer and the top electrode to form an insulating side portion covering the top electrode and the resistive layer; A sidewall layer is formed covering the second medium layer and the side portion; A second via is formed, the second via penetrating the sidewall layer and the second dielectric layer, reaching the top electrode; and A contact wire is formed within the second via, the width of which is less than the width between the outer surfaces of the side portion. A portion of the bottom surface and a portion of the side surface of the contact wire are in contact with the side portion. The side portion is used to prevent oxygen from diffusing from the resistive layer and to prevent short circuits between the contact wire and the resistive layer.

2. The method according to claim 1, characterized in that: The width of the contact wire is greater than the width of the top electrode.

3. The method according to claim 1, characterized in that: The side of the contact wire is in contact with the sidewall layer and the second dielectric layer.

4. The method according to claim 1, characterized in that: The bottom electrode includes at least one of TiN, TaN, and W.

5. The method according to claim 1, characterized in that: The top electrode includes at least one of TiN, TaN, Ru, Pt, Ir, and W.

6. The method according to claim 1, characterized in that: The resistive layer comprises a metal oxide.

7. The method according to claim 6, characterized in that: The metal oxides include Ta2O5 and TaO. x WO x TiO x ZrO x At least one of them.

8. The method according to claim 1, characterized in that: The resistive layer includes Ta2O5 and TaO. x At least one of them.

9. The method according to claim 8, characterized in that: The resistive layer includes a first thin film and a second thin film disposed on the first thin film, the second thin film being different from the first thin film.

10. The method according to claim 9, characterized in that: The first thin film comprises a first metal oxide; and The second thin film comprises a second metal oxide.

11. The method according to claim 10, characterized in that: The first metal oxide is Ta2O5; and The second metal oxide is TaO x .

12. The method according to claim 1, characterized in that: The contact wire includes at least one of Cu, Al, Au, Pt, and W.

13. The method according to claim 1, characterized in that: The sidewall layer includes at least one of SiO2, Si3N4, TEOS, and CSiNH.

14. The method according to claim 1, characterized in that: The first dielectric layer is formed on the first metal line by physical vapor deposition or chemical vapor deposition.

15. The method according to claim 1, characterized in that: The first via is formed by photolithography etching.

16. The method according to claim 15, characterized in that, The photolithography etching includes: A photoresist layer is formed, the photoresist layer including an opening corresponding to the first via; Expose the photoresist layer; Etching the first dielectric layer at the opening to reach the first metal line; and The photoresist layer is removed by chemical mechanical polishing.

17. The method according to claim 1, characterized in that: The sidewall layer is used to prevent oxygen from diffusing from the resistive layer to other parts of the storage cell.

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