Electronic device

Abstract

An electronic device is provided. The electronic device includes a plurality of units. Each unit includes an integrated substrate. The integrated substrate includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer. The first dielectric layer has a first side and a second side opposite to the first side. The first conductive layer is disposed on the first side. The second dielectric layer has a third side facing the second side and a fourth side opposite to the third side. The second conductive layer is disposed on the fourth side. A loss tangent of at least one of the first dielectric layer and the second dielectric layer is less than or equal to 0.1 and greater than 0. The electronic device of the embodiments of the present disclosure can improve the yield of products.

Description

Technical Field

[0001] This disclosure relates to an electronic device, and more particularly to an electronic device that can improve product yield. Background Technology

[0002] Electronic devices, or spliced ​​electronic devices, are widely used in mobile phones, televisions, monitors, tablets, automotive displays, wearable devices, and desktop computers. With the rapid development of electronic devices, the quality requirements for them are increasing, and these electronic products often also function as electronic modulation devices, for example, as antennas that can modulate electromagnetic waves. However, existing antenna devices still do not fully meet consumer needs in every aspect. Summary of the Invention

[0003] This disclosure provides an electronic device that can improve product yield.

[0004] According to embodiments disclosed herein, an electronic device includes multiple units, and each unit includes an integrated substrate. The integrated substrate includes a first dielectric layer, a first conductive layer, a second dielectric layer, and a second conductive layer. The first dielectric layer has a first side and a second side opposite to the first side. The first conductive layer is disposed on the first side. The second dielectric layer has a third side facing the second side and a fourth side opposite to the third side. The second conductive layer is disposed on the fourth side. The loss tangent of at least one of the first dielectric layer and the second dielectric layer is less than or equal to 0.1 and greater than 0.

[0005] According to embodiments disclosed herein, an electronic device includes multiple conductive structures. Each conductive structure includes a third dielectric layer, a via, a third conductive layer, an opening, and a fourth conductive layer. The via is disposed in the third dielectric layer. The third conductive layer is disposed on the third dielectric layer. The opening is disposed in the third conductive layer. The fourth conductive layer is disposed on the third conductive layer. The fourth conductive layer directly contacts the top surface of the third conductive layer and passes through the opening. Attached Figure Description

[0006] The accompanying drawings are included to further illustrate the present disclosure, and are incorporated in and form a part of this specification. The drawings illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

[0007] Figure 1 This is a functional schematic diagram of an electronic device according to an embodiment of the present disclosure;

[0008] Figures 2A to 2F This is a schematic cross-sectional view of a method for manufacturing an electronic device according to an embodiment of the present disclosure;

[0009] Figure 3 for Figure 2F A top view schematic diagram of an electronic device;

[0010] Figure 4 This is a top view schematic diagram of an electronic device according to another embodiment of the present disclosure;

[0011] Figures 5A to 5D This is a partial top view schematic diagram of the conductive structure of several embodiments disclosed herein.

[0012] Explanation of icon numbers

[0013] 10, 20, 20a: Electronic devices;

[0014] 11: Baseband circuit;

[0015] 13: Phased array antenna;

[0016] 15: Antenna components;

[0017] 110: Digital-to-Analog Converter;

[0018] 120: Analog-to-digital converter;

[0019] 140: Intermediate frequency circuit;

[0020] 141, 145, 166: Filters;

[0021] 142, 146: Amplifiers;

[0022] 143, 161: Mixers;

[0023] 144, 162: Local oscillator;

[0024] 241: Slot;

[0025] 160: Radio frequency circuit;

[0026] 163: Phase shifter;

[0027] 164: Power amplifier;

[0028] 165: Duplexer;

[0029] 167: Low-noise amplifier;

[0030] 22: Unit;

[0031] 24, 24a, 24b, 24c, 24d: Conductive structures;

[0032] 202: Integrated substrate;

[0033] 202a: First Component;

[0034] 202b: Second Component;

[0035] 202c: Third Component;

[0036] 210: First dielectric layer;

[0037] 211: First side;

[0038] 212: Second side;

[0039] 220, 220a: First conductive layer;

[0040] 230: Second dielectric layer;

[0041] 231: The third side;

[0042] 232: Fourth side;

[0043] 240: Second conductive layer;

[0044] 250: Third dielectric layer;

[0045] 251: Fifth side;

[0046] 252: Sixth side;

[0047] 254: Through hole;

[0048] 260, 260a: Third conductive layer;

[0049] 261: Top surface;

[0050] 262, 263, 2852, 2853: Gap;

[0051] 265: Opening;

[0052] 270, 271, 271a: Fourth conductive layer;

[0053] 275: Welding ball;

[0054] 280: Conductor;

[0055] 285, 285a: Bottom conductive layer;

[0056] 2851: Surface;

[0057] 290: Fourth dielectric layer;

[0058] 300: Chip;

[0059] 310: Connecting pad;

[0060] IS1, IS2, IS3: First insulating layer;

[0061] OP1, OP2, OP3, OP4, OP5: Openings;

[0062] P: Spacing;

[0063] T1, T2: Total thickness;

[0064] VB: Bias trace. Detailed Implementation

[0065] This disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings. It should be noted that, for ease of understanding and for the sake of brevity, many of the drawings in this disclosure depict only a portion of the electronic device, and certain components in the drawings are not drawn to scale. Furthermore, the number and dimensions of the components in the drawings are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0066] In the following description and claims, the words “containing” and “including” are open-ended terms, and therefore should be interpreted as “containing but not limited to…”.

[0067] It should be understood that when an element or membrane is referred to as being "on" or "connected" to another element or membrane, it can be directly on or directly connected to that other element or membrane, or there may be an inserted element or membrane between them (indirect cases). Conversely, when an element is referred to as being "directly" on or "directly connected" to another element or membrane, there may be no inserted element or membrane between them.

[0068] Although the terms "first," "second," "third," etc., can be used to describe multiple components, the components are not limited to these terms. These terms are used only to distinguish a single component from other components in the specification. The same terms may not be used in the claims, but rather replaced by "first," "second," "third," etc., according to the order of the elements declared in the claims. Therefore, in the following description, a first component may be a second component in the claims.

[0069] In this text, the terms "about," "approximately," "substantially," and "roughly" typically indicate that a given value or range is within 10%, 5%, 3%, 2%, 1%, or 0.5%. The given quantity is an approximate quantity; that is, even without specific mention of "about," "approximately," "substantially," or "roughly," the meaning of "about," "approximately," "substantially," or "roughly" can still be implied.

[0070] In this disclosure, the length, width, thickness, height, or area, or the distance or spacing between elements, can be measured using an optical microscopy (OM), a scanning electron microscope (SEM), an alpha-step thickness gauge, an elliptic gauge, or other suitable methods. Specifically, according to some embodiments, a scanning electron microscope can be used to obtain a cross-sectional structural image containing the elements to be measured, and to measure the width, thickness, height, or area of ​​each element, or the distance or spacing between elements, but this is not a limitation.

[0071] In some embodiments disclosed herein, terms such as "connection" and "interconnection," unless specifically defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein another structure is disposed between the two structures. Furthermore, these terms regarding engagement and connection may also include situations where both structures are movable or both structures are fixed. In addition, the term "coupled" includes any direct and indirect electrical connection means.

[0072] The electronic devices disclosed herein may include, but are not limited to, display devices, backlight devices, antenna devices, sensing devices, or splicing devices. The electronic devices may be bendable or flexible. Display devices may be non-emissive or emissive. Antenna devices may be liquid crystal type or non-liquid crystal type antenna devices; sensing devices may be sensing capacitance, light, heat, or ultrasound, but are not limited to these. Electronic components may include passive and active components, such as capacitors, resistors, inductors, diodes, transistors, etc. Diodes may include light-emitting diodes (LEDs) or photodiodes. Light-emitting diodes may include, for example, organic light-emitting diodes (OLEDs), mini LEDs, micro LEDs, or quantum dot LEDs, but are not limited to these. Splicing devices may be, for example, display splicing devices or antenna splicing devices, but are not limited to these. It should be noted that the electronic devices may be any combination of the foregoing, but are not limited to these. The following description uses the antenna device as an electronic device or splicing device to illustrate the contents of this disclosure, but this disclosure is not limited thereto.

[0073] It should be understood that the features in the following embodiments can be replaced, recombined, or mixed to complete other embodiments without departing from the spirit of this disclosure. Features between embodiments can be arbitrarily mixed and combined as long as they do not violate the spirit of the invention or conflict with it.

[0074] Reference will now be made in detail to the exemplary embodiments disclosed herein, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0075] Figure 1 This is a functional schematic diagram of an electronic device according to an embodiment of this disclosure. Please refer to... Figure 1 In this embodiment, the electronic device 10 can be regarded as an antenna device, including a baseband circuit 11 and a phase array antenna 13.

[0076] Specifically, in this embodiment, the phase array antenna 13 may employ analog beamforming technology, but is not limited thereto. The phase array antenna 13 may include multiple elements 22 ( Figure 1 (Illustratively, a single antenna is used as an example), and multiple units 22 are arranged in an array (not shown). Each unit 22 includes a digital-to-analog converter 110, an analog-to-digital converter 120, an intermediate frequency circuit 140, a radio frequency circuit 160, and an antenna element 15. The intermediate frequency circuit 140 includes a filter 141, an amplifier 142, a mixer 143, a local oscillator 144, a filter 145, and an amplifier 146. The radio frequency circuit 160 includes a mixer 161, a local oscillator 162, a phase shifter 163, a power amplifier 164, a duplexer 165, a filter 166, and a low noise amplifier 167.

[0077] In this embodiment, when the electronic device 10 transmits a signal, the baseband circuit 11 first converts the low-frequency digital signal into a low-frequency analog signal through the digital-to-analog converter 110 in unit 22 and transmits it to the intermediate frequency circuit 140; then, the low-frequency analog signal is converted into an intermediate frequency analog signal through the filter 141, amplifier 142, mixer 143, local oscillator 144, filter 145 and amplifier 146 in the intermediate frequency circuit 140 and transmitted to the radio frequency circuit 160; then, the intermediate frequency analog signal is converted into a high-frequency analog signal through the mixer 161, local oscillator 162, phase shifter 163, power amplifier 164 and duplexer 165 in the radio frequency circuit 160 and transmitted to the antenna element 15; then, the high-frequency analog signal (i.e., electromagnetic wave) is transmitted to the outside through the antenna element 15.

[0078] Conversely, when the electronic device 10 receives a signal, it first uses the antenna element 15 to receive electromagnetic waves from the outside world and transmits them to the radio frequency circuit 160 in the unit 22; then, the radio frequency circuit 160 converts the high-frequency analog signal into an intermediate frequency analog signal and transmits it to the intermediate frequency circuit 140; then, the intermediate frequency circuit 140 converts the intermediate frequency analog signal into a low-frequency analog signal and transmits it to the analog-to-digital converter 120; then, the analog-to-digital converter 120 converts the low-frequency analog signal into a low-frequency digital signal and transmits it to the baseband circuit 11.

[0079] In some embodiments, the phase array antenna may also employ digital beamforming technology (not shown), in which case each element in the phase array antenna may include a digital-to-analog converter, an analog-to-digital converter, a power amplifier, a duplexer, a filter, and a low-noise amplifier.

[0080] Figures 2A to 2F This is a cross-sectional schematic diagram of a method for manufacturing an electronic device according to an embodiment of the present disclosure. Figure 3 for Figure 2F A top view of the electronic device. Figure 2F for Figure 3 A cross-sectional view of the electronic device along section line I-I'. For clarity and ease of explanation, the accompanying drawings are provided. Figure 3 Several components of the electronic device 20 are omitted from the diagram.

[0081] Please refer to the following: Figure 2F and Figure 3 The electronic device 20 in this embodiment includes a plurality of units 22 ( Figure 2F (Illustratively, taking one unit as an example), unit 22 includes conductive structure 24 ( Figure 2FSchematically taking one conductive structure as an example) and the wafer 300. Specifically, each unit 22 includes an integrated substrate 202. The integrated substrate 202 includes a first dielectric layer 210, a first conductive layer 220a, a second dielectric layer 230, and a second conductive layer 240. The first dielectric layer 210 has a first side 211 and a second side 212 opposite to the first side 211. The first conductive layer 220a is disposed on the first side 211. The second dielectric layer 230 has a third side 231 facing the second side 212 and a fourth side 232 opposite to the third side 231. The second conductive layer 240 is disposed on the fourth side 232. Since the loss tangent Df of at least one of the first dielectric layer 210 and the second dielectric layer 230 is less than or equal to 0.1 and greater than 0 (i.e., 0 < Df ≤ 0.1), the loss of electromagnetic waves in the first dielectric layer 210 and the second dielectric layer 230 can be reduced, and thus the emission efficiency of the electromagnetic waves can be better.

[0082] In addition, each conductive structure 24 includes a third dielectric layer 250, a through hole 254, a third conductive layer 260, an opening 265, and fourth conductive layers 270, 271. The third dielectric layer 250 has a fifth side at 251 facing the fourth side 232 and a sixth side 252 opposite to the fifth side 251. The through hole is provided in the third dielectric layer 250. The third conductive layer 260 is disposed on the third dielectric layer 250 and on the sixth side 252. The opening 265 is provided in the third conductive layer 260. The fourth conductive layers 270, 271 are disposed on the third conductive layer 260. The fourth conductive layers 270, 271 directly contact the top surface 261 of the third conductive layer 260 and pass through the opening 265. Among them, multiple fourth conductive layers 270 can surround the wafer 300 and can be used to transmit a ground signal to the second conductive layer 24 = 0. In other embodiments, multiple fourth conductive layers 270 may not surround the wafer 300.

[0083] In this embodiment, each conductive structure 24 further includes a conductor 280, a bottom conductive layer 285, and a fourth dielectric layer 290. The conductor 280 is disposed on the fourth dielectric layer The conductor 280 is electrically connected to the fourth conductive layers 270, 271. The bottom conductive layer 285 is disposed between the third dielectric layer 250 and the third conductive layer 260. The bottom conductive layer 285 can directly contact the third conductive layer 260. The fourth dielectric layer 290 is combined with the third dielectric layer 250.

[0084] In this embodiment, the direction X and the normal direction Y of the electronic device 20 are different directions. The direction X is perpendicular to the normal direction Y, and the direction X is substantially the extension direction of the section line I-I', but this is not limited thereto.

[0085] Furthermore, in this embodiment, in the normal direction Y of the electronic device 20, the shape of the third conductive layer 260 can correspond to the shape of the fourth conductive layers 270 and 271. The shape of the third conductive layer 260 can be a closed ring or a ring with a notch, and the shapes of the fourth conductive layers 270 and 271 can be solid shapes. For example, such as Figure 3 As shown in the top view of the electronic device 20, the outer contour of the third conductive layer 260 is, for example, circular, and the outer contours of the fourth conductive layer 270 and the fourth conductive layer 271 are also correspondingly circular, but not limited thereto. In this embodiment, the shape of the third conductive layer 260 (or the shape of the bottom conductive layer 285) can limit the shape and range of the fourth conductive layers 270 and 271, so that the fourth conductive layers 270 and 271 can be confined within the range of the shape of the third conductive layer 260 (or within the range of the shape of the bottom conductive layer 285) during fabrication, thereby reducing the problem of the fourth conductive layers 270 and 271 overflowing outside the range of the shape of the third conductive layer 260 (or outside the range of the shape of the bottom conductive layer 285) during fabrication. In this embodiment, the shape of the fourth conductive layer 270 may be substantially the same as the shape of the fourth conductive layer 271, but not limited thereto. In some embodiments, the shape of the fourth conductive layer 270 may also be different from the shape of the fourth conductive layer 271, such as Figures 5A to 5D As shown.

[0086] Please refer to again Figure 3 The second conductive layer 240 has a slot 145, and the slot 241 may correspond to the first conductive layer 220a. A plurality of fourth conductive layers 271 may surround the slot 241 and the antenna element 15 to prevent electromagnetic interference (EMI) and ensure the signal quality output from the wafer 300. The EMI may be, for example, electromagnetic waves leaking from other traces. In this embodiment, the plurality of fourth conductive layers 271 are separated from each other, and there is a spacing P between adjacent fourth conductive layers 271. The spacing P is the distance from the center of one fourth conductive layer 271 to the center of the adjacent fourth conductive layer 271. In this embodiment, the spacing P may be, for example, less than half the wavelength W1 of the electromagnetic wave transmitted between the bottom conductive layer 285 and the second conductive layer 240, i.e., P < 1 / 2 × W1, but is not limited thereto.

[0087] The electronic device 20 of this embodiment also includes a voltage bias trace VB and a conductive layer 287. The voltage bias trace VB can serve as a signal line for a radio frequency circuit, a signal line for an intermediate frequency circuit, a power supply line, or a high-speed digital signal line. The voltage bias trace VB can be a single-layer or multi-layer structure, and its material can include, for example, copper, silver, gold, aluminum, tin, alloys (e.g., electroless nickel-gold (ENIG)) or combinations thereof, but is not limited thereto. The conductive layer 287 can transmit signals (e.g., high-frequency signals) output from the chip 300 to the via 241, and then couple the signals to the first conductive layer 220a.

[0088] In this embodiment, one wafer 300 may correspond to one antenna element 15, but this is not a limitation. In some embodiments, one wafer 300 may also correspond to multiple antenna elements 15 (not shown). Furthermore, in this embodiment, the wafer 300 is not disposed corresponding to the first conductive layer 220a, and the wafer 300 does not overlap with the first conductive layer 220a in the normal direction Y of the electronic device 20, but this is not a limitation. In some embodiments, the wafer may also be disposed corresponding to the first conductive layer (not shown), and the wafer may also overlap with the first conductive layer (not shown) in the normal direction of the electronic device.

[0089] Please refer to Figures 2A to 2F The manufacturing method of the electronic device 20 according to this embodiment will be described below. The manufacturing method of the electronic device 20 according to this embodiment, taking one unit 22 as an example, may include, but is not limited to, the following steps:

[0090] First, please refer to Figure 2AThe first component 202a is formed. Specifically, forming the first component 202a may include, for example, the following steps: forming a first dielectric layer 210, wherein the first dielectric layer 210 has a first side 211 and a second side 212 opposite to the first side 211. The material of the first dielectric layer 210 may be, for example, glass, printed circuit board (PCB), low temperature co-fired ceramic (LTCC), liquid crystal polymer (LCP), polyimide (PI), ceramic, plastic film (e.g., cycloolefin polymer (COP), polyethylene naphthalate (PEN)), other suitable dielectric materials, or combinations thereof, but is not limited thereto. Next, a first conductive layer 220 is formed on the first side 211, and the first conductive layer 220 is patterned to expose a portion of the first dielectric layer 210, and the patterned first conductive layer 220a is formed. Next, a first insulating layer IS1 is formed on the first conductive layer 220a to cover the first conductive layer 220a and the portion of the first dielectric layer 210 exposed by the first conductive layer 220a. At this point, the first component 202a has been fabricated.

[0091] Next, please refer to Figure 2B The second component 202b is then formed. Specifically, forming the second component 202b may include, for example, the following steps: forming a second dielectric layer 230, wherein the second dielectric layer 230 has a third side 231 and a fourth side 232 opposite to the third side 231. The material of the second dielectric layer 230 may be, for example, glass, printed circuit board (PCB), low temperature co-fired ceramic (LTCC), liquid crystal polymer (LCP), polyimide (PI), ceramic, plastic film (e.g., cycloolefin polymer (COP), polyethylene naphthalate (PEN)), other suitable dielectric materials, or combinations thereof, but is not limited thereto. The materials of the first dielectric layer and the second dielectric layer may be the same or different. Next, a second conductive layer 240 is formed on the fourth side 232, and a patterned second insulating layer IS2 is formed on the second conductive layer 240. The second insulating layer IS2 has an opening OP1 to expose a portion of the second conductive layer 240. Next, a conductor 280 is formed within the opening OP1 so that the conductor 280 can contact the second conductive layer 240. At this point, the second component 202b is complete.

[0092] Next, please refer to Figure 2C , to form the third component 202c. Specifically, forming the third component 202c may include, for example, the following steps: forming a third dielectric layer 250, where the third dielectric layer 250 has a fifth side 251 and a sixth side 252 opposite to the fifth side 251. Next, form a patterned bottom conductive layer 285 on the sixth side 252, and form a patterned third insulating layer IS3 on the bottom conductive layer 285. The bottom conductive layer 285 has openings OP2 and OP3 to expose a portion of the third dielectric layer 250. The third insulating layer IS3 may be disposed within the opening OP3 and has openings OP4 and OP5. The opening OP4 is disposed corresponding to the opening OP2, and the openings OP4 and OP5 may expose a surface 2851 of a portion of the bottom conductive layer 285 away from the third dielectric layer 250. Next, optionally form a patterned third conductive layer 260 within the openings OP4 and OP5 such that the third conductive layer 260 is disposed on the surface 2851 of the portion of the bottom conductive layer 285 exposed by the openings OP4 and OP5. Wherein, the bottom conductive layer 285 may be disposed between the third dielectric layer 250 and the third conductive layer 260. The third conductive layer 260 may directly contact the bottom conductive layer 285 to prevent oxidation of the bottom conductive layer 285. The third conductive layer 260 has an opening 265 to communicate with the opening OP2.至此,已制作完成第三组件202c。

[0093] Next, please refer to Figure 2D , to bond the first component 202a to the second component 202b such that the third side 231 of the second dielectric layer 230 in the second component 202b can face the second side 212 of the first dielectric layer 210 in the first component 202a, and the third side 231 can be combined with the second side 212. Next, form a fourth dielectric layer 290 on the surface of the second insulating layer IS2 away from the second conductive layer 240 such that the fourth dielectric layer 290 can cover the conductor 280 and the second insulating layer IS2. In this embodiment, the third side 231 may be directly adhered to the second side 212, for example, by a colloid (not shown) and, for example, by a thermal compression process, but not limited thereto. In this embodiment, the total thickness T1 of the first dielectric layer 210 and the second dielectric layer 230 may be, for example, less than half of the wavelength W2 of the electromagnetic wave emitted by the electronic device 20 and greater than 100 micrometers (μm), that is, 100μm < T1 < 1 / 2×W2, but not limited thereto. Wherein, the total thickness T1 is, for example, the thickness measured along the normal direction Y of the electronic device 20 for the first dielectric layer 210 and the second dielectric layer 230.

[0094] In some embodiments, the third side 231 may be indirectly bonded to the second side 212, for example, through a spacer (not shown) and, for example, by a one-drop filling (ODF) process. In this case, a gap (not shown) may exist between the second side 212, the third side 231, and the spacer. This gap may be an air gap or a vacuum gap, or it may be filled with a solid material (e.g., a colloid or adhesive sheet) or a liquid (e.g., water), but is not limited thereto. The thickness of the gap may, for example, be less than one-quarter of the wavelength W2 of the electromagnetic wave emitted by the electronic device 20, i.e., the thickness of the gap < 1 / 4 × W2, but is not limited thereto.

[0095] Next, please refer to Figure 2E The third component 202c is bonded to the fourth dielectric layer 290, so that the third dielectric layer 250 in the third component 202c can be bonded to the fourth dielectric layer 290, and the fifth side 251 of the third dielectric layer 250 can face the fourth side 232 of the second dielectric layer 230. Next, a via 254 is formed in the third dielectric layer 250 and the fourth dielectric layer 290, so that the via 254 can connect the opening OP2 and the opening 265 and expose the conductor 280. In this embodiment, the method for forming the via 254 may include, for example, laser drilling, mechanical drilling, or chemical etching, but is not limited thereto. In this embodiment, the total thickness of the third dielectric layer 250 and the fourth dielectric layer 290 is T2, and the ratio of the total thickness T1 to the total thickness T2 may be, for example, between 2 and 20, i.e., 2 ≤ T1 / T2 ≤ 20, but is not limited thereto. The total thickness T2 is, for example, the thickness of the third dielectric layer 250 and the fourth dielectric layer 290 measured along the normal direction Y of the electronic device 20.

[0096] Next, please refer to Figure 2F A fourth conductive layer 270, 271 and solder balls 275 are formed on the top surface 261 of the third conductive layer 260 away from the third dielectric layer 250. The fourth conductive layer 270, 271 are also formed within openings OP2, 265, and vias 254, allowing the fourth conductive layer 270, 271 to be electrically connected to conductor 280 and to be electrically connected to the second conductive layer 240 via conductor 280. The fourth conductive layer 270, 271 can directly contact the top surface 261 of the third conductive layer 260. In this embodiment, the method for forming the fourth conductive layer 270, 271 may include, for example, tin spraying, electroplating, sputtering, or screen printing, but is not limited thereto. Next, a wafer 300 is disposed on the top surface 261 of the third conductive layer 260. The chip 300 has pads 310, and the chip 300 can be electrically connected to the third conductive layer 260 via the pads 310 and solder balls 275. In some embodiments, the chip 300 may be Figure 1The intermediate frequency (IF) circuit, radio frequency (RF) circuit, or integrated circuit of IF and RF circuits in the phase array antenna.

[0097] In this embodiment, the provision of the third conductive layer 260 allows the fourth conductive layers 270 and 271 to be easily attached to the top surface 261 of the third conductive layer 260 and formed into a spherical shape during fabrication. This confines the fourth conductive layers 270 and 271 within the area of ​​the top surface 261, reducing the problem of the fourth conductive layers 270 and 271 overflowing beyond the area of ​​the top surface 261. In some embodiments, one of the third and fourth conductive layers can be omitted. When the third conductive layer is omitted, the fourth conductive layers 270 and 271 can be formed on the top surface of another conductive layer. In this case, the other conductive layer can also be used to confine the area of ​​the fourth conductive layers 270 and 271, reducing the problem of the fourth conductive layers 270 and 271 overflowing beyond their designated area.

[0098] In this embodiment, by using at least two dielectric layers (i.e., the first dielectric layer 210 and the second dielectric layer 230) and by placing the first conductive layer 220a and the second conductive layer 240 on different dielectric layers, the first conductive layer 220a and the second conductive layer 240 do not need to be placed in the same dielectric layer, thereby reducing the risk of damage to the first conductive layer 220a and the second conductive layer 240 during fabrication. Furthermore, by adjusting the thickness of the dielectric layer (i.e., the first dielectric layer 210 and the second dielectric layer 230) between the two metal plates (i.e., the first conductive layer 220a and the second conductive layer 240), the radiated electromagnetic wave energy can be increased. Thus, the electronic device 20 of this embodiment has been fabricated.

[0099] Other embodiments will be listed below for illustration. It must be noted that the following embodiments use the component reference numerals and some content from the foregoing embodiments, with the same reference numerals representing the same or similar components, and descriptions of identical technical content omitted. For explanations of the omitted parts, please refer to the foregoing embodiments; these will not be repeated in the following embodiments.

[0100] Figure 4 This is a top view schematic diagram of an electronic device according to another embodiment of this disclosure. Please also refer to... Figure 3 and Figure 4 The electronic device 20a in this embodiment is generally similar to Figure 3The electronic device 20 is the same as that in the two embodiments, so the same and similar components will not be repeated here. The electronic device 20a of this embodiment differs from electronic device 20 in that, in the antenna element 15 of electronic device 20a of this embodiment, the fourth conductive layer 271a, the third conductive layer 260a and the bottom conductive layer 285a are continuous and uninterrupted patterns that surround the slot 241. In addition, the shape of the fourth conductive layer 271a may correspond to the shape of the third conductive layer 260a, and the shape of the third conductive layer 260a may also correspond to the shape of the bottom conductive layer 285a.

[0101] Figures 5A to 5D This is a partial top view schematic diagram of the conductive structure of several embodiments disclosed herein. Please also refer to... Figure 3 as well as Figures 5A to 5D The conductive structures 24a, 24b, 24c, and 24d in this embodiment are substantially similar to... Figure 3 The conductive structure 24 is the same as that in both embodiments, so the same and similar components will not be repeated here. The conductive structures 24a, 24b, 24c, and 24d in this embodiment differ from conductive structure 24 in that, in the conductive structures 24a, 24b, 24c, and 24d in this embodiment, the shape of the fourth conductive layer 270 and the shape of the fourth conductive layer 271 can be closed or partially closed shapes other than circles, so that the fourth conductive layers 270 and 271 can be limited to the range of the shape of the third conductive layer 260 or the range of the shape of the bottom conductive layer 285 during manufacturing.

[0102] Specifically, please refer to Figure 5A The third conductive layer 260 in the conductive structure 24a has a closed square shape, and the fourth conductive layer 270 in the conductive structure 24a also has a corresponding closed square shape.

[0103] Please refer to Figure 5B The third conductive layer 260 in the conductive structure 24b has a closed pentagon shape, and the fourth conductive layer 270 in the conductive structure 24b also has a corresponding closed pentagon shape.

[0104] Please refer to Figure 5C The bottom conductive layer 285 is partially closed in shape and has a notch 2852. The third conductive layer 260 in the conductive structure 24c is partially closed in shape and has a notch 262, and the notch 262 can connect to the notch 2852. The fourth conductive layer 271 in the conductive structure 24c is partially closed in shape and extends into the notches 262 and 2852.

[0105] Please refer to Figure 5D, the shape of the bottom conductive layer 285 is a partially enclosed square and has gaps 2852 and 2853. The shape of the third conductive layer 260 in the conductive structure 24c is a partially enclosed square and has gaps 262 and 263, where the gap 262 can be connected to the gap 2852, and the gap 263 can be connected to the gap 2853. The shape of the fourth conductive layer 271 in the conductive structure 24c is a partially enclosed square and extends into the gaps 262, 263, 2852, and 2853.

[0106] In this embodiment, although the shape of the third conductive layer 260 can be circular, square, or pentagonal, and the shape of the fourth conductive layer 270 and the shape of the fourth conductive layer 270 can be circular, square, or pentagonal, the present disclosure does not limit the shape of the third conductive layer 260, the shape of the fourth conductive layer 270, and the shape of the fourth conductive layer 270, as long as the fourth conductive layer 270 and the fourth conductive layer 271 can be restricted within the range of the shape of the third conductive layer 260 or within the range of the shape of the bottom conductive layer 285 during fabrication.

[0107] In summary, in the electronic device of the present disclosure embodiment, through the arrangement of at least two dielectric layers (i.e., the first dielectric layer and the second dielectric layer), and by disposing the first conductive layer and the second conductive layer on different dielectric layers respectively, the first conductive layer and the second conductive layer do not need to be disposed in the same dielectric layer, so as to reduce the problem of damage to the first conductive layer and the second conductive layer during fabrication. In this embodiment, since the loss tangent Df of at least one of the first dielectric layer and the second dielectric layer is less than or equal to 0.1 and greater than 0 (i.e., 0 < Df ≤ 0.1), the loss of electromagnetic waves in the first dielectric layer and the second dielectric layer can be reduced, and thus the emission efficiency of electromagnetic waves can be better. In this embodiment, since the shape of the third conductive layer (or the shape of the bottom conductive layer) can enclose the shape of the fourth conductive layer, the fourth conductive layer can be restricted within the range of the shape of the third conductive layer (or within the range of the shape of the bottom conductive layer) during fabrication, and thus the problem of the fourth conductive layer overflowing outside the range of the shape of the third conductive layer (or outside the range of the shape of the bottom conductive layer) during fabrication can be reduced.

[0108] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, and are not intended to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An electronic device comprising multiple units, characterized in that, Each of the plurality of units includes: An integrated substrate, wherein the integrated substrate comprises: A first dielectric layer has a first side and a second side opposite to the first side; A first conductive layer is disposed on the first side; The second dielectric layer has a third side facing the second side and a fourth side opposite to the third side; and A second conductive layer is disposed on the fourth side and has a slot, wherein the loss tangent of at least one of the first dielectric layer and the second dielectric layer is less than or equal to 0.1 and greater than 0. Multiple conductive structures are disposed on the integrated substrate, and each of the multiple conductive structures includes a third dielectric layer, a third conductive layer, a fourth dielectric layer, and a fourth conductive layer; A wafer, surrounded by the fourth conductive layer and electrically connected to the plurality of conductive structures; and The antenna element is surrounded by the fourth conductive layer. The slots are provided corresponding to the first conductive layer, and the slots are surrounded by the fourth conductive layer. The total thickness of the first and second dielectric layers is T1, and the total thickness of the third and fourth dielectric layers is T2. The ratio of T1 to T2 is between 2 and 20. The total thickness of the first and second dielectric layers is less than half the wavelength of the electromagnetic wave emitted by the electronic device and greater than 100 micrometers. The third conductive layer comprises a first portion and a second portion, wherein the first portion is electrically connected to the wafer, and the top surface of the second portion is in direct contact with the fourth conductive layer.

2. The electronic device according to claim 1, characterized in that, The third side is combined with the second side.

3. The electronic device according to claim 2, characterized in that, There is an air gap between the second side and the third side.

4. The electronic device according to claim 2, characterized in that, The third side is attached to the second side by an adhesive.

5. An electronic device comprising a plurality of units, characterized in that, Each of the plurality of units includes: An integrated substrate, comprising a first dielectric layer and a second dielectric layer; and Multiple conductive structures are disposed on the integrated substrate, and each of the multiple conductive structures includes: Third dielectric layer; Fourth dielectric layer; A through-hole is provided in the third dielectric layer; A third conductive layer is disposed on the third dielectric layer; An opening is provided in the third conductive layer; A fourth conductive layer is disposed on the third conductive layer; and A conductor is disposed between the second dielectric layer and the fourth dielectric layer. The fourth conductive layer directly contacts the top surface of the third conductive layer and passes through the opening. The total thickness of the first and second dielectric layers is T1, and the total thickness of the third and fourth dielectric layers is T2. The ratio of T1 to T2 is between 2 and 20. The third conductive layer comprises a first portion and a second portion, wherein the first portion is electrically connected to the wafer, and the second portion is electrically connected to the conductor through the fourth conductive layer.

6. The electronic device according to claim 5, characterized in that, Each of the plurality of conductive structures further includes: A bottom conductive layer is disposed between the third dielectric layer and the third conductive layer, wherein the third conductive layer directly contacts the bottom conductive layer.

7. The electronic device according to claim 5, characterized in that, The conductor is disposed on the fourth dielectric layer, and the fourth dielectric layer is bonded to the third dielectric layer.

8. The electronic device according to claim 5, characterized in that, In the normal direction of the electronic device, the shape of the third conductive layer corresponds to the shape of the fourth conductive layer.

9. The electronic device according to claim 5, characterized in that, In the normal direction of the electronic device, the plurality of conductive structures surround one of the plurality of cells.

10. The electronic device according to claim 9, characterized in that, The integrated substrate also includes: A second conductive layer is disposed between the second dielectric layer and the fourth dielectric layer. The fourth conductive layer is electrically connected to the second conductive layer.

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