Hiccup mode control circuit for DC-DC converter, and DC-DC converter

Abstract

Embodiments of the present disclosure provide a hiccup mode control circuit for a DC-DC converter. The hiccup mode control circuit includes: a timing circuit, a logic control circuit, and an output circuit. The timing circuit generates first and second indication signals according to an overcurrent indication signal of the DC-DC converter, provides the first indication signal to the output circuit, and provides the second indication signal to the logic control circuit. The first indication signal flips to an active level when a first time period elapses from when the overcurrent indication signal flips to an active level. The second indication signal flips to an active level when a second time period elapses from when the overcurrent indication signal flips to an active level. The first time period is longer than the second time period. The logic control circuit generates a logic control signal according to the overcurrent indication signal, a zero current indication signal of the DC-DC converter, and the second indication signal, and provides the logic control signal to the output circuit. The output circuit generates a hiccup mode indication signal according to the first indication signal and the logic control signal.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of integrated circuit technologies, and more particularly, to a hiccup mode control circuit for a DC-DC converter and a DC-DC converter. Background Art

[0002] Zero current detection (ZCD) is a function of a DC-DC converter for detecting the zero value of the inductor current. The inductor current corresponding to when the ZCD signal is flipped to an effective level is denoted as IL. ZCD If IL ZCD is adjusted too high or too low, the efficiency of the DC-DC converter will be reduced. Therefore, when designing a DC-DC converter, IL ZCD is generally adjusted to be close to 0A. However, the pre-designed IL ZCD will also vary with factors such as process corner, temperature, output voltage, etc., and thus will be negative under some operating conditions.

[0003] With the increasingly wide application of DC-DC converters, more attention and emphasis have been paid to the fault detection and circuit protection of DC-DC converters. Hiccup is an overcurrent protection method for DC-DC converters. When the output of the DC-DC converter is short-circuited for a long time, the HICCUP signal can be used to indicate turning off the DC-DC converter to reduce the heat generated by the short-circuit current. For a buck DC-DC converter (BUCK), since the inductor current is large when an overcurrent occurs in the DC-DC converter, in order to prevent the large current from flowing through the body diode of the lower transistor and damaging the lower transistor after turning off the DC-DC converter, it is necessary to keep the lower transistor conducting for a period of time until the inductor current is discharged to 0A before turning off the DC-DC converter. Therefore, the ZCD signal is often used to control the DC-DC converter to enter the HICCUP mode (for example, the DC-DC converter enters the HICCUP mode when the ZCD signal is flipped to a high level), and the DC-DC converter is turned off. After entering the HICCUP mode, a timer is needed to count to a fixed time (such as 12 ms) before exiting the HICCUP mode. After exiting the HICCUP mode, the DC-DC converter can be restarted. Summary of the Invention

[0004] Embodiments described herein provide a hiccup mode control circuit for a DC-DC converter and a DC-DC converter.

[0005] According to a first aspect of the present disclosure, there is provided a hiccup mode control circuit for a DC-DC converter. The hiccup mode control circuit includes: a timing circuit, a logic control circuit, and an output circuit. Among them, the timing circuit is configured to: generate a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, provide the first indication signal to the output circuit via a first node, and provide the second indication signal to the logic control circuit via a second node. Among them, the first indication signal flips to an active level when a first time period has elapsed since the overcurrent indication signal flips to an active level. The second indication signal flips to an active level when a second time period has elapsed since the overcurrent indication signal flips to an active level. The first time period is longer than the second time period. The logic control circuit is configured to: generate a logic control signal according to the overcurrent indication signal, a zero current indication signal of the DC-DC converter, and the second indication signal, and provide the logic control signal to the output circuit via a third node. The output circuit is configured to: generate a hiccup mode indication signal according to the first indication signal and the logic control signal.

[0006] In some embodiments of the present disclosure, the active level of the zero current indication signal indicates that the inductor current of the DC-DC converter drops to 0 amperes.

[0007] In some embodiments of the present disclosure, when the overcurrent indication signal is at an active level and one of the zero current indication signal and the second indication signal of the DC-DC converter flips to an active level, the logic control signal flips to an active level.

[0008] In some embodiments of the present disclosure, when the first indication signal is at an inactive level and the logic control signal is at an active level, the hiccup mode indication signal is at a first level to indicate entry into the hiccup mode.

[0009] In some embodiments of the present disclosure, when the first indication signal is at an active level, the hiccup mode indication signal is at a second level to indicate exit from the hiccup mode.

[0010] In some embodiments of the present disclosure, the inactive level of the first indication signal is a high level. The active level of the first indication signal is a low level.

[0011] In some embodiments of the present disclosure, the active level of the second indication signal is a high level. The inactive level of the second indication signal is a low level.

[0012] In some embodiments of the present disclosure, the active level of the logic control signal is a high level. The inactive level of the logic control signal is a low level.

[0013] In some embodiments of the present disclosure, the active level of the overcurrent indication signal is a high level. The inactive level of the overcurrent indication signal is a low level.

[0014] In some embodiments of the present disclosure, the valid level of the zero-current indication signal is a high level. The invalid level of the zero-current indication signal is a low level.

[0015] In some embodiments of the present disclosure, the first level is a high level. The second level is a low level.

[0016] In some embodiments of the present disclosure, the logic control circuit includes: an inverter, a first NOR gate, and a second NOR gate. Among them, the input terminal of the inverter is provided with an over-current indication signal. The output terminal of the inverter is coupled to the first input terminal of the first NOR gate. The second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate. The output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate and a third node. The second input terminal of the second NOR gate is provided with a zero-current indication signal. The third input terminal of the second NOR gate is coupled to a second node.

[0017] In some embodiments of the present disclosure, the output circuit includes: an AND gate. Among them, the first input terminal of the AND gate is coupled to a first node. The second input terminal of the AND gate is coupled to the third node. A hiccup mode indication signal is output from the output terminal of the AND gate.

[0018] In some embodiments of the present disclosure, the over-current indication signal of the DC-DC converter flips to the valid level when the number of times the inductor current of the DC-DC converter reaches the over-current peak value is equal to the threshold number of times.

[0019] In some embodiments of the present disclosure, the threshold number of times is equal to 7.

[0020] In some embodiments of the present disclosure, the first time period is 12 ms.

[0021] In some embodiments of the present disclosure, the second time period is 6 ms.

[0022] According to a second aspect of the present disclosure, there is provided a hiccup mode control circuit for a DC-DC converter. The hiccup mode control circuit includes: a timing circuit, an inverter, a first NOR gate, a second NOR gate, and an AND gate. Among them, the timing circuit is configured to: generate a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, provide the first indication signal to a first input terminal of the AND gate, and provide the second indication signal to a third input terminal of the second NOR gate. Among them, the first indication signal flips to an active level when a first time period elapses since the overcurrent indication signal flips to an active level. The second indication signal flips to an active level when a second time period elapses since the overcurrent indication signal flips to an active level. The first time period is longer than the second time period. The input terminal of the inverter is provided with the overcurrent indication signal. The output terminal of the inverter is coupled to the first input terminal of the first NOR gate. The second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate. The output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate and the second input terminal of the AND gate. The second input terminal of the second NOR gate is provided with a zero current indication signal of the DC-DC converter. A hiccup mode indication signal is output from the output terminal of the AND gate.

[0023] According to a third aspect of the present disclosure, there is provided a DC-DC converter. The DC-DC converter includes the hiccup mode control circuit according to the first aspect or the second aspect of the present disclosure. Description of the Drawings

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly described below. It should be understood that the following described drawings only relate to some embodiments of the present disclosure and do not limit the present disclosure, where:

[0025] Figure 1 is an exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter;

[0026] Figure 2 is for Figure 1 some signal timing diagrams of the hiccup mode control circuit shown;

[0027] Figure 3 is a schematic block diagram of a hiccup mode control circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0028] Figure 4 is an exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter according to an embodiment of the present disclosure;

[0029] Figure 5 is for Figure 3 or Figure 4 some exemplary signal timing diagrams of the hiccup mode control circuit shown; and

[0030] Figure 6 is for Figure 3 or Figure 4 Another exemplary timing diagram of some signals of the hiccup mode control circuit shown.

[0031] In the drawings, reference numerals with the same last two digits correspond to the same elements. It should be noted that the elements in the drawings are schematic and not drawn to scale. Detailed Description of the Invention

[0032] In order to make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall also fall within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Further, it will be understood that terms such as those defined in commonly used dictionaries shall be interpreted as having a meaning that is consistent with their meaning in the context of the specification and the relevant art and will not be interpreted in an idealized or overly formal manner unless expressly so defined herein. As used herein, a statement that two or more parts are "connected" or "coupled" together shall mean that the parts are directly joined together or joined through one or more intermediate components. Additionally, terms such as "first" and "second" are used only to distinguish one component (or part of a component) from another component (or another part of a component).

[0034] Figure 1 An exemplary circuit diagram of a hiccup mode control circuit 100 for a DC-DC converter is shown. The hiccup mode control circuit 100 includes: a timer CNT, an inverter NG, a first NOR gate NOR1, a second NOR gate NOR2, and an AND gate. The DC-DC converter is, for example, a buck DC-DC converter (BUCK).

[0035] After the inductor current of the DC-DC converter experiences overcurrent and, for example, 7 peaks of the inductor current occur (the peaks that appear in the overcurrent situation can be referred to as "overcurrent peaks" in the context), the DC-DC converter can cause the overcurrent indication signal Cycle_7 to flip to a high level. The overcurrent indication signal Cycle_7 is provided to the input terminal of the inverter NG. The output terminal of the inverter NG is coupled to the first input terminal of the first NOR gate NOR1. The second input terminal of the first NOR gate NOR1 is coupled to the output terminal of the second NOR gate NOR2. The output terminal of the first NOR gate NOR1 is coupled to the first input terminal of the second NOR gate NOR2. The ZCD signal is provided to the second input terminal of the second NOR gate NOR2. After the overcurrent indication signal Cycle_7 flips to a high level, the lower transistor of the DC-DC converter remains on, enabling the inductor current to continue to decrease to 0A. After detecting that the inductor current is discharged to 0A, the ZCD signal flips to a high level. When the ZCD signal flips to a high level, the signal RESET output from the output terminal of the first NOR gate NOR1 flips to a high level. The signal RESET is provided to the enable terminal of the timer CNT. Therefore, the timer CNT starts timing from when the signal RESET flips to a high level, and at this time, the output signal S12 of the timer CNT is at a high level. Since both input terminals of the AND gate AND are at a high level, the signal HICCUP output by the AND gate AND flips to a high level, thereby controlling the DC-DC converter to enter the HICCUP mode. In the HICCUP mode, both the upper transistor and the lower transistor of the DC-DC converter are turned off.

[0036] When the timing of the timer CNT reaches, for example, 12 ms, the output signal S12 of the timer CNT flips to a low level, thereby causing the signal HICCUP to flip to a low level to indicate that the DC-DC converter exits the HICCUP mode. After the DC-DC converter exits the HICCUP mode, the DC-DC converter restarts.

[0037] Figure 2 Shown for Figure 1Timing diagram of some signals of the hiccup mode control circuit shown. After, for example, 7 overcurrent peaks appear in the inductor current IL, at time t1, the overcurrent indication signal Cycle_7 flips to high level. After a period of time, the inductor current IL drops to 0A at time t2, so a high-level pulse appears in the ZCD signal. Starting from time t2, the timer CNT starts timing, and the signal HICCUP flips to high level to control the DC-DC converter to enter the HICCUP mode. In the HICCUP mode, the enable signal ENDC of the DC-DC converter flips to low level, so that both the upper and lower switches of the DC-DC converter are turned off. Starting from time t2, when it reaches 12 ms at time t3, the signal HICCUP flips to low level to indicate that the DC-DC converter exits the HICCUP mode. After the DC-DC converter exits the HICCUP mode, the enable signal ENDC of the DC-DC converter flips to high level to control the DC-DC converter to restart.

[0038] As described above, the pre-designed IL ZCD will also vary with factors such as process corner, temperature, output voltage, etc., and thus be negative under some working conditions. When IL ZCD deviates to a negative value, in the HICCUP mode, since the output voltage of the DC-DC converter is close to 0V, the inductor current will not drop to a negative value, so the ZCD signal cannot flip to high level, resulting in the DC-DC converter being unable to enter the HICCUP mode and the lower switch remaining on, and the DC-DC converter being unable to restart. In addition, the 12-ms timing starts when the signal HICCUP flips to high level, that is, starts timing from when the ZCD signal flips to high level. Since the value of IL ZCD is unstable, if timing starts from when the ZCD signal flips to high level, a more accurate 12 ms cannot be obtained, so the accurate time to exit the HICCUP mode cannot be obtained.

[0039] In view of the above problems, embodiments of the present disclosure propose a hiccup mode control circuit for a DC-DC converter. Figure 3 A schematic block diagram of a hiccup mode control circuit 300 for a DC-DC converter according to an embodiment of the present disclosure is shown. The hiccup mode control circuit 300 includes: a timing circuit 310, a logic control circuit 320, and an output circuit 330.

[0040] The timing circuit 310 may be coupled to the output circuit 330 via the first node N1. The timing circuit 310 may be coupled to the logic control circuit 320 via the second node N2. The timing circuit 310 may be configured to: generate a first indication signal S12 and a second indication signal Cycle_6ms according to the overcurrent indication signal Cycle_7 of the DC-DC converter, provide the first indication signal S12 to the output circuit 330 via the first node N1, and provide the second indication signal Cycle_6ms to the logic control circuit 320 via the second node N2. Wherein, the first indication signal S12 flips to the active level when a first time period elapses from the moment when the overcurrent indication signal Cycle_7 flips to the active level. The second indication signal Cycle_6ms flips to the active level when a second time period elapses from the moment when the overcurrent indication signal Cycle_7 flips to the active level. The first time period is longer than the second time period. In some embodiments of the present disclosure, the first time period is 12 ms. The second time period is 6 ms.

[0041] In some embodiments of the present disclosure, the inactive level of the first indication signal S12 is the high level. The active level of the first indication signal S12 is the low level. The active level of the second indication signal Cycle_6ms is the high level. The inactive level of the second indication signal Cycle_6ms is the low level. The active level of the overcurrent indication signal Cycle_7 is the high level. The inactive level of the overcurrent indication signal Cycle_7 is the low level.

[0042] In some embodiments of the present disclosure, the overcurrent indication signal Cycle_7 of the DC-DC converter flips to the active level when the number of times the inductor current of the DC-DC converter reaches the overcurrent peak value is equal to the threshold number of times. In some embodiments of the present disclosure, the threshold number of times is equal to 7.

[0043] The logic control circuit 320 may be coupled to the timing circuit 310 via the second node N2. The logic control circuit 320 may be coupled to the output circuit 330 via the third node N3. The logic control circuit 320 may be configured to: generate a logic control signal RESET according to the overcurrent indication signal Cycle_7, the zero current indication signal ZCD of the DC-DC converter, and the second indication signal Cycle_6ms, and provide the logic control signal RESET to the output circuit 330 via the third node N3. In some embodiments of the present disclosure, the active level of the zero current indication signal ZCD indicates that the inductor current of the DC-DC converter drops to 0 amperes. In some other embodiments of the present disclosure, due to factors such as process corner, temperature, output voltage, etc., the active level of the zero current indication signal ZCD indicates that the inductor current of the DC-DC converter drops to a negative value.

[0044] The output circuit 330 may be coupled to the timing circuit 310 via the first node N1. The output circuit 330 may be coupled to the logic control circuit 320 via the third node N3. The output circuit 330 may be configured to generate a hiccup mode indication signal HICCUP according to the first indication signal S12 and the logic control signal RESET.

[0045] In some embodiments of the present disclosure, when the overcurrent indication signal Cycle_7 is at an effective level and one of the zero current indication signal ZCD of the DC-DC converter and the second indication signal Cycle_6ms flips to an effective level, the logic control signal RESET flips to an effective level.

[0046] In some embodiments of the present disclosure, when the first indication signal S12 is at an invalid level and the logic control signal RESET is at an effective level, the hiccup mode indication signal HICCUP is at a first level to indicate entering the hiccup mode. When the first indication signal S12 is at an effective level, the hiccup mode indication signal HICCUP is at a second level to indicate exiting the hiccup mode.

[0047] In some embodiments of the present disclosure, the effective level of the logic control signal RESET is a high level. The invalid level of the logic control signal RESET is a low level. The effective level of the zero current indication signal ZCD is a high level. The invalid level of the zero current indication signal ZCD is a low level. The first level is a high level. The second level is a low level.

[0048] The hiccup mode control circuit according to an embodiment of the present disclosure introduces timing control in parallel with the zero current indication signal ZCD control. When the zero current indication signal ZCD can flip to a high level, the DC-DC converter can be made to enter the HICCUP mode through the zero current indication signal ZCD. When IL ZCD deviates to a negative value and the zero current indication signal ZCD cannot flip to a high level, after the lower transistor is turned on for a second time period (e.g., 6 ms), the DC-DC converter is forced to enter the HICCUP mode, which will not affect the restart of the DC-DC converter.

[0049] In addition, the timing (the first time period) for exiting the HICCUP mode starts from when the overcurrent indication signal Cycle_7 flips to an effective level, rather than when the zero current indication signal ZCD flips to an effective level. By looking at the time corresponding to the last peak of the inductor current before the DC-DC converter enters the HICCUP mode, the exit time of the HICCUP mode can be accurately obtained.

[0050] Figure 4An exemplary circuit diagram of a hiccup mode control circuit for a DC-DC converter according to an embodiment of the present disclosure is shown. The timing circuit 410 may be a timer. The overcurrent indication signal Cycle_7 is provided to the enable terminal EN of the timer. The timer starts timing from when the overcurrent indication signal Cycle_7 flips to the high level. When the timing reaches the second time period (e.g., 6 ms), the second indication signal Cycle_6ms flips to the effective level. When the timing reaches the first time period (e.g., 12 ms), the first indication signal S12 flips to the effective level.

[0051] The logic control circuit 420 may include: an inverter NG, a first nor gate NOR1, and a second nor gate NOR2. Among them, the input terminal of the inverter NG is provided with the overcurrent indication signal Cycle_7. The output terminal of the inverter NG is coupled to the first input terminal of the first nor gate NOR1. The second input terminal of the first nor gate NOR1 is coupled to the output terminal of the second nor gate NOR2. The output terminal of the first nor gate NOR1 is coupled to the first input terminal of the second nor gate NOR2 and the third node N3. The second input terminal of the second nor gate NOR2 is provided with the zero current indication signal ZCD. The third input terminal of the second nor gate NOR2 is coupled to the second node N2.

[0052] The output circuit 430 may include: an and gate AND. Among them, the first input terminal of the and gate AND is coupled to the first node N1. The second input terminal of the and gate AND is coupled to the third node N3. The hiccup mode indication signal HICCUP is output from the output terminal of the and gate AND.

[0053] Those skilled in the art should understand that variations made to the Figure 4 circuit shown based on the above inventive concept should also fall within the protection scope of the present disclosure. In this variation, the effective levels of each signal and the gate circuits may also have settings different from those of the Figure 4 example shown.

[0054] Next, in combination with Figure 5 and Figure 6 the working principle of the hiccup mode control circuit according to an embodiment of the present disclosure will be described.

[0055] As Figure 5 and Figure 6 shown, the overcurrent indication signal Cycle_7 flips to the high level when the number of times the inductor current IL of the DC-DC converter reaches the overcurrent peak value is equal to 7 times (at time T1). The timer starts counting (represented by CNT). Before the timing reaches the second time period (e.g., 6 ms), the second indication signal Cycle_6ms is at the low level. Before the timing reaches the first time period (e.g., 12 ms), the first indication signal S12 (not shown in ​ and ​ ) is at the high level.

[0056] Since the input signal of the inverter NG is the overcurrent indication signal Cycle_7 at a high level, the output signal of the inverter NG is a low-level signal. This low-level signal is provided to the first input terminal of the first NOR gate NOR1.

[0057] When the zero-current indication signal ZCD can be inverted to a high level (at time T2) (such as ​ the example), the second NOR gate NOR2 outputs a low-level signal. At this time, both input terminals of the first NOR gate NOR1 are input with low-level signals, so the output logic control signal RESET is inverted to a high level. Since both input terminals of the AND gate AND are input with high-level signals, the output hiccup mode indication signal HICCUP is inverted to a high level at time T2, causing the DC-DC converter to enter the HICCUP mode. In the HICCUP mode, the enable signal ENDC of the DC-DC converter is inverted to a low level, so that both the upper and lower switches of the DC-DC converter are turned off.

[0058] At time T3, when the timing reaches the first time period (for example, 12 ms), the first indication signal S12 is inverted to a low level. Therefore, the hiccup mode indication signal HICCUP output by the AND gate AND is inverted to a low level at time T3, causing the DC-DC converter to exit the HICCUP mode, and the enable signal ENDC of the DC-DC converter is inverted to a high level, thereby controlling the DC-DC converter to restart. From ​ it can be seen that the time difference between time T1 and time T3 is 12 ms.

[0059] When the zero-current indication signal ZCD cannot be inverted to a high level (such as ​ the example), at time T2', when the timing reaches the second time period (for example, 6 ms), the second indication signal Cycle_6ms is inverted to a high level. The second NOR gate NOR2 outputs a low-level signal. At this time, both input terminals of the first NOR gate NOR1 are input with low-level signals, so the output logic control signal RESET is inverted to a high level. Since both input terminals of the AND gate AND are input with high-level signals, the output hiccup mode indication signal HICCUP is inverted to a high level at time T2', causing the DC-DC converter to enter the HICCUP mode. In the HICCUP mode, the enable signal ENDC of the DC-DC converter is inverted to a low level, so that both the upper and lower switches of the DC-DC converter are turned off.

[0060] At time T3, when the timing reaches the first time period (e.g., 12 ms), the first indication signal S12 flips to a low level. Therefore, the hiccup mode indication signal HICCUP output by the AND gate flips to a low level at time T3, causing the DC-DC converter to exit the HICCUP mode, and the enable signal ENDC of the DC-DC converter flips to a high level, thereby controlling the DC-DC converter to restart. From ​ It can be seen that the time difference between time T1 and time T3 is 12 ms.

[0061] From ​ and ​ As can be seen from the examples, the hiccup mode control circuit according to the embodiments of the present disclosure can control the DC-DC converter to enter the HICCUP mode even when the zero current indication signal ZCD cannot flip to a high level by introducing timing control parallel to the zero current indication signal ZCD control, without affecting the restart of the DC-DC converter. And the time for the DC-DC converter to exit the HICCUP mode is clear.

[0062] In summary, the hiccup mode control circuit according to the embodiments of the present disclosure introduces timing control parallel to the zero current indication signal ZCD control. When the zero current indication signal ZCD can flip to a high level, the DC-DC converter can be made to enter the HICCUP mode through the zero current indication signal ZCD. When the IL ZCD deviates to a negative value and the zero current indication signal ZCD cannot flip to a high level, after the lower transistor is turned on for the second time period (e.g., 6 ms), the DC-DC converter is forced to enter the HICCUP mode, without affecting the restart of the DC-DC converter. In addition, the timing (the first time period) for exiting the HICCUP mode starts from when the overcurrent indication signal Cycle_7 flips to a valid level, rather than from when the zero current indication signal ZCD flips to a valid level. By checking the time corresponding to the last peak of the inductor current before the DC-DC converter enters the HICCUP mode, the exit time of the HICCUP mode can be accurately obtained.

[0063] Unless the context clearly indicates otherwise, the singular forms of words used in this specification and the appended claims include the plural, and vice versa. Thus, when referring to the singular, it generally includes the corresponding plural. Similarly, the terms "comprising" and "including" will be interpreted as inclusive rather than exclusive. Likewise, the terms "including" and "or" should be interpreted as inclusive, unless such an interpretation is expressly prohibited herein. Where the term "example" is used in this specification, particularly when it is located after a group of terms, the "example" is merely exemplary and illustrative and should not be considered exclusive or extensive.

[0064] Further aspects and scope of adaptability will become apparent from the description provided herein. It should be understood that various aspects of the present application can be implemented alone or in combination with one or more other aspects. It should also be understood that the description and specific embodiments herein are for illustrative purposes only and are not intended to limit the scope of the present application.

[0065] The above has described several embodiments of the present disclosure in detail. However, it is obvious that those skilled in the art can make various modifications and variations to the embodiments of the present disclosure without departing from the spirit and scope of the present disclosure. The protection scope of the present disclosure is defined by the appended claims.

Claims

1. A hiccup mode control circuit for a DC-DC converter, comprising: A timing circuit, a logic control circuit, and an output circuit, wherein the timing circuit is configured to: generate a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, provide the first indication signal to the output circuit via a first node, and provide the second indication signal to the logic control circuit via a second node; wherein the first indication signal flips to an active level when a first time period elapses since the overcurrent indication signal flips to an active level, and the second indication signal flips to an active level when a second time period elapses since the overcurrent indication signal flips to an active level, and the first time period is longer than the second time period; the logic control circuit is configured to: generate a logic control signal according to the overcurrent indication signal, a zero current indication signal of the DC-DC converter, and the second indication signal, and provide the logic control signal to the output circuit via a third node; the output circuit is configured to: generate a hiccup mode indication signal according to the first indication signal and the logic control signal.

2. The hiccup mode control circuit according to claim 1, wherein, The active level of the zero current indication signal indicates that the inductor current of the DC-DC converter drops to 0 A.

3. The hiccup mode control circuit according to claim 1, wherein, When the overcurrent indication signal is at an active level and one of the zero current indication signal and the second indication signal of the DC-DC converter flips to an active level, the logic control signal flips to an active level.

4. The hiccup mode control circuit according to claim 1, wherein, When the first indication signal is at an inactive level and the logic control signal is at an active level, the hiccup mode indication signal is at a first level to indicate entering the hiccup mode; when the first indication signal is at an active level, the hiccup mode indication signal is at a second level to indicate exiting the hiccup mode.

5. The hiccup mode control circuit according to any one of claims 1 to 4, wherein, The inactive level of the first indication signal is a high level, and the active level of the first indication signal is a low level.

6. The hiccup mode control circuit according to claim 1, wherein, The logic control circuit includes: an inverter, a first NOR gate, and a second NOR gate, wherein the input terminal of the inverter is provided with the overcurrent indication signal, and the output terminal of the inverter is coupled to the first input terminal of the first NOR gate; the second input terminal of the first NOR gate is coupled to the output terminal of the second NOR gate, and the output terminal of the first NOR gate is coupled to the first input terminal of the second NOR gate and the third node; the second input terminal of the second NOR gate is provided with the zero current indication signal, and the third input terminal of the second NOR gate is coupled to the second node.

7. The hiccup mode control circuit according to claim 1, wherein, The output circuit includes: an AND gate, wherein the first input terminal of the AND gate is coupled to the first node, the second input terminal of the AND gate is coupled to the third node, and the hiccup mode indication signal is output from the output terminal of the AND gate.

8. The hiccup mode control circuit according to claim 1, wherein, The overcurrent indication signal of the DC-DC converter flips to an active level when the number of times the inductor current of the DC-DC converter reaches the overcurrent peak value is equal to a threshold number of times.

9. A hiccup mode control circuit for a DC-DC converter, comprising: A timing circuit, an inverter, a first NOR gate, a second NOR gate, and an AND gate, Wherein, the timing circuit is configured to: generate a first indication signal and a second indication signal according to an overcurrent indication signal of the DC-DC converter, provide the first indication signal to a first input end of the AND gate, and provide the second indication signal to a third input end of the second NOR gate; wherein, the first indication signal turns to an active level when a first time period elapses from the moment when the overcurrent indication signal turns to an active level, and the second indication signal turns to an active level when a second time period elapses from the moment when the overcurrent indication signal turns to an active level, and the first time period is longer than the second time period; The input end of the inverter is provided with the overcurrent indication signal, and the output end of the inverter is coupled to a first input end of the first NOR gate; A second input end of the first NOR gate is coupled to an output end of the second NOR gate, and an output end of the first NOR gate is coupled to a first input end of the second NOR gate and a second input end of the AND gate; A second input end of the second NOR gate is provided with a zero-current indication signal of the DC-DC converter; A hiccup mode indication signal is output from the output end of the AND gate.

10. A DC-DC converter, comprising: The hiccup mode control circuit according to any one of claims 1 to 9.

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