Optoelectronic image sensor and pixel circuit, data readout method, medium thereof

Abstract

A pixel circuit comprises a reset transistor, an amplification transistor, a row scanning transistor and a photodiode; a first electrode of the reset transistor is connected to a first level, a second electrode of the reset transistor is connected to the photodiode, a connection node between the second electrode of the reset transistor and the photodiode is a node G, and the reset transistor turns on to reset the node G to the first level; the photodiode is used for sensing light and generating a photo-generated current, and charges or discharges the node G to form a photosensitive voltage; a control electrode of the row scanning transistor is used for inputting a row scanning signal; a control electrode of the amplification transistor is connected to the node G, and the amplification transistor outputs a current related to the photosensitive voltage of the node G to a data readout line. Due to the amplification effect of the amplification transistor Ta, the gain of the output signal charge of the pixel circuit can be improved, so that the photoelectric image sensor has a higher signal-to-noise ratio. The application also discloses a photoelectric image sensor and a medium comprising the pixel circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photoelectric sensing, in particular to a photoelectric image sensor, a pixel circuit thereof, a data readout method and a medium. BACKGROUND

[0002] Flat panel image sensors based on thin-film transistor (TFT) pixel array play an increasingly important role in medical imaging, industrial electronics, consumer electronics, etc. This is mainly because the TFT image sensing array is suitable for large-area high-precision imaging, thereby facilitating the application of X-ray medical imaging to human organ and tissue detection. The TFT image sensing array has good process preparation compatibility with the photoelectric conversion and sensing layer thereon, and can be integrated at a relatively low preparation temperature, such as a scintillator layer for converting X-rays into visible light, an amorphous silicon diode layer for converting visible light into photo-generated carriers, etc. The TFT array has a pixel circuit of the order of ten million, and the photo-generated charges converted from X-rays are transferred row by row to peripheral charge amplifiers, analog-to-digital converters, digital processing circuits, etc., thereby obtaining an X-ray image with a high signal-to-noise ratio.

[0003] Please refer to Figure 1 , the traditional flat panel image sensor is based on amorphous silicon TFT (a-Si), and its array preparation method is consistent with that of a semiconductor display backplane. The device structure adopts a bottom-gate inverted stack type, the active layer is amorphous silicon, and the pixel circuit generally includes a three-terminal switching transistor Tscan. The gate of the switching transistor Tscan is connected to a row scan line Scan[n], the source is connected to a readout data line Data[m], and the drain is connected to a photodiode PD.

[0004] Please refer to Figure 2 , and its working principle is roughly as follows: 1) in the reset phase, the row scan line Scan[n] is high. For a-Si TFT, it is generally an electron conduction type, and the high level of the gate makes the switching transistor Tscan enter the conductive state. Thus, through the data line Data[m] connected to the peripheral charge amplifier, through a proper feedback loop, the voltage of the photodiode PD and its storage capacitor C PD in the pixel is initialized to the reference voltage Vref, which is generally low. 2) in the exposure integration phase, the row scan line Scan[n] is low, so that the switching transistor Tscan enters the off state. The photodiode PD begins to respond to the visible light converted from X-rays, and generates charges according to the light intensity, and the voltage of the photodiode PD and its storage capacitor C PDThe photo-generated current is formed by directional movement under the electric field of the initialized voltage. Within the exposure integration time Tint, the amount of charge accumulated by the photo-generated current Iph will reach Iph x Tint, and these charges will be stored to the storage capacitor C PD 3) In the readout stage, the row scanning line Scan[n] becomes high level, so that the switch transistor Tscan enters the conducting state. The charge on the storage capacitor C PD is transferred to the external amplification circuit row by row through the switch transistor Tscan, and is converted into a digital signal.

[0005] In the circuit shown in Figure 1 , the traditional flat panel image sensor directly stores and outputs the photo-generated current generated by the photodiode, resulting in destructive readout of the pixel charge, and the photo-generated charge disappears after one readout. Moreover, the charge transfer speed in the pixel is limited by the switch transistor, the pixel circuit output signal charge gain is less than 1, and the signal-to-noise ratio is low due to the influence of various noises.

[0006] Therefore, the traditional flat panel image sensor at least has the following disadvantages: 1) The charge transfer process is long, and due to the limitation of the parasitic resistance-capacitance (RC) delay on the row and column lines of the array, the image sensor is difficult to realize high frame rate, and there are many technical bottlenecks in real-time imaging applications. 2) The pixel charge is destructively read out, and the photo-generated charge disappears after one readout, but for X-ray imaging and other applications, multiple readouts are often required to support different imaging modes. 3) The pixel circuit output signal charge gain is less than 1, and is easily affected by various noises, so the signal-to-noise ratio is low. SUMMARY

[0007] The main technical problem solved by the present application is how to realize multiple readout of the pixel circuit and improve the signal-to-noise ratio and readout speed of the pixel circuit.

[0008] According to a first aspect, in an embodiment, a pixel circuit is provided, comprising a reset transistor, an amplification transistor, a row scanning transistor and a photodiode;

[0009] The first electrode of the reset transistor is connected to a first level, the second electrode is connected to the photodiode, and the connection node between the second electrode of the reset transistor and the photodiode is node G. The control electrode of the reset transistor is connected to a reset signal end for inputting a reset signal to turn on when the active level of the reset signal comes, and reset node G to the first level;

[0010] The photodiode is used to sense light and generate photo-generated current, charge or discharge node G, so that the voltage of node G after charging or discharging is a photosensitive voltage related to the intensity of light;

[0011] The row scanning transistor and the amplification transistor are connected between a high level and a data readout line, the potential of the data readout line is lower than the high level, the control electrode of the row scanning transistor is connected to a row scanning signal line for inputting a row scanning signal so as to be turned on when the row scanning signal arrives, the first electrode and the second electrode of the amplification transistor are connected between the high level and the data readout line; the control electrode of the amplification transistor is connected to a node G, the photosensitive voltage of the node G makes the amplification transistor in an amplification state, and during the turning on of the row scanning transistor, the amplification transistor outputs a current related to the photosensitive voltage of the node G to the data readout line.

[0012] According to the second aspect, in an embodiment, a pixel circuit is provided, comprising a reset transistor, an amplification transistor and a photodiode.

[0013] The first electrode of the reset transistor is connected to a first level, the second electrode is connected to the photodiode, the connection node between the second electrode of the reset transistor and the photodiode is node G, and the control electrode of the reset transistor is connected to a reset signal terminal for inputting a reset signal so as to be turned on when the active level of the reset signal arrives, and reset the node G to the first level.

[0014] The photodiode is used to sense light and generate a photo-generated current, charge or discharge the node G, and the voltage of the node G after charging or discharging is a photosensitive voltage related to the intensity of the light;

[0015] The amplification transistor is a double-gate transistor, the first electrode and the second electrode of the amplification transistor are connected to a high level and a data readout line respectively, the main gate of the amplification transistor is connected to the node G, and the auxiliary gate is connected to a row scanning signal line for inputting a row scanning signal so as to be turned on when the row scanning signal arrives, and the amplification transistor is in an amplification state under the control of the photosensitive voltage of the node G, and outputs a current related to the photosensitive voltage of the node G to the data readout line.

[0016] According to the third aspect, in an embodiment, a photoelectric image sensor is provided, comprising:

[0017] M row scanning signal lines extending in a first direction, and N data readout lines extending in a second direction, the M and N are integers greater than 1, and the first direction and the second direction are perpendicular;

[0018] The pixel circuit as described in the first aspect or the second aspect is located in the region formed by the intersection of the M rows and the N columns;

[0019] A charge amplifier corresponding to each of the N data readout lines, the input terminal of the charge amplifier is connected to the respective corresponding data readout line, for integrating the charge signal on the column data readout line and outputting a voltage signal.

[0020] According to a fourth aspect, a data readout method of a pixel circuit is provided in an embodiment, applied to the pixel circuit as described in the first aspect, and the method comprises:

[0021] The data readout process of each pixel circuit is sequentially divided into a reset phase, an exposure phase, and a readout phase;

[0022] In the reset phase, a reset signal is outputted, so that the reset transistor resets the node G to a first level;

[0023] In the exposure phase, light is controlled to irradiate the photodiode, so that the photodiode generates a photo-generated current due to the induction of the light, and the node G is charged or discharged, so that the voltage of the node G after the charging or discharging is a photosensitive voltage related to the light intensity;

[0024] In the readout phase, a scan signal is outputted, so that the amplification transistor is in an amplification state under the control of the photosensitive voltage of the node G, and outputs a current related to the photosensitive voltage of the node G to a data readout line.

[0025] According to a fifth aspect, a data readout method of a pixel circuit is provided in an embodiment, applied to the pixel circuit as described in the second aspect, and the method comprises:

[0026] The data readout process of each pixel circuit is sequentially divided into a reset phase, an exposure phase, and a readout phase, and the reset phase comprises a reset phase front segment and a reset phase rear segment;

[0027] In the reset phase front segment, a reset signal is outputted, and the threshold adjustment switch is turned on, so that the reset transistor resets the node G to a high level;

[0028] In the reset phase rear segment, a reset signal is outputted, and the scan signal received by the auxiliary gate is an adjustment voltage, and the threshold adjustment switch is turned off, so as to form a discharge path of the node G to the reset transistor, the amplification transistor, and the data readout line, until the threshold voltage of the amplification transistor is set to the adjustment voltage;

[0029] In the exposure phase, light is controlled to irradiate the photodiode, so that the photodiode generates a photo-generated current due to the induction of the light, and the node G is discharged, so that the voltage of the node G after the discharging is a photosensitive voltage related to the light intensity;

[0030] In the readout phase, a scan signal is outputted, so that the amplification transistor is in an amplification state under the control of the photosensitive voltage of the node G, and outputs a current related to the photosensitive voltage of the node G to a data readout line.

[0031] According to a sixth aspect, a computer readable storage medium is provided in an embodiment, on which a program is stored, which can be executed by a processor to implement the method according to the fourth aspect or the fifth aspect.

[0032] According to the pixel circuit of the above embodiment, the amplification transistor Ta is controlled to amplify by the photosensitive voltage related to the light intensity at node G, and outputs a current related to the photosensitive voltage to the data readout line. Therefore, the readout mode of the pixel circuit in the present application is non-destructive readout, and the pixel circuit can be read out more times without resetting and exposing the pixel circuit again. Compared with the destructive readout mode of the pixel circuit in the prior art, the pixel circuit in the present application can support more readout modes, and then different image processing such as mean filtering and smoothing filtering can be performed after multiple readouts to improve the signal-to-noise ratio of imaging. The amplification effect of the amplification transistor Ta can improve the gain of the output signal charge of the pixel circuit to improve the signal-to-noise ratio. After the signal-to-noise ratio is improved, the ability of the pixel circuit to detect small signals can be improved, the exposure dose can be reduced, and the dynamic working range of the pixel circuit can be expanded. Due to the maintaining effect of the photodiode PD, the voltage of the node G in the pixel remains the voltage in the exposure stage, so that the threshold voltage of the amplification transistor Ta and the gate-source voltage of the amplification transistor Ta are basically unchanged, so that the pixel circuit is read out at a constant current Ipx, and the speed of charge establishment and transfer mainly depends on the driving ability of the external charge amplifier, which is usually prepared by a standard CMOS single-crystal silicon integrated circuit process. Compared with the traditional charge transfer type TFT image sensing technology (the readout current Ipx is not constant, and the value of Ipx becomes smaller and smaller with the process of charge transfer), the circuit response and readout speed in the embodiment of the present application will be significantly improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 A structural diagram of a pixel circuit in the prior art is shown in FIG. 1;

[0034] Figure 2 A timing diagram of the pixel circuit in the prior art is shown in FIG. 2;

[0035] Figure 3 A structural diagram of a pixel circuit in an embodiment of the present application is shown in FIG. 3;

[0036] Figure 4 A structural diagram of a pixel circuit in an embodiment of the present application is shown in FIG. 4;

[0037] Figure 5 A timing diagram of the pixel circuit in an embodiment of the present application is shown in FIG. 5;

[0038] Figure 6 A structural diagram of a pixel circuit in an embodiment of the present application is shown in FIG. 6;

[0039] Figure 7 Timing diagram of pixel circuit of one embodiment of the present application;

[0040] Figure 8 Structure diagram of pixel circuit of one embodiment of the present application;

[0041] Figure 9 Structure diagram of pixel circuit of one embodiment of the present application;

[0042] Figure 10 Structure diagram of pixel circuit of one embodiment of the present application;

[0043] Figure 11 Structure diagram of pixel circuit of one embodiment of the present application;

[0044] Figure 12 Structure diagram of pixel circuit of another embodiment of the present application;

[0045] Figure 13 Timing diagram of pixel circuit of another embodiment of the present application;

[0046] Figure 14 Structure diagram of pixel circuit of another embodiment of the present application;

[0047] Figure 15 Timing diagram of pixel circuit of another embodiment of the present application;

[0048] Figure 16 Structure diagram of pixel circuit of yet another embodiment of the present application;

[0049] Figure 17 Timing diagram of pixel circuit of yet another embodiment of the present application;

[0050] Figure 18 Structure diagram of photoelectric image sensor of one embodiment of the present application;

[0051] Figure 19 Structure diagram of charge amplifier of photoelectric image sensor of one embodiment of the present application. DETAILED DESCRIPTION

[0052] The application will be described in further detail below with specific reference to the drawings. Like elements in different embodiments are denoted by like reference numerals. In the following description, numerous specific details are described to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without these specific details. In other instances, well-known structures have not been described in detail in order to avoid obscuring the application. In the following description, the terms "couple" and "coupled" refer to an electrical connection, whether direct and / or indirect, that is created by having one or more wires, cables, and / or printed materials connect one device / component / subsystem / piece of code / droplet / portion to another device / component / subsystem / piece of code / droplet / portion.

[0053] In addition, features, operations, or steps described in the specification can be combined in any suitable manner without departing from the scope of the application. Similarly, the various steps or acts in a method can be combined, reordered, or omitted without departing from the scope of the application. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0054] In this document, relational terms such as first and second, and the like can be used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms "coupled" and "connected," or the like, and variations thereof, are intended to include any connection, coupling, or relation between or among two or more entities, do not require direct or physical connections or interactions between such entities and can encompass passive or active connections or relations.

[0055] It should be noted that the transistor in the present application, unless otherwise specified, can be any structure of transistor, such as bipolar transistor (BJT), field effect transistor (FET) or thin film transistor (TFT). When the transistor is a bipolar transistor, the control electrode refers to the gate of the bipolar transistor, the first electrode can be the collector or the emitter of the bipolar transistor, and the corresponding second electrode can be the emitter or the collector of the bipolar transistor. In actual application, the "emitter" and the "collector" can be interchanged according to the signal flow direction. When the transistor is a field effect transistor, the control electrode refers to the gate of the field effect transistor, the first electrode can be the drain or the source of the field effect transistor, and the corresponding second electrode can be the source or the drain of the field effect transistor. In actual application, the "source" and the "drain" can be interchanged according to the signal flow direction. The reset transistor TS1 and the amplification transistor Ta in the embodiment of the present application are all N-type thin film transistors TFT.

[0056] In the embodiment of the present application, a transistor is added in the pixel, and through circuit topology and timing control, the transistor is in an amplification state in the data readout stage, forming an amplification circuit in the pixel, and the photo-generated current of the photodiode is amplified through the amplification transistor and then output from the pixel circuit, so that in-situ amplification of the photoelectric signal in the pixel circuit is realized. Compared with the prior art, the signal-to-noise ratio can be improved, and the charge transfer speed in the pixel is not limited by the structure in the pixel, and the charge can be repeatedly read out. The present application is described below through specific embodiments. For the convenience of description, thin film field effect transistors are taken as examples for description.

[0057] Embodiment one:

[0058] Please refer to Figure 3 The present embodiment provides a pixel circuit, which comprises a reset transistor TS1, an amplification transistor Ta, a row scanning transistor Ts2 and a photodiode PD.

[0059] The first electrode of the reset transistor TS1 is connected to a first level, the second electrode of the reset transistor TS1 is connected to the photodiode PD, and the connection node between the second electrode of the reset transistor TS1 and the photodiode PD is node G. The control electrode of the reset transistor TS1 is connected to a reset signal end, and the reset signal end is used to input a reset signal RST, so that the reset transistor TS1 is turned on when the active level of the reset signal RST comes, and the node G is reset to the first level.

[0060] The photodiode PD is used to sense light and generate a photo-generated current Iph, and the photo-generated current Iph charges or discharges the node G, so that the voltage of the node G after charging or discharging is a photosensitive voltage related to the intensity of light. In the present embodiment, the photodiode PD has a storage capacitor C PD Therefore, the photodiode PD can store the charge of the node G to maintain the voltage of the node G.

[0061] The row scanning transistor Ts2 and the amplifying transistor Ta are connected between the high level VDD and the data readout line Iout, for example, the row scanning transistor Ts2 is connected to the high level VDD, and the amplifying transistor Ta is connected to the data readout line Iout, to form a current output channel from the high level VDD, the row scanning transistor Ts2, the amplifying transistor Ta to the data readout line Iout, or the row scanning transistor Ts2 is connected to the high level VDD, and the amplifying transistor Ta is connected to the data readout line Iout, to form a current output channel from the high level VDD, the amplifying transistor Ta, the row scanning transistor Ts2 to the data readout line Iout. The potential of the data readout line Iout is lower than the high level VDD, and generally, the potential of the data readout line Iout is low. The control electrode of the row scanning transistor Ts2 is connected to the row scanning signal line, and the row scanning signal line is used to input the row scanning signal Scan[n] to drive the row scanning transistor Ts2 to turn on when the row scanning signal Scan[n] comes, so that the first electrode and the second electrode of the amplifying transistor Ta are connected between the high level VDD and the data readout line Iout. The control electrode of the amplifying transistor Ta is connected to the node G, and the photosensitive voltage of the node G makes the amplifying transistor Ta in the amplifying state, and during the conduction of the row scanning transistor Ts2, the amplifying transistor Ta outputs the current related to the photosensitive voltage of the node G to the data readout line Iout.

[0062] Please refer to Figure 4 In some embodiments, the first level connected to the first electrode (drain) of the reset transistor TS1 is the high level VDD. The second electrode (source) of the reset transistor TS1 is connected to the cathode of the photodiode PD, and the connection node between the source of the reset transistor TS1 and the cathode of the photodiode PD is the node G.

[0063] The cathode of the photodiode PD is connected to the source of the reset transistor TS1, and the anode of the photodiode PD is used to connect a bias voltage Vbias lower than the high level VDD. In general, the bias voltage Vbias is low. The photodiode PD is used to sense light and generate a photo-generated current Iph, and discharge the node G, so that the voltage of the discharged node G is a photosensitive voltage related to the intensity of the light. In this embodiment, due to the bias voltage Vbias, the photosensitive voltage of the discharged node G will not be lower than the bias voltage Vbias, and will also not be higher than the high level VDD reset by the reset transistor TS1. In this embodiment, the photo-generated current Iph generated by the photodiode PD is related to the intensity of the light, that is, the stronger the light, the greater the photo-generated current Iph. The greater the photo-generated current Iph, the more the node G is discharged and the potential is lowered to a lower photosensitive voltage, so that the voltage of the discharged node G is related to the intensity of the light and decreases with the increase of the intensity of the light. In this embodiment, the anodes of the photodiodes PD are connected to the same potential, which is called common anode connection.

[0064] Please refer to Figure 5 In this embodiment, the pixel circuit sequentially operates in the reset phase, the exposure phase, and the readout phase.

[0065] When in the reset phase, the reset signal RST outputs a high level VDD, and the row scanning signal Scan[n] outputs a low level. Only the reset transistor TS1 is turned on, and the node G is reset to a high level VDD, and the photodiode PD maintains the high level VDD of the node G. Although the high level VDD of the node G increases the gate-source voltage difference of the amplification transistor Ta and exceeds the threshold voltage of the amplification transistor Ta and makes it enter the on state, but the row scanning transistor Ts2 is cut off, so the pixel circuit does not have output current conducted to the data readout line Iout.

[0066] When in the exposure phase, the reset signal RST and the row scanning signal Scan[n] both output low levels, so that the reset transistor TS1 and the row scanning transistor Ts2 are both cut off. At this time, with different light intensities, the photodiode PD senses light and generates a photo-generated current Iph, and discharges the node G, so that the voltage of the discharged node G is a photosensitive voltage related to the intensity of the light, and the photodiode PD also maintains the photosensitive voltage of the node G.

[0067] When in the readout stage, the reset signal RST outputs low level, the row scanning signal Scan[n] outputs high level VDD, so that only the row scanning transistor Ts2 is turned on, while the amplification transistor Ta is in the amplification state under the control of the photosensitive voltage of the node G, and outputs the current related to the photosensitive voltage of the node G to the data readout line Iout. In this embodiment, the current Ipx output by the amplification transistor Ta can be represented as:

[0068]

[0069] Here V T represents the threshold voltage of the amplification transistor Ta, W Ta , L Ta are the channel width and channel length of the amplification transistor Ta respectively, μ0 represents the equivalent field effect mobility, C I is the gate dielectric layer capacitance per unit area, V REF is the source voltage of the amplification transistor Ta, V G is the voltage of the node G. It can be known that the current Ipx output by the amplification transistor Ta is related to the threshold voltage of the amplification transistor Ta and the gate-source voltage of the amplification transistor Ta in addition to the performance of the amplification transistor Ta itself.

[0070] In the embodiment, the working process of the pixel circuit shows that: 1) in the readout stage, the voltage of the node G in the pixel circuit remains the voltage in the exposure stage due to the maintaining effect of the photodiode PD, which means that the readout mode of the pixel circuit in the embodiment is non-destructive readout. Therefore, the pixel circuit can be read out more times as long as the reset and exposure actions are not performed again. Compared with the destructive readout mode of the pixel circuit in the prior art, the pixel circuit in the embodiment can support more readout modes due to the multiple readout feature, and then different image processing such as mean filtering and smoothing filtering can be performed after multiple readouts to improve the signal-to-noise ratio of imaging. 2) Due to the maintaining effect of the photodiode PD, the voltage of the node G in the pixel circuit in the embodiment remains the voltage in the exposure stage, so the threshold voltage of the amplification transistor Ta and the gate-source voltage of the amplification transistor Ta are basically unchanged, which makes the pixel circuit read out at a constant current Ipx, and the speed of charge establishment and transfer mainly depends on the driving capability of the external charge amplifier. The charge amplifier is usually prepared by a standard CMOS single-crystal silicon integrated circuit process, and its driving capability and circuit response speed are greatly improved compared with a thin-film transistor process. The traditional TFT image sensing technology is to perform charge transfer readout, and the readout current Ipx is not constant, and the value of Ipx becomes smaller and smaller with the process of charge transfer. The embodiment of the present application adopts constant current readout, and the sensing response and readout speed of the circuit will be significantly improved. 3) The current related to the photosensitive voltage of the node G is output to the data readout line Iout through the amplification of the amplification transistor Ta, which can improve the gain of the output signal charge of the pixel circuit to improve the signal-to-noise ratio. After the signal-to-noise ratio is improved, the ability to detect small signals of the pixel circuit can be improved, the exposure dose can be reduced, and the dynamic working range of the pixel circuit can be expanded.

[0071] Please refer to Figure 6 In some embodiments, the first level connected with the first electrode (drain) of the reset transistor TS1 is a low level (for example, GND). The second electrode (source) of the reset transistor TS1 is connected with the anode of the photodiode PD, and the connection node between the source of the reset transistor TS1 and the anode of the photodiode PD is the node G.

[0072] The anode of the photodiode PD is connected to the source of the reset transistor TS1, and the cathode of the photodiode PD is connected to the high voltage VDD. The photodiode PD is used to sense the light and generate the photo-generated current Iph, and charge the node G to a voltage related to the intensity of the light. In this embodiment, the bias voltage Vbias is high voltage VDD, so that the voltage of the charged node G will not be higher than the high voltage VDD, and will not be lower than the low voltage reset by the reset transistor TS1. In this embodiment, the greater the photo-generated current Iph generated by the photodiode PD, the more the node G is charged and the potential rises to a higher light-sensing voltage, so that the voltage of the charged node G is related to the intensity of the light and increases with the increase of the intensity of the light. In this embodiment, the cathode of the photodiode PD is connected to the same potential, which is called common cathode connection.

[0073] Please refer to Figure 7 In this embodiment, the pixel circuit works in the reset phase, the exposure phase and the readout phase in sequence. When in the reset phase, only the reset transistor TS1 is turned on, and the node G is reset to a low voltage, and the photodiode PD maintains the low voltage of the node G. When in the exposure phase, both the reset transistor TS1 and the row scanning transistor Ts2 are turned off, the photodiode PD senses the light and generates the photo-generated current Iph, and charges the node G to a voltage related to the intensity of the light, and the photodiode PD maintains the light-sensing voltage of the node G. When in the readout phase, only the row scanning transistor Ts2 is turned on, so that the amplification transistor Ta is in an amplification state under the control of the light-sensing voltage of the node G, and outputs a current related to the light-sensing voltage of the node G to the data readout line Iout.

[0074] Please refer to Figure 4 and Figure 6 In some embodiments, the first electrode of the row scanning transistor Ts2 is connected to the high voltage VDD, the second electrode of the row scanning transistor Ts2 is connected to the first electrode of the amplification transistor Ta, and the second electrode of the amplification transistor Ta is connected to the data readout line Iout. In this embodiment, since the current output from the second electrode of the amplification transistor Ta is to the data readout line Iout, the voltage of the second electrode of the amplification transistor Ta is prevented from rising due to the voltage drop of the row scanning transistor Ts2, so that the gate-source voltage between the control electrode and the second electrode of the amplification transistor Ta is larger, so as to increase the transconductance value of the amplification transistor Ta, and thus increase the amplification gain of the amplification transistor Ta.

[0075] In some embodiments, the amplification transistor Ta is an oxide TFT. In this embodiment, the oxide TFT has a higher carrier mobility (>10 cm 2V0, the signal charge amount S (i.e. the charge amount) = Cpx x V0, and the noise amount related to the switching of the switching transistor of the amorphous silicon TFT and the pixel internal capacitance Cpx is N. Therefore, the signal-to-noise ratio S / N of the conventional amorphous silicon image sensing scheme = Cpx x V0 / N.

[0076] In the present embodiment, because the high-quality oxide TFT amplifier is introduced into the pixel, the voltage amount V0 on the pixel internal capacitance Cpx is used to modulate the gate potential of the amplification transistor Ta, and then the amount of output current is adjusted by the amplification transistor Ta (the transconductance value of the amplification transistor Ta is gm), and the total output charge signal amount S1 is increased to V0 x gm x Tr in the amplification readout time Tr. Generally, Cpx = 1 pF, the transconductance value gm of the amplification transistor Ta is 10 uS, and the amplification readout time Tr value is 33 us, so the signal amount increase coefficient can be calculated as S1 / S = gm x Tr / Cpx (about equal to 330 times, i.e. more than 2 orders of magnitude). In terms of noise, because the pixel internal capacitance Cpx remains unchanged, and the leakage current of the oxide TFT is much lower than that of the amorphous silicon TFT (generally more than 2 orders of magnitude lower), the noise level in the present embodiment can be lower than that of the conventional amorphous silicon TFT scheme.

[0077] As can be seen from the above, the oxide TFT amplifier embedded pixel circuit in the present embodiment can achieve obvious advantages in the signal-to-noise ratio of the image sensor, and the signal amount is increased by more than 2 orders of magnitude on the basis of maintaining a low noise level, so that the signal-to-noise ratio S / N is increased by more than 2 orders of magnitude.

[0078] In some embodiments, the pixel circuit can be integrated by a transistor technology. In some embodiments, the reset transistor (TS1), the scanning transistor (TS2), and the amplification transistor (Ta) in the pixel circuit are oxide TFTs, polycrystalline silicon TFTs, amorphous silicon TFTs, or single-crystal silicon field effect transistors.

[0079] In some embodiments, for modern TFT process, there can also be heterogeneous integration of different active layer TFTs on the same substrate, so the pixel circuit can also be heterogeneous integration of multiple transistor technologies. In some embodiments, the reset transistor (TS1) and the scanning transistor (TS2) in the pixel circuit are oxide TFTs, and the amplification transistor (Ta) is a polysilicon TFT. In some embodiments, the reset transistor (TS1) and the scanning transistor (TS2) in the pixel circuit are oxide TFTs, and the amplification transistor (Ta) is an amorphous silicon TFT.

[0080] Based on the newly developed TFT device, a new type of image sensor is developed to overcome the shortcomings of traditional flat panel image sensors, realize real-time imaging and higher signal-to-noise ratio. Moreover, the new type of image sensor is not limited to the flat panel form, and can realize flexibility, bendable and curling, etc., so as to be more in line with the requirements of medical imaging and reduce the floor area of the whole detector.

[0081] In the above embodiments, the amplification transistor Ta is a single-gate transistor. At this time, the gate of the amplification transistor Ta is connected to the node G.

[0082] Please refer to Figures 8-11 In some embodiments, the amplification transistor Ta is a double-gate transistor. At this time, the main gate of the amplification transistor Ta is connected to the node G, and the auxiliary gate is used to input a predetermined voltage to adjust the threshold voltage of the amplification transistor Ta. In this embodiment, since the threshold voltage of the amplification transistor Ta is jointly adjusted by the main gate and the auxiliary gate, the output current Ipx of the amplification transistor Ta is not only adjusted by the potential of the main gate, but also adjusted by the auxiliary gate. Its specific performance is that when the voltage of the auxiliary gate rises, the threshold voltage of the amplification transistor Ta decreases, and vice versa. Therefore, by inputting a predetermined voltage through the auxiliary gate, the threshold voltage of the amplification transistor Ta can be adjusted differently, so as to be suitable for different use occasions.

[0083] Please refer to Figure 8 In some embodiments, the auxiliary gate is connected to the node G. When the auxiliary gate is connected to the node G, both the main gate and the auxiliary gate are connected to the node G, so that the output current Ipx of the amplification transistor Ta is not only adjusted by the potential of the main gate, but also adjusted by the auxiliary gate in the same direction, thereby enhancing the amplification effect of the amplification transistor Ta on the current related to the light-induced voltage of the node G.

[0084] Please refer to Figure 9In some embodiments, the auxiliary gate is connected to a high level VDD to reduce the threshold voltage of the amplification transistor Ta. Since the voltage of the auxiliary gate is increased to the high level, the threshold voltage of the amplification transistor Ta is reduced compared with the conventional case, and thus the transconductance value of the amplification transistor Ta is increased, so that the amplification effect of the amplification transistor Ta on the current related to the light sensing voltage of the node G is improved. Compared with the case where the auxiliary gate is connected to the node G, in this embodiment, since the potential of the auxiliary gate is fixed to the high level VDD, the amplification coefficient of the amplification transistor Ta can be stably improved.

[0085] Please refer to Figure 10 In some embodiments, the auxiliary gate is connected to a row scanning signal line, and when the row scanning signal Scan[n] is enabled, the threshold voltage of the amplification transistor Ta is reduced, and when the row scanning signal Scan[n] is disabled, the threshold voltage of the amplification transistor Ta is increased. Since the row scanning signal Scan[n] is at the high level VDD when it is enabled, the threshold voltage of the amplification transistor Ta is low, so that the threshold voltage is reduced compared with the conventional case, which is beneficial to improve the amplification effect of the amplification transistor Ta on the current related to the light sensing voltage of the node G. When the row scanning signal Scan[n] is disabled, it is at the low level, so that the threshold voltage of the amplification transistor Ta is high, which can reduce the influence of the leakage current of the pixel circuit in the row on the reading of the pixel circuits in other rows. In this embodiment, when the pixel circuit does not need to be read out, i.e. when the row scanning signal Scan[n] is disabled, the influence of the leakage current of the pixel circuit in the row on the reading of the pixel circuits in other rows can be reduced, and when the pixel circuit needs to be read out, i.e. when the row scanning signal Scan[n] is enabled, the amplification effect of the amplification transistor Ta on the current related to the light sensing voltage of the node G is improved, so that the potential of the auxiliary gate can be adaptively adjusted, and the transconductance value of the amplification transistor Ta can be dynamically adjusted, so that a good compromise between high gain and low leakage current can be achieved for the pixel circuit.

[0086] Please refer to Figure 11 In some embodiments, the auxiliary gate is used to connect the source of the amplification transistor Ta to increase the threshold voltage of the amplification transistor Ta, and the source of the amplification transistor Ta is used to connect a data readout line Iout at a low level to maintain the low level. Since the voltage of the auxiliary gate is reduced to the low level, the threshold voltage of the amplification transistor Ta is high, so that the amplification transistor Ta can maintain a small leakage current. This is more suitable for some occasions that require lower leakage current and higher signal-to-noise ratio.

[0087] Embodiment two:

[0088] The difference between this embodiment and the above-mentioned embodiments is that the amplification transistor Ta is a double-gate transistor. Please refer to Figure 12The embodiment provides a pixel circuit, which comprises a reset transistor TS1, an amplification transistor Ta and a photodiode PD.

[0089] The drain of the reset transistor TS1 is connected to a first level, the source of the reset transistor TS1 is connected to the photodiode PD, and a connection node between the source of the reset transistor TS1 and the photodiode PD is a node G. The gate of the reset transistor TS1 is connected to a reset signal RST terminal, the reset signal RST terminal is used for inputting a reset signal RST, so that the reset transistor TS1 is turned on when the active level of the reset signal RST comes, and the node G is reset to the first level. According to whether the photodiode PD is connected in common anode or common cathode, the first level is designed as a high level VDD or ground GND correspondingly.

[0090] The amplification transistor Ta is a double-gate transistor. The drain and the source of the amplification transistor Ta are connected to a high level VDD and a data readout line Iout respectively, the main gate of the amplification transistor Ta is connected to the node G, and the auxiliary gate of the amplification transistor Ta is connected to a row scanning signal line, the row scanning signal line is used for inputting a row scanning signal Scan[n] so that the amplification transistor Ta is turned on when the row scanning signal Scan[n] comes, and the amplification transistor Ta is in an amplification state under the control of the photosensitive voltage of the node G, and outputs a current related to the photosensitive voltage of the node G to the data readout line Iout.

[0091] In the embodiment, since the threshold voltage of the amplification transistor Ta is jointly regulated by the main gate and the auxiliary gate, the turn-on of the amplification transistor Ta is not only regulated by the potential of the main gate, but also regulated by the auxiliary gate. Specifically, when the voltage of the auxiliary gate rises, the threshold voltage of the amplification transistor Ta decreases, and the driving voltage required by the main gate when the amplification transistor Ta is turned on is smaller, and vice versa, the threshold voltage of the amplification transistor Ta increases, and the driving voltage required by the main gate when the amplification transistor Ta is turned on is larger. Therefore, the threshold voltage of the amplification transistor Ta can be regulated differently by inputting a predetermined voltage through the auxiliary gate, so as to control the turn-on and turn-off of the amplification transistor Ta.

[0092] Please refer to Figure 13 In the embodiment, the pixel circuit sequentially works in a reset phase, an exposure phase and a readout phase.

[0093] When in the reset stage, the reset signal RST outputs high level VDD, and the row scanning signal Scan[n] outputs low level. Only the reset transistor TS1 is turned on, and the node G is reset to the first level, which is maintained by the photodiode PD. At this time, no matter whether the node G is high level VDD to increase the main gate-source voltage difference of the amplification transistor Ta or low level to decrease the main gate-source voltage difference of the amplification transistor Ta, the auxiliary gate of the amplification transistor Ta is low level, so the threshold voltage of the amplification transistor Ta is high, and thus the amplification transistor Ta is in the cut-off state, and no output current of the pixel circuit is conducted to the data readout line Iout.

[0094] When in the exposure stage, the reset signal RST and the row scanning signal Scan[n] both output low level, so that the reset transistor TS1 and the amplification transistor Ta are both cut off. At this time, the photodiode PD senses the light and generates different photo-generated currents Iph according to different light intensities, and discharges or charges the node G, so that the voltage of the discharged or charged node G is the photosensitive voltage related to the light intensity, and the photodiode PD maintains the photosensitive voltage of the node G.

[0095] When in the readout stage, the reset signal RST outputs low level, and the row scanning signal Scan[n] outputs high level VDD. Only the amplification transistor Ta is turned on, and the amplification transistor Ta is in the amplification state under the control of the photosensitive voltage of the node G, and outputs the current related to the photosensitive voltage of the node G to the data readout line Iout. At this time, the auxiliary gate of the amplification transistor Ta is high level VDD, so the threshold voltage of the amplification transistor Ta is low, and thus the photosensitive voltage of the node G can make the amplification transistor Ta enter the conductive amplification state.

[0096] In the embodiment, the generation and output of the pixel circuit current Ipx are completed by adjusting the auxiliary gate potential of the amplification transistor Ta. The row scanning signal Scan[n] directly acts on the auxiliary gate of the amplification transistor Ta, thereby saving the row scanning transistor Ts2 of the first embodiment. Correspondingly, when the row scanning signal Scan[n] is high level VDD, the dual-gate amplification transistor Ta works in the readout amplification state with low threshold voltage, and when the row scanning signal Scan[n] is low level, the dual-gate amplification transistor Ta works in the cut-off state with high threshold voltage. By realizing the multi-mode application of the dual-gate amplification transistor Ta, the dual-gate amplification transistor Ta can be saved, so that the structure of the pixel circuit in the embodiment is simpler, the number of transistors is less, and it is beneficial to high-resolution image sensing.

[0097] Please refer to Figure 14 and 15In some embodiments, the control electrode of the reset transistor TS1 can be coupled to the adjacent row scan signal line. For example, the control electrode of the reset transistor TS1 of the Jth row is connected to the row scan signal line of the Kth row, and the scan timing of the Kth row is after the scan timing of the Jth row in a frame scan. In this embodiment, the row scan signal line of the Kth row pixel circuit is equivalent to the reset signal RST line of the Jth row pixel circuit, and since all pixel circuits need to receive the reset signal RST for resetting at the end of a frame scan and entering the next frame scan, the row scan signal line of the Kth row with later scan timing is used as the reset signal RST line of the Jth row with earlier scan timing, which can make the pixel circuit of the Jth row reset after outputting the current in the readout stage, so that no additional reset signal RST is needed, and the requirement and wiring of the external reset signal RST are reduced, which is beneficial to further improving the resolution of the photoelectric image sensor.

[0098] Embodiment three:

[0099] Please refer to Figure 16 In this embodiment, the first electrode of the reset transistor TS1 and the first electrode of the amplification transistor Ta are connected to the high level VDD through the threshold adjustment switch SW1, and the connection node between the first electrode of the reset transistor TS1, the first electrode of the amplification transistor Ta and the threshold adjustment switch SW1 is node D. In the reset stage, the threshold adjustment switch SW1 is first turned on, so that the reset transistor TS1 is turned on and the node G is reset to the high level VDD, and then the threshold adjustment switch SW1 is turned off again, so that the main gate and the first electrode of the amplification transistor Ta are short-circuited, forming a discharge path of the node G to the reset transistor TS1, the amplification transistor Ta and the data readout line Iout, until the threshold voltage of the amplification transistor Ta is set to the adjustment voltage VR0 applied to the auxiliary gate through the row scan signal line.

[0100] Please refer to Figure 17 In this embodiment, the pixel circuit works in the reset stage, the exposure stage and the readout stage in sequence. The reset stage includes the front part of the reset stage and the rear part of the reset stage.

[0101] In the former part of the reset stage, the reset signal RST outputs high voltage VDD, the row scanning signal Scan[n] outputs low voltage, and the threshold adjusting switch SW1 is turned on. Because the threshold adjusting switch SW1 is turned on, the first electrode of the reset transistor TS1 and the first electrode of the amplification transistor Ta are connected to high voltage VDD. At this time, only the reset transistor TS1 is turned on, and the node G is reset to high voltage VDD, and the photodiode PD maintains the high voltage VDD of the node G. Although the high voltage VDD of the node G makes the main gate-source voltage difference of the amplification transistor Ta increase, the auxiliary gate of the amplification transistor Ta is low voltage, so that the threshold voltage of the amplification transistor Ta is high, and thus the amplification transistor Ta is in the cut-off state, and the pixel circuit does not have output current conduction to the data readout line Iout.

[0102] In the latter part of the reset stage, the reset signal RST outputs high voltage VDD, the row scanning signal Scan[n] outputs preset adjusting voltage VR0, and the threshold adjusting switch SW1 is turned off. Because the threshold adjusting switch SW1 is turned off, the first electrode of the reset transistor TS1 and the first electrode of the amplification transistor Ta are connected, and the reset transistor TS1 is turned on to make the main gate of the amplification transistor Ta shorted with the first electrode. The preset adjusting voltage VR0 output by the row scanning signal Scan[n] is lower than the high voltage VDD, and can make the amplification transistor Ta conduct, so as to form a discharge path of the node G to the reset transistor TS1, the amplification transistor Ta and the data readout line Iout. With the discharge of the discharge path, the voltage of the node G gradually decreases from the high voltage VDD, and from the auxiliary gate of the amplification transistor Ta, the threshold voltage of the amplification transistor Ta increases with the decrease of the voltage on the main gate. Only when the threshold voltage of the amplification transistor Ta increases to equal the preset adjusting voltage VR0 output by the row scanning signal Scan[n], the discharge path is disconnected due to the cut-off of the amplification transistor Ta. Therefore, the process in the latter part of the reset stage actually sets the threshold voltage of the amplification transistor Ta of the pixel circuit to the preset adjusting voltage VR0, so as to compensate the threshold voltage drift of the amplification transistor Ta.

[0103] When in the exposure stage, the reset signal RST and the row scanning signal Scan[n] both output low voltage, so that the reset transistor TS1 and the amplification transistor Ta are both cut off. At this time, with the difference of the light intensity, the photodiode PD senses the light and generates different photo-generated current Iph, and discharges the node G, so that the voltage of the discharged node G is the light-sensing voltage related to the light intensity, and the photodiode PD also maintains the light-sensing voltage of the node G.

[0104] When in the readout stage, the reset signal RST outputs low level, the row scanning signal Scan[n] outputs high level VDD, so that only the row scanning transistor Ts2 is turned on, and the amplification transistor Ta is in the amplification state under the control of the photosensitive voltage of the node G, and outputs the current related to the photosensitive voltage of the node G to the data readout line Iout. At this time, since the auxiliary gate of the amplification transistor Ta is high level VDD, the threshold voltage of the amplification transistor Ta is low, so that the photosensitive voltage of the node G can make the amplification transistor Ta enter the conductive amplification state.

[0105] In the embodiment, the threshold voltage of the amplification transistor Ta (the threshold voltage seen from the auxiliary gate) is adjusted in the two stages: 1) in the latter part of the reset stage, the threshold voltage of the amplification transistor Ta is initialized to the preset adjustment voltage VR0 by the reset pull-up of the main gate of the amplification transistor Ta to high level VDD by the reset transistor TS1 and the discharge of the node G after the threshold adjustment switch SW1 is disconnected; 2) in the exposure stage, the threshold voltage of the amplification transistor Ta is linearly changed by the photo-generated current Iph of the photodiode PD, so that the value of the output current of each pixel circuit is modulated by the photo-generated current Iph of the photodiode PD.

[0106] Correspondingly, the threshold voltage of the amplification transistor Ta can be expressed as,

[0107]

[0108] Here K refers to the modulation coefficient of the voltage of the main gate of the amplification transistor Ta to the threshold voltage of the auxiliary gate side, for example, its typical value is -1, which means that when the voltage of the main gate decreases by 1V, the value of the threshold voltage seen from the auxiliary gate side increases by 1V.

[0109] In some embodiments, the threshold adjustment switch SW1 can be implemented by a single-gate or double-gate TFT, or by an external single-crystal silicon CMOS integrated technology. When the threshold adjustment switch SW1 is implemented by a TFT, 3 TFTs are needed in the pixel circuit, and the external connection line of the pixel circuit is a constant potential VDD; when the threshold adjustment switch SW1 is implemented by a single-crystal silicon CMOS, only 2 TFTs are needed in the pixel circuit, and the voltage on the external connection line of the pixel circuit is not constant.

[0110] Embodiment four:

[0111] Please refer to Figure 18 The embodiment provides an optoelectronic image sensor, which comprises M rows of row scanning signal lines extending in a first direction, N columns of data readout lines extending in a second direction, pixel circuits located in regions formed by the intersection of the M rows and the N columns, and charge amplifiers corresponding to the N columns of data readout lines one by one.

[0112] The number of row scanning signal lines and data readout lines of the photoelectric image sensor is at least one, i.e. M and N are integers greater than 1, and the first direction in which the row scanning signal lines extend and the second direction in which the data readout lines extend are perpendicular, thereby forming an array of pixel circuits.

[0113] The pixel circuit located in the region formed by the intersection of the M rows and the N columns can be any one of the pixel circuits in Embodiment 1, Embodiment 2 or Embodiment 3. The row scanning signal lines can all be connected to the driving module, and the row scanning signal lines are used to transmit the row scanning signal Scan[n] output by the driving module to the pixel circuit. The data readout line is used to transmit the current related to the light intensity output by the pixel circuit to the input end of the column charge amplifier at which the data readout line is located, and each charge amplifier is used to output a voltage signal after integrating the charge signal on the column data readout line at which the charge amplifier is located. Since the speed of charge buildup and transfer of the pixel circuit mainly depends on the driving capability of the external charge amplifier, and the charge amplifier is prepared by a standard CMOS monocrystalline silicon integrated circuit process, the driving capability and circuit response speed of the charge amplifier are greatly improved compared with the thin-film transistor process, so the charge readout speed in the embodiment of the present application will be significantly improved.

[0114] Please refer to Figure 19 In some embodiments, the charge amplifier comprises an operational amplifier and an integration capacitor. The first input end of the operational amplifier is connected to the column data readout line at which the operational amplifier is located, and the second input end of the operational amplifier is used to connect a reference voltage, so that the first input end of the operational amplifier and the column data readout line at which the operational amplifier is located maintain a low level. The first end of the integration capacitor is connected to the first input end of the operational amplifier, the second end of the integration capacitor is connected to the output end of the operational amplifier, and the integration capacitor is used to integrate the charge signal on the column data readout line. The output end of the operational amplifier is used to output a corresponding voltage signal according to the integrated charge signal of the integration capacitor. In this embodiment, the first input end of the operational amplifier is a negative phase input end, and the second input end of the operational amplifier is a positive phase input end. The reference voltage is usually a low voltage, for example, a low level. Due to the "virtual short" feature of the operational amplifier, the negative phase input end of the operational amplifier will maintain the reference voltage, for example, a low level. Again, due to the "virtual break" feature of the operational amplifier, the negative phase input end of the operational amplifier cannot receive or provide current, so the current output by the data readout line is collected by the integration capacitor, and a corresponding output voltage is induced at the output end of the operational amplifier.

[0115] Similarly to the pixel circuit described above, Figure 19 The operational amplifier can be integrated by one or more transistor technologies. For example, the operational amplifier can be integrated by all monocrystalline silicon complementary metal oxide semiconductor (CMOS) field effect transistors, or by a mixture of N-type oxide TFTs and P-type polysilicon TFTs.

[0116] In some embodiments, the operational amplifier further comprises a reset switch. The reset switch is connected in parallel across the integration capacitor. When the reset switch is closed, the operational amplifier is in a unity gain negative feedback configuration, so that the residual charge on the integration capacitor is cleared.

[0117] In some embodiments, the photoelectric image sensor further comprises M rows of reset signal RST lines extending in the first direction. The reset signal RST lines can be connected to the driving modules, and the reset signal RST lines are used to transmit the reset signal RST output by the driving modules to the control electrode of the reset transistor TS1 of the pixel circuit.

[0118] In some embodiments, when applied to the pixel circuit in Embodiment One and Embodiment Two, the control electrode of the reset transistor TS1 of the Jth row is connected to the row scan signal line of the Kth row, and in a frame scanning, the scanning timing of the Kth row is after the scanning timing of the Jth row. In this embodiment, the row scan signal line of the Kth row of the pixel circuit is equivalent to the reset signal RST line of the Jth row of the pixel circuit. Since all the pixel circuits need to receive the reset signal RST for resetting when entering the next frame scanning after the end of a frame scanning, the row scan signal line of the Kth row with later scanning timing is used as the reset signal RST line of the Jth row with earlier scanning timing, so that the pixel circuit of the Jth row can be reset after outputting the current in the readout stage, thereby eliminating the need for additional reset signal RST and reducing the requirement for external reset signal RST and wiring, which is conducive to further improving the resolution of the photoelectric image sensor.

[0119] The photoelectric image sensor of the embodiment can be a flat panel sensor or a flexible sensor. The flexible and bendable image sensor is more in line with the requirements of medical imaging and reduces the actual floor area of the detector.

[0120] The timing control process of the above-mentioned embodiments can be controlled by a computer executable program. When all or part of the functions in the above-mentioned embodiments are realized by a computer program, the program can be stored in a computer readable medium, which can include a semiconductor chip, a read-only memory, a random access memory, a magnetic disk, an optical disk, a hard disk, etc. The above-mentioned functions are realized by executing the program by a computer. For example, the program is stored in the memory of the device, and when the program in the memory is executed by the processor, all or part of the above-mentioned functions are realized. Or directly embedded in various driver chips. In addition, when all or part of the functions in the above-mentioned embodiments are realized by a computer program, the program can also be stored in a server, another computer, a disk, an optical disk, a flash disk or a mobile hard disk, etc. The storage medium is saved in the memory of the local device by downloading or copying, or the system of the local device is updated in version, and when the program in the memory is executed by the processor, all or part of the functions in the above-mentioned embodiments are realized.

[0121] The above application of specific examples to illustrate the present application, is only used to help understand the present application, and not to limit the present application. For the skilled in the art to which the present application belongs, according to the idea of the present application, can make a number of simple deduction, deformation or replacement.

Claims

1. A pixel circuit, characterized by comprising: The pixel circuit comprises a reset transistor (TS1), an amplification transistor (Ta) and a photodiode (PD); The first electrode of the reset transistor (TS1) is connected to a first level, and the second electrode is connected to the photodiode (PD). A connection node between the second electrode of the reset transistor (TS1) and the photodiode (PD) is node G. The control electrode of the reset transistor (TS1) is connected to a reset signal end for inputting a reset signal (RST) so as to be turned on when the active level of the reset signal (RST) comes, and reset node G to the first level. The photodiode (PD) is used for sensing light and generating photo-generated current, charging or discharging node G, and making the voltage of the charged or discharged node G a photosensitive voltage related to the light intensity. The amplification transistor (Ta) is a double-gate transistor. The first electrode and the second electrode of the amplification transistor (Ta) are connected to a high level (VDD) and a data readout line (Iout) respectively. The main gate of the amplification transistor (Ta) is connected to node G, and the auxiliary gate is connected to a row scanning signal line for inputting a row scanning signal so as to be turned on when the row scanning signal comes, and make the amplification transistor (Ta) be in an amplification state under the control of the photosensitive voltage of node G, and output a current related to the photosensitive voltage of node G to the data readout line (Iout). The pixel circuit sequentially works in a reset phase, an exposure phase and a readout phase. The reset transistor (TS1) is only turned on in the reset phase to reset node G to the first level. The photodiode (PD) senses light and generates photo-generated current in the exposure phase. The amplification transistor (Ta) is turned on in the readout phase and is in an amplification state under the control of the photosensitive voltage of node G. The first level is a high level (VDD). The second electrode of the reset transistor (TS1) is connected to the cathode of the photodiode (PD). The anode of the photodiode (PD) is used for connecting a bias voltage (Vbias) lower than the high level (VDD). The photosensitive voltage of node G is between the bias voltage (Vbias) and the high level (VDD), and the photosensitive voltage of node G decreases with the increase of the light intensity. The first electrode of the reset transistor (TS1) and the first electrode of the amplification transistor (Ta) are connected to the high level (VDD) through a threshold adjustment switch. In the reset phase, the threshold adjustment switch is first turned on and then disconnected to make the main gate of the amplification transistor (Ta) short-circuit with the first electrode, forming a discharging path of node G to the reset transistor (TS1), the amplification transistor (Ta) and the data readout line (Iout), until the threshold voltage of the amplification transistor (Ta) is set to an adjustment voltage applied on the auxiliary gate through the row scanning signal line.

2. The pixel circuit of claim 1, wherein, The amplification transistor (Ta) and the reset transistor (TS1) are oxide TFT, polycrystalline silicon TFT, amorphous silicon TFT or single-crystal silicon field effect transistor. Or the reset transistor (TS1) is an oxide TFT, and the amplification transistor (Ta) is a polysilicon TFT or an amorphous silicon TFT.

3. The pixel circuit of claim 1, wherein, The reset stage includes a reset stage front section and a reset stage rear section. In the reset stage front section, the threshold adjustment switch and the reset transistor (TS1) are turned on, and the node G is reset to a first level. In the reset stage rear section, the threshold adjustment switch is turned off, the scan signal received by the auxiliary gate is an adjustment voltage, and the reset transistor (TS1) is turned on, so that the threshold voltage of the amplification transistor (Ta) reaches a preset adjustment voltage due to the voltage reduction of the node G.

4. An optoelectronic image sensor, characterized by The pixel circuit comprises: M rows of row scan signal lines extending in a first direction and N columns of data readout lines extending in a second direction, wherein M and N are integers greater than 1, and the first direction and the second direction are perpendicular to each other; The pixel circuit according to any one of claims 1-3 is located in a region formed by the intersection of the M rows and the N columns; A charge amplifier corresponding to each of the N columns of data readout lines, wherein an input end of the charge amplifier is connected to the corresponding data readout line, and the charge amplifier is configured to output a voltage signal after integrating a charge signal on the corresponding data readout line.

5. The photoelectric image sensor of claim 4, wherein The charge amplifier comprises an operational amplifier and an integration capacitor. A first input end of the operational amplifier is connected to the corresponding data readout line, a second input end of the operational amplifier is configured to be connected to a reference voltage, so that the first input end of the operational amplifier and the corresponding data readout line maintain a low level, a first end of the integration capacitor is connected to the first input end of the operational amplifier, and a second end of the integration capacitor is connected to an output end of the operational amplifier, so as to integrate the charge signal on the corresponding data readout line, and the output end of the operational amplifier is configured to output a corresponding voltage signal according to the integrated charge signal of the integration capacitor.

6. The photoelectric image sensor of claim 4, wherein Further comprising M rows of reset signal lines extending in the first direction, and a control electrode of the reset transistor (TS1) is connected to the reset signal line.

7. The photoelectric image sensor of claim 4, wherein A control electrode of the reset transistor (TS1) of the Jth row is connected to a row scan signal line of the Kth row, and in a frame scanning, a scan timing of the Kth row is after a scan timing of the Jth row.

8. A data readout method of a pixel circuit, characterized by, The method is applied to the pixel circuit according to any one of claims 1-3, and the method comprises: The data readout process of each pixel circuit is sequentially divided into a reset stage, an exposure stage and a readout stage, and the reset stage includes a reset stage front section and a reset stage rear section; In the reset stage front section, a reset signal is output, and the threshold adjustment switch is turned on, so that the reset transistor (TS1) resets the node G to a high level (VDD). In the reset stage rear section, a reset signal is output, and a scan signal received by the auxiliary gate is an adjustment voltage, the threshold adjustment switch is turned off, and a discharge path of the node G to the reset transistor (TS1), the amplification transistor (Ta) and the data readout line (Iout) is formed, so as to set the threshold voltage of the amplification transistor (Ta) to the adjustment voltage. In the exposure stage, light irradiates the photodiode (PD) so that the photodiode (PD) generates a photo-generated current due to the light irradiation, discharges the node G, and makes the voltage of the discharged node G a photosensitive voltage related to the light intensity; In the readout stage, the scanning signal is outputted so that the amplification transistor (Ta) is in an amplification state under the control of the photosensitive voltage of the node G, and outputs a current related to the photosensitive voltage of the node G to the data readout line.

9. A computer-readable storage medium, characterized in that, The medium has a program stored thereon, and the program can be executed by the processor to implement the method of claim 8. The medium has a program stored thereon, and the program can be executed by the processor to implement the method of claim 8.

Images