Display device

Abstract

A display device is provided. The display device includes: a first substrate; a semiconductor layer arranged on the first substrate; a first gate conductive layer arranged on the semiconductor layer and including a scan line; a sensing line and a gate electrode; a first data conductive layer arranged on the first gate conductive layer and including a first data line, a second data line, and one electrode and another electrode of a transistor; a second data conductive layer arranged on the first data conductive layer and including a first voltage wiring and a second voltage wiring; a first electrode and a second electrode arranged on the second data conductive layer; a light emitting element, both ends of the light emitting element being arranged on the first electrode and the second electrode, respectively; and a first transistor and a second transistor, the first transistor being electrically connected to the first electrode and the first voltage wiring, and the second transistor being electrically connected to the second electrode and the first data line.

Description

Technical Field

[0001] The invention relates to a display device. Background Art

[0002] As multimedia technology develops, the importance of display devices has steadily increased. In response to this, various types of display devices such as organic light emitting displays, liquid crystal displays (LCDs), etc. have been used.

[0003] The display device is a device for displaying an image, and includes a display panel such as an organic light-emitting display panel or a liquid crystal display panel. The light-emitting display panel may include a light-emitting element (e.g., a light-emitting diode (LED)), examples of which include an organic light-emitting diode (OLED) using an organic material as a fluorescent material and an inorganic light-emitting diode using an inorganic material as a fluorescent material. Summary of the invention

[0004] Technical issues

[0005] The present invention is directed to providing a display device which allows the number of processes to be reduced by including a separate transistor configured to apply an alignment signal in a manufacturing process.

[0006] It should be noted that the disclosed aspects are not limited thereto, and other aspects not mentioned herein will be apparent to those of ordinary skill in the art through the following description.

[0007] Technical Solution

[0008] According to a disclosed embodiment, a display device includes: a first substrate; a semiconductor layer, which is disposed on the first substrate and includes a plurality of active layers; a first gate conductive layer, which is disposed on the semiconductor layer and includes a scan line and a sense line and a plurality of gate electrodes, the scan line and the sense line extend in a first direction, and the plurality of gate electrodes are disposed to partially overlap with the semiconductor layer; a first data conductive layer, which is disposed on the first gate conductive layer and includes a first data line and a second data line and one electrode and another electrode of each of a plurality of transistors, the first data line and the second data line extend in a second direction intersecting the first direction and are spaced apart from each other in the first direction; a second data conductive layer, which is disposed on the first data conductive layer and includes a first voltage wiring and a second voltage wiring, the first voltage wiring and the second voltage wiring extending in the second direction between the first data line and the second data line; a first electrode and a second electrode, the first electrode being arranged on the second data conductive layer and extending in the second direction, the second electrode being spaced apart from the first electrode and extending in the second direction; and a plurality of light emitting elements each having two ends respectively arranged on the first electrode and the second electrode, wherein the transistor comprises a first transistor and a second transistor, the first transistor having an electrode electrically connected to the first electrode and another electrode electrically connected to the first voltage wiring, and the second transistor having an electrode electrically connected to the second electrode and another electrode electrically connected to the first data line.

[0009] The transistor may further include a third transistor having one electrode electrically connected to the gate electrode of the first transistor, another electrode electrically connected to the second data line, and a gate electrode electrically connected to the scan line.

[0010] The first data conductive layer may further include an initialization voltage wiring disposed at one side of the first data line and extending in the second direction, and the transistor may further include a fourth transistor having one electrode electrically connected to the first electrode and another electrode electrically connected to the initialization voltage wiring.

[0011] The first gate conductive layer may further include an alignment signal line disposed at one side of the sensing line and extending in the first direction, and the second transistor may have a gate electrode electrically connected to the alignment signal line.

[0012] Each of the second transistor and the fourth transistor may have a gate electrode electrically connected to the sensing line.

[0013] The first gate conductive layer may further include a conductive pattern disposed to overlap the first data conductive layer and the initialization voltage wiring and electrically connected to the second data line and the drain electrode of the second transistor.

[0014] The second electrode may be electrically connected to the second voltage wiring.

[0015] The second data conductive layer may further include a first electrode conductive pattern contacting one electrode of the first transistor and the first electrode, and a second electrode conductive pattern contacting one electrode of the second transistor and the second electrode.

[0016] The display device may further include a third electrode disposed between the first electrode and the second electrode, wherein the third electrode may be electrically connected to a second voltage wiring, and the light-emitting element may include a first light-emitting element and a second light-emitting element, the first light-emitting element being disposed on the first electrode and the third electrode, and the second light-emitting element being disposed on the third electrode and the second electrode.

[0017] The display device may further include: a first gate insulating layer, arranged between the semiconductor layer and the first gate conductive layer; a first protective layer, arranged between the first gate conductive layer and the first data conductive layer; a first interlayer insulating layer, arranged between the first data conductive layer and the second data conductive layer; a first planarization layer, arranged between the second data conductive layer and the first electrode and the second electrode; and a first insulating layer, partially covering the first electrode and the second electrode, wherein the light-emitting element may be arranged on the first insulating layer.

[0018] The display device may further include: a first contact electrode provided on the first electrode and in contact with one end of each of the light emitting elements; and a second contact electrode provided on the second electrode and in contact with the other end of each of the light emitting elements.

[0019] The first electrode may include a bent portion, an extended portion, and a connecting portion, the bent portion extending in a direction different from the first direction and the second direction, the extended portion extending in the second direction and having a width greater than a width of the bent portion, the connecting portion being configured to connect the bent portion and the extended portion and extending in the second direction, and one end of each of the light emitting elements may be disposed on the extended portion of the first electrode.

[0020] The second electrode may have a symmetrical structure to the first electrode, and the other end portion of each of the light emitting elements may be disposed on an extension portion of the second electrode.

[0021] The interval between the extended portion of the first electrode and the extended portion of the second electrode may be smaller than the interval between the connected portion of the first electrode and the connected portion of the second electrode, and the shortest interval between the bent portion of the first electrode and the bent portion of the second electrode may be larger than the interval between the extended portions and smaller than the interval between the connected portions.

[0022] According to the disclosed embodiment, the display device includes: a first voltage wiring and a second voltage wiring, a first power supply voltage is applied to the first voltage wiring, and a second power supply voltage is applied to the second voltage wiring; a first data line and a second data line, through which different data signals are applied; a light emitting diode, having one end electrically connected to the first voltage wiring and the other end connected to the second voltage wiring; a first transistor, having an electrode electrically connected to one end of the light emitting diode and another electrode electrically connected to the first voltage wiring; a second transistor, having an electrode electrically connected to the other end of the light emitting diode and another electrode electrically connected to the second data line; a third transistor, having an electrode connected to the gate electrode of the first transistor and another electrode electrically connected to the first data line; and a storage capacitor, electrically connected to the gate electrode of the first transistor and one electrode of the first transistor.

[0023] The display device may further include: a scan line to which a scan signal is applied and which is electrically connected to a gate electrode of a third transistor; an alignment signal line to which an alignment signal is applied and which is electrically connected to a gate electrode of a second transistor; and a sensing line to which a sensing signal is applied, wherein the display device may further include a fourth transistor having a gate electrode electrically connected to the sensing line, an electrode electrically connected to one end of a light emitting diode, and another electrode connected to an initialization voltage wiring to which an initialization voltage is applied.

[0024] In a manufacturing mode of the display device, the second transistor and the fourth transistor may be turned on in response to signals applied by aligning the signal line and the sensing line, respectively, and the first transistor and the third transistor may be turned off.

[0025] In the manufacturing mode, the first alignment voltage applied to the initialization voltage wiring may be transmitted to one end of the light emitting diode through the fourth transistor, and the second alignment voltage applied to the second data line may be transmitted to the other end of the light emitting diode through the second transistor.

[0026] In a driving mode of the display device, a first power supply voltage may be transmitted to one end of the light emitting diode through the first transistor, and a second power supply voltage may be transmitted to the other end of the light emitting diode through the second voltage wiring.

[0027] The light-emitting diode may include a first light-emitting diode and a second light-emitting diode connected in series to each other, and in a manufacturing mode, a first alignment voltage applied to the initialization voltage wiring can be transmitted to one end of the first light-emitting diode through a fourth transistor, a third alignment voltage applied to the second data line can be transmitted to one end of the second light-emitting diode through the second transistor, and a second alignment voltage can be transmitted to the other end of the first light-emitting diode and the other end of the second light-emitting diode through the second voltage wiring.

[0028] Details of other embodiments are included in the detailed description and accompanying drawings.

[0029] Beneficial Effects

[0030] A display device according to an embodiment includes a transistor connected to one end of a light emitting diode and applying an alignment signal during a manufacturing process. The transistor substantially does not transmit a signal or may be turned off when the light emitting diode emits light, and during the manufacturing process, the transistor may be turned on and apply an alignment signal for aligning the light emitting element of the light emitting diode to the light emitting diode. Therefore, the display device may allow the number of manufacturing processes to be reduced by including electrodes separated for each pixel and by omitting a disconnection process of each electrode performed after aligning the light emitting element.

[0031] The effects according to the embodiments are not limited to the above-exemplified contents, and more various effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0033] Figure 2 is a schematic layout diagram showing wiring included in a display device according to one embodiment.

[0034] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0035] Figure 4 is a schematic plan view showing wiring provided in one pixel of a display device according to one embodiment.

[0036] Figure 5 is a layout diagram showing a plurality of conductive layers included in one sub-pixel of a display device according to an embodiment.

[0037] Figure 6 is a layout diagram showing a plurality of conductive layers included in one pixel of a display device according to an embodiment.

[0038] Figure 7 is a schematic plan view showing a plurality of electrodes and a plurality of banks included in one pixel of a display device according to one embodiment.

[0039] Figure 8 It is along Figure 7 Cross-sectional views taken along line Q1 - Q1 ′, line Q2 - Q2 ′, and line Q3 - Q3 ′.

[0040] Fig. 9 It is along Figure 7A cross-sectional view taken along line Q4-Q4' and line Q5-Q5'.

[0041] Fig.10 is a schematic cross-sectional view showing a portion of a display device according to another embodiment.

[0042] Fig.11 is a schematic diagram of a light emitting element according to an embodiment.

[0043] Fig.12 and Fig.13 1 is a schematic plan view illustrating some operations of a manufacturing process of a display device according to an embodiment.

[0044] Fig.14 is a schematic circuit diagram illustrating one operation of a manufacturing process of a display device according to one embodiment.

[0045] Fig.15 is a schematic plan view illustrating one operation of a manufacturing process of a display device according to one embodiment.

[0046] Fig.16 is a schematic plan view showing one sub-pixel of a display device according to still another embodiment.

[0047] Fig.17 yes Fig.16 Equivalent circuit diagram of a sub-pixel.

[0048] Fig.18 It is shown Fig.16 A schematic plan view of one operation of a manufacturing process of a display device.

[0049] Fig.19 It is shown Fig.16 A schematic circuit diagram of one operation of a manufacturing process of a display device.

[0050] Fig. 20 is a layout diagram showing a plurality of conductive layers included in one sub-pixel of a display device according to still another embodiment.

[0051] Fig.21 yes Fig. 20 Equivalent circuit diagram of a sub-pixel.

[0052] Fig. 22 and Fig.23 is a schematic cross-sectional view showing a portion of a display device according to still another embodiment.

[0053] Fig.24 is a plan view showing one sub-pixel of a display device according to still another embodiment.

[0054] Fig.25is a plan view showing one sub-pixel of a display device according to still another embodiment.

[0055] Fig.26 It is along Fig.25 A cross-sectional view taken along line QX-QX'. DETAILED DESCRIPTION

[0056] The invention will now be described more fully hereinafter with reference to the accompanying drawings in which preferred embodiments of the invention are shown. However, the invention may be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and these embodiments will fully convey the scope of the invention to those skilled in the art.

[0057] It will also be understood that when a layer is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Like reference numerals refer to like components throughout the specification.

[0058] It will be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, without departing from the teachings of the invention, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element.

[0059] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0060] Figure 1 is a schematic plan view of a display device according to an embodiment.

[0061] In the specification, regarding the display device 10, the term "upper", "top" or "upper surface" refers to an upper direction (i.e., one direction in the third direction DR3), and the term "lower", "bottom" and "lower surface" refers to the other direction in the third direction DR3. In addition, the terms "left", "right", "upper", and "lower" refer to directions when the display device 10 is viewed in a plan view. For example, the term "left" refers to one direction in the first direction DR1, the term "right" refers to the other direction in the first direction DR1, the term "upper" refers to one direction in the second direction DR2, and the term "lower" refers to the other direction in the second direction DR2.

[0062] Reference Figure 1, the display device 10 displays a video or a still image. The display device 10 may refer to all electronic devices that provide a display screen. For example, the display device 10 may include a television, a laptop computer, a monitor, a billboard, an Internet of Things device, a mobile phone, a smart phone, a tablet personal computer (PC), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notepad, an electronic book reader, a portable multimedia player (PMP), a navigation system, a game console, a digital camera, and a video camera that provide a display screen.

[0063] The display device 10 includes a display panel that provides a display screen. Examples of the display panel may include an inorganic light emitting diode display panel, an organic light emitting display panel, a quantum dot light emitting display panel, a plasma display panel, and a field emission display panel. Hereinafter, a case where an inorganic light emitting diode display panel is applied as an example of a display panel is shown, but the invention is not limited thereto, and a device to which the same technical spirit can be applied may be applied to other display panels.

[0064] The shape of the display device 10 may be variously changed. For example, the display device 10 may have a shape such as a rectangular shape with long horizontal sides, a rectangular shape with long vertical sides, a square shape, a quadrilateral shape whose corners (vertices) are rounded (chamfered), other polygonal shapes, or a circular shape. The shape of the display area DPA of the display device 10 may also be similar to the overall shape of the display device 10. Figure 1 , the display device 10 and the display area DPA having a rectangular shape with its horizontal sides being long are shown.

[0065] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where a picture can be displayed, and the non-display area NDA is an area where no image is displayed. The display area DPA may be referred to as an active area, and the non-display area NDA may be referred to as an inactive area. The display area DPA may substantially occupy the center of the display device 10.

[0066] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix form. The shape of each pixel PX may be a rectangular shape or a square shape in a plan view, but is not limited thereto, and the shape may be a rhombus shape in which each side thereof is inclined relative to one direction. The pixels PX may be alternately arranged in a stripe type or In addition, each of the pixels PX may include one or more light emitting elements 30 that emit light in a specific wavelength band to display a specific color.

[0067] The non-display area NDA may be disposed around the display area DPA. The non-display area NDA may completely or partially surround the display area DPA. The display area DPA has a rectangular shape, and the non-display area NDA may be disposed adjacent to four sides of the display area DPA. The non-display area NDA may form a frame of the display device 10. In each non-display area NDA, a wiring or circuit driver included in the display device 10 may be disposed, or an external device may be installed.

[0068] Figure 2 is a schematic layout diagram showing wiring included in a display device according to one embodiment.

[0069] Reference Figure 2 , the display device 10 may include a plurality of wirings. The plurality of wirings may include a scan line SCL, a sensing line SSL, an alignment signal line ASL, a data line DTL, an initialization voltage wiring VIL, a first voltage wiring VDL, and a second voltage wiring VSL, etc. In addition, although not shown in the drawings, other wirings may be further provided in the display device 10.

[0070] The scan lines SCL, the sensing lines SSL, and the alignment signal lines ASL may extend in the first direction DR1. The scan lines SCL and the sensing lines SSL may be connected to a scan driver SDR. The scan driver SDR may include a driving circuit. The scan driver SDR may be disposed at one side of the display area DPA in the first direction DR1, but the invention is not limited thereto. The scan driver SDR may be connected to a signal connection wiring CWL, and at least one end of the signal connection wiring CWL may form a pad (or pad) WPD_CW in the non-display area NDA to be connected to an external device. The alignment signal line ASL may also include a portion extending in the second direction DR2, and the portion of the alignment signal line ASL extending in the second direction DR2 may be connected to a pad WPD_AS in a pad area PDA of the non-display area NDA.

[0071] Meanwhile, in the specification, the term "connection" may mean that one component is connected to another component by physical contact, and also means that one component is connected to another component through another component. In addition, it is understood that one component and another component are integrated into one component, and a part of the integrated component is connected to another part of the integrated component. In addition, the connection between one component and another component may be interpreted as including an electrical connection through another component in addition to a direct contact connection.

[0072] The data line DTL and the initialization voltage wiring VIL may extend in a second direction DR2 intersecting the first direction DR1. In addition to the portion extending in the second direction DR2, the initialization voltage wiring VIL may also include a portion branching from it in the first direction DR1. Each of the first voltage wiring VDL and the second voltage wiring VSL may also include a portion extending in the second direction DR2 and a portion extending in the first direction DR1. The first voltage wiring VDL and the second voltage wiring VSL may have a mesh structure, but the invention is not limited thereto. Although not shown in the drawings, each of the pixels PX of the display device 10 may be connected to at least one data line DTL, the initialization voltage wiring VIL, the first voltage wiring VDL, and the second voltage wiring VSL.

[0073] The data line DTL, the initialization voltage wiring VIL, the first voltage wiring VDL and the second voltage wiring VSL may be electrically connected to at least one wiring pad WPD. Each wiring pad WPD may be arranged in the non-display area NDA. In one embodiment, the wiring pad WPD_DT (hereinafter referred to as "data pad") of the data line DTL may be arranged in the pad area PDA on one side of the display area DPA in the second direction DR2, the wiring pad WPD_Vint (hereinafter referred to as "initialization voltage pad") of the initialization voltage wiring VIL, the wiring pad WPD_VDD (hereinafter referred to as "first power pad") of the first voltage wiring VDL and the wiring pad WPD_VSS (hereinafter referred to as "second power pad") of the second voltage wiring VSL may be arranged in the pad area PDA on the other side of the display area DPA in the second direction DR2. As another example, the data pad WPD_DT, the initialization voltage pad WPD_Vint, the first power pad WPD_VDD and the second power pad WPD_VSS may all be arranged in the same area (for example, in the non-display area NDA located on the upper side of the display area DPA). An external device may be mounted on the wiring pad WPD. The external device may be mounted on the wiring pad WPD through an anisotropic conductive film or ultrasonic bonding or the like.

[0074] Each pixel PX or sub-pixel PXn (where n is an integer from 1 to 3) of the display device 10 may include a pixel driving circuit. Through the above wiring, a driving signal may be applied to each pixel driving circuit while passing through or surrounding each pixel PX. The pixel driving circuit may include a transistor and a capacitor. The number of transistors and capacitors of each pixel driving circuit may be modified differently. According to one embodiment, each sub-pixel PXn of the display device 10 may have a 4T1C structure in which the pixel driving circuit includes four transistors and one capacitor. In the following, the pixel driving circuit will be described by exemplifying a 4T1C structure, but the invention is not limited thereto. Various other modified structures of the pixel PX (such as a 2T1C structure, a 7T1C structure, and a 6T1C structure) may be applied.

[0075] Figure 3 is an equivalent circuit diagram of a sub-pixel according to an embodiment.

[0076] Reference Figure 3 , each sub-pixel PXn of the display device 10 according to one embodiment includes four transistors T1 , T2 , T3 , and T4 and a storage capacitor Cst in addition to the light emitting diode EL.

[0077] The light emitting diode EL emits light according to the current supplied by the first transistor T1. The light emitting diode EL includes a first electrode, a second electrode, and one or more light emitting elements disposed between the first electrode and the second electrode. The light emitting element can emit light having a specific wavelength band due to an electrical signal transmitted from the first electrode and the second electrode.

[0078] One end of the light emitting diode EL may be connected to the source electrode of the first transistor T1, and the other end thereof may be connected to the second voltage wiring VSL to which a low potential voltage (hereinafter, referred to as a second power supply voltage) lower than a high potential voltage of the first voltage wiring VDL (hereinafter, referred to as a first power supply voltage) is supplied. In addition, the other end of the light emitting diode EL may be connected to the source electrode of the second transistor T2.

[0079] The first transistor T1 adjusts the current flowing from the first voltage wiring VDL supplied with the first power supply voltage to the light emitting diode EL according to the voltage difference between the gate electrode and the source electrode thereof. As an example, the first transistor T1 may be a driving transistor for driving the light emitting diode EL. The gate electrode of the first transistor T1 may be connected to the source electrode of the third transistor T3, the source electrode of which may be connected to the first electrode of the light emitting diode EL, and the drain electrode of which may be connected to the first voltage wiring VDL to which the first power supply voltage is applied.

[0080] The second transistor T2 may be turned on in response to a signal of the alignment signal line ASL to transmit a voltage applied to the data line DTL (DTLk or DTLk+1) to the second electrode of the light emitting diode EL. The gate electrode of the second transistor T2 may be connected to the alignment signal line ASL, the source electrode thereof may be connected to the second electrode of the light emitting diode EL, and the drain electrode thereof may be connected to the k+1th data line DTLk+1 (where k is an integer greater than or equal to 1) of a timing different from that of the corresponding sub-pixel PXn. During the manufacturing process of the display device 10, the second transistor T2 may be turned on at the same timing as the fourth transistor T4 to be described below. The second transistor T2 may be turned on simultaneously with the fourth transistor T4 to transmit an electrical signal applied to the k+1th data line DTLk+1 to the other end of the light emitting diode EL. However, during the driving of the display device 10, a signal may not be applied to the alignment signal line ASL, and the second transistor T2 may remain in a cut-off state so that the electrical signal applied to the k+1th data line DTLk+1 may not be transmitted to the other end of the light emitting diode EL.

[0081] The third transistor T3 is turned on in response to a scan signal of the scan line SCL so that the data line DTL (DTLk or DTLk+1) is connected to the gate electrode of the first transistor T1. The gate electrode of the third transistor T3 may be connected to the scan line SCL, the source electrode thereof may be connected to the gate electrode of the first transistor T1, and the drain electrode thereof may be connected to the kth data line DTLk (where k is an integer greater than or equal to 1).

[0082] The fourth transistor T4 is turned on in response to the sensing signal of the sensing line SSL so that the initialization voltage wiring VIL is connected to one end of the light emitting diode EL. The gate electrode of the fourth transistor T4 can be connected to the sensing line SSL, the drain electrode thereof can be connected to the initialization voltage wiring VIL, and the source electrode thereof can be connected to one end of the light emitting diode EL or the source electrode of the first transistor T1.

[0083] In one embodiment, the source electrode and the drain electrode of each of the transistors T1 , T2 , T3 , and T4 are not limited to those described above, and the situation may be reversed.

[0084] The storage capacitor Cst is formed between the gate electrode and the source electrode of the first transistor T1. The storage capacitor Cst stores a voltage difference between the gate voltage and the source voltage of the first transistor T1.

[0085] Each of the transistors T1, T2, T3 and T4 may be formed as a thin film transistor. Figure 3In the present invention, the description has been given based on each of the transistors T1, T2, T3 and T4 being formed as an N-type metal oxide semiconductor field effect transistor (MOSFET), but the invention is not limited thereto. That is, each of the transistors T1, T2, T3 and T4 may be formed as a P-type MOSFET, or some of them may be formed as an N-type MOSFET and others of them may be formed as a P-type MOSFET.

[0086] Hereinafter, the structure of one pixel PX of the display device 10 according to one embodiment will be described in detail with further reference to other drawings.

[0087] Figure 4 1 is a schematic plan view showing wiring provided in one pixel of a display device according to one embodiment. Figure 4 , schematic shapes of a plurality of wirings and a second bank 45 provided in each pixel PX of the display device 10 are shown, and members provided in the light emitting area EMA of each sub-pixel PXn and some conductive layers provided under the members are omitted. In each of the following drawings, both sides in the first direction DR1 may be referred to as a left side and a right side, respectively, and both sides in the second direction DR2 may be referred to as an upper side and a lower side, respectively.

[0088] Reference Figure 4 , each of the multiple pixels PX of the display device 10 may include multiple sub-pixels PXn (where n is an integer from one to three). For example, one pixel PX may include a first sub-pixel PX1, a second sub-pixel PX2, and a third sub-pixel PX3. The first sub-pixel PX1 may emit light having a first color, the second sub-pixel PX2 may emit light having a second color, and the third sub-pixel PX3 may emit light having a third color. The first color may be blue, the second color may be green, and the third color may be red. However, the invention is not limited thereto, and the sub-pixels PXn may emit light having the same color.

[0089] Each of the sub-pixels PXn of the display device 10 may include a light emitting region EMA and a non-light emitting region (not shown). The light emitting region EMA may be a region in which the light emitting element 30 (see FIG. 1 ) is disposed. Figure 7 ) so as to emit light having a specific wavelength band, and the non-luminescent region may be a region in which the light emitting element 30 is not disposed so that the light emitted from the light emitting element 30 does not reach and is not emitted. The luminescent region may include a region in which the light emitting element 30 is disposed and a region adjacent to the light emitting element 30 and to which the light emitted from the light emitting element 30 is output.

[0090] The invention is not limited thereto, and the light emitting region may also include a region to which light emitted from the light emitting element 30 is output due to reflection or refraction by another member. A plurality of light emitting elements 30 may be provided in each sub-pixel PXn, wherein a region in which the plurality of light emitting elements 30 are provided and a region adjacent to the region may form a light emitting region.

[0091] In addition, each sub-pixel PXn may include a cutout region CBA disposed in a non-luminous region. The cutout region CBA may be disposed at one side of the luminous region EMA in the second direction DR2. The cutout region CBA may be disposed between the luminous regions EMA of the sub-pixels PXn adjacent along the second direction DR2. That is, a plurality of luminous regions EMA and a plurality of cutout regions CBA may be disposed in the display region DPA of the display device 10. For example, a plurality of luminous regions EMA and a plurality of cutout regions CBA may be repeatedly disposed in the first direction DR1, and the luminous regions EMA and the cutout regions CBA may be alternately disposed in the second direction DR2. In addition, the space interval between the cutout regions CBA in the first direction DR1 may be smaller than the space interval between the luminous regions EMA in the first direction DR1. As will be described below, the second embankment 45 may be disposed between the cutout regions CBA and between the luminous regions EMA, and the interval between the cutout regions CBA and between the luminous regions EMA may be changed according to the width of the second embankment 45. Since the light emitting element 30 is not disposed in the cutout area CBA, light is not emitted through the cutout area CBA, but the electrodes 21 and 22 (see FIG. 2A ) disposed in each sub-pixel PXn are Figure 7 Some of the electrodes 21 and 22 provided for each sub-pixel PXn may be separated from each other and provided in the cutout area CBA.

[0092] The second bank 45 may be provided on the entire surface of the display area DPA in a grid pattern including portions extending in the first direction DR1 and the second direction DR2 in a plan view. The second bank 45 may be provided to cross the boundary of the sub-pixel PXn to distinguish adjacent sub-pixels PXn. In addition, the second bank 45 may be provided to surround the emission area EMA and the cutout area CBA provided for each sub-pixel PXn to distinguish the emission area EMA from the cutout area CBA. In the portion of the second bank 45 extending along the second direction DR2, the width of the portion provided between the emission areas EMA may be greater than the width of the portion provided between the cutout areas CBA. Therefore, the interval between the cutout areas CBA may be smaller than the interval between the emission areas EMA. A more detailed description of the second bank 45 will be described below.

[0093] A plurality of wirings are provided in each pixel PX and sub-pixel PXn of the display device 10. For example, in addition to the scan line SCL, the sense line SSL, and the alignment signal line ASL provided to extend in the first direction DR1, the display device 10 further includes an initialization voltage distribution line IDL provided to extend in the first direction DR1 and to cross some of the sub-pixels PXn. In addition, the display device 10 includes a data line DTL, an initialization voltage wiring VIL, a first voltage wiring VDL, and a second voltage wiring VSL provided to extend in the second direction DR2.

[0094] The scan line SCL extends in the first direction DR1 and is arranged to cross a plurality of sub-pixels PXn arranged in the first direction DR1. In addition, the plurality of scan lines SCL are arranged to be spaced apart from each other in the second direction DR2 and to cross the entire surface of the display area DPA. The scan line SCL may be arranged at the upper side of the center of each pixel PX or sub-pixel PXn. The scan line SCL may be electrically connected to the gate electrode of the third transistor T3 and may apply a scan signal to the third transistor T3.

[0095] Similarly, the sensing line SSL extends in the first direction DR1 and is disposed to cross a plurality of sub-pixels PXn arranged in the first direction DR1. In addition, a plurality of sensing lines SSL are disposed to be spaced apart from each other in the second direction DR2 and to cross the entire surface of the display area DPA. The sensing line SSL may be disposed at a lower side relative to the center of each pixel PX or sub-pixel PXn. The sensing line SSL may be electrically connected to the gate electrode of the fourth transistor T4, and a sensing signal or an alignment signal may be applied to the fourth transistor T4.

[0096] The alignment signal line ASL also extends in the first direction DR1 and is disposed to cross a plurality of sub-pixels PXn arranged in the first direction DR1. A plurality of alignment signal lines ASL are disposed to be spaced apart from each other in the second direction DR2 and to cross the entire surface of the display area DPA. The alignment signal line ASL may be disposed below the sensing line SSL of each pixel PX or sub-pixel PXn. The alignment signal line ASL may be electrically connected to the gate electrode of the second transistor T2 and may apply an alignment signal to the second transistor T2.

[0097] The initialization voltage distribution line IDL may be provided for each pixel PX and may be provided to cross three sub-pixels PXn. The initialization voltage distribution line IDL may have a shape provided above the sensing line SSL and extending in the first direction DR1. The initialization voltage distribution line IDL may be electrically connected to the initialization voltage wiring VIL and may transmit the initialization voltage Vint applied for each pixel PX to each sub-pixel PXn. As an example, the initialization voltage distribution line IDL may be in direct contact with the initialization voltage wiring VIL through the contact hole CT11 (see FIG. 11 ). Figure 5 ). The initialization voltage distribution line IDL may be electrically connected to the drain electrode of the fourth transistor T4 of each sub-pixel PXn. The initialization voltage distribution line IDL may apply the initialization voltage applied from the initialization voltage wiring VIL to the fourth transistor T4.

[0098] The scan lines SCL, the sensing lines SSL, the alignment signal lines ASL, and the initialization voltage distribution lines IDL may be formed of a first gate conductive layer to be described below. The first gate conductive layer may further include more conductive layers in addition to the above-mentioned lines.

[0099] The data line DTL extends in the second direction DR2 and is arranged to cross a plurality of sub-pixels PXn arranged in the second direction DR2. In addition, a plurality of data lines DTL are arranged to be spaced apart from each other in the first direction DR1 and to cross the entire surface of the display area DPA. The data line DTL may be arranged on the right side of each sub-pixel PXn. The data line DTL transmitting a data signal to any one sub-pixel PXn may be arranged on the right side of another sub-pixel PXn adjacent along the first direction DR1, and the data line DTL arranged on the right side of the corresponding sub-pixel PXn may transmit a data signal to another sub-pixel PXn. That is, the data line DTL may not be arranged in an area occupied by the sub-pixel PXn to which the data line DTL is connected. However, the invention is not limited thereto. The data line DTL may be electrically connected to the drain electrode of the third transistor T3, and a data signal may be applied to the third transistor T3.

[0100] The initialization voltage wiring VIL extends in the second direction DR2 and is arranged to cross a plurality of pixels PX arranged in the second direction DR2. In addition, a plurality of initialization voltage wirings VIL are arranged to be spaced apart from each other in the first direction DR1 and to cross the entire surface of the display area DPA. The initialization voltage wiring VIL may be arranged for every three sub-pixels PXn or for each pixel PX. As an example, the initialization voltage wiring VIL may be arranged on the left side of the data line DTL connected to one sub-pixel PXn. In the accompanying drawings, the initialization voltage wiring VIL is arranged on the left side of the data line DTL connected to the second sub-pixel PX2, and the data line DTL is arranged in the area occupied by the first sub-pixel PX1, but the invention is not limited thereto. The initialization voltage wiring VIL may be electrically connected to the initialization voltage distribution line IDL, and may transmit the initialization voltage to each sub-pixel PXn. The initialization voltage wiring VIL may be electrically connected to the drain electrode of the fourth transistor T4, and may apply the initialization voltage to the fourth transistor T4.

[0101] The data line DTL and the initialization voltage wiring VIL may be formed of a first data conductive layer to be described below. The first data conductive layer may further include more conductive layers in addition to the above-mentioned lines and wirings.

[0102] The first voltage wiring VDL and the second voltage wiring VSL may extend in the second direction DR2 and may be arranged to cross a plurality of sub-pixels PXn adjacent in the second direction DR2. In addition, a plurality of first voltage wirings VDL and a plurality of second voltage wirings VSL are arranged to be spaced apart from each other in the first direction DR1 and to cross the entire surface of the display area DPA. In a plan view, the first voltage wiring VDL and the second voltage wiring VSL may be arranged between a plurality of data lines DTL. The first voltage wiring VDL may be arranged on the left side relative to the center of each sub-pixel PXn, and the second voltage wiring VSL may be arranged on the right side thereof. However, the first voltage wiring VDL may extend in the second direction DR2 and may be partially bent. For example, in addition to a portion arranged to extend downward from the upper side of each sub-pixel PXn, the first voltage wiring VDL may also include a portion bent toward the second voltage wiring VSL. Therefore, the interval between the first voltage wiring VDL and the second voltage wiring VSL arranged in each sub-pixel PXn may be partially changed.

[0103] The first voltage wiring VDL may be electrically connected to the drain electrode of the first transistor T1 and may apply a first power supply voltage to the first transistor T1. The second voltage wiring VSL may be electrically connected to the second electrode of the light emitting diode EL and may apply a second power supply voltage to the light emitting element. The first voltage wiring VDL and the second voltage wiring VSL may be formed of a second data conductive layer to be described below.

[0104] Figure 5 is a layout diagram showing a plurality of conductive layers included in one sub-pixel of a display device according to an embodiment. Figure 6 is a layout diagram showing a plurality of conductive layers included in one pixel of a display device according to an embodiment. Figure 7 is a schematic plan view showing a plurality of electrodes and a plurality of banks included in one pixel of a display device according to one embodiment. Figure 8 It is along Figure 7 Cross-sectional views taken along line Q1 - Q1 ′, line Q2 - Q2 ′, and line Q3 - Q3 ′. Fig. 9 It is along Figure 7 A cross-sectional view taken along line Q4-Q4' and line Q5-Q5'.

[0105] exist Figure 5 In FIG. 1 , as a circuit element layer provided in each sub-pixel PXn, a layout diagram of a conductive layer provided in a first sub-pixel PX1 and wirings and transistors connected to the conductive layer are shown, and in FIG. Figure 6 , a layout diagram of a conductive layer disposed in one pixel PX and wiring and transistors connected to the conductive layer are shown. Figure 5 and Figure 6 , the first voltage wiring VDL and the second voltage wiring VSL are omitted. Figure 6 The sub-pixels PXn shown in FIG. 1 are shown without dividing the area occupied by the sub-pixels, and are shown with dividing the circuit element layer connected to the light emitting diode EL provided in each sub-pixel PXn.

[0106] In addition, Figure 7 , as a display element layer provided in each pixel PX, in addition to the electrodes 21 and 22 constituting the light emitting diode EL and the light emitting element 30, an arrangement of a plurality of banks 40 and 45 and a plurality of contact electrodes 26 and 27 is shown. In addition to the first transistor T1, Figure 8 A cross section through both ends of the light emitting element 30 is also shown, and Fig. 9 The cross sections of the second transistor T2 to the fourth transistor T4 are shown.

[0107] Combination Figure 4 Reference Figures 5 to 9, the display device 10 may include a circuit element layer and a display element layer. The display element layer may be a layer in which the first electrode 21 and the second electrode 22 of the light emitting diode EL and the light emitting element 30 are disposed, and the circuit element layer may be a layer in which a plurality of wirings for driving the light emitting diode EL and pixel circuit elements are disposed. For example, in addition to the scan line SCL, the sense line SSL, the alignment signal line ASL, the data line DTL, the initialization voltage wiring VIL, the first voltage wiring VDL, and the second voltage wiring VSL, the circuit element layer may also include each of the transistors T1, T2, T3, and T4.

[0108] Specifically, the display device 10 includes a first substrate 11 on which a circuit element layer and a display element layer are disposed. The first substrate 11 may be an insulating substrate and may be made of an insulating material such as glass, quartz, or a polymer resin, etc. In addition, the first substrate 11 may be a rigid substrate, but may also be a flexible substrate that is bendable, foldable, and rollable.

[0109] The light blocking layer BML may be disposed on the first substrate 11. The light blocking layer BML is disposed to overlap with the first active layer ACT1 of the first transistor T1 of the display device 10. The light blocking layer BML may include a material that blocks light, thereby preventing light from being incident on the active layer ACT1 of the first transistor. As an example, the light blocking layer BML may be made of an opaque metal material that blocks light transmission. However, the invention is not limited thereto, and the light blocking layer BML may be omitted, or the light blocking layer BML may be disposed to overlap with the active layers of the other transistors T1, T2, T3, and T4.

[0110] The buffer layer 12 may be completely disposed on the first substrate 11 and the light blocking layer BML. The buffer layer 12 may be formed on the first substrate 11 to protect each of the transistors T1, T2, T3, and T4 from moisture penetration through the first substrate 11 susceptible to moisture penetration, and may perform a surface planarization function. The buffer layer 12 may include a plurality of inorganic layers alternately stacked. For example, the buffer layer 12 may be formed to include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) and a plurality of layers of inorganic layers alternately stacked.

[0111] The semiconductor layer is disposed on the buffer layer 12. The semiconductor layer may include each of the active layers ACT1, ACT2, ACT3, and ACT4 of the transistors T1, T2, T3, and T4. The first active layer ACT1 of the first transistor T1 may be disposed below each subpixel PXn to be adjacent to the center of each subpixel PXn. The third active layer ACT3 of the third transistor T3 may be disposed on the upper side with respect to the center of each subpixel PXn, and the fourth active layer ACT4 of the fourth transistor T4 may be disposed below the first active layer ACT1. The second active layer ACT2 of the second transistor T2 may be disposed on the right side of the fourth active layer ACT4.

[0112] Meanwhile, in an embodiment, the semiconductor layer may include polycrystalline silicon, monocrystalline silicon, oxide semiconductors, and the like. Polycrystalline silicon may be formed by crystallizing amorphous silicon. When the semiconductor layer includes an oxide semiconductor, each of the active layers ACT1, ACT2, ACT3, and ACT4 may include a plurality of conductive regions ACTa and ACTb and a channel region ACTc disposed between the conductive regions ACTa and ACTb. The oxide semiconductor may be an oxide semiconductor including indium (In). In some embodiments, the oxide semiconductor may be indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), or indium gallium zinc tin oxide (IGZTO), and the like.

[0113] In another embodiment, the semiconductor layer may include polycrystalline silicon. Polycrystalline silicon may be formed by crystallizing amorphous silicon, in which case the conductive region of each of the active layers ACT1, ACT2, ACT3, and ACT4 may be a doped region doped with impurities. However, the invention is not limited thereto.

[0114] The first gate insulating layer 13 is disposed on the semiconductor layer and the buffer layer 12. The first gate insulating layer 13 may include a semiconductor layer and may be disposed on the buffer layer 12. The first gate insulating layer 13 may be used as a gate insulating film of each transistor in the transistor. The first gate insulating layer 13 may be formed to include a silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) or a stacked structure thereof.

[0115] The first gate conductive layer is disposed on the first gate insulating layer 13. The first gate conductive layer may include each of the gate electrodes G1, G2, G3, and G4 of the transistors T1, T2, T3, and T4, the scan line SCL, the sensing line SSL, the alignment signal line ASL, the initialization voltage distribution line IDL, and the first capacitor electrode CSE1 of the storage capacitor. Since the description of the scan line SCL, the sensing line SSL, the alignment signal line ASL, and the initialization voltage distribution line IDL is the same as above, the plurality of gate electrodes and the first capacitor electrode CSE1 will be described below.

[0116] The gate electrodes G1, G2, G3, and G4 of the first gate conductive layer may be disposed to partially overlap the active layers of the transistors T1, T2, T3, and T4, respectively. For example, the first gate electrode G1 of the first transistor T1 may be disposed to partially overlap the first active layer ACT1. The first gate electrode G1 may be connected to and integral with the first capacitor electrode CSE1 of the storage capacitor, which will be described below.

[0117] The second gate electrode G2 of the second transistor T2 may be disposed to partially overlap the second active layer ACT2, the third gate electrode G3 of the third transistor T3 may be disposed to partially overlap the third active layer ACT3, and the fourth gate electrode G4 of the fourth transistor T4 may be disposed to partially overlap the fourth active layer ACT4. The second gate electrode G2 may be electrically connected to the alignment signal line ASL, and the alignment signal may be applied to the second transistor T2 during the manufacturing process of the display device 10. The third gate electrode G3 may be electrically connected to the scan line SCL, and the scan signal may be applied to the third transistor T3. The fourth gate electrode G4 may be electrically connected to the sensing line SSL, and the sensing signal or the alignment signal may be applied to the gate electrode of the fourth transistor T4.

[0118] The first capacitor electrode CSE1 of the storage capacitor Cst is disposed between the scan line SCL and the sensing line SSL. The first capacitor electrode CSE1 may be electrically connected to the first gate electrode G1 of the first transistor T1 and the source electrode of the third transistor T3. As an example, the first capacitor electrode CSE1 may be integrally formed with the first gate electrode G1 and may be connected to the source electrode of the third transistor T3 through a contact hole CT7.

[0119] In one embodiment, the first gate conductive layer may further include a fourth conductive pattern DP4 overlapping the data line DTL and the initialization voltage wiring VIL in the thickness direction. As will be described below, the drain electrode of the second transistor T2 may be connected to the data line DTL, and in some sub-pixels PXn, the initialization voltage wiring VIL may be disposed between the second active layer ACT2 of the second transistor T2 and the data line DTL. Since the data line DTL and the initialization voltage wiring VIL may be formed by the first data conductive layer disposed in the same layer, a bridge electrode connecting the data line DTL and the drain electrode of the second transistor T2 may also be required. According to one embodiment, the fourth conductive pattern DP4 disposed in the first gate conductive layer may include a bridge electrode, which is configured to interconnect the drain electrode of the second transistor T2 disposed in one sub-pixel (e.g., the first sub-pixel PX1) and the data line DTL connected to the second sub-pixel PX2. The fourth conductive pattern DP4 may be disposed to overlap the initialization voltage wiring VIL and the data line DTL in the thickness direction, and may be connected to the drain electrode of the second transistor T2. For example, the fourth conductive pattern DP4 may contact the data line DTL and the second drain electrode D2 of the second transistor T2 through a contact hole CT12 passing through an insulating layer disposed above the fourth conductive pattern DP4. The fourth conductive pattern DP4 may not be provided for each sub-pixel PXn, but may be provided for each sub-pixel PXn in which the initialization voltage wiring VIL is provided. However, the invention is not limited thereto.

[0120] The first gate conductive layer may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. However, the present invention is not limited thereto.

[0121] The first protective layer 15 is disposed on the first gate conductive layer. The first protective layer 15 may be disposed to cover the first gate conductive layer and may be used to protect the first gate conductive layer. The first protective layer 15 may be formed to include, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) or a stacked structure thereof.

[0122] The first data conductive layer is disposed on the first protective layer 15. In addition to the source electrodes and drain electrodes of the transistors T1, T2, T3, and T4, the data line DTL, the initialization voltage wiring VIL, and the second capacitor electrode CSE2 of the storage capacitor, the first data conductive layer may further include a plurality of conductive patterns. Since the description of the data line DTL and the initialization voltage wiring VIL is the same as above, the plurality of source electrodes, the plurality of drain electrodes, the second capacitor electrode CSE2, and the conductive patterns will be described below.

[0123] The first source electrode S1 and the first drain electrode D1 of the first transistor T1 are arranged to partially overlap the first active layer ACT1. The first source electrode S1 and the first drain electrode D1 may both contact the first active layer ACT1 through the contact hole CT1 passing through the first protective layer 15 and the first gate insulating layer 13. In addition, the first source electrode S1 may contact the light blocking layer BML through the contact hole CT5 passing through the first protective layer 15, the first gate insulating layer 13, and the buffer layer 12. The first drain electrode D1 may be electrically connected to the first voltage wiring VDL, and the first source electrode S1 may be connected to the second capacitor electrode CSE2 of the storage capacitor connected to the first electrode 21 of the light emitting diode EL. As an example, the first drain electrode D1 may be directly in contact with the first voltage wiring VDL through the contact hole, and the first source electrode S1 may be integral with the second capacitor electrode CSE2 and connected to the second capacitor electrode CSE2. The first transistor T1 may be turned on in response to the data signal transmitted from the third transistor T3 to transmit the first power supply voltage to the first electrode 21.

[0124] The second source electrode S2 and the second drain electrode D2 of the second transistor T2 are arranged to partially overlap the second active layer ACT2. The second source electrode S2 and the second drain electrode D2 can both contact the second active layer ACT2 through the contact hole CT2 passing through the first protective layer 15 and the first gate insulating layer 13. The second drain electrode D2 can be integral with the data line DTL and connected to the data line DTL, and the second source electrode S2 can be electrically connected to the second electrode 22 of the light emitting diode EL, which will be described below. However, the invention is not limited to this, and as described above, the second drain electrode D2 can be electrically connected to the data line DTL through the fourth conductive pattern DP4. The second source electrode S2 can be in direct contact with the second electrode 22 through the contact hole CTA of the insulating layer disposed thereon. The second transistor T2 can be turned on in response to a signal of the alignment signal line ASL to transmit the signal applied to the data line DTL to the second electrode 22.

[0125] The third source electrode S3 and the third drain electrode D3 of the third transistor T3 may be disposed to partially overlap the third active layer ACT3. The third source electrode S3 and the third drain electrode D3 may each contact the third active layer ACT3 through a contact hole CT3 passing through the first protective layer 15 and the first gate insulating layer 13. The third drain electrode D3 may be integral with and connected to the data line DTL, and the third source electrode S3 may contact the first capacitor electrode CSE1 through a contact hole CT7 passing through the first protective layer 15. The third transistor T3 may be turned on in response to a scan signal to transmit a data signal applied from the data line DTL to the first gate electrode G1 of the first transistor T1.

[0126] Meanwhile, the second transistor T2 and the third transistor T3 may both be connected to the data line DTL, but may be connected to different signal lines, so the second transistor T2 and the third transistor T3 of each sub-pixel PXn may not be turned on at the same time. The second transistor T2 may be turned on in response to a signal of the alignment signal line ASL, and the third transistor T3 may be turned on in response to a signal of the scan line SCL. In addition, since the second transistor T2 is turned on only during the manufacturing process of the display device 10, even when the third transistor T3 is turned on during the driving of the display device 10 to transmit a data signal to the first transistor T1, since the second transistor T2 is in a cut-off state, the signal passing through the second transistor T2 is not transmitted to the second electrode 22. As will be described below, the second electrode 22 is connected to the second voltage wiring VSL so that the second power supply voltage is applied thereto, and when the light emitting element 30 emits light, the electrical signal via the second transistor T2 may not be transmitted to the second electrode 22, and only the second power supply voltage may be transmitted to the second electrode 22.

[0127] The display device 10 may turn on the second transistor T2 and the fourth transistor T4 simultaneously during its manufacturing process, so that the alignment signal may be transmitted to the first electrode 21 and the second electrode 22. The display device 10 may turn on the second transistor T2 and the fourth transistor T4 simultaneously by applying a signal to each of the alignment signal line ASL and the sensing line SSL during its manufacturing process, and may keep the second transistor T2 in an off state by not applying a signal to the alignment signal line ASL during driving of the display device 10. That is, the second transistor T2 may be turned on only during the manufacturing process of the display device 10, and may be turned off during driving of the display device 10.

[0128] The fourth source electrode S4 and the fourth drain electrode D4 of the fourth transistor T4 are arranged to partially overlap with the fourth active layer ACT4. The fourth source electrode S4 and the fourth drain electrode D4 may both contact the fourth active layer ACT4 through the contact hole CT4 passing through the first protective layer 15 and the first gate insulating layer 13. The fourth drain electrode D4 may contact the initialization voltage distribution line IDL through the contact hole CT9 passing through the first protective layer 15, and the fourth source electrode S4 may be connected to the second capacitor electrode CSE2 of the storage capacitor. As an example, the fourth source electrode S4 may be integral with the second capacitor electrode CSE2 and connected to the second capacitor electrode CSE2. In addition, the initialization voltage distribution line IDL may be connected to the initialization voltage wiring VIL through the contact hole CT11 passing through the first protective layer 15 so that the initialization voltage distribution line IDL may be connected to the initialization voltage wiring VIL, and the initialization voltage may be transmitted to the fourth drain electrode D4. The fourth transistor T4 may be turned on in response to the sensing signal to transmit the initialization voltage to the first electrode 21 of the light emitting diode EL through the second capacitor electrode CSE2.

[0129] The second capacitor electrode CSE2 of the storage capacitor Cst is disposed to overlap with the first capacitor electrode CSE1. The second capacitor electrode CSE2 may be integral with the first source electrode S1 of the first transistor T1 and the fourth source electrode S4 of the fourth transistor T4 and connected to the first source electrode S1 of the first transistor T1 and the fourth source electrode S4 of the fourth transistor T4. In addition, as will be described below, the second capacitor electrode CSE2 may be electrically connected to the first electrode 21 of the light emitting diode EL through an electrode contact hole CTD passing through an insulating layer disposed thereover. In the accompanying drawings, it is shown that the second capacitor electrode CSE2 is in direct contact with the first electrode 21, but the invention is not limited thereto. In some embodiments, the second capacitor electrode CSE2 may be electrically connected to the first electrode 21 through an electrode formed by a conductive layer disposed thereover.

[0130] The first conductive pattern DP1 is arranged to overlap with the scan line SCL and the third gate electrode G3. The first conductive pattern DP1 may contact the scan line SCL and the third gate electrode G3 through the contact hole CT6 passing through the first protective layer 15. The third gate electrode G3 may be electrically connected to the scan line SCL through the first conductive pattern DP1. The second conductive pattern DP2 is arranged to overlap with the sensing line SSL and the fourth gate electrode G4. The second conductive pattern DP2 may contact the sensing line SSL and the fourth gate electrode G4 through the contact hole CT8 passing through the first protective layer 15. The fourth gate electrode G4 may be electrically connected to the sensing line SSL through the second conductive pattern DP2. The third conductive pattern DP3 is arranged to overlap with the alignment signal line ASL and the second gate electrode G2. The third conductive pattern DP3 may contact the alignment signal line ASL and the second gate electrode G2 through the contact hole CT10 passing through the first protective layer 15. The second gate electrode G2 may be electrically connected to the alignment signal line ASL through the third conductive pattern DP3.

[0131] The first data conductive layer may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the present invention is not limited thereto.

[0132] The first interlayer insulating layer 17 is disposed on the first data conductive layer. The first interlayer insulating layer 17 may be used as an insulating film between the first data conductive layer and other layers disposed thereon. In addition, the first interlayer insulating layer 17 may cover the first data conductive layer and serve to protect the first data conductive layer. The first interlayer insulating layer 17 may be formed to include a silicon oxide (SiO x ), Silicon Nitride (SiN x ) and silicon oxynitride (SiON) or a stacked structure thereof.

[0133] The second data conductive layer is disposed on the first interlayer insulating layer 17. The second data conductive layer includes a first voltage wiring VDL and a second voltage wiring VSL. However, the invention is not limited thereto, and the second data conductive layer may also include a plurality of conductive patterns. The first voltage wiring VDL may be electrically connected to the first drain electrode D1 of the first transistor T1 through a contact hole passing through the first interlayer insulating layer 17. The first power supply voltage applied to the first voltage wiring VDL may be transmitted to the first electrode 21 of the light emitting diode EL through the first transistor T1. The second voltage wiring VSL may be electrically connected to the second electrode 22 of the light emitting diode EL, and may transmit the second power supply voltage to the second electrode 22. Since the description of the first voltage wiring VDL and the second voltage wiring VSL is the same as above, the detailed description thereof will be omitted.

[0134] The second data conductive layer may be formed as a single layer or multiple layers made of one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or alloys thereof. However, the present invention is not limited thereto.

[0135] The first planarization layer 19 is disposed on the second data conductive layer. The first planarization layer 19 may include an organic insulating material (eg, an organic material such as polyimide (PI)), and may perform a surface planarization function.

[0136] A plurality of first banks 40, a plurality of electrodes 21 and 22, a light emitting element 30, a second bank 45, and a plurality of contact electrodes 26 and 27 are provided on the first planarization layer 19. In addition, a plurality of insulating layers 51, 52, 53, and 54 may be further provided on the first planarization layer 19.

[0137] A plurality of first embankments 40 may be disposed directly on the first planarization layer 19. The plurality of first embankments 40 may extend in the second direction DR2 in each sub-pixel PXn, and may be disposed in the light emitting area EMA so as not to extend to other sub-pixels PXn adjacent in the second direction DR2. In addition, the plurality of first embankments 40 may be disposed to be spaced apart from each other in the first direction DR1, and an area in which the light emitting element 30 is disposed between the plurality of first embankments 40 may be formed. A plurality of first embankments 40 may be disposed for each sub-pixel PXn to form a linear pattern in the display area DPA of the display device 10. Two first embankments 40 are shown in the drawings, but the invention is not limited thereto. A larger number of first embankments 40 may also be disposed according to the number of electrodes 21 and 22, which will be described below.

[0138] The first bank 40 may have a structure in which at least a portion thereof protrudes based on the upper surface of the first planarization layer 19. The protruding portion of the first bank 40 may have an inclined side surface, and the light emitted from the light emitting element 30 may travel toward the inclined side surface of the first bank 40. The electrodes 21 and 22 disposed on the first bank 40 may include a material having a high reflectivity, so that the light emitted from the light emitting element 30 may be reflected from the electrodes 21 and 22 disposed on the side surface of the first bank 40 to be emitted in an upward direction relative to the first planarization layer 19. That is, the first bank 40 may provide a region in which the light emitting element 30 is disposed, and at the same time may serve as a reflective partition wall that reflects the light emitted from the light emitting element 30 upward. The side surface of the first bank 40 may be inclined in a linear shape, but the invention is not limited thereto. The first bank 40 may have an outer surface having a curved semicircular shape or a semi-elliptical shape. In an embodiment, the first bank 40 may include an organic insulating material such as polyimide (PI), but the invention is not limited thereto.

[0139] The plurality of electrodes 21 and 22 are disposed on the first bank 40 and the first planarization layer 19. The plurality of electrodes 21 and 22 may include first electrodes 21 and second electrodes 22. The first electrodes 21 and second electrodes 22 may extend in the second direction DR2 and may be disposed to be spaced apart from each other in the first direction DR1.

[0140] The first electrode 21 and the second electrode 22 may both extend in the second direction DR2 in the sub-pixel PXn, and may be separated from the other electrodes 21 and 22 in the cutout area CBA. In some embodiments, the cutout area CBA may be disposed between the emission areas EMA of the sub-pixels PXn adjacent in the second direction DR2, and in the cutout area CBA, the first electrode 21 and the second electrode 22 may be separated from another first electrode 21 and another second electrode 22 disposed in the sub-pixel PXn adjacent in the second direction DR2. However, the invention is not limited thereto, and some of the electrodes 21 and 22 may be disposed to extend across the sub-pixels PXn adjacent in the second direction DR2 instead of being separated for each sub-pixel PXn, or only one of the first electrode 21 and the second electrode 22 may be separated.

[0141] The first electrode 21 may be electrically connected to the first transistor T1 and the fourth transistor T4, and the second electrode 22 may be electrically connected to the second voltage wiring VSL and the second transistor T2. For example, the first electrode 21 may contact the first source electrode S1 or the second capacitor electrode CSE2 through the first electrode contact hole CTD passing through the first planarization layer 19 and the first interlayer insulating layer 17. The second electrode 22 may be connected to the second voltage wiring VSL through the second electrode contact hole CTS passing through the first planarization layer 19, and may contact the second source electrode S2 through the third electrode contact hole CTA. As an example, the first electrode 21 and the second electrode 22 may overlap with a portion of the second bank 45 extending in the first direction DR1, and the first electrode contact hole CTD and the second electrode contact hole CTS may be respectively formed in a region where the electrodes 21 and 22 overlap with the second bank 45. The third electrode contact hole CTA may be formed in the portion where the second electrode 22 is disposed on the first planarization layer 19 in the light emitting area EMA of each sub-pixel PXn. However, the invention is not limited thereto. As long as the second transistor T2 and the second electrode 22 can be electrically connected, the position of the third electrode contact hole CTA may be modified differently. In addition, the first electrode 21 and the second electrode 22 may contact the electrode conductive pattern provided in the second data conductive layer, and since the electrode conductive pattern is provided, the positions of the electrode contact holes CTD, CTS and CTA may be changed. For example, all of the electrode contact holes CTD, CTS and CTA may be formed in the light emitting area EMA.

[0142] In the drawings, it is shown that one first electrode 21 and one second electrode 22 are provided for each sub-pixel PXn, but the invention is not limited thereto. In some embodiments, a larger number of first electrodes 21 and second electrodes 22 may be provided for each sub-pixel PXn. In addition, the first electrode 21 and the second electrode 22 provided in each sub-pixel PXn may not necessarily have a shape extending in one direction, and the first electrode 21 and the second electrode 22 may be provided in various structures. For example, the first electrode 21 and the second electrode 22 may have a partially curved or bent shape, or may be provided so that any one electrode surrounds the other electrode.

[0143] Each of the first electrode 21 and the second electrode 22 may be disposed on the first bank 40. In some embodiments, each of the first electrode 21 and the second electrode 22 may be formed to have a width greater than that of the first bank 40. For example, each of the first electrode 21 and the second electrode 22 may be disposed to cover an outer surface of the first bank 40. Each of the first electrode 21 and the second electrode 22 may be disposed on a side surface of the first bank 40, and an interval between the first electrode 21 and the second electrode 22 may be smaller than an interval between the first banks 40. In addition, at least a partial region of each of the first electrode 21 and the second electrode 22 may be directly disposed on the first planarization layer 19.

[0144] Each of the electrodes 21 and 22 may include a conductive material having high reflectivity. For example, the material having high reflectivity of each of the electrodes 21 and 22 may include a metal such as silver (Ag), copper (Cu), and aluminum (Al), or may be an alloy including aluminum (Al), nickel (Ni), and lanthanum (La), etc. Each of the electrodes 21 and 22 may reflect light emitted from the light emitting element 30 and traveling toward the side surface of the first bank 40 in an upward direction relative to each sub-pixel PXn.

[0145] However, the invention is not limited thereto, and each of the electrodes 21 and 22 may further include a transparent conductive material. For example, each of the electrodes 21 and 22 may include materials such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In some embodiments, each of the electrodes 21 and 22 may have a structure in which one or more layers of a transparent conductive material and one or more layers of a metal material having a high reflectivity are stacked, or each of the electrodes 21 and 22 may be formed as a single layer including a transparent conductive material and a metal material having a high reflectivity. For example, each of the electrodes 21 and 22 may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0146] The plurality of electrodes 21 and 22 may be electrically connected to the light emitting element 30, and a predetermined voltage may be applied to the plurality of electrodes 21 and 22 so that the light emitting element 30 emits light. For example, the plurality of electrodes 21 and 22 may be electrically connected to the light emitting element 30 by contact electrodes 26 and 27 to be described below, and an electrical signal applied to the electrodes 21 and 22 may be transmitted to the light emitting element 30 through the contact electrodes 26 and 27.

[0147] In an embodiment, one of the first electrode 21 and the second electrode 22 may be electrically connected to the anode of the light emitting element 30, and the other thereof may be electrically connected to the cathode of the light emitting element 30. However, the invention is not limited thereto, and the opposite may be true.

[0148] In addition, each of the electrodes 21 and 22 may also be used to form an electric field in the sub-pixel PXn to align the light-emitting element 30. The light-emitting element 30 may be disposed between the first electrode 21 and the second electrode 22 due to the electric field formed on the first electrode 21 and the second electrode 22. In an embodiment, the light-emitting element 30 of the display device 10 may be ejected onto the electrodes 21 and 22 by an inkjet printing process. When the ink including the light-emitting element 30 is ejected onto the electrodes 21 and 22, an alignment signal is applied to the electrodes 21 and 22 to generate an electric field. The light-emitting element 30 dispersed in the ink may be subjected to a dielectrophoretic force due to the electric field generated on the electrodes 21 and 22, and may be aligned on the electrodes 21 and 22.

[0149] The first insulating layer 51 is disposed on the first planarization layer 19, the first electrode 21, and the second electrode 22. The first insulating layer 51 may be disposed to partially cover the first electrode 21 and the second electrode 22 and to cover the region between the first electrode 21 and the second electrode 22. For example, the first insulating layer 51 may be disposed to cover most of the upper surface of each of the first electrode 21 and the second electrode 22, but may be disposed to expose a portion of the first electrode 21 and the second electrode 22. In other words, the first insulating layer 51 may be substantially completely formed on the first planarization layer 19, and may include an opening (not shown) that partially exposes the first electrode 21 and the second electrode 22.

[0150] In an embodiment, a step portion may be formed in the first insulating layer 51 between the first electrode 21 and the second electrode 22 so that a portion of the upper surface of the first insulating layer 51 is recessed. However, the invention is not limited thereto. The first insulating layer 51 may form a flat upper surface to allow the light emitting element 30 to be disposed.

[0151] The first insulating layer 51 can protect the first electrode 21 and the second electrode 22, and at the same time insulate the first electrode 21 from the second electrode 22. In addition, the first insulating layer 51 can prevent the light emitting element 30 disposed thereon from being damaged due to direct contact with other components. However, the shape and structure of the first insulating layer 51 are not limited thereto.

[0152] The second bank 45 may be disposed on the first insulating layer 51. The second bank 45 may be disposed on the entire surface of the display area DPA in a grid pattern including portions extending in the first direction DR1 and the second direction DR2 in a plan view. The second bank 45 may be disposed to cross a boundary of the sub-pixel PXn to distinguish adjacent sub-pixels PXn. In addition, according to one embodiment, the second bank 45 may be formed to have a height greater than that of the first bank 40. The second bank 45 may be used to prevent ink from overflowing to adjacent sub-pixels PXn in an inkjet printing process of a manufacturing process of the display device 10. The second bank 45 may separate ink in which different light emitting elements 30 are dispersed in different sub-pixels PXn to prevent the inks from mixing with each other.

[0153] In addition, the second bank 45 may be disposed to surround the light emitting area EMA and the cutout area CBA disposed for each sub-pixel PXn to distinguish the light emitting area EMA from the cutout area CBA. The first electrode 21 and the second electrode 22 may extend in the second direction DR2, and may be disposed to intersect with a portion of the second bank 45 extending in the first direction DR1. Among the portions of the second bank 45 extending in the second direction DR2, a portion disposed between the light emitting areas EMA may have a width greater than a width of a portion disposed between the cutout areas CBA. Therefore, the interval between the cutout areas CBA may be smaller than the interval between the light emitting areas EMA. Similar to the first bank 40, the second bank 45 may include polyimide (PI), but the invention is not limited thereto.

[0154] The light emitting element 30 may be disposed on the first insulating layer 51. The plurality of light emitting elements 30 may be disposed to be spaced apart from each other in the second direction DR2 along which each of the electrodes 21 and 22 extends, and may be aligned to be substantially parallel to each other. The spatial interval between the light emitting elements 30 is not particularly limited. In addition, the light emitting element 30 may have a shape extending in one direction, and the extending direction of the light emitting element 30 may be substantially perpendicular to the direction along which each of the electrodes 21 and 22 extends. However, the invention is not limited thereto, and the light emitting element 30 may be disposed obliquely, not perpendicular to the direction along which each of the electrodes 21 and 22 extends.

[0155] The light emitting element 30 may include a light emitting layer 36 of different materials to emit light having different wavelength bands to the outside. The display device 10 may include a light emitting element 30 that emits light in different wavelength bands. Therefore, the first color light, the second color light, and the third color light may be emitted from the first sub-pixel PX1, the second sub-pixel PX2, and the third sub-pixel PX3, respectively. However, the invention is not limited thereto. In some cases, each of the sub-pixels PXn may include a light emitting element 30 of the same type to emit light of substantially the same color.

[0156] In addition, both ends of the light emitting element 30 may be respectively disposed on the electrodes 21 and 22 between the first bank 40. For example, the light emitting element 30 may be disposed so that one end thereof is placed on the first electrode 21, and the other end thereof is placed on the second electrode 22. The length of the light emitting element 30 may extend longer than the interval between the first electrode 21 and the second electrode 22, and both ends of the light emitting element 30 may be respectively disposed on the first electrode 21 and the second electrode 22.

[0157] The light emitting element 30 may include a plurality of layers arranged along the first direction DR1. The light emitting element 30 of the display device 10 may be arranged so that one direction along which the light emitting element 30 extends is parallel to the first planarization layer 19, and a plurality of semiconductor layers included in the light emitting element 30 may be sequentially arranged in a direction parallel to the upper surface of the first planarization layer 19. However, the invention is not limited thereto. In some cases, when the light emitting element 30 has a different structure, a plurality of layers may be arranged in a direction perpendicular to the first planarization layer 19.

[0158] In addition, both ends of the light emitting element 30 may be in contact with the contact electrodes 26 and 27, respectively. According to one embodiment, since the insulating film 38 is not formed on the surface of the end in one direction along which the light emitting element 30 extends and the semiconductor layer is partially exposed, the exposed semiconductor layer may be in contact with the contact electrodes 26 and 27. However, the invention is not limited thereto. In some cases, in the light emitting element 30, at least a portion of the insulating film 38 may be removed, and the insulating film 38 may be removed to partially expose the side surfaces of both ends of the semiconductor layer. The exposed side surfaces of the semiconductor layer may be in direct contact with the contact electrodes 26 and 27.

[0159] The second insulating layer 52 may be partially disposed on the light emitting element 30. As an example, the second insulating layer 52 may be disposed to partially surround the outer surface of the light emitting element 30, and to not cover one end and the other end of the light emitting element 30. The contact electrodes 26 and 27 to be described below may contact both ends of the light emitting element 30 that are not covered by the second insulating layer 52. The portion of the second insulating layer 52 disposed on the light emitting element 30 may be disposed to extend in the second direction DR2 on the first insulating layer 51 in a plan view, thereby forming a linear shape pattern or an island shape pattern in each sub-pixel PXn. The second insulating layer 52 may protect the light emitting element 30 and fix the light emitting element 30 at the same time in the manufacturing process of the display device 10.

[0160] A plurality of contact electrodes 26 and 27 and a third insulating layer 53 may be disposed on the second insulating layer 52 .

[0161] The plurality of contact electrodes 26 and 27 may have a shape extending in one direction. The first contact electrode 26 and the second contact electrode 27 of the contact electrodes 26 and 27 may be disposed on a portion of the first electrode 21 and a portion of the second electrode 22, respectively. The first contact electrode 26 may be disposed on the first electrode 21, the second contact electrode 27 may be disposed on the second electrode 22, and each of the first contact electrode 26 and the second contact electrode 27 may have a shape extending in the second direction DR2. The first contact electrode 26 and the second contact electrode 27 may be spaced apart from each other in the first direction DR1, and may form a stripe pattern in the emission area EMA of each sub-pixel PXn.

[0162] In some embodiments, the width of each of the first contact electrode 26 and the second contact electrode 27 measured in one direction may be less than or equal to the width of each of the first electrode 21 and the second electrode 22 measured in the one direction. The first contact electrode 26 and the second contact electrode 27 may be disposed to contact one end and the other end of the light emitting element 30, respectively, and simultaneously cover a portion of the upper surface of the first electrode 21 and a portion of the upper surface of the second electrode 22, respectively.

[0163] Each of the plurality of contact electrodes 26 and 27 may be in contact with the light emitting element 30, and may be in contact with the electrodes 21 and 22, respectively. The semiconductor layer may be exposed on the surfaces of both ends in the direction in which the light emitting element 30 extends, and the first contact electrode 26 and the second contact electrode 27 may be in contact with the surface of the end at which the semiconductor layer of the light emitting element 30 is exposed. One end of the light emitting element 30 may be electrically connected to the first electrode 21 through the first contact electrode 26, and the other end thereof may be electrically connected to the second electrode 22 through the second contact electrode 27.

[0164] In the drawings, one first contact electrode 26 and one second contact electrode 27 are provided in one subpixel PXn, but the invention is not limited thereto. The number of first contact electrodes 26 and second contact electrodes 27 may vary according to the number of first electrodes 21 and second electrodes 22 provided in each subpixel PXn.

[0165] The third insulating layer 53 is disposed on the first contact electrode 26. The third insulating layer 53 can electrically insulate the first contact electrode 26 and the second contact electrode 27 from each other. The third insulating layer 53 may be disposed to cover the first contact electrode 26, and may not be disposed on the other end of the light emitting element 30 so that the light emitting element 30 can contact the second contact electrode 27. The third insulating layer 53 may partially contact the first contact electrode 26 and the second insulating layer 52 at the upper surface of the second insulating layer 52. The side surface of the third insulating layer 53 facing the side where the second electrode 220 is disposed may be aligned with one side surface of the second insulating layer 52. In addition, the third insulating layer 53 may also be disposed in a non-light emitting region (for example, on the first insulating layer 51 disposed on the first planarization layer 19). However, the invention is not limited thereto.

[0166] The second contact electrode 27 is disposed on the second electrode 22, the second insulating layer 52, and the third insulating layer 53. The second contact electrode 27 may contact the other end of the light emitting element 30 and the exposed upper surface of the second electrode 22. The other end of the light emitting element 30 may be electrically connected to the second electrode 22 through the second contact electrode 27.

[0167] The second contact electrode 27 may partially contact the second insulating layer 52, the third insulating layer 53, the second electrode 22, and the light emitting element 30. The first contact electrode 26 and the second contact electrode 27 may not contact each other due to the second insulating layer 52 and the third insulating layer 53. However, the present invention is not limited thereto, and in some cases, the third insulating layer 53 may be omitted.

[0168] The contact electrodes 26 and 27 may include a conductive material. For example, the contact electrodes 26 and 27 may include ITO, IZO, ITZO, or aluminum (Al), etc. As an example, the contact electrodes 26 and 27 may include a transparent conductive material, and the light emitted from the light emitting element 30 may pass through the contact electrodes 26 and 27 and travel toward the electrodes 21 and 22. However, the invention is not limited thereto.

[0169] The fourth insulating layer 54 may be completely disposed on the first substrate 11. The fourth insulating layer 54 may serve to protect components disposed on the first substrate 11 from external environments.

[0170] Each of the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may include an inorganic insulating material or an organic insulating material. In an embodiment, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53, and the fourth insulating layer 54 may include an inorganic insulating material or an organic insulating material. x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (Al2 O 3 ) or an inorganic insulating material such as aluminum nitride (AlN). Alternatively, the first insulating layer 51, the second insulating layer 52, the third insulating layer 53 and the fourth insulating layer 54 may include an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, PI resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin, benzocyclobutene, cardo resin, siloxane resin, silsesquioxane resin, polymethyl methacrylate, polycarbonate or polymethyl methacrylate-polycarbonate synthetic resin. However, the invention is not limited thereto.

[0171] At the same time, the first electrode 21 and the second electrode 22 may transmit a driving signal to the light emitting element 30 during the driving of the display device 10, so that the light emitting element 30 emits light. During the driving of the display device 10 or in the driving mode, the first power supply voltage may be transmitted to the first electrode 21 through the first transistor T1, and the second power supply voltage may be transmitted to the second electrode 22 through the second voltage wiring VSL. In addition, the data signal may be applied to the first gate electrode G1 of the first transistor T1 through the third transistor T3, and the initialization voltage may be transmitted to the first source electrode S1 or the first electrode 21 through the fourth transistor T4.

[0172] During the manufacturing process of the display device 10, an alignment signal is applied to the first electrode 21 and the second electrode 22. When the alignment signal is applied to the first electrode 21 and the second electrode 22, an electric field may be generated above the electrodes 21 and 22 due to the voltage difference between the electrodes 21 and 22. In the manufacturing process or manufacturing mode of the display device 10, the light emitting element 30 may be ejected onto the electrodes 21 and 22 in a state dispersed in ink, and the light emitting element 30 subjected to the dielectrophoretic force due to the electric field may be arranged so that both ends thereof are placed on the electrodes 21 and 22 during the change of its alignment direction and position. That is, different electric signals may be transmitted to the first electrode 21 and the second electrode 22 according to the driving or manufacturing process of the display device 10.

[0173] In the manufacturing process of the display device 10, when each of the electrodes 21 and 22 is formed in a separated state and an alignment signal is applied through the first transistor T1 and the second voltage wiring VSL connected to the electrodes 21 and 22, a voltage drop of a signal applied through the second voltage wiring VSL or damage of the first transistor T1 due to the alignment voltage may occur. In order to prevent this, after forming each of the electrodes 21 and 22 disposed in a connected state in a plurality of pixels PX or a plurality of sub-pixels PXn, an alignment signal may be applied to the electrodes 21 and 22 through a separate pad. However, in order for the light emitting element 30 to emit light individually for each sub-pixel PXn, a process of separating each of the electrodes 21 and 22 for each sub-pixel PXn may be necessary.

[0174] Unlike the transistor to which the driving signal for driving the light emitting element 30 is applied, the display device 10 according to one embodiment may further include a transistor to which an alignment signal for aligning the light emitting element 30 is applied. The second transistor T2 and the fourth transistor T4 of the display device 10 may be electrically connected to the second electrode 22 and the first electrode 21, respectively, and the alignment signal for aligning the light emitting element 30 may be applied through the second transistor T2 and the fourth transistor T4, respectively, during the manufacturing process of the display device 10. Each of the second transistor T2 and the fourth transistor T4 has a gate electrode that may be connected to the alignment signal line ASL or the sensing line SSL, and may be turned on at the same timing. During the manufacturing process of the display device 10, by turning on the second transistor T2 and the fourth transistor T4, the alignment signal may be applied to the first electrode 21 and the second electrode 22, respectively, through the data line DTL and the initialization voltage wiring VIL.

[0175] In particular, the second transistor T2 may be a transistor that substantially does not transmit a signal to the second electrode 22 when the display device 10 is driven. The fourth transistor T4 may be turned on when the corresponding sub-pixel PXn is driven to transmit an initialization voltage, but the second transistor T2 may remain in an off state when the corresponding sub-pixel PXn is driven, or may be turned on but may not transmit an electrical signal. The signal applied to the alignment signal line ASL may be applied through the pad WPD_AS provided in the pad area PDA, and the signal may not be applied during the driving of the display device 10. The alignment signal line ASL may be used during the manufacturing process, and thereafter, the alignment signal line ASL may be maintained as a floating wiring during driving. Since the second transistor T2 is not turned on in response to the signal of the alignment signal line ASL even when the second drain electrode D2 of the second transistor T2 is connected to the data line DTL, the signal of the second transistor T2 may not be transmitted when the light emitting element 30 is driven.

[0176] In addition, the second transistor T2 connected to the second electrode 22 is connected to the second data line DTL2 to which the data signal is applied at a timing different from the timing of the first data line DTL1 to which the data signal for causing the corresponding sub-pixel PXn to emit light is applied. Even when the second transistor T2 is turned on during the driving of the display device 10, the signal for causing the corresponding sub-pixel PXn to emit light is not applied. Therefore, the second transistor T2 may apply an alignment signal to the second electrode 22 during the manufacturing process of the display device 10, but may not transmit an electrical signal to the second electrode 22 during the driving of the display device 10.

[0177] However, the invention is not limited thereto, and in the display device 10, the alignment signal line ASL may be omitted, and the second transistor T2 may be connected to the sensing line SSL. Although the second transistor T2 and the fourth transistor T4 may be turned on simultaneously in response to the sensing line SSL, even when the second transistor T2 is turned on during driving of the display device 10, the influence on the light emission of each sub-pixel PXn may be small.

[0178] Since each of the electrodes 21 and 22 can be formed in a separated state when the display device 10 includes the second transistor T2, an additional separation process of the electrodes 21 and 22 can be omitted after aligning the light emitting element 30. In addition, since the second transistor T2 to which the electrical signal is substantially not transmitted in the driving mode of the display device 10 is included, the alignment signal can be applied through the second transistor T2, thereby preventing the first transistor T1 as the driving transistor from being damaged by the alignment signal in the manufacturing mode of the display device 10.

[0179] Fig.10 is a schematic cross-sectional view showing a portion of a display device according to another embodiment.

[0180] Reference Fig.10 , the third insulating layer 53 may be omitted from the display device 10. A portion of the second contact electrode 27 may be directly disposed on the second insulating layer 52, and the first contact electrode 26 and the second contact electrode 27 may be spaced apart from each other on the second insulating layer 52. In the display device 10 according to one embodiment, even if the third insulating layer 53 is omitted, the second insulating layer 52 may include an organic insulating material for fixing the light emitting element 30. In addition, the first contact electrode 26 and the second contact electrode 27 may be formed simultaneously by a patterning process. In addition to omitting the third insulating layer 53, Fig.10 Examples and Figure 8 Hereinafter, repeated description will be omitted.

[0181] Fig.11 is a schematic diagram of a light emitting element according to an embodiment.

[0182] The light emitting element 30 may be a light emitting diode (LED), specifically, an inorganic LED having a size in micrometer units or nanometer units and made of an inorganic material. When an electric field is formed in a specific direction between two electrodes facing each other, the inorganic LED may be aligned between the two electrodes in which polarity is formed. The light emitting element 30 may be aligned between the two electrodes due to the electric field formed on the two electrodes.

[0183] The light emitting element 30 according to one embodiment may have a shape extending in one direction. The light emitting element 30 may have a rod-like, linear or tubular shape, etc. In an embodiment, the light emitting element 30 may have a cylindrical shape or a rod-like shape. However, the shape of the light emitting element 30 is not limited thereto, and the light emitting element 30 may have various forms such as a cube, a cuboid, a polygonal column such as a hexagonal column, or a shape extending in one direction and having a partially inclined outer surface. The plurality of semiconductors included in the light emitting element 30 described below may have a structure in which the semiconductors are sequentially arranged or stacked in one direction.

[0184] The light emitting element 30 may include a semiconductor layer doped with impurities of any conductive type (eg, p-type or n-type), and the semiconductor layer may emit light of a specific wavelength band by receiving an electrical signal applied from an external power source.

[0185] refer to Fig.11 The light emitting element 30 may include a first semiconductor layer 31 , a second semiconductor layer 32 , a light emitting layer 36 , an electrode layer 37 and an insulating film 38 .

[0186] The first semiconductor layer 31 may be an n-type semiconductor. As an example, when the light emitting element 30 emits light in the blue band, the first semiconductor layer 31 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-y N (0≤x≤1, 0≤y≤1, and 0≤x+y≤1) semiconductor material. For example, the semiconductor material may be one or more of n-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The first semiconductor layer 31 may be doped with an n-type dopant. As an example, the n-type dopant may be Si, Ge, Se, or Sn, etc. In an embodiment, the first semiconductor layer 31 may include n-GaN doped with n-type Si. The first semiconductor layer 31 may have a length in the range of 1.5 μm to 5 μm, but the invention is not limited thereto.

[0187] The second semiconductor layer 32 is disposed on the light emitting layer 36 to be described below. The second semiconductor layer 32 may be a p-type semiconductor. As an example, when the light emitting element 30 emits light in a blue band or a green band, the second semiconductor layer 32 may include a semiconductor having a chemical formula of Al x Ga y In 1-x-yN (0≤x≤1, 0≤y≤1, and 0≤x+y≤1) semiconductor material. For example, the semiconductor material may be one or more of p-doped AlGaInN, GaN, AlGaN, InGaN, AlN, and InN. The second semiconductor layer 32 may be doped with a p-type dopant, and as an example, the p-type dopant may be Mg, Zn, Ca, or Ba, etc. In an embodiment, the second semiconductor layer 32 may include p-GaN doped with p-type Mg. The second semiconductor layer 32 may have a length in the range of 0.05 μm to 0.10 μm, but the invention is not limited thereto.

[0188] Meanwhile, in the drawings, each of the first semiconductor layer 31 and the second semiconductor layer 32 is shown as being formed as one layer, but the invention is not limited thereto. According to some embodiments, each of the first semiconductor layer 31 and the second semiconductor layer 32 may also include a larger number of layers (e.g., a cap layer or a tensile strain barrier reduction (TSBR) layer) according to the material of the light emitting layer 36.

[0189] The light emitting layer 36 is disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light emitting layer 36 may include a material having a single quantum well structure or a multi-quantum well structure. When the light emitting layer 36 includes a material having a multi-quantum well structure, the light emitting layer 36 may have a structure in which a plurality of quantum layers and a plurality of well layers are alternately stacked. The light emitting layer 36 may emit light due to a combination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. As an example, when the light emitting layer 36 emits light in a blue band, the light emitting layer 36 may include a material such as AlGaN or AlGaInN. In particular, in the case where the light emitting layer 36 has a multi-quantum well structure in which quantum layers and well layers are alternately stacked, the quantum layer may include a material such as AlGaN or AlGaInN, and the well layer may include a material such as GaN or AlInN. In an embodiment, the light emitting layer 36 may include AlGaInN as a quantum layer, and the light emitting layer 36 may emit blue light having a central band in the range of 450nm to 495nm.

[0190] However, the invention is not limited thereto, and the light emitting layer 36 may have a structure in which a semiconductor material having a high energy band gap and a semiconductor material having a low energy band gap are alternately stacked, or may include other III-group to V-group semiconductor materials according to the wavelength band of the emitted light. The light emitted by the light emitting layer 36 is not limited to light in the blue wavelength band, and in some cases, the light emitting layer 36 may also emit light in the red wavelength band or the green wavelength band. The light emitting layer 36 may have a length in the range of 0.05 μm to 0.10 μm, but the invention is not limited thereto.

[0191] Meanwhile, light emitted from the light emitting layer 36 may also be emitted to both side surfaces in the length direction of the light emitting element 30 in addition to the outer surface of the light emitting element 30. Directivity of light emitted from the light emitting layer 36 is not limited to one direction.

[0192] The electrode layer 37 may be an ohmic contact electrode. However, the present invention is not limited thereto, and the electrode layer 37 may also be a Schottky contact electrode. The light emitting element 30 may include at least one electrode layer 37. Fig.11 37. The light emitting element 30 is shown as including one electrode layer 37, but the invention is not limited thereto. In some cases, the light emitting element 30 may include a larger number of electrode layers 37, or the electrode layer 37 may be omitted. Even when the number of electrode layers 37 is changed or the light emitting element 30 includes other structures, the following description of the light emitting element 30 may also be applied in the same manner.

[0193] In the display device 10 according to an embodiment, when the light emitting element 30 is electrically connected to the electrode or the contact electrode, the electrode layer 37 can reduce the resistance between the light emitting element 30 and the electrode or between the light emitting element 30 and the contact electrode. The electrode layer 37 may include a conductive metal. For example, the electrode layer 37 may include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO). In addition, the electrode layer 37 may include a semiconductor material doped with n-type or p-type. The electrode layer 370 may include the same material or different materials, but the invention is not limited thereto.

[0194] The insulating film 38 is provided to surround the outer surfaces of the plurality of semiconductor layers and the electrode layer. In an embodiment, the insulating film 38 may be provided to surround at least the outer surface of the light emitting layer 36, and may extend in one direction along which the light emitting element 30 extends. The insulating film 38 may be used to protect the member. As an example, the insulating film 38 may be formed to surround the side surface of the member, and may be formed to expose both ends of the light emitting element 30 in the length direction.

[0195] In the drawings, the insulating film 38 is shown to be formed to extend in the length direction of the light emitting element 30 to cover from the side surface of the first semiconductor layer 31 to the side surface of the electrode layer 37, but the invention is not limited thereto. Since the insulating film 38 covers only the outer surfaces of some semiconductor layers including the light emitting layer 36 or only covers a portion of the outer surface of the electrode layer 37, the outer surface of the electrode layer 37 may be partially exposed. In addition, the upper surface of the insulating film 38 may be formed to be rounded in cross section in a region adjacent to at least one end of the light emitting element 30.

[0196] The insulating film 38 may have a thickness in the range of 10 nm to 1.0 μm, but the invention is not limited thereto. Preferably, the insulating film 38 may have a thickness of about 40 nm.

[0197] The insulating film 38 may include a material having insulating properties, for example, silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum nitride (AlN) and aluminum oxide (Al 2 O 3 ) etc. Therefore, it is possible to prevent an electrical short circuit that may occur when the light emitting layer 36 is in direct contact with an electrode through which an electrical signal is transmitted to the light emitting element 30. In addition, since the insulating film 38 protects the outer surface of the light emitting element 30 including the light emitting layer 36, it is possible to prevent the light emission efficiency from being deteriorated.

[0198] In addition, in some embodiments, the outer surface of the insulating film 38 may be surface-treated. The light-emitting element 30 dispersed in a predetermined ink may be ejected onto the electrode and aligned thereon. Here, in order to maintain a state in which the light-emitting element 30 is dispersed in the ink without agglomerating with other adjacent light-emitting elements 30, the surface of the insulating film 38 may be treated to be hydrophobic or hydrophilic.

[0199] The light emitting element 30 may have a length h in the range of 1 μm to 10 μm or 2 μm to 6 μm, and preferably in the range of 3 μm to 5 μm. In addition, the diameter of the light emitting element 30 may be in the range of 300 nm to 700 nm, and the aspect ratio of the light emitting element 30 may be in the range of 1.2 to 100. However, the invention is not limited thereto, and the plurality of light emitting elements 30 included in the display device 10 may have different diameters according to the composition difference of the light emitting layer 36. Preferably, the diameter of the light emitting element 30 may have a range of about 500 nm.

[0200] Hereinafter, a manufacturing process of the display device 10 according to one embodiment will be described further with reference to other drawings.

[0201] A manufacturing method of a display device 10 according to an embodiment may include ejecting ink including a light emitting element 30 on electrodes 21 and 22, and applying an alignment signal to the electrodes 21 and 22 so that the light emitting element 30 is mounted on the electrodes 21 and 22. Unlike when the display device 10 is driven, the alignment signal applied to the first electrode 21 and the second electrode 22 may be transmitted through the fourth transistor T4 and the second transistor T2, respectively. Each of the second transistor T2 and the fourth transistor T4 has a gate electrode connected to the alignment signal line ASL or the sensing line SSL, and may be turned on simultaneously. The alignment signal applied to the data line DTL and the initialization voltage wiring VIL may be transmitted to the second electrode 22 and the first electrode 21, respectively, through the turned-on second transistor T2 and the fourth transistor T4. Hereinafter, the manufacturing process of the display device 10 will be further described with reference to other drawings.

[0202] Fig.12 and Fig.13 1 is a schematic plan view illustrating some operations of a manufacturing process of a display device according to an embodiment.

[0203] First, refer to Fig.12 , a plurality of electrodes 21 and 22 and a first insulating layer 51 and a second bank 45 disposed on the electrodes 21 and 22 are formed. Each of the first electrode 21 and the second electrode 22 is disposed to extend in the second direction DR2. Each of the electrodes 21 and 22 extends in the second direction DR2 in the emission area EMA of each sub-pixel PXn, and may be separated from the other electrodes 21 and 22 at the cutout area CBA. The description of the arrangement and shape of the first insulating layer 51, the first bank 40 and the second bank 45 is the same as the above description.

[0204] Then, refer to Fig.13 , ink (not shown) in which the light-emitting elements 30 are dispersed is ejected onto the electrodes 21 and 22 disposed in the light-emitting area EMA surrounded by the second bank 45. In an embodiment, the light-emitting elements 30 are prepared in a state dispersed in the ink, and the light-emitting elements 30 can be ejected onto the electrodes 21 and 22 by a printing process using an inkjet printing device. The ink ejected by the inkjet printing device can settle in the area surrounded by the second bank 45. The light-emitting element 30 may have a shape extending in one direction, and may have an alignment direction in which one end thereof points to one of the electrodes 21 and 22. As shown in the accompanying drawings, a plurality of light-emitting elements 30 dispersed in the ink may have a random alignment direction rather than a constant alignment direction. Some light-emitting elements 30 may be placed between the electrodes 21 and 22 and the second bank 45 or above the electrodes 21 and 22, which are areas other than the area between the electrodes 21 and 22.

[0205] In order to align the light emitting element 30 on the electrodes 21 and 22, an alignment signal is applied to each of the electrodes 21 and 22 to generate an electric field on the electrodes 21 and 22. Each of the light emitting elements 30 dispersed in the ink can be arranged so that both ends thereof are placed on the electrodes 21 and 22 while its position and alignment direction are changed due to the electric field.

[0206] Fig.14 is a schematic circuit diagram illustrating one operation of a manufacturing process of a display device according to one embodiment. Fig.15 is a schematic plan view illustrating one operation of a manufacturing process of a display device according to one embodiment.

[0207] Reference Fig.14 and Fig.15 , the alignment voltages ASN1 and ASN2 are applied to the first electrode 21 and the second electrode 22 respectively through the fourth transistor T4 and the second transistor T2 of each sub-pixel PXn to generate an electric field E on the electrodes 21 and 22. According to one embodiment, during the manufacturing process of the display device 10, the second transistor T2 and the fourth transistor T4 are turned on at the same timing by applying a signal through the alignment signal line ASL and the sensing line SSL, and the alignment voltages ASN1 and ASN2 are applied through the initialization voltage wiring VIL and the data line DTL respectively. The fourth transistor T4 can transmit the first alignment voltage ASN1 applied through the initialization voltage wiring VIL or the initialization voltage distribution line IDL to the first electrode 21, and the second transistor T2 can transmit the second alignment voltage ASN2 applied through the data line DTL to the second electrode 22. The electric field E can be generated on the first electrode 21 and the second electrode 22 by the voltage difference between the applied alignment voltages ASN1 and ASN2, and the light emitting element 30 can be disposed on the electrodes 21 and 22 while changing its position and alignment direction due to the electric field E.

[0208] The light emitting element 30 dispersed in the ink may have a dipole moment therein because the plurality of semiconductor layers have polarity. The light emitting element 30 having a dipole moment may be subjected to a dielectrophoretic force according to the intensity or direction of the electric field E and may move so that both ends thereof may be placed on the electrodes 21 and 22, respectively.

[0209] The display device 10 may apply an alignment signal to each of the electrodes 21 and 22 using a transistor other than the first transistor T1 as a driving transistor. The second transistor T2, which substantially does not transmit a signal during driving of the display device 10, may be turned on simultaneously with the fourth transistor T4 at the same timing. Since the fourth transistor T4 is electrically connected to the first electrode 21 and the second transistor T2 is electrically connected to the second electrode 22, during the manufacturing process of the display device 10, alignment voltages ASN1 and ASN2 may be transmitted to the first electrode 21 and the second electrode 22 through the fourth transistor T4 and the second transistor T2, respectively. The second transistor T2 and the fourth transistor T4 may be turned on simultaneously through the alignment signal line ASL and the sensing line SSL, respectively, and the alignment voltages ASN1 and ASN2 may be applied through the initialization voltage wiring VIL and the data line DTL, respectively, so that the light emitting element 30 is aligned on the first electrode 21 and the second electrode 22.

[0210] The first alignment voltage ASN1 transmitted by the fourth transistor T4 may be different from the second alignment voltage ASN2 transmitted by the second transistor T2. In some embodiments, the second alignment voltage ASN2 transmitted by the second transistor T2 may be an alternating current (AC) voltage or a direct current (DC) voltage, and the first alignment voltage ASN1 transmitted by the fourth transistor T4 may be a ground voltage. That is, when the first electrode 21 is grounded and the AC voltage or the DC voltage is transmitted to the second electrode 22, an electric field E may be generated by the voltage difference therebetween. However, the invention is not limited thereto, and the alignment signals applied to the first electrode 21 and the second electrode 22 may be opposite to each other, and in some cases, the AC voltage or the DC voltage may be applied to each of the first electrode 21 and the second electrode 22.

[0211] Subsequently, although not shown in the drawings, after removing the ink, a second insulating layer 52, a third insulating layer 53, a first contact electrode 26, a second contact electrode 27, and a fourth insulating layer 54 are formed on the light emitting element 30. The description of their arrangement and shape is the same as the above description. The display device 10 including a plurality of light emitting elements 30 can be manufactured by the above process.

[0212] In the display device 10 according to one embodiment, transistors for applying signals to the first electrode 21 and the second electrode 22 during the driving and manufacturing processes of the display device 10 may be different. In particular, since an alignment signal can be applied by a transistor other than the driving transistor during the manufacturing process, an alignment signal can be applied individually to each sub-pixel PXn. Therefore, even when a plurality of electrodes 21 and 22 are formed in a separated state for each sub-pixel PXn, an alignment signal can be applied, and a process of separating each of the electrodes 21 and 22 for each sub-pixel PXn after aligning the light emitting element 30 can be omitted.

[0213] Hereinafter, other embodiments of the display device 10 will be described with reference to other drawings.

[0214] Fig.16 is a schematic plan view showing one sub-pixel of a display device according to still another embodiment. Fig.17 yes Fig.16 The equivalent circuit diagram of a sub-pixel. Fig.16 , only the display element layer of the first sub-pixel PX1 is schematically shown.

[0215] Reference Fig.16 and Fig.17 According to an embodiment, the display device 10 may include a large number of electrodes 21_1, 22_1, and 23_1 for each sub-pixel PXn. The display device 10 may also include a third electrode 23_1 for each sub-pixel PXn, and the light emitting element 30 may also be disposed between the second electrode 22_1 and the third electrode 23_1. Figure 7 The embodiment of the present invention is different in that a third electrode 23_1 provided for each sub-pixel PXn is further included. Hereinafter, redundant descriptions will be omitted, and descriptions will be provided based on differences from the above-mentioned contents.

[0216] Each sub-pixel PXn of the display device 10 further includes a third electrode 23_1 spaced apart from the second electrode 22_1 in the first direction DR1 and extending in the second direction DR2. The shape of the third electrode 23_1 is substantially the same as that of the first electrode 21_1 and the second electrode 22_1. A larger number of first banks 40 may be disposed in the emission area EMA of each sub-pixel PXn, and at least a portion of each of the electrodes 21_1, 22_1, and 23_1 may be disposed on the first banks 40.

[0217] A plurality of light emitting elements 30A and 30B (collectively referred to as 30) may include a first light emitting element 30A disposed on the first electrode 21_1 and the second electrode 22_1 and a second light emitting element 30B disposed on the second electrode 22_1 and the third electrode 23_1. One end of the first light emitting element 30A is disposed on the first electrode 21_1, and the other end thereof is disposed on the second electrode 22_1. One end of the second light emitting element 30B is disposed on the third electrode 23_1, and the other end thereof is disposed on the second electrode 22_1. The one end of the first light emitting element 30A and the one end of the second light emitting element 30B may face opposite directions. During the manufacturing process of the display device 10, when the same alignment signal is applied to the first electrode 21_1 and the third electrode 23_1 and a different alignment signal is applied to the second electrode 22_1, the direction in which one end of the light emitting element 30 faces may be different due to the voltage difference therebetween.

[0218] In addition, since the display device 10 includes a larger number of electrodes 21_1 , 22_1 , and 23_1 , the display device 10 may include a larger number of contact electrodes 26_1 , 27_1 , and 28_1 .

[0219] In an embodiment, the contact electrodes 26_1 , 27_1 and 28_1 may include a first contact electrode 26_1 disposed on the first electrode 21_1 , a second contact electrode 27_1 disposed on one side of the second electrode 22_1 , and a third contact electrode 28_1 disposed on the other side of the second electrode 22_1 and the third electrode 23_1 and surrounding the second contact electrode 27_1 .

[0220] The first contact electrode 26_1 may be disposed on the first electrode 21_1 on which one end of the first light emitting element 30A is disposed, and may be in contact with the one end of the first light emitting element 30A. The second contact electrode 27_1 may be disposed on the second electrode 22_1 on which the other end of the second light emitting element 30B is disposed, and may be in contact with the other end of the second light emitting element 30B. The first contact electrode 26_1 and the second contact electrode 27_1 may be in contact with the first electrode 21_1 and the second electrode 22_1, respectively. The first contact electrode 26_1 may be in contact with the first electrode 21_1 electrically connected to the first transistor T1 through the first electrode contact hole CTD, and the second contact electrode 27_1 may be in contact with the second electrode 22_1 electrically connected to the second voltage wiring VSL through the second electrode contact hole CTS. The first contact electrode 26_1 and the second contact electrode 27_1 may transmit an electrical signal applied from the first transistor T1 or the second voltage wiring VSL to the light emitting element 30.

[0221] Each subpixel PXn may include a third electrode 23_1 in which the first electrode contact hole CTD and the second electrode contact hole CTS are not formed. When the display device 10 is driven, the third electrode 23_1 may be in a floating state in which an electric signal is not directly applied from the first transistor T1 or the second voltage wiring VSL. However, a third contact electrode 28_1 may be provided on the third electrode 23_1, and an electric signal transmitted to the light emitting element 30 may flow through the third contact electrode 28_1.

[0222] The third contact electrode 28_1 may be disposed on the third electrode 23_1 to surround the second contact electrode 27_1. The third contact electrode 28_1 may surround the second contact electrode 27_1 by including a portion extending in the second direction DR2 and a portion extending in the first direction DR1 and configured to connect the portion extending in the second direction DR2. The portion of the third contact electrode 28_1 extending in the second direction DR2 may be disposed on one side of the third electrode 23_1 and the other side of the second electrode 22_1, and may contact the light emitting element 30. For example, the portion of the third contact electrode 28_1 disposed on the second electrode 22_1 may contact the other end of the first light emitting element 30A, and the portion of the third contact electrode 28_1 disposed on the third electrode 23_1 may contact one end of the second light emitting element 30B. The portion of the third contact electrode 28_1 extending in the first direction DR1 and the second electrode 22_1 may overlap each other, but may not directly contact each other because another insulating layer (not shown) may be disposed therebetween.

[0223] The electric signal transmitted from the first contact electrode 26_1 to one end of the first light emitting element 30A is transmitted to the third contact electrode 28_1 in contact with the other end of the first light emitting element 30A. The third contact electrode 28_1 may transmit the electric signal to one end of the second light emitting element 30B, and the electric signal may be transmitted to the second electrode 22_1 through the second contact electrode 27_1. Therefore, the electric signal transmitted from the first transistor T1 and the second voltage wiring VSL to allow the light emitting element 30 to emit light may be transmitted only to the first electrode 21_1 and the second electrode 22_1, and the first light emitting diode ELA including the first light emitting element 30A and the second light emitting diode ELB including the second light emitting element 30B may be connected in series through the third electrode 23_1 and the third contact electrode 28_1 as the light emitting diode EL provided in each sub-pixel PXn.

[0224] Meanwhile, an alignment signal for the manufacturing process of the display device 10 may be transmitted to each of the first electrode 21_1, the second electrode 22_1, and the third electrode 23_1. The first electrode 21_1 may be electrically connected to the first transistor T1 and the fourth transistor T4. However, according to one embodiment, the second electrode 22_1 may be electrically connected to the second voltage wiring VSL, and the third electrode 23_1 may be electrically connected to the second transistor T2 through the third electrode contact hole CTA. This embodiment is different from other embodiments in that the second transistor T2 is connected to the third electrode 23_1 and is thus connected between the first light emitting diode ELA and the second light emitting diode ELB. The second transistor T2 may be electrically connected to the third electrode 23_1, and the first light emitting diode ELA and the second light emitting diode ELB are connected in series through the third electrode 23_1. During the manufacturing process of the display device 10, the alignment signal may be applied to the first electrode 21_1 and the third electrode 23_1 through the fourth transistor T4 and the second transistor T2, respectively, and the alignment signal may be applied to the second electrode 22_1 through the second voltage wiring VSL. When the alignment signal applied to the second electrode 22_1 has a voltage difference with the alignment signals applied to the first electrode 21_1 and the third electrode 23_1 , an electric field E may be generated therebetween so that the light emitting elements 30A and 30B (collectively referred to as 30 ) may be aligned.

[0225] Fig.18 It is shown Fig.16 A schematic plan view of one operation of a manufacturing process of a display device. Fig.19 It is shown Fig.16 A schematic circuit diagram of one operation of a manufacturing process of a display device.

[0226] Reference Fig.18 and Fig.19When the ink in which the light emitting elements 30 are dispersed is ejected on the electrodes 21_1, 22_1, and 23_1, the alignment voltages ASN1, ASN2, and ASN3 may be applied through the fourth transistor T4, the second voltage wiring VSL, and the second transistor T2, respectively. The second transistor T2 and the fourth transistor T4 may be turned on in response to the signals applied through the alignment signal line ASL and the sensing line SSL, respectively, to transmit the alignment voltages to the third electrode 23_1 and the first electrode 21_1, respectively. In addition, the alignment voltage may also be applied to the second voltage wiring VSL, and may be transmitted to the second electrode 22_1. In an embodiment, the first alignment voltage ASN1 and the third alignment voltage ASN3 respectively applied to the first electrode 21_1 and the third electrode 23_1 are the same voltage, the second alignment voltage ASN2 applied to the second electrode 22_1 is different from the first alignment voltage ASN1 and the third alignment voltage ASN3, and due to the voltage difference of the alignment signal between the first electrode 21_1 and the second electrode 22_1 and between the second electrode 22_1 and the third electrode 23_1, an electric field E may be generated between the first electrode 21_1 and the second electrode 22_1 and between the second electrode 22_1 and the third electrode 23_1. As an example, an AC voltage may be applied to the first electrode 21_1 and the third electrode 23_1, and a DC voltage may be applied to the second electrode 22_1. The voltage difference between the first electrode 21_1 and the third electrode 23_1 and the second electrode 22_1 may generate an electric field E therebetween, and the light emitting element 30 may be aligned on the electrodes 21_1, 22_1, and 23_1 by the electric field. However, the present invention is not limited thereto, and the types of the alignment voltages ASN1 , ASN2 , and ASN3 applied to the respective electrodes 21_1 , 22_1 , and 23_1 may be opposite to or different from each other.

[0227] The display device 10 according to the embodiment may include a larger number of electrodes 21_1, 22_1, and 23_1 to increase the number of light emitting elements 30 provided for each sub-pixel PXn. In addition, since the first light emitting element 30A and the second light emitting element 30B are connected in series, even when one light emitting element is short-circuited, current can flow through the other light emitting element, thereby reducing the defect rate of the sub-pixel PXn. In addition, since the second transistor T2 for applying the alignment signal during the manufacturing process of the display device 10 can be connected to an electrode different from the second voltage wiring VSL, the alignment signal can be applied to each of the electrodes 21_1, 22_1, and 23_1.

[0228] Fig. 20 is a layout diagram showing a plurality of conductive layers included in one sub-pixel of a display device according to still another embodiment. Fig.21 yes Fig. 20 The equivalent circuit diagram of a sub-pixel. Fig. 20, a layout diagram of a light blocking layer, a semiconductor layer, a first gate conductive layer, and a first data conductive layer of a circuit element layer disposed in a second subpixel PX2 is shown.

[0229] Reference Fig. 20 and Fig.21 In the display device 10, the alignment signal line ASL may be omitted, and the second gate electrode G2 of the second transistor T2 may be electrically connected to the sensing line SSL_2. A signal for turning on the second transistor T2 and the fourth transistor T4 may be applied to the sensing line SSL_2 during the manufacturing process of the display device 10, and this embodiment is different from Figure 5 and Figure 6 The embodiment of FIG. 1 is different in that the second gate electrode G2 of the second transistor T2 is connected to the sensing line SSL_2. Hereinafter, redundant descriptions will be omitted and descriptions will be provided based on differences from the above.

[0230] The third conductive pattern DP3 may contact the sensing line SSL_2 and the second gate electrode G2 through the contact hole CT10 passing through the first protection layer 15 disposed under the third conductive pattern DP3. The second gate electrode G2 may be electrically connected to the sensing line SSL_2 through the third conductive pattern DP3, and the second transistor T2 may be turned on in response to a signal applied from the sensing line SSL_2.

[0231] and Figure 3 and Figure 5 In different embodiments, the second transistor T2 and the third transistor T3 may be connected to the data line DTL, but may be connected to different signal lines so that the second transistor T2 and the third transistor T3 of each sub-pixel PXn may not be turned on at the same time. The second transistor T2 may be turned on in response to the signal of the sensing line SSL_2, and the third transistor T3 may be turned on in response to the signal of the scanning line SCL. In addition, the second transistor T2 and the third transistor T3 of the corresponding sub-pixel PXn are connected to the data lines DTL of different timings. For example, the third transistor T3 may be connected to the first data line DTL1 of the corresponding sub-pixel PXn, and the second transistor T2 may be connected to the second data line DTL2 of another sub-pixel PXn. Even when the second transistor T2 is turned on in response to the sensing signal, the data signal that may be transmitted by the second transistor T2 may be a signal transmitted at a timing different from the timing of the data signal that causes the corresponding sub-pixel PXn to emit light. Therefore, even when the second transistor T2 is turned on, the second transistor T2 may not transmit a signal when the corresponding sub-pixel PXn emits light.

[0232] In addition, since the second transistor T2 is turned on simultaneously with the fourth transistor T4 configured to transmit an initialization voltage to one electrode of the light emitting diode EL, the driving time can be reduced. Even when the second transistor T2 is turned on and data signals of different timings are transmitted to the second electrode 22, the influence on the light emission of the corresponding sub-pixel PXn can be small. In the display device 10 according to the embodiment, the alignment signal line ASL is omitted, and the second transistor T2 and the fourth transistor T4 can be turned on simultaneously using one wiring (e.g., the sensing line SSL_2), thereby reducing the number of wirings set in each sub-pixel PXn. Fig. 22 and Fig.23 is a schematic cross-sectional view showing a portion of a display device according to still another embodiment.

[0233] Reference Fig. 22 and Fig.23 , the display device 10 may further include a plurality of electrode conductive patterns CDP1_3 and CDP2_3 disposed in the second data conductive layer. The electrode conductive patterns CDP1_3 and CDP2_3 may include a first electrode conductive pattern CDP1_3 in contact with the second capacitor electrode CSE2 (or the first source electrode S1 and the first electrode 21 of the first transistor T1) and a second electrode conductive pattern CDP2_3 in contact with the second source electrode S2 and the second electrode 22 of the second transistor T2. The first electrode 21 and the second electrode 22 may be electrically connected to the first transistor T1 and the second transistor T2, respectively, and may be connected to the first transistor T1 and the second transistor T2, respectively, through the electrode conductive patterns CDP1_3 and CDP2_3 disposed in the second data conductive layer. This embodiment is different from Figure 8 and Fig. 9 The difference of the embodiment is that it further includes an electrode conductive pattern arranged in the second data conductive layer. In the following, redundant description will be omitted.

[0234] Meanwhile, the first electrode 21 and the second electrode 22 may not necessarily have a shape extending in one direction. In some embodiments, the electrodes 21 and 22 of the display device 10 may have a shape including portions extending in different directions and having different widths.

[0235] Fig.24 is a plan view showing one sub-pixel of a display device according to still another embodiment.

[0236] Reference Fig.24, each of the electrodes 21_4 and 22_4 of the display device 10 according to one embodiment may include an extension portion RE-E extending in the second direction DR2 and having a greater width than other portions, bent portions RE-B1 and RE-B2 extending in a direction inclined relative to the first direction DR1 and the second direction DR2, and connecting portions RE-C1 and RE-C2 connecting the bent portions RE-B1 and RE-B2 to the extension portion RE-E. Each of the electrodes 21_4 and 22_4 may have an overall shape extending in the second direction DR2, and may have a shape having a partially large width or bent in a direction inclined relative to the second direction DR2. The first electrode 21_4 and the second electrode 22_4 may be disposed in a symmetrical structure with respect to the first insulating layer 51 disposed therebetween. Hereinafter, the shape of the first electrode 21_4 will be mainly described.

[0237] The first electrode 21_4 may include an extension portion RE-E having a greater width than other portions. The extension portion RE-E may be disposed on the first bank 40 in the light emitting area EMA of the subpixel PXn, and may extend in the second direction DR2. The first insulating layer 51 may be disposed between the extension portion RE-E of the first electrode 21_4 and the extension portion RE-E of the second electrode 22_4, and the light emitting element 30 may be disposed on the first insulating layer 51. In addition, the first contact electrode 26_4 and the second contact electrode 27_4 may be disposed on the extension portions RE-E of the electrodes 21_4 and 22_4, respectively, and each may have a width smaller than the width of the extension portion RE-E.

[0238] The connection portions RE-C1 and RE-C2 may be connected to both sides of each of the extension portions RE-E in the second direction DR2. The first connection portion RE-C1 is disposed at one side of the extension portion RE-E in the second direction DR2, and the second connection portion RE-C2 is disposed at the other side of the extension portion RE-E. The connection portions RE-C1 and RE-C2 may be connected to the extension portion RE-E and may be disposed to cross the emission area EMA and the second bank 45 of each sub-pixel PXn.

[0239] The width of each of the first connection portion RE-C1 and the second connection portion RE-C2 may be smaller than the width of the extension portion RE-E. One side of each of the connection portions RE-C1 and RE-C2 extending in the second direction DR2 in the first direction DR1 may be collinear with one side of the extension portion RE-E extending in the second direction DR2. For example, among both sides of the extension portion RE-E in the first direction DR1 and both sides of the connection portions RE-C1 and RE-C2 in the first direction DR1, one side of the extension portion RE-E located at the outer side based on the center of the light emitting area EMA and one side of the connection portions RE-C1 and RE-C2 located at the outer side based on the center of the light emitting area EMA may extend to be connected to each other. Therefore, the interval DE1 between the extension portion RE-E of the first electrode 21_4 and the extension portion RE-E of the second electrode 22_4 may be smaller than the interval DE2 between the connection portions RE-C1 and RE-C2.

[0240] The bent portions RE-B1 and RE-B2 are connected to the connection portions RE-C1 and RE-C2, respectively. The bent portions RE-B1 and RE-B2 may include a first bent portion RE-B1 connected to the first connection portion RE-C1 and disposed to cross the second bank 45 and the cutout area CBA, and a second bent portion RE-B2 connected to the second connection portion RE-C2 and disposed to cross the second bank 45 and the cutout area CBA of another sub-pixel PXn. The bent portions RE-B1 and RE-B2 may be connected to the connection portions RE-C1 and RE-C2, respectively, and bend in a direction inclined relative to the second direction DR2 (e.g., toward the center of the sub-pixel PXn). Therefore, the shortest interval DE3 between the bent portions RE-B1 and RE-B2 of the first electrode 21_4 and the second electrode 22_4 may be smaller than the interval DE2 between the connection portions RE-C1 and RE-C2. However, the shortest interval DE3 between the bent portions RE-B1 and RE-B2 may be greater than the interval DE1 between the extended portions RE-E.

[0241] A contact portion RE-P having a relatively large width may be formed at a portion where the first connection portion RE-C1 and the first bent portion RE-B1 are connected. The contact portion RE-P may overlap the second bank 45, in which a first electrode contact hole CTD of the first electrode 21_4 and a second electrode contact hole CTS of the second electrode 22_4 may be formed.

[0242] In addition, a segment portion RE-D remaining after each of the first electrode 21_4 and the second electrode 22_4 is separated by the cutout area CBA may be formed at one end of the first bent portion RE-B1. The segment portion RE-D may be a portion remaining after each of the electrodes 21-4 and 22-4 of the sub-pixels PXn adjacent in the second direction DR2 is disconnected in the cutout area CBA.

[0243] Fig.24 Examples and Figure 7 The embodiment of the present invention is different in that each of the first electrode 21_4 and the second electrode 22_4 includes an extension portion RE-E, connection portions RE-C1 and RE-C2, and bent portions RE-B1 and RE-B2 that are symmetrically disposed with respect to the center of the subpixel PXn. However, the invention is not limited thereto, and in some cases, the first electrode 21_4 and the second electrode 22_4 may have different shapes.

[0244] Fig.25 is a plan view showing one sub-pixel of a display device according to still another embodiment. Fig.26 It is along Fig.25 A cross-sectional view taken along line QX-QX'.

[0245] Reference Fig.25 and Fig.26 The display device 10 may include a plurality of first electrodes 21_5 and a plurality of second electrodes 22_5 for each sub-pixel PXn. The first electrode 21_5 may have Fig.24 The second electrode 22_5 may have the same shape as the first electrode 21_4 in the embodiment of the present invention, and a plurality of first electrodes 21_5 (for example, two first electrodes 21_5) may be symmetrically arranged with respect to the center of the sub-pixel PXn. Figure 7 In the embodiment of the present invention, the first electrode 21 has the same shape as the shape of the first electrode 21, and a plurality of second electrodes 22_5 (for example, two second electrodes 22_5) may be disposed between the first electrode 21_5. The interval between the first electrode 21_5 and the second electrode 22_5 may be changed according to the portion of the first electrode 21_5. For example, the interval DE1 between the extension portion RE-E and the second electrode 22_5 may be smaller than the interval DE2 between each of the connecting portions RE-C1 and RE-C2 and the second electrode 22_5 and the interval DE3 between each of the bending portions RE-B1 and RE-B2 and the second electrode 22_5. The interval DE2 between each of the connecting portions RE-C1 and RE-C2 and the second electrode 22_5 may be larger than the interval DE3 between each of the bending portions RE-B1 and RE-B2 and the second electrode 22_5. However, the invention is not limited thereto. Since the shape of each of the electrodes 21_5 and 22_5 is the same as that described above with reference to Figure 7 and Fig.24 The descriptions are the same, so their detailed descriptions will be omitted.

[0246] Meanwhile, the arrangement and shape of the first banks 41_5 and 42_5 (collectively referred to as 40 ) and the contact electrodes 26_5 , 27_5 , and 28_5 provided in each subpixel PXn may be changed according to the arrangement of the first electrode 21_5 and the second electrode 22_5 .

[0247] The first bank 40 may include a first sub-bank 41_5 and a second sub-bank 42_5 having different widths. The first sub-bank 41_5 and the second sub-bank 42_5 may both extend in the second direction DR2, and the widths measured in the first direction DR1 may be different. Since the first sub-bank 41_5 has a greater width than the second sub-bank 42_5, the first sub-bank 41_5 may be arranged to cross the boundary of the sub-pixels PXn adjacent in the first direction DR1. For example, the first sub-bank 41_5 may also be arranged at the boundary between them and the emission area EMA of each sub-pixel PXn. Therefore, a portion of the second bank 45_5 extending in the second direction DR2 may be partially arranged on the first sub-bank 41_5. Two first sub-banks 41_5 may be partially arranged in one sub-pixel PXn. One second sub-bank 42_5 may be arranged between the first sub-banks 41_5.

[0248] The second sub-bank 42_5 may extend in the second direction DR2 at the central portion of the emission area EMA of the sub-pixel PXn. The second sub-bank 42_5 may have a width smaller than that of the first sub-bank 41_5 and may be disposed between the first sub-banks 41_5 to be spaced apart therefrom.

[0249] The extension RE-E of the first electrode 21_5 and the second bank 45_5 may be disposed on the first sub-bank 41_5. The extension RE-E of the first electrode 21_5 of the sub-pixel PXn adjacent in the first direction DR1 may be disposed on the first sub-bank 41_5. That is, the extension RE-E of the two first electrodes 21_5 are disposed on one first sub-bank 41_5. Two second electrodes 22_5 may be disposed on the second sub-bank 42_5. The second electrodes 22_5 may be disposed on both sides of the second sub-bank 42_5 extending in the second direction DR2, and may be spaced apart from each other on the second sub-bank 42_5.

[0250] One of the first electrodes 21_5 may include a contact portion RE-P such that a first electrode contact hole CTD is formed in the contact portion RE-P, and the contact portion RE-P may not be formed in the other first electrode 21_5. Similarly, the contact portion RE-P may be formed in one of the second electrodes 22_5 such that a second electrode contact hole CTS is formed in the contact portion RE-P, and the contact portion RE-P may not be formed in the other second electrode 22_5. An electrical signal may be transmitted to the first transistor T1 (or the first electrode 21_5) and the second electrode 22_5 connected to the second voltage wiring VSL through the first electrode contact hole CTD and the second electrode contact hole CTS, respectively, and the electrical signal may be transmitted to the other electrodes 21_5 and 22_5 through the contact electrodes 26_5, 27_5, and 28_5.

[0251] Both ends of each of the light emitting elements 30 are disposed on the extension portion RE-E of the first electrode 21_5 and the second electrode 22_5 on the first insulating layer 51. One end in which the second semiconductor layer 32 is disposed, of both ends of each of the light emitting elements 30, may be disposed on the first electrode 21_5. Therefore, one end of each of the first light emitting elements 30A disposed between the electrodes 21_5 and 22_5 on the left side with respect to the center of each sub-pixel PXn and one end of each of the second light emitting elements 30B disposed between the electrodes 21_5 and 22_5 on the right side with respect to the center of each sub-pixel PXn may face opposite directions.

[0252] Since the display device 10 includes a larger number of electrodes 21_5 and 22_5 , the display device 10 may include a larger number of contact electrodes 26_5 , 27_5 , and 28_5 .

[0253] In an embodiment, the contact electrodes 26_5, 27_5 and 28_5 may include a first contact electrode 26_5 disposed on one first electrode 21_5, a second contact electrode 27_5 disposed on one second electrode 22_5, and a third contact electrode 28_5 disposed on another first electrode 21_5 and another second electrode 22_5 and surrounding the second contact electrode 27_5.

[0254] The first contact electrode 26_5 is disposed on one first electrode 21_5. For example, the first contact electrode 26_5 is disposed on an extension portion RE-E of the first electrode 21_5 on which one end portion of the first light emitting element 30A is disposed. The first contact electrode 26_5 may be in contact with each of the extension portion RE-E of the first electrode 21_5 and one end portion of the first light emitting element 30A. The second contact electrode 27_5 is disposed on the second electrode 22_5. For example, the second contact electrode 27_5 is disposed on the second electrode 22_5 on which the other end portion of the second light emitting element 30b is disposed. The second contact electrode 27_5 may be in contact with each of the other end portions of the second electrode 22_5 and the second light emitting element 30b. The first contact electrode 26_5 and the second contact electrode 27_5 may be in contact with the first electrode 21_5 in which the first electrode contact hole CTD is formed and the second electrode 22_5 in which the second electrode contact hole CTS is formed, respectively. The first contact electrode 26_5 may contact the first electrode 21_5 electrically connected to the first transistor T1 through the first electrode contact hole CTD, and the second contact electrode 27_5 may contact the second electrode 22_5 electrically connected to the second voltage wiring VSL through the second electrode contact hole CTS. The first contact electrode 26_5 and the second contact electrode 27_5 may transmit an electrical signal applied from the first transistor T1 or the second voltage wiring VSL to the light emitting element 30. The first contact electrode 26_5 and the second contact electrode 27_5 are substantially the same as the above-mentioned contact electrodes.

[0255] The electrodes 21_5 and 22_5 in which the electrode contact holes CTD and CTS are not formed are also provided in each sub-pixel PXn. The electrodes 21_5 and 22_5 may be substantially in a floating state in which an electrical signal is not directly applied from the first transistor T1 or the second voltage wiring VSL. However, the third contact electrode 28_5 may be provided on the electrodes 21_5 and 22_5 in which the electrode contact holes CTD and CTS are not formed, and the electrical signal transmitted to the light emitting element 30 may flow through the third contact electrode 28_5.

[0256] The third contact electrode 28_5 may be disposed on the first electrode 21_5 and the second electrode 22_5 in which the electrode contact holes CTD and CTS are not formed, and may be disposed to surround the second contact electrode 27_5. The third contact electrode 28_5 may surround the second contact electrode 27_5 by including a portion extending in the second direction DR2 and a portion extending in the first direction DR1 and connecting the portion extending in the second direction DR2. The portions of the third contact electrode 28_5 extending in the second direction DR2 may be disposed on the first electrode 21_5 and the second electrode 22_5 in which the electrode contact holes CTD and CTS are not formed, respectively, and may contact the light emitting element 30. For example, the portion of the third contact electrode 28_5 disposed on the second electrode 22_5 may contact the other end of the first light emitting element 30A, and the portion of the third contact electrode 28_5 disposed on the first electrode 21_5 may contact one end of the second light emitting element 30B. The portion of the third contact electrode 28_5 extending in the first direction DR1 and the second electrode 22_5 in which the second electrode contact hole CTS is formed may overlap each other, but may not directly contact each other because another insulating layer (not shown) may be disposed therebetween. Fig.16 In the embodiment of FIG. 5 , the first light emitting element 30A and the second light emitting element 30B may be connected in series via the third contact electrode 28_5 .

[0257] In the case of this embodiment, the second transistor T2 may be connected to each of the first electrode 21_5 and the second electrode 22_5 in which the first electrode contact hole CTD and the second electrode contact hole CTS are not formed. During the manufacturing process of the display device 10, the same type of alignment signal may be applied to the first electrode 21_5 connected to the fourth transistor T4 through the first electrode contact hole CTD and the second electrode 22_5 connected to the second voltage wiring VSL through the second electrode contact hole CTS, and different alignment signals may be applied to the electrodes connected to the second transistor T2 as the other electrodes 21_5 and 22_5. Therefore, between these electrodes, an electric field is generated by the voltage difference between the alignment signals, and the light emitting element 30 can be aligned. The detailed description thereof is the same as the above description.

[0258] At the end of the detailed description, it will be appreciated by those skilled in the art that many changes and modifications may be made to the preferred embodiment without departing substantially from the principles of the invention. Therefore, the preferred embodiments of the disclosed invention are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: first base; A semiconductor layer, disposed on the first substrate and comprising a plurality of active layers; a first gate conductive layer disposed on the semiconductor layer and comprising a scan line and a sensing line and a plurality of gate electrodes, the scan line and the sensing line extending in a first direction, the plurality of gate electrodes being disposed to partially overlap the semiconductor layer; a first data conductive layer disposed on the first gate conductive layer and including first and second data lines and one electrode and another electrode of each of a plurality of transistors, the first and second data lines extending in a second direction crossing the first direction and spaced apart from each other in the first direction; a second data conductive layer disposed on the first data conductive layer and comprising a first voltage wiring and a second voltage wiring, the first voltage wiring and the second voltage wiring extending between the first data line and the second data line in the second direction; a first electrode and a second electrode, the first electrode being disposed on the second data conductive layer and extending in the second direction, the second electrode being spaced apart from the first electrode and extending in the second direction; as well as A plurality of light emitting elements each having two ends disposed on the first electrode and the second electrode, The multiple transistors include a first transistor and a second transistor, the first transistor having an electrode electrically connected to the first electrode and another electrode electrically connected to the first voltage wiring, and the second transistor having an electrode electrically connected to the second electrode and another electrode electrically connected to the first data line.

2. The display device according to claim 1, wherein: The plurality of transistors further include a third transistor having one electrode electrically connected to the gate electrode of the first transistor, another electrode electrically connected to the second data line, and a gate electrode electrically connected to the scan line.

3. The display device according to claim 2, wherein: The first data conductive layer further includes an initialization voltage wiring disposed at one side of the first data line and extending in the second direction, and The plurality of transistors further include a fourth transistor having one electrode electrically connected to the first electrode and another electrode electrically connected to the initialization voltage wiring.

4. The display device according to claim 3, wherein: The first gate conductive layer further includes an alignment signal line, which is disposed at one side of the sensing line and extends in the first direction, and The second transistor has a gate electrode electrically connected to the alignment signal line.

5. The display device according to claim 3, wherein: Each of the second transistor and the fourth transistor has a gate electrode electrically connected to the sensing line.

6. The display device according to claim 3, wherein: The first gate conductive layer further includes a conductive pattern disposed to overlap the first data conductive layer and the initialization voltage wiring and electrically connected to the first data line and a drain electrode of the second transistor.

7. The display device according to claim 1, wherein: The second electrode is electrically connected to the second voltage wiring.

8. The display device according to claim 7, wherein: The second data conductive layer further includes a first electrode conductive pattern contacting the one electrode of the first transistor and the first electrode, and a second electrode conductive pattern contacting the one electrode of the second transistor and the second electrode.

9. The display device according to claim 1, further comprising a third electrode disposed between the first electrode and the second electrode, in, The third electrode is electrically connected to the second voltage wiring, and The plurality of light emitting elements include a first light emitting element and a second light emitting element, the first light emitting element being disposed on the first electrode and the third electrode, and the second light emitting element being disposed on the third electrode and the second electrode.

10. The display device according to claim 1, further comprising: A first gate insulating layer, disposed between the semiconductor layer and the first gate conductive layer; A first protection layer, disposed between the first gate conductive layer and the first data conductive layer; A first interlayer insulating layer, disposed between the first data conductive layer and the second data conductive layer; A first planarization layer is disposed between the second data conductive layer and the first electrode and the second electrode; as well as a first insulating layer partially covering the first electrode and the second electrode, Wherein, the plurality of light emitting elements are arranged on the first insulating layer.

11. The display device according to claim 10, further comprising: a first contact electrode disposed on the first electrode and in contact with one end portion of each of the plurality of light emitting elements; as well as A second contact electrode is provided on the second electrode and is in contact with the other end portion of each of the plurality of light emitting elements.

12. The display device according to claim 1, wherein: The first electrode includes a bent portion extending in a direction different from the first direction and the second direction, an extending portion extending in the second direction and having a width greater than that of the bent portion, and a connecting portion configured to connect the bent portion and the extending portion and extending in the second direction, and One end portion of each of the plurality of light emitting elements is disposed on the extending portion of the first electrode.

13. The display device according to claim 12, wherein: The second electrode has a symmetrical structure with the first electrode, and The other end portion of each of the plurality of light emitting elements is disposed on the extending portion of the second electrode.

14. The display device according to claim 13, wherein: The interval between the extending portion of the first electrode and the extending portion of the second electrode is smaller than the interval between the connecting portion of the first electrode and the connecting portion of the second electrode, and The shortest interval between the bent portion of the first electrode and the bent portion of the second electrode is larger than the interval between the extending portions and smaller than the interval between the connecting portions.

15. A display device, comprising: a first voltage wiring to which a first power supply voltage is applied and a second voltage wiring to which a second power supply voltage is applied; a first data line and a second data line, through which different data signals are applied; a light emitting diode having one end electrically connected to the first voltage wiring and the other end connected to the second voltage wiring; a first transistor having one electrode electrically connected to the one end of the light emitting diode and another electrode electrically connected to the first voltage wiring; a second transistor having one electrode electrically connected to the other end of the light emitting diode and another electrode electrically connected to the second data line; a third transistor having one electrode connected to the gate electrode of the first transistor and another electrode electrically connected to the first data line; as well as A storage capacitor is electrically connected to the gate electrode of the first transistor and the one electrode of the first transistor.

16. The display device according to claim 15, further comprising: a scan line to which a scan signal is applied and which is electrically connected to a gate electrode of the third transistor; an alignment signal line to which an alignment signal is applied and which is electrically connected to a gate electrode of the second transistor; as well as a sensing line to which a sensing signal is applied, The display device further includes a fourth transistor having a gate electrode electrically connected to the sensing line, an electrode electrically connected to the one end of the light-emitting diode, and another electrode connected to an initialization voltage wiring to which an initialization voltage is applied.

17. The display device according to claim 16, wherein: In the manufacturing mode of the display device, The second transistor and the fourth transistor are turned on in response to signals applied through the alignment signal line and the sensing line, respectively, and The first transistor and the third transistor are turned off.

18. The display device according to claim 17, wherein: In the manufacturing mode, The first alignment voltage applied to the initialization voltage wiring is transmitted to the one end of the light emitting diode through the fourth transistor, and A second alignment voltage applied to the second data line is transmitted to the other end of the light emitting diode through the second transistor.

19. The display device according to claim 18, wherein: In the driving mode of the display device, The first power supply voltage is transmitted to the one end of the light emitting diode through the first transistor, and The second power supply voltage is transmitted to the other end of the light emitting diode through the second voltage wiring.

20. The display device according to claim 17, wherein: The light emitting diode includes a first light emitting diode and a second light emitting diode connected in series with each other, and In the manufacturing mode, a first alignment voltage applied to the initialization voltage wiring is transmitted to one end of the first light emitting diode through the fourth transistor, A third alignment voltage applied to the second data line is transmitted to one end of the second light emitting diode through the second transistor, and A second alignment voltage is transmitted to the other end of the first light emitting diode and the other end of the second light emitting diode through the second voltage wiring.

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