Electronic paper and manufacturing method thereof, and display device

Abstract

Electronic paper and its manufacturing method and display device relate to the field of display technology. The present application sets a first switch unit, a second switch unit, a pixel electrode and an auxiliary electrode in each sub-pixel area of ​​an array substrate; the control end and the input end of the first switch unit are connected to the gate line, and the output end of the first switch unit is connected to the auxiliary electrode; the positive projection of the auxiliary electrode on the first substrate at least covers the positive projection of the channel area of ​​the second switch unit on the first substrate. Therefore, when the electronic paper displays a picture, the gate line inputs a gate scanning signal, turns on the first switch unit and charges a positive voltage to the auxiliary electrode, and the auxiliary electrode attracts negatively charged white particles and repels positively charged black particles, so that black charged particles are accumulated above the channel area of ​​the second switch unit to block external light.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an electronic paper and a manufacturing method thereof, and a display device. Background Art

[0002] Electronic paper (E-Paper) has been widely used in the display field due to its advantages such as lightness, flexibility and energy saving. For example, electronic paper can be used in billboards, labels, watches, electronic paper readers, etc. Summary of the invention

[0003] Some embodiments of the present disclosure provide the following technical solutions:

[0004] In a first aspect, an electronic paper is provided, comprising: an array substrate, a cell substrate, and an electrophoretic liquid disposed between the array substrate and the cell substrate, wherein the electrophoretic liquid contains black charged particles and white charged particles;

[0005] The array substrate has a plurality of sub-pixel regions defined by the intersection of a plurality of gate lines and a plurality of data lines, each of the sub-pixel regions comprising: an auxiliary electrode disposed on one side of the first substrate, a first switch unit connected to the auxiliary electrode, a pixel electrode, and a second switch unit connected to the pixel electrode;

[0006] The cell substrate is provided with a first common electrode, and an electric field is formed between the first common electrode and the pixel electrode to control the movement of the black charged particles and the white charged particles in the electrophoretic liquid to realize different images;

[0007] Wherein, the control end and the input end of the first switch unit are respectively connected to the gate line, and the output end of the first switch unit is connected to the auxiliary electrode;

[0008] The auxiliary electrode is located on a side of the first switch unit away from the first substrate, and an orthographic projection of the auxiliary electrode on the first substrate at least covers an orthographic projection of a channel region of the second switch unit on the first substrate.

[0009] In a second aspect, a method for manufacturing an electronic paper is provided, comprising:

[0010] An array substrate is formed; the array substrate has a plurality of sub-pixel regions defined by the intersection of a plurality of gate lines and a plurality of data lines, each of the sub-pixel regions includes an auxiliary electrode disposed on one side of a first substrate, a first switch unit connected to the auxiliary electrode, a pixel electrode, and a second switch unit connected to the pixel electrode;

[0011] forming a cell substrate; the cell substrate is provided with a first common electrode;

[0012] Injecting electrophoretic liquid between the array substrate and the cell substrate; the electrophoretic liquid contains black charged particles and white charged particles;

[0013] Among them, an electric field is formed between the first common electrode and the pixel electrode to control the movement of the black charged particles and the white charged particles in the electrophoretic liquid to achieve different pictures; the control end and the input end of the first switch unit are respectively connected to the gate line, and the output end of the first switch unit is connected to the auxiliary electrode; the auxiliary electrode is located on a side of the first switch unit away from the first substrate, and the orthographic projection of the auxiliary electrode on the first substrate at least covers the orthographic projection of the channel region of the second switch unit on the first substrate.

[0014] In a third aspect, a display device is provided, comprising the above-mentioned electronic paper.

[0015] In the embodiment of the present application, by adding a first switch unit to each sub-pixel region of the array substrate, the control end and the input end of the first switch unit are connected to the gate line, the output end of the first switch unit is connected to the auxiliary electrode, and the positive projection of the auxiliary electrode on the first substrate at least covers the positive projection of the channel region of the second switch unit on the first substrate. When the electronic paper displays each frame of the picture, the gate line will input a gate scanning signal, thereby turning on the first switch unit and charging a positive voltage to the auxiliary electrode. Therefore, the auxiliary electrode will attract the negatively charged white charged particles between the array substrate and the box substrate, and repel the positively charged black charged particles, so that black charged particles are accumulated above the channel region of the second switch unit. When external light irradiates the electronic paper, the black charged particles accumulated above the channel region of the second switch unit will block the external light to reduce the external light irradiating the channel region of the second switch unit, thereby improving the leakage current of the second switch unit and reducing the phenomenon of poor white spots.

[0016] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, a brief introduction will be given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1The structure diagram of an electronic paper according to an embodiment of the present application is schematically shown;

[0019] Figure 2 A schematic diagram of the structure of an array substrate according to an embodiment of the present application is schematically shown;

[0020] Figure 3 Schematically shows Figure 2 A cross-sectional view of the array substrate along section AA' is shown;

[0021] Figure 4 A schematic diagram of the structure of another array substrate according to an embodiment of the present application is shown;

[0022] Figure 5 Schematically shows Figure 4 A cross-sectional view of the array substrate along section BB' is shown;

[0023] Figure 6 Schematically shows Figure 2 and Figure 4 A cross-sectional view of the array substrate along section CC' is shown;

[0024] Figure 7 A flowchart schematically shows a method for manufacturing electronic paper according to an embodiment of the present application;

[0025] Figure 8 The schematic diagram of the structure after the first gate layer and the second gate layer are formed on the first substrate is shown;

[0026] Fig. 9 Schematically shows the Figure 8 A schematic diagram of a structure after a first active layer and a second active layer are formed on the basis of;

[0027] Fig.10 Schematically shows the Fig. 9 A schematic diagram of a structure after a data line, a first source-drain electrode layer and a second source-drain electrode layer are formed on the basis of the substrate;

[0028] Fig.11 Schematically shows the Fig.10 A schematic diagram of a structure after a via hole penetrating the passivation layer is formed on the basis of the above;

[0029] Fig.12 Schematically shows the Figure 8 Another structural schematic diagram after the first active layer and the second active layer are formed on the basis of;

[0030] Fig.13 Schematically shows the Fig.12 Another structural schematic diagram after forming a data line, a first source-drain electrode layer and a second source-drain electrode layer on the basis of;

[0031] Fig.14 Schematically shows the Fig.13 Another structural schematic diagram after a via hole penetrating the passivation layer is formed on the basis of. Specific embodiments

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0033] In the related art, electronic paper includes an array substrate having a plurality of sub-pixel areas defined by the intersection of a plurality of gate lines and a plurality of data lines. A switching unit and a pixel electrode connected to the switching unit are provided in each sub-pixel area. The pixel electrode is charged through the switching unit to control the movement of charged particles between the array substrate and the counter substrate for display.

[0034] When the electronic paper in the related art is displayed, external light will directly irradiate the channel region of the switch unit to generate electron-hole pairs, thereby causing leakage current in the switch unit and causing white point defects.

[0035] Therefore, the present application adds a first switch unit to each sub-pixel region of the array substrate, the control end and the input end of the first switch unit are connected to the gate line, the output end of the first switch unit is connected to the auxiliary electrode, and the positive projection of the auxiliary electrode on the first substrate at least covers the positive projection of the channel region of the second switch unit on the first substrate. When the electronic paper displays each frame, the gate line will input a gate scanning signal, thereby turning on the first switch unit and charging a positive voltage to the auxiliary electrode. Therefore, the auxiliary electrode will attract the negatively charged white charged particles between the array substrate and the box substrate, and repel the positively charged black charged particles, so that black charged particles are accumulated above the channel region of the second switch unit. When external light irradiates the electronic paper, the black charged particles accumulated above the channel region of the second switch unit will block the external light to reduce the external light irradiating the channel region of the second switch unit, thereby improving the leakage current of the second switch unit and reducing the phenomenon of poor white spots.

[0036] Reference Figure 1 , schematically shows a structural diagram of an electronic paper according to an embodiment of the present application, Figure 2 A schematic structural diagram of an array substrate according to an embodiment of the present application is shown. Figure 3 Shows Figure 2The cross-sectional view of the array substrate along the section AA' is shown. Figure 4 A schematic diagram showing the structure of another array substrate according to an embodiment of the present application is shown. Figure 5 Shows Figure 4 The cross-sectional view of the array substrate along the cross section BB' is shown. Figure 6 Shows Figure 2 and Figure 4 The array substrate is shown in a cross-sectional view along the cross section CC'.

[0037] The embodiment of the present application provides an electronic paper, including an array substrate 100 , a counter substrate 200 , and an electrophoretic liquid disposed between the array substrate 100 and the counter substrate 200 , wherein the electrophoretic liquid contains black charged particles 301 and white charged particles 302 .

[0038] The array substrate 100 has a plurality of sub-pixel areas 13 defined by the intersection of a plurality of gate lines 11 and a plurality of data lines 12, each sub-pixel area 13 includes: an auxiliary electrode 42 arranged on one side of the first substrate 10, a first switch unit 20 connected to the auxiliary electrode 42, a pixel electrode 41, and a second switch unit 30 connected to the pixel electrode 41; a first common electrode 201 is arranged on the box substrate 200, an electric field is formed between the first common electrode 201 and the pixel electrode 41, and the movement of black charged particles 301 and white charged particles 302 in the electrophoretic liquid is controlled to achieve different pictures.

[0039] Among them, the control end and the input end of the first switch unit 20 are respectively connected to the gate line 11, and the output end of the first switch unit 20 is connected to the auxiliary electrode 42; the auxiliary electrode 42 is located on the side of the first switch unit 20 away from the first substrate 10, and the orthographic projection of the auxiliary electrode 42 on the first substrate 10 at least covers the orthographic projection of the channel region of the second switch unit 30 on the first substrate 10.

[0040] In actual products, the first substrate 10 in the array substrate 100 can be a glass substrate or a PI (Polyimide) substrate, etc., and a plurality of gate lines 11 and a plurality of data lines 12 are arranged on the first substrate 10, each gate line 11 is distributed along a first direction of the array substrate 100, and each data line 12 is distributed along a second direction of the array substrate 100. The angle between the first direction and the second direction is not 0, for example, the first direction is the row direction, and the second direction is the column direction. At this time, the first direction and the second direction are perpendicular.

[0041] Based on a plurality of gate lines 11 and a plurality of data lines 12 arranged in an intersecting manner, the array substrate 100 is divided into a plurality of sub-pixel areas 13 distributed in an array, each sub-pixel area 13 is provided with a first switch unit 20, a second switch unit 30, a pixel electrode 41 and an auxiliary electrode 42, the first switch unit 20 is connected to the auxiliary electrode 42, and the second switch unit 30 is connected to the pixel electrode 41.

[0042] The second switch unit 30 includes a control end, an input end and an output end. The control end of the second switch unit 30 is connected to the gate line 11 , the input end of the second switch unit 30 is connected to the data line 12 , and the output end of the second switch unit 30 is connected to the pixel electrode 41 .

[0043] The counter-box substrate 200 has a first common electrode 201, and an electrophoretic liquid is arranged between the array substrate 100 and the counter-box substrate 200, specifically, an electrophoretic liquid is arranged between the pixel electrode 41 in the array substrate 100 and the first common electrode 201 in the counter-box substrate 200, and black charged particles 301 and white charged particles 302 are arranged in the electrophoretic liquid.

[0044] Therefore, when the electronic paper is displayed, the gate scanning signal transmitted on the gate line 11 controls the second switch unit 30 to be turned on, so as to provide the data signal transmitted on the data line 12 to the pixel electrode 41, charge the pixel electrode 41, and generate an electric field between the pixel electrode 41 and the first common electrode 201 set on the box substrate 200. Under the action of the electric field, the white charged particles 302 and the black charged particles 301 between the array substrate 100 and the box substrate 200 move. When the white charged particles 302 rise to the surface of the box substrate 200 facing the array substrate 100, the external light irradiated on the surface of the box substrate 200 facing the array substrate 100 is reflected by the white charged particles 302 and displayed in white. When the black charged particles 301 rise to the surface of the box substrate 200 facing the array substrate 100, the external light irradiated on the surface of the box substrate 200 facing the array substrate 100 is absorbed and displayed in black, thereby realizing the display function. In other words, the second switch unit 30 is a driving element for driving the electronic paper display.

[0045] The first switch unit 20 includes a control end, an input end and an output end. The control end of the first switch unit 20 is connected to the gate line 11 , the input end of the first switch unit 20 is connected to the gate line 11 , and the output end of the first switch unit 20 is connected to the auxiliary electrode 42 .

[0046] When the electronic paper displays each frame, the gate line 11 inputs a gate scanning signal, thereby turning on the first switch unit 20 and charging a positive voltage to the auxiliary electrode 42. Under the action of the gate scanning signal repeatedly input by the gate line 11, the auxiliary electrode 42 always maintains a positive voltage, so the auxiliary electrode 42 attracts the negatively charged white charged particles 302 between the array substrate 100 and the counter substrate 200, and repels the positively charged black charged particles 301. In addition, since the positive projection of the auxiliary electrode 42 on the first substrate 10 at least covers the positive projection of the channel region of the second switch unit 30 on the first substrate 10, the black charged particles can be accumulated above the channel region of the second switch unit 30 through the auxiliary electrode 42. When external light irradiates the electronic paper, the black charged particles accumulated above the channel region of the second switch unit 30 will block the external light to reduce the external light irradiating the channel region of the second switch unit 30, thereby improving the leakage current of the second switch unit 30 and reducing the phenomenon of poor white spots.

[0047] It should be noted that the voltage of the gate scanning signal can be a positive voltage, in which case the black charged particles 301 are positively charged and the white charged particles 302 are negatively charged; of course, the voltage of the gate scanning signal can also be a negative voltage, in which case the black charged particles 301 are negatively charged and the white charged particles 302 are positively charged.

[0048] In an optional embodiment of the present application, as Figure 2 and Figure 3 As shown, the first switch unit 20 includes a first transistor 21; the gate of the first transistor 21 is the control end of the first switch unit 20, the first pole 212 of the first transistor 21 is the input end of the first switch unit 20, and the second pole 213 of the first transistor 21 is the output end of the first switch unit 20; one of the first pole 212 and the second pole 213 is the source, and the other is the drain.

[0049] The first switch unit 20 is actually a transistor, which may include only one first transistor 21. The first transistor 21 is an N-type transistor. In this case, it is necessary to ensure that the voltage of the gate scan signal is a positive voltage, the black charged particles 301 are positively charged, and the white charged particles 302 are negatively charged. Of course, it is understandable that the first transistor 21 may also be a P-type transistor. In this case, it is necessary to ensure that the voltage of the gate scan signal is a negative voltage, the black charged particles 301 are negatively charged, and the white charged particles 302 are positively charged.

[0050] When the first switch unit 20 includes only one first transistor 21 , the gate of the first transistor 21 is connected to the gate line 11 , the first electrode 212 of the first transistor 21 is connected to the gate line 11 , and the second electrode 213 of the first transistor 21 is connected to the auxiliary electrode 42 .

[0051] In another optional embodiment of the present application, Figure 4 and Figure 5 As shown, the first switch unit 20 includes a second transistor 22 and a third transistor 23, the second transistor 22 and the third transistor 23 are connected in series; the gate of the second transistor 22 is connected to the gate of the third transistor 23, and the gate of the second transistor 22 and the gate of the third transistor 23 are both control terminals of the first switch unit 20; the first electrode 222 of the second transistor 22 is the input terminal of the first switch unit 20, the second electrode 223 of the second transistor 22 is connected to the first electrode 232 of the third transistor 23, and the second electrode 233 of the third transistor 23 is the output terminal of the first switch unit 20; one of the first electrode 222 of the second transistor 22 and the second electrode 223 of the second transistor 22 is a source, and the other is a drain, and one of the first electrode 232 of the third transistor 23 and the second electrode 233 of the third transistor 23 is a source, and the other is a drain.

[0052] The first switch unit 20 is actually a transistor, which may include two transistors, namely, a second transistor 22 and a third transistor 23. The second transistor 22 and the third transistor 23 are both N-type transistors. At this time, it is necessary to ensure that the voltage of the gate scan signal is a positive voltage, the black charged particles 301 are positively charged, and the white charged particles 302 are negatively charged. Of course, it is understandable that the second transistor 22 and the third transistor 23 may also be P-type transistors. At this time, it is necessary to ensure that the voltage of the gate scan signal is a negative voltage, the black charged particles 301 are negatively charged, and the white charged particles 302 are positively charged.

[0053] When the first switching unit 20 includes a second transistor 22 and a third transistor 23 connected in series, the gate of the second transistor 22 is connected to the gate of the third transistor 23, and both are connected to the gate line 11, the first electrode 222 of the second transistor 22 is connected to the gate line 11, the second electrode 223 of the second transistor 22 is connected to the first electrode 232 of the third transistor 23, and the second electrode 233 of the third transistor 23 is connected to the auxiliary electrode 42.

[0054] Since the refresh frequency of the electronic paper is low and a frame of the picture is maintained for a long time, in order to ensure that the voltage on the auxiliary electrode 42 can be maintained during the display time of each frame of the picture, the second transistor 22 and the third transistor 23 connected in series are required to be used as the first switching unit 20, and the voltage holding ability of the auxiliary electrode 42 is improved by turning on the two transistors.

[0055] It should be noted that, when the number of transistors connected in series in the first switch unit 20 is greater, the effect of improving the leakage current of the second switch unit 30 is better, but when the number of transistors connected in series in the first switch unit 20 is greater, the on-state current is correspondingly smaller and the area occupied by the array substrate 100 is increased. Therefore, in the embodiment of the present application, the first switch unit 20 is preferably a first transistor 21, or a second transistor 22 and a third transistor 23 connected in series.

[0056] In some embodiments, the first switching unit 20 includes a first transistor 21, the gate of the first transistor 21 is the gate line 11, and the first electrode 212 of the first transistor 21 and the second electrode 213 of the first transistor 21 on the first substrate 10 are at least partially located within the positive projection of the gate line 11 on the first substrate 10.

[0057] In other embodiments, the first switching unit 20 includes a second transistor 22 and a third transistor 23 connected in series, the gate of the second transistor 22 and the gate of the third transistor 23 are both the gate line 11, and the first electrode 222 of the second transistor 22, the second electrode 223 of the second transistor 22, the first electrode 232 of the third transistor 23, and the second electrode 233 of the third transistor 23 are all at least partially located within the orthographic projection of the gate line 11 on the first substrate 10.

[0058] By using the gate line 11 as the control end of the first switch unit 20, that is, using the gate line 11 as the gate of the first transistor 21, or the gate of the second transistor 22 and the gate of the third transistor 23, the structural design of the first switch unit 20 can be simplified; and the orthographic projections of the source and drain of the transistor included in the first switch unit 20 on the first substrate 10 are arranged to be at least partially located within the orthographic projection of the gate line 11 on the first substrate 10, which can ensure that the area occupied by the newly added first switch unit 20 is small.

[0059] In an actual product, the first switch unit 20 includes a first gate layer, a gate insulating layer 51, a first active layer, and a first source-drain electrode layer, which are sequentially stacked on the first substrate 10. That is, the first gate layer is disposed on the first substrate 10, the gate insulating layer 51 covers the first gate layer and the first substrate 10, the first active layer is disposed on a side of the gate insulating layer 51 away from the first substrate 10, and the first source-drain electrode layer is also disposed on a side of the gate insulating layer 51 away from the first substrate 10.

[0060] like Figure 3As shown, the first switching unit 20 includes a first transistor 21, the gate of the first transistor 21 is located in the first gate layer, the first electrode 212 of the first transistor 21 and the second electrode 213 of the first transistor 21 are both located in the first source-drain electrode layer; and the first active layer includes a first active sublayer 211, the first electrode 212 of the first transistor 21 and the second electrode 213 of the first transistor 21 both partially cover the first active sublayer 211.

[0061] like Figure 5 As shown, the first switch unit 20 includes a second transistor 22 and a third transistor 23, and the second transistor 22 is connected in series with the third transistor 23, the gate of the second transistor 22 and the gate of the third transistor 23 are both located in the first gate layer, the first electrode 222 of the second transistor 22, the second electrode 223 of the second transistor 22, the first electrode 232 of the third transistor 23 and the second electrode 233 of the third transistor 23 are all located in the first source-drain electrode layer; and the first active layer includes a second active sublayer 221 and a third active sublayer 231, the first electrode 222 of the second transistor 22 and the second electrode 223 of the second transistor 22 partially cover the second active sublayer 221, and the first electrode 232 of the third transistor 23 and the second electrode 233 of the third transistor 23 partially cover the third active sublayer 231.

[0062] Among them, when the first switching unit 20 includes a first transistor 21, the orthographic projection of the first active sublayer 211 on the first substrate 10 is located within the orthographic projection of the gate line 11 on the first substrate 10; when the second switching unit 20 includes a second transistor 22 and a third transistor 23 connected in series, the orthographic projections of the second active sublayer 221 and the third active sublayer 231 on the first substrate 10 are located within the orthographic projection of the gate line 11 on the first substrate 10.

[0063] like Figure 6 As shown, the second switch unit 30 includes a fourth transistor 31 and a fifth transistor 32, and the fourth transistor 31 is connected in series with the fifth transistor 32; the gate 311 of the fourth transistor 31 is connected to the gate 321 of the fifth transistor 32, and the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32 are both control terminals of the second switch unit 30; the first electrode 313 of the fourth transistor 31 is the input terminal of the second switch unit 30, the second electrode 314 of the fourth transistor 31 is connected to the first electrode 323 of the fifth transistor 32, and the second electrode 324 of the fifth transistor 32 is the output terminal of the second switch unit 30.

[0064] That is, the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32 are connected to the gate line 11, the first electrode 313 of the fourth transistor 31 is connected to the data line 12, the second electrode 314 of the fourth transistor 31 is connected to the first electrode 323 of the fifth transistor 32, and the second electrode 324 of the fifth transistor 32 is connected to the pixel electrode 41.

[0065] Among them, one of the first electrode 313 of the fourth transistor 31 and the second electrode 314 of the fourth transistor 31 is a source, and the other is a drain; one of the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 is a source, and the other is a drain.

[0066] Furthermore, the fourth transistor 31 and the fifth transistor 32 may both be N-type transistors or P-type transistors. However, the transistor type in the first switch unit 20 needs to be the same as the transistor type in the second switch unit 30. For example, when the first transistor 21 is an N-type transistor, the fourth transistor 31 and the fifth transistor 32 are also N-type transistors, and when the first transistor 21 is a P-type transistor, the fourth transistor 31 and the fifth transistor 32 are also P-type transistors.

[0067] It should be noted that the second switch unit 30 may also include only one transistor, such as a sixth transistor, the gate of the sixth transistor is the control end of the second switch unit 30, the first pole of the sixth transistor is the input end of the second switch unit 30, and the second pole of the sixth transistor is the output end of the second switch unit 30.

[0068] In an actual product, the second switch unit 30 includes a second gate layer, a gate insulating layer 51, a second active layer, and a second source-drain electrode layer stacked in sequence on the first substrate 10. That is, the second gate layer is disposed on the first substrate 10, the gate insulating layer 51 covers the second gate layer and the first substrate 10, the second active layer is disposed on a side of the gate insulating layer 51 away from the first substrate 10, and the second source-drain electrode layer is also disposed on a side of the gate insulating layer 51 away from the first substrate 10.

[0069] like Figure 6As shown, the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32 are both located in the second gate layer, the first electrode 313 of the fourth transistor 31, the second electrode 314 of the fourth transistor 31, the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 are all located in the second source-drain electrode layer; and the second active layer includes a fourth active sublayer 312 and a fifth active sublayer 322, the first electrode 313 of the fourth transistor 31 and the second electrode 314 of the fourth transistor 31 partially cover the fourth active sublayer 312, and the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 partially cover the fifth active sublayer 322.

[0070] At this time, the channel region of the second switching unit 30 refers to: the area in the fourth active sublayer 312 that is not covered by the first pole 313 of the fourth transistor 31 and the second pole 314 of the fourth transistor 31, and the area in the fifth active sublayer 322 that is not covered by the first pole 323 of the fifth transistor 32 and the second pole 324 of the fifth transistor 32.

[0071] In some embodiments, the orthographic projection of the auxiliary electrode 42 on the first substrate 10 also covers the orthographic projections of the first electrode 313 of the fourth transistor 31 , the second electrode 314 of the fourth transistor 31 , the first electrode 323 of the fifth transistor 32 , and part of the second electrode 324 of the fifth transistor 32 on the first substrate 10 .

[0072] When the electronic paper is displayed, external light from various angles will be incident on the electronic paper. In order to prevent the light obliquely incident on the electronic paper (i.e., the light when the angle between the incident light and the normal direction of the electronic paper light emitting surface is not 0) from irradiating the channel area of ​​the second switch unit 30, it is necessary to make the orthographic projection of the auxiliary electrode 42 on the first substrate 10 also cover the orthographic projections of the first electrode 313 of the fourth transistor 31, the second electrode 314 of the fourth transistor 31, the first electrode 323 of the fifth transistor 32 and part of the second electrode 324 of the fifth transistor 32 on the first substrate 10, so as to further reduce the external light irradiating the channel area of ​​the second switch unit 30, so as to further improve the leakage current of the second switch unit 30.

[0073] It should be noted that when the second switch unit 30 includes only one sixth transistor, the orthographic projection of the auxiliary electrode 42 on the first substrate 10 also covers the orthographic projections of the first electrode of the sixth transistor and part of the second electrode of the sixth transistor on the first substrate 10 .

[0074] In some embodiments, the first gate layer and the second gate layer are disposed in the same layer; the first active layer and the second active layer are disposed in the same layer; the data line 12, the first source-drain electrode layer and the second source-drain electrode layer are disposed in the same layer.

[0075] Wherein, when the first switch unit 20 includes a first transistor 21, the first gate layer includes the gate of the first transistor 21, and the gate of the first transistor 21 is the gate line 11, therefore, the gate line 11 is also located in the first gate layer; when the first switch unit 20 is connected in series with a second transistor 22 and a third transistor 23, the first gate layer includes the gate of the second transistor 22 and the gate of the third transistor 23, and the gate of the second transistor 22 and the gate of the third transistor 23 are the gate line 11, therefore, the gate line 11 is also located in the first gate layer. The second switch unit 30 includes a fourth transistor 31 and a fifth transistor 32 connected in series, and the second gate layer includes the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32. The first gate layer and the second gate layer are arranged in the same layer, which means that the gate line 11, the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32 are arranged in the same layer.

[0076] When the first switch unit 20 includes a first transistor 21, the first active layer is the first active sublayer 211, and the second active layer includes the fourth active sublayer 312 and the fifth active sublayer 322, therefore, the first active layer and the second active layer are arranged in the same layer, which means: the first active sublayer 211, the fourth active sublayer 312 and the fifth active sublayer 322 are arranged in the same layer. When the first switch unit 20 has a second transistor 22 and a third transistor 23 connected in series, the first active layer includes the second active sublayer 221 and the third active sublayer 231, and the second active layer includes the fourth active sublayer 312 and the fifth active sublayer 322, therefore, the first active layer and the second active layer are arranged in the same layer, which means: the second active sublayer 221, the third active sublayer 231, the fourth active sublayer 312 and the fifth active sublayer 322 are arranged in the same layer.

[0077] When the first switching unit 20 includes a first transistor 21, the first source-drain electrode layer includes a first electrode 212 and a second electrode 213 of the first transistor 21, and the second source-drain electrode layer includes a first electrode 313 and a second electrode 314 of the fourth transistor 31, a first electrode 323 and a second electrode 324 of the fifth transistor 32. Therefore, the data line 12, the first source-drain electrode layer and the second source-drain electrode layer are all arranged in the same layer, which means that the data line 12, the first electrode 212 of the first transistor 21, the second electrode 213 of the first transistor 21, the first electrode 313 of the fourth transistor 31, the second electrode 314 of the fourth transistor 31, the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 are arranged in the same layer.

[0078] When the first switching unit 20 is connected in series with the second transistor 22 and the third transistor 23, the first source-drain electrode layer includes the first electrode 222 of the second transistor 22, the second electrode 223 of the second transistor 22, the first electrode 232 of the third transistor 23 and the second electrode 233 of the third transistor 23. Therefore, the data line 12, the first source-drain electrode layer and the second source-drain electrode layer are all arranged in the same layer, which means that the data line 12, the first electrode 222 of the second transistor 22, the second electrode 223 of the second transistor 22, the first electrode 232 of the third transistor 23, the second electrode 233 of the third transistor 23, the first electrode 313 of the fourth transistor 31, the second electrode 314 of the fourth transistor 31, the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 are arranged in the same layer.

[0079] In the embodiments of the present application, as 1 to Figure 6 As shown, the array substrate 100 also includes a passivation layer 52 covering the first switch unit 20 and the second switch unit 30, and a bridging electrode 43 arranged on the passivation layer 52; the pixel electrode 41 and the auxiliary electrode 42 are located on the side of the passivation layer 52 away from the first switch unit 20; the bridging electrode 43 is connected to the gate line 11 through a first via hole penetrating the passivation layer 52 and the gate insulating layer 51, and the bridging electrode 43 is also connected to the input end of the first switch unit 20 through a second via hole penetrating the passivation layer 52; the auxiliary electrode 42 is connected to the output end of the first switch unit 20 through a third via hole penetrating the passivation layer 52; the pixel electrode 41 is connected to the output end of the second switch unit 30 through a fourth via hole penetrating the passivation layer 52.

[0080] When the first switch unit 20 includes a first transistor 21, the bridge electrode 43 is connected to the first electrode 212 of the first transistor 21 through the second via hole penetrating the passivation layer 52, and the auxiliary electrode 42 is connected to the second electrode 213 of the first transistor 21 through the third via hole penetrating the passivation layer 52; when the first switch unit 20 includes a second transistor 22 and a third transistor 23 connected in series, the bridge electrode 43 is connected to the first electrode 222 of the second transistor 22 through the second via hole penetrating the passivation layer 52, and the auxiliary electrode 42 is connected to the second electrode 233 of the third transistor 23 through the third via hole penetrating the passivation layer 52; and the pixel electrode 41 is connected to the second electrode 324 of the fifth transistor 32 through the fourth via hole penetrating the passivation layer 52. The function of the bridge electrode 43 is to realize the connection between the input end of the first switch unit 20 and the gate line 11.

[0081] In some embodiments, the bridging electrode 43 , the pixel electrode 41 and the auxiliary electrode 42 are arranged in the same layer, and their orthographic projections on the first substrate 10 do not overlap, and there is a gap between any two of them.

[0082] That is, any two of the bridge electrode 43 , the pixel electrode 41 and the auxiliary electrode 42 will not contact each other, thereby avoiding mutual influence between the electrodes to cause the first switch unit 20 and the second switch unit 30 to fail to work normally.

[0083] The bridge electrode 43 , the pixel electrode 41 and the auxiliary electrode 42 are made of the same material, which is ITO (Indium Tin Oxides). Of course, the bridge electrode 43 , the pixel electrode 41 and the auxiliary electrode 42 may also be made of other metal or oxide conductor materials.

[0084] In some embodiments, the array substrate 100 further includes a second common electrode disposed on one side of the first substrate 10 and located in each sub-pixel region 13; the second common electrodes in any two adjacent sub-pixel regions 13 are connected to each other, and the second common electrodes are also connected to the ground terminal.

[0085] The counter substrate 200 includes a second substrate 202 and a first common electrode 201 disposed on a side of the second substrate 202 close to the array substrate 100 , and the first common electrode 201 is connected to the second common electrode.

[0086] The second common electrode is used to connect to the first common electrode 201 set on the box substrate 200, so that the first common electrode 201 is connected to the ground end. When the pixel electrode 41 on the array substrate 100 is charged with voltage, an electric field is formed between the pixel electrode 41 and the first common electrode 201, thereby controlling the movement of white charged particles 302 and black charged particles 301 between the pixel electrode 41 and the first common electrode 201 to achieve a display function.

[0087] The second common electrode is disposed in the same layer as the gate line 11 , the gate electrode 311 of the fourth transistor 31 , and the gate electrode 321 of the fifth transistor 32 .

[0088] It should be noted that the first common electrode 201 is a planar electrode, and its orthographic projection on the array substrate 100 covers the pixel electrode 41 , the auxiliary electrode 42 and the bridge electrode 43 in each sub-pixel region 13 .

[0089] In the embodiment of the present application, by adding a first switch unit to each sub-pixel region of the array substrate, the control end and the input end of the first switch unit are connected to the gate line, the output end of the first switch unit is connected to the auxiliary electrode, and the positive projection of the auxiliary electrode on the first substrate at least covers the positive projection of the channel region of the second switch unit on the first substrate. When the electronic paper displays each frame of the picture, the gate line will input a gate scanning signal, thereby turning on the first switch unit and charging a positive voltage to the auxiliary electrode. Therefore, the auxiliary electrode will attract the negatively charged white charged particles between the array substrate and the box substrate, and repel the positively charged black charged particles, so that black charged particles are accumulated above the channel region of the second switch unit. When external light irradiates the electronic paper, the black charged particles accumulated above the channel region of the second switch unit will block the external light to reduce the external light irradiating the channel region of the second switch unit, thereby improving the leakage current of the second switch unit and reducing the phenomenon of poor white spots.

[0090] Reference Figure 7 , shows a flow chart of a method for manufacturing an electronic paper according to an embodiment of the present application, which may specifically include the following steps:

[0091] Step 701, forming an array substrate; the array substrate has a plurality of sub-pixel areas defined by the intersection of a plurality of gate lines and a plurality of data lines, each of the sub-pixel areas includes an auxiliary electrode arranged on one side of a first substrate, a first switching unit connected to the auxiliary electrode, a pixel electrode, and a second switching unit connected to the pixel electrode.

[0092] In an embodiment of the present application, first, a first substrate 10 is provided, which has a plurality of sub-pixel areas 13 defined by the intersection of a plurality of gate lines 11 and a plurality of data lines 12 formed subsequently, and then, each sub-pixel area 13 on the first substrate 10 forms a first switching unit 20, a second switching unit 30, a pixel electrode 41 and an auxiliary electrode 42, respectively.

[0093] Among them, the control end and the input end of the first switch unit 20 are respectively connected to the gate line 11, and the output end of the first switch unit 20 is connected to the auxiliary electrode 42; the auxiliary electrode 42 is located on the side of the first switch unit 20 away from the first substrate 10, and the orthographic projection of the auxiliary electrode 42 on the first substrate 10 at least covers the orthographic projection of the channel region of the second switch unit 30 on the first substrate 10.

[0094] Specifically, step 701 includes sub-steps 7011 to 7016:

[0095] Sub-step 7011, forming a first gate layer and a second gate layer on the first substrate;

[0096] Sub-step 7012, forming a gate insulating layer covering the first gate layer, the second gate layer and the first substrate;

[0097] Sub-step 7013, forming a first active layer and a second active layer on the gate insulating layer;

[0098] Sub-step 7014, forming the data line, the first source-drain electrode layer and the second source-drain electrode layer on the gate insulating layer;

[0099] Sub-step 7015, forming a passivation layer covering the data line, the first source-drain electrode layer, the second source-drain electrode layer, the first active layer, the second active layer and the gate insulating layer;

[0100] Sub-step 7016, forming a bridge electrode, the pixel electrode and the auxiliary electrode on the passivation layer.

[0101] like Figure 8 As shown, a first gate layer and a second gate layer are formed on a first substrate 10 by a patterning process. Among them, the control end of the first switch unit 20 is a gate line 11, and the gate line 11 is located in the first gate layer, that is, the first gate layer includes the gate line 11. Specifically, when the first switch unit 20 includes a first transistor 21, the first gate layer includes the gate of the first transistor 21, and the gate of the first transistor 21 is the gate line 11; when the first switch unit 20 includes a second transistor 22 and a third transistor 23 connected in series, the first gate layer includes the gate of the second transistor 22 and the gate of the third transistor 23, and the gate of the second transistor 22 and the gate of the third transistor 23 are the gate line 11.

[0102] The control end of the second switch unit 30 is located at the second gate layer. Specifically, when the second switch unit 30 includes a fourth transistor 31 and a fifth transistor 32 connected in series, the second gate layer includes a gate 311 of the fourth transistor 31 and a gate 321 of the fifth transistor 32, and the gate 311 of the fourth transistor 31 and the gate 321 of the fifth transistor 32 are both connected to the gate line 11.

[0103] In addition, when the array substrate 100 also includes a second common electrode 53 arranged on the first substrate 10 and located in each sub-pixel area 13, a composition process can also be used to form the second common electrode 53 on the first substrate 10. At this time, the second common electrode 53, the gate line 11, the gate 311 of the fourth transistor 31, and the gate 321 of the fifth transistor 32 are arranged on the same layer, and there is a gap between the orthographic projection of the second common electrode 53 on the first substrate 10 and the orthographic projection of the gate line 11, the gate 311 of the fourth transistor 31, and the gate 321 of the fifth transistor 32 on the first substrate 10.

[0104] After forming the first gate layer and the second gate layer on the first substrate 10, a gate insulating layer 51 covering the first gate layer, the second gate layer and the first substrate 10 is formed. The gate insulating layer 51 can be formed by a CVD (Chemical Vapor Deposition) process, and the material of the gate insulating layer 51 is an inorganic material, such as at least one of silicon nitride and silicon oxide.

[0105] Next, a first active layer and a second active layer are formed on the gate insulating layer 51 by a patterning process.

[0106] In some embodiments, Fig. 9 As shown, when the first switch unit 20 includes a first transistor 21, the first active layer is the first active sublayer 211, and the second active layer includes the fourth active sublayer 312 and the fifth active sublayer 322. The orthographic projection of the first active sublayer 211 on the first substrate 10 is located within the orthographic projection of the gate line 11 on the first substrate 10.

[0107] In other embodiments, Fig.12 As shown, when the first switch unit 20 is connected in series with the second transistor 22 and the third transistor 23, the first active layer includes the second active sublayer 221 and the third active sublayer 231, and the second active layer includes the fourth active sublayer 312 and the fifth active sublayer 322. The orthographic projections of the second active sublayer 221 and the third active sublayer 231 on the first substrate 10 are located within the orthographic projection of the gate line 11 on the first substrate 10.

[0108] like Fig. 9 and Fig.12 As shown, the orthographic projection of the fourth active sublayer 312 on the first substrate 10 is located within the orthographic projection of the gate 311 of the fourth transistor 31 on the first substrate 10, and the orthographic projection of the fifth active sublayer 322 on the first substrate 10 is located within the orthographic projection of the gate 321 of the fifth transistor 32 on the first substrate 10.

[0109] After forming the first active layer and the second active layer on the gate insulating layer 51, a data line 12, a first source-drain electrode layer and a second source-drain electrode layer are formed on the gate insulating layer 51 by a patterning process. The input end of the first switch unit 20 and the output end of the first switch unit 20 are both located in the first source-drain electrode layer, and the input end of the second switch unit 30 and the output end of the second switch unit 30 are both located in the second source-drain electrode layer.

[0110] In some embodiments, Fig.10As shown, when the first switch unit 20 includes a first transistor 21, the first electrode 212 of the first transistor 21 is the input terminal of the first switch unit 20, and the second electrode 213 of the first transistor 21 is the output terminal of the first switch unit 20. Therefore, the first source-drain electrode layer includes the first electrode 212 of the first transistor 21 and the second electrode 213 of the first transistor 21, and the first electrode 212 of the first transistor 21 and the second electrode 213 of the first transistor 21 both partially cover the first active sublayer 211.

[0111] In other embodiments, Fig.13 As shown, when the first switch unit 20 is connected in series with the second transistor 22 and the third transistor 23, the first electrode 222 of the second transistor 22 is the input end of the first switch unit 20, the second electrode 223 of the second transistor 22 is connected to the first electrode 232 of the third transistor 23, and the second electrode 233 of the third transistor 23 is the output end of the first switch unit 20. Therefore, the first source-drain electrode layer includes the first electrode 222 of the second transistor 22, the second electrode 223 of the second transistor 22, the first electrode 232 of the third transistor 23, and the second electrode 233 of the third transistor 23, and the first electrode 222 of the second transistor 22 and the second electrode 223 of the second transistor 22 partially cover the second active sub-layer 221, and the first electrode 232 of the third transistor 23 and the second electrode 233 of the third transistor 23 partially cover the third active sub-layer 231.

[0112] like Fig.10 and Fig.13 As shown, the second switch unit 30 includes a fourth transistor 31 and a fifth transistor 32 connected in series, the first electrode 313 of the fourth transistor 31 is the input terminal of the second switch unit 30, the second electrode 314 of the fourth transistor 31 is connected to the first electrode 323 of the fifth transistor 32, and the second electrode 324 of the fifth transistor 32 is the output terminal of the second switch unit 30. Therefore, the second source-drain electrode layer includes the first electrode 313 of the fourth transistor 31, the second electrode 314 of the fourth transistor 31, the first electrode 323 of the fifth transistor 32, and the second electrode 324 of the fifth transistor 32, and the first electrode 313 of the fourth transistor 31 and the second electrode 314 of the fourth transistor 31 partially cover the fourth active sub-layer 312, and the first electrode 323 of the fifth transistor 32 and the second electrode 324 of the fifth transistor 32 partially cover the fifth active sub-layer 322.

[0113] After forming the data line 12, the first source-drain electrode layer and the second source-drain electrode layer on the gate insulating layer 51, as shown in FIG. Fig.11 and Fig.14As shown, a passivation layer 52 covering the data line 12, the first source-drain electrode layer, the second source-drain electrode layer, the first active layer, the second active layer and the gate insulating layer 51 is formed, and a photoresist is coated on the passivation layer 52. After the photoresist is exposed and developed, the passivation layer 52 at the photoresist removal area is etched to form a transition hole penetrating the passivation layer 52, a second via hole 522, a third via hole 523 and a fourth via hole 524, and then the gate insulating layer 51 at the position of the transition hole is etched to finally form a first via hole 521 penetrating the passivation layer 52 and the gate insulating layer 51.

[0114] Finally, a bridging electrode 43, a pixel electrode 41 and an auxiliary electrode 42 are formed on the passivation layer 52 by a patterning process. The bridging electrode 43 is connected to the gate line 11 through a first via hole 521 penetrating the passivation layer 52 and the gate insulating layer 51, and the bridging electrode 43 is also connected to the input end of the first switch unit 20 through a second via hole 522 penetrating the passivation layer 52; the auxiliary electrode 42 is connected to the output end of the first switch unit 20 through a third via hole 523 penetrating the passivation layer 52; and the pixel electrode 41 is connected to the output end of the second switch unit 30 through a fourth via hole 524 penetrating the passivation layer 52.

[0115] It should be noted that when Fig.11 After forming the bridge electrode 43, the pixel electrode 41 and the auxiliary electrode 42 on the structure shown in FIG. Figure 2 The array substrate 100 shown in FIG. Fig.14 After forming the bridge electrode 43, the pixel electrode 41 and the auxiliary electrode 42 on the structure shown in FIG. Figure 4 The array substrate 100 is shown.

[0116] In the embodiment of the present application, the first gate layer and the second gate layer are formed simultaneously by the same patterning process; the first active layer and the second active layer are formed simultaneously by the same patterning process; the data line 12, the first source-drain electrode layer and the second source-drain electrode layer are formed simultaneously by the same patterning process; the bridging electrode 43, the pixel electrode 41 and the auxiliary electrode 42 are formed simultaneously by the same patterning process.

[0117] When the film structures located at the same layer are formed simultaneously by using the same patterning process, the process steps of the array substrate 100 can be simplified.

[0118] Step 702, forming a cell-matching substrate; the cell-matching substrate is provided with a first common electrode.

[0119] In the embodiment of the present application, a second substrate 202 is provided, and a first common electrode 201 is formed on the second substrate 202 by a deposition process to obtain a cell substrate 200. The material of the first common electrode 201 is a transparent conductive material, such as ITO.

[0120] Step 703 , injecting electrophoretic liquid between the array substrate and the cell substrate; the electrophoretic liquid contains black charged particles and white charged particles.

[0121] In the embodiment of the present application, after the array substrate 100 and the counter substrate 200 are formed, an electrophoretic liquid is injected between the array substrate 100 and the counter substrate 200 , and the electrophoretic liquid contains black charged particles 301 and white charged particles 302 .

[0122] An electric field is formed between the first common electrode 201 and the pixel electrode 41 to control the movement of the black charged particles 301 and the white charged particles 302 in the electrophoretic liquid to realize different images.

[0123] In the embodiment of the present application, by adding a first switch unit to each sub-pixel region of the array substrate, the control end and the input end of the first switch unit are connected to the gate line, the output end of the first switch unit is connected to the auxiliary electrode, and the positive projection of the auxiliary electrode on the first substrate at least covers the positive projection of the channel region of the second switch unit on the first substrate. When the electronic paper displays each frame of the picture, the gate line will input a gate scanning signal, thereby turning on the first switch unit and charging a positive voltage to the auxiliary electrode. Therefore, the auxiliary electrode will attract the negatively charged white charged particles between the array substrate and the box substrate, and repel the positively charged black charged particles, so that black charged particles are accumulated above the channel region of the second switch unit. When external light irradiates the electronic paper, the black charged particles accumulated above the channel region of the second switch unit will block the external light to reduce the external light irradiating the channel region of the second switch unit, thereby improving the leakage current of the second switch unit and reducing the phenomenon of poor white spots.

[0124] The embodiment of the present application also discloses a display device, including the above-mentioned electronic paper.

[0125] In addition, the display device also includes components such as a driving chip connected to the gate lines 11 and the data lines 12 in the electronic paper.

[0126] The term "one embodiment", "embodiment" or "one or more embodiments" herein means that a particular feature, structure or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present application. In addition, please note that the examples of the term "in one embodiment" here do not necessarily all refer to the same embodiment.

[0127] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present application can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0128] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present application may be implemented by means of hardware comprising several different elements and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An electronic paper, characterized in that: include: An array substrate, a cell substrate, and an electrophoretic liquid disposed between the array substrate and the cell substrate, wherein the electrophoretic liquid contains black charged particles and white charged particles; The array substrate has a plurality of sub-pixel regions defined by the intersection of a plurality of gate lines and a plurality of data lines, each of the sub-pixel regions comprising: an auxiliary electrode disposed on one side of the first substrate, a first switch unit connected to the auxiliary electrode, a pixel electrode, and a second switch unit connected to the pixel electrode; The cell substrate is provided with a first common electrode, and an electric field is formed between the first common electrode and the pixel electrode to control the movement of the black charged particles and the white charged particles in the electrophoretic liquid to realize different images; Wherein, the control end and the input end of the first switch unit are respectively connected to the gate line, and the output end of the first switch unit is connected to the auxiliary electrode; The auxiliary electrode is located at a side of the first switch unit away from the first substrate, and the orthographic projection of the auxiliary electrode on the first substrate at least covers the orthographic projection of the channel region of the second switch unit on the first substrate; The second switch unit includes a fourth transistor and a fifth transistor, and the fourth transistor is connected in series with the fifth transistor; The gate of the fourth transistor is connected to the gate of the fifth transistor, and both the gate of the fourth transistor and the gate of the fifth transistor are control terminals of the second switch unit; The first electrode of the fourth transistor is the input terminal of the second switch unit, the second electrode of the fourth transistor is connected to the first electrode of the fifth transistor, and the second electrode of the fifth transistor is the output terminal of the second switch unit; The orthographic projection of the auxiliary electrode on the first substrate also covers the orthographic projections of the first electrode of the fourth transistor, the second electrode of the fourth transistor, the first electrode of the fifth transistor and part of the second electrode of the fifth transistor on the first substrate.

2. The electronic paper according to claim 1, characterized in that: The first switch unit includes a first transistor; The gate of the first transistor is the control terminal of the first switch unit, the first pole of the first transistor is the input terminal of the first switch unit, and the second pole of the first transistor is the output terminal of the first switch unit; One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

3. The electronic paper according to claim 2, characterized in that: The gate of the first transistor is the gate line; the orthographic projections of the first electrode of the first transistor and the second electrode of the first transistor on the first substrate are both at least partially located within the orthographic projection of the gate line on the first substrate.

4. The electronic paper according to claim 1, characterized in that: The first switch unit includes a second transistor and a third transistor, and the second transistor is connected in series with the third transistor; The gate of the second transistor is connected to the gate of the third transistor, and both the gate of the second transistor and the gate of the third transistor are control terminals of the first switch unit; The first electrode of the second transistor is the input terminal of the first switch unit, the second electrode of the second transistor is connected to the first electrode of the third transistor, and the second electrode of the third transistor is the output terminal of the first switch unit; One of the first electrode and the second electrode is a source electrode, and the other is a drain electrode.

5. The electronic paper according to claim 4, characterized in that: The gate of the second transistor and the gate of the third transistor are both the gate line; the first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor and the second electrode of the third transistor are all at least partially located within the orthographic projection of the gate line on the first substrate.

6. The electronic paper according to claim 2 or 4, characterized in that: The first switch unit includes a first gate layer, a gate insulating layer, a first active layer and a first source-drain electrode layer which are sequentially stacked on the first substrate; Wherein, the first switch unit includes a first transistor, the gate of the first transistor is located in the first gate layer, the first electrode of the first transistor and the second electrode of the first transistor are both located in the first source-drain electrode layer; and the first active layer includes a first active sublayer, the first electrode of the first transistor and the second electrode of the first transistor both partially cover the first active sublayer; or, The first switching unit includes a second transistor and a third transistor, and the second transistor is connected in series with the third transistor, the gate of the second transistor and the gate of the third transistor are both located in the first gate layer, the first electrode of the second transistor, the second electrode of the second transistor, the first electrode of the third transistor and the second electrode of the third transistor are all located in the first source-drain electrode layer; and the first active layer includes a second active sublayer and a third active sublayer, the first electrode of the second transistor and the second electrode of the second transistor partially cover the second active sublayer, and the first electrode of the third transistor and the second electrode of the third transistor partially cover the third active sublayer.

7. The electronic paper according to claim 6, characterized in that: The second switch unit includes a second gate layer, the gate insulating layer, a second active layer, and a second source-drain electrode layer which are sequentially stacked on the first substrate; The gate of the fourth transistor and the gate of the fifth transistor are both located in the second gate layer, and the first electrode of the fourth transistor, the second electrode of the fourth transistor, the first electrode of the fifth transistor and the second electrode of the fifth transistor are all located in the second source-drain electrode layer; Furthermore, the second active layer includes a fourth active sublayer and a fifth active sublayer, the first electrode of the fourth transistor and the second electrode of the fourth transistor partially cover the fourth active sublayer, and the first electrode of the fifth transistor and the second electrode of the fifth transistor partially cover the fifth active sublayer.

8. The electronic paper according to claim 7, characterized in that: The first gate layer and the second gate layer are arranged in the same layer; The first active layer and the second active layer are arranged in the same layer; The data line, the first source-drain electrode layer and the second source-drain electrode layer are all arranged in the same layer.

9. The electronic paper according to claim 6, characterized in that: The array substrate further includes a passivation layer covering the first switch unit and the second switch unit, and a bridging electrode disposed on the passivation layer; the pixel electrode and the auxiliary electrode are located on a side of the passivation layer away from the first switch unit; The bridge electrode is connected to the gate line through a first via hole penetrating the passivation layer and the gate insulating layer, and the bridge electrode is also connected to the input end of the first switch unit through a second via hole penetrating the passivation layer; The auxiliary electrode is connected to the output end of the first switch unit through a third via hole penetrating the passivation layer; The pixel electrode is connected to the output end of the second switch unit through a fourth via hole penetrating the passivation layer.

10. The electronic paper according to claim 9, characterized in that: The bridging electrode, the pixel electrode and the auxiliary electrode are arranged in the same layer, and the orthographic projections of the bridging electrode, the pixel electrode and the auxiliary electrode on the first substrate do not have any overlapping areas, and there is a gap between any two of them.

11. The electronic paper according to claim 1, characterized in that: The array substrate further comprises a second common electrode disposed on one side of the first substrate and located in each sub-pixel region; The second common electrodes in any two adjacent sub-pixel regions are connected to each other, and the second common electrode is also connected to a ground terminal.

12. The electronic paper according to claim 11, characterized in that: The cell substrate includes a second substrate and the first common electrode disposed on a side of the second substrate close to the array substrate, and the first common electrode is connected to the second common electrode.

13. A method for manufacturing electronic paper, characterized in that: include: forming an array substrate; The array substrate has a plurality of sub-pixel regions defined by the intersection of a plurality of gate lines and a plurality of data lines, each of the sub-pixel regions includes an auxiliary electrode disposed on one side of the first substrate, a first switch unit connected to the auxiliary electrode, a pixel electrode, and a second switch unit connected to the pixel electrode; forming a cell substrate; the cell substrate is provided with a first common electrode; Injecting electrophoretic liquid between the array substrate and the cell substrate; the electrophoretic liquid contains black charged particles and white charged particles; Wherein, an electric field is formed between the first common electrode and the pixel electrode to control the movement of the black charged particles and the white charged particles in the electrophoretic liquid to realize different images; the control end and the input end of the first switch unit are respectively connected to the gate line, and the output end of the first switch unit is connected to the auxiliary electrode; the auxiliary electrode is located on a side of the first switch unit away from the first substrate, and the orthographic projection of the auxiliary electrode on the first substrate at least covers the orthographic projection of the channel region of the second switch unit on the first substrate; The step of forming the array substrate comprises: forming a first gate layer and a second gate layer on the first substrate; forming a gate insulating layer covering the first gate layer, the second gate layer and the first substrate; forming a first active layer and a second active layer on the gate insulating layer; forming the data line, the first source-drain electrode layer and the second source-drain electrode layer on the gate insulating layer; forming a passivation layer covering the data line, the first source-drain electrode layer, the second source-drain electrode layer, the first active layer, the second active layer and the gate insulating layer; forming a bridge electrode, the pixel electrode and the auxiliary electrode on the passivation layer; The control end of the first switch unit is the gate line, and the gate line is located in the first gate layer, and the input end of the first switch unit and the output end of the first switch unit are both located in the first source-drain electrode layer; the control end of the second switch unit is located in the second gate layer, and the input end of the second switch unit and the output end of the second switch unit are both located in the second source-drain electrode layer; The bridging electrode is connected to the gate line through a first via hole penetrating the passivation layer and the gate insulating layer, and the bridging electrode is also connected to the input end of the first switching unit through a second via hole penetrating the passivation layer; the auxiliary electrode is connected to the output end of the first switching unit through a third via hole penetrating the passivation layer; and the pixel electrode is connected to the output end of the second switching unit through a fourth via hole penetrating the passivation layer.

14. The method according to claim 13, characterized in that The first gate layer and the second gate layer are formed simultaneously by using the same patterning process; The first active layer and the second active layer are formed simultaneously by using the same patterning process; The data line, the first source-drain electrode layer and the second source-drain electrode layer are formed simultaneously by using the same patterning process; The bridge electrode, the pixel electrode and the auxiliary electrode are formed simultaneously by using the same patterning process.

15. A display device, characterized in that: The electronic paper comprises the electronic paper as claimed in any one of claims 1 to 12.

Images