A silicon nanowire gyroscope based on gate control and its processing method

Abstract

The present invention relates to a gate-controlled silicon nanowire gyroscope and its processing method. The silicon nanowire gyroscope comprises an SOI silicon wafer, with a silicon nitride film disposed on the top silicon surface of the SOI silicon wafer. The top silicon wafer forms a suspended mass block and three connected silicon nanowires, with the silicon nanowires distributed along the periphery of the mass block. The surface of the mass block and the silicon nanowires are both adhered with a silicon nitride film. Positive and negative electrodes are disposed on the top silicon wafer, conductively connected to the bulk silicon. The SOI silicon wafer also has an isolation channel etched from the silicon nitride film to the oxide layer to achieve physical isolation between the positive and negative electrodes. A gate is disposed on the suspended silicon nitride film, which is used to modulate the carrier concentration of the silicon nanowire channel, that is, to adjust the conductance of the silicon nanowire channel, thereby finding the optimal operating point of the device.

Description

Technical Field

[0001] The present invention belongs to the technical field of MEMS sensors, and in particular relates to a silicon nanowire gyroscope based on gate regulation and a processing method thereof. Background Art

[0002] With the rapid advancement of technology, the demand for miniaturization and integration of sensor devices is growing stronger. Traditional capacitive and piezoresistive gyroscopes are difficult to significantly reduce in size while maintaining their accuracy and resolution, resulting in the large size of existing gyroscopes. Furthermore, gyroscopes are difficult to adjust to their optimal operating state based on actual application scenarios. Summary of the Invention

[0003] The purpose of the present invention is to address the above-mentioned problems and provide a silicon nanowire gyroscope based on gate regulation and its processing method. By using single-crystal silicon nanowires instead of traditional varistors as a detection method, the device can be miniaturized, and the carrier concentration of the silicon nanowire channel is adjusted by the gate to find the optimal operating point of the gyroscope.

[0004] In order to achieve the above object of the invention, the present invention adopts the following technical solutions:

[0005] A gate-controlled silicon nanowire gyroscope includes an SOI silicon wafer with a silicon nitride film on the top silicon surface. The top silicon wafer has a suspended proof mass and three connected silicon nanowires, which are distributed around the periphery of the proof mass. The surfaces of the proof mass and the silicon nanowires are both covered with a silicon nitride film.

[0006] Positive and negative electrodes conductively connected to the bulk silicon are provided on the top silicon layer;

[0007] The SOI silicon wafer also has an isolation channel etched from the silicon nitride film to the oxide layer to achieve physical isolation between the positive and negative electrodes;

[0008] A gate is set on the suspended silicon nitride film, and the gate is used to modulate the carrier concentration of the silicon nanowire channel.

[0009] As a preferred solution, the gate is located directly above the silicon nanowires and each silicon nanowire is covered by the gate.

[0010] As a preferred solution, the width of the gate is 1-100 μm.

[0011] As a preferred solution, the width of the silicon nanowire is 10-800 nm.

[0012] The present invention also provides a method for processing the silicon nanowire gyroscope as described in any of the above solutions, comprising the following steps:

[0013] S1, preparing a silicon nitride film on the top silicon surface of a (111) type SOI silicon wafer to form a dielectric mask layer;

[0014] S2. Form three circularly distributed triangular patterns in the dielectric mask layer by photolithography, and etch the silicon nitride at the pattern to form three triangular windows; dry-etch the silicon at each triangular window and etch it down to the oxide layer of the SOI silicon wafer to form three vertical triangular grooves of the same depth;

[0015] S3, using dry etching to sequentially etch the silicon oxide layer under the vertical triangular groove and the underlying silicon to a preset depth to obtain a triangular etched groove;

[0016] S4. Remove the photoresist and perform anisotropic wet etching on the triangular etching grooves to form hexagonal etching grooves. A single-crystal silicon thin-wall structure is formed between adjacent hexagonal etching grooves. Two opposing pyramidal structures appear between the three hexagonal etching grooves. The etching grooves on the bottom silicon with a 100 crystal orientation release the two connected pyramidal structures on the top silicon to form a mass block.

[0017] S5. Thermally oxidizing the silicon wafer using a self-limiting thermal oxidation process to form a single-crystal silicon nanowire at the top center of the single-crystal silicon thin-wall structure;

[0018] S6. Etching the silicon nitride film at appropriate locations on the silicon wafer to form square windows, implanting boron ions into the square windows and then annealing them, and then fabricating positive and negative electrodes;

[0019] S7, preparing a gate on the suspended silicon nitride film;

[0020] S8. Making isolation trenches at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes;

[0021] S9. Remove the oxidized single crystal silicon thin wall structure and release the entire structure.

[0022] As a preferred solution, the silicon nitride film is produced by using a low-stress CVD film growth technology.

[0023] As a preferred solution, the thickness of the silicon nitride film is 50 nm-5 μm.

[0024] As a preferred solution, the depth of the vertical triangular groove is 1-100 μm.

[0025] As a preferred solution, the preset depth of etching the bottom silicon layer is 1-100 μm.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The present invention uses a silicon nitride film and three silicon nanowires to jointly support the mass block, and adopts single-crystal silicon nanowires to replace traditional piezoresistors as the detection method of the gyroscope. This not only achieves innovation in the device structure, but also because the piezoresistance coefficient of silicon nanowires is higher than that of piezoresistors, the gyroscope of the present invention has higher sensitivity.

[0028] The present invention creatively prepares a gate on the gyroscope, and the gate can find the optimal working point of the gyroscope by adjusting the carrier concentration of the silicon nanowire channel.

[0029] Due to the special design of the silicon nanowire and mass block structure, the silicon nanowire gyroscope of the present invention causes greater stress on the silicon nanowire when the gyroscope is subjected to a relatively small angular acceleration, thereby improving the output sensitivity of the gyroscope. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 Schematic diagram of fabricating a silicon nitride film on top silicon in accordance with embodiment 1 of the present invention;

[0031] Figure 2 Schematic diagram of making triangular etching grooves on a silicon wafer according to Example 1 of the present invention;

[0032] Figure 3 Schematic diagram of forming inclined hexagonal etching grooves by wet etching triangular grooves according to Example 1 of the present invention;

[0033] Figure 4 3D schematic diagram of the structure of the inclined hexagonal etching groove formed by wet etching the triangular groove in Example 1 of the present invention;

[0034] Figure 5 Schematic diagram of thermal oxidation of silicon nanowalls to form silicon nanowires according to Example 1 of the present invention;

[0035] Figure 6 Schematic diagram of preparing gold electrodes and gates on a silicon wafer in Example 1 of the present invention;

[0036] Figure 7 is a side view schematic diagram of the silicon nanowires supporting the mass block after the entire structure is released according to embodiment 1 of the present invention;

[0037] Figure 8 1 is a schematic structural diagram of a silicon nanowire gyroscope according to Example 1 of the present invention;

[0038] Figure 9 This is a photograph of a triangular groove after wet etching according to Example 1 of the present invention;

[0039] Figure 10 This is a photograph of a triangular groove formed after wet etching according to Example 2 of the present invention. DETAILED DESCRIPTION

[0040] To more clearly illustrate the embodiments of the present invention, specific embodiments of the present invention will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings and other embodiments can be obtained based on these drawings without inventive efforts.

[0041] Example 1:

[0042] like Figure 1-8 As shown, the structure of the gate-controlled silicon nanowire gyroscope of this embodiment mainly includes silicon nanowires 8, silicon nitride film, mass block 9, gold electrode 12, isolation channel 11, gate 13 and SOI silicon wafer.

[0043] Specifically, a silicon nitride film 1 is applied to the top silicon layer 2 of the SOI wafer. A suspended proof mass 9 and three connected silicon nanowires 8 are formed on the top silicon layer 2, with the silicon nanowires 8 distributed along the periphery of the proof mass 9. The silicon nitride film 1 is also adhered to the surfaces of the proof mass 9 and the silicon nanowires 8. Gold electrodes 12, conductively connected to the bulk silicon 4, serve as positive and negative electrodes on the top silicon layer 2.

[0044] Moreover, the SOI silicon wafer also has an isolation channel 11 etched from the silicon nitride film to the oxide layer 3 to achieve physical isolation between the positive and negative electrodes;

[0045] In addition, a gate 13 is disposed on the suspended silicon nitride film 1. Gate 13 is used to modulate the carrier concentration of the silicon nanowire channel. Specifically, gate 13 is located directly above the silicon nanowires 8, and each silicon nanowire is covered by the gate. The width of the silicon nanowires is preferably 10-800 nm, and the width of the gate is preferably 1-100 μm.

[0046] When the silicon nanowire gyroscope is subjected to external angular acceleration, the mass block 9 rotates in the direction of the angular acceleration, causing the silicon nanowire 8 supporting the mass block to deform. The deformation causes the conductivity of the silicon nanowire to change, thereby outputting a changing signal.

[0047] The gate 13 of the silicon nanowire gyroscope of this embodiment can modulate the carrier concentration of the silicon nanowire channel, thereby finding the optimal operating point of the gyroscope.

[0048] The following is a detailed description of the method for manufacturing the gate-controlled silicon nanowire gyroscope according to this embodiment, which includes the following steps:

[0049] 1. First, select a (111) type SOI silicon wafer with a bottom silicon of 100 type, and use low stress CVD thin film growth technology to prepare a layer of silicon nitride film 1 with a thickness of 50nm-5μm on its top silicon surface to form a dense dielectric mask layer, such as Figure 1 shown.

[0050] 2. Three tilted triangle patterns 5 are formed in the dielectric mask layer by photolithography, as shown in FIG. Figure 2 shown.

[0051] The triangular pattern 5 is subjected to RIE, etching the silicon nitride 1 at the pattern to form three triangular windows. The silicon at these three triangular windows is dry-etched until it reaches the oxide layer 3 of the (111) SOI silicon wafer, with the etching depth equal to the thickness of the top silicon 2, thus forming vertical triangular grooves of uniform depth. The oxide layer 3 below the vertical triangular grooves is further etched using a dry etching process, with the etching depth equal to the thickness of the oxide layer 3. The bottom silicon 4 is then etched downwards by approximately 1-100 μm.

[0052] 3. Remove the photoresist, and then anisotropically wet etch the triangular grooves in step 2 in a 10-80 wt% KOH solution at 10-100° C. to form hexagonal etching grooves 6, each of whose sidewalls belongs to the {111} crystal plane family, and form a single crystal silicon thin-wall structure 7 with a preset width of less than 1 μm between two adjacent hexagonal etching grooves, as shown in FIG. Figure 3 、 4 and 9.

[0053] Two connected pyramidal structures appear in the middle of the three hexagonal etching grooves. These two pyramidal structures are the mass block 9 of the silicon nanowire gyroscope. At the same time, the etching grooves appearing in the bottom silicon with a crystal orientation of 100 release the two connected pyramidal structures on the top silicon to form a mass block (the mass block can only be suspended in the air through BOE later). Figure 7 shown.

[0054] 4. After the silicon wafer is oxidized based on the self-limiting thermal oxidation process, a single crystal silicon nanowire 8 is formed at the top center of the single crystal silicon thin-wall structure 7, as shown in FIG. Figure 5 shown.

[0055] 5. Etch silicon nitride 1 to form windows at the upper left and lower right corners of the silicon wafer. Implant boron ions into the windows and then anneal. The ion implantation energy is 5-100 KeV and the ion implantation dose is 0.1E15 cm -2 -10E15cm -2 The annealing temperature is 200-4000℃ and the annealing time is 5 minutes to 10 hours. A gold electrode 12 is made in this area. Then a gate 13 is prepared on the suspended silicon nitride film. The gate is located directly above the silicon nanowire and each silicon nanowire is covered by the gate. Figure 6 shown.

[0056] 5. Etch the silicon wafer to the bottom silicon 4 at the appropriate position of the silicon wafer to make an isolation channel 11, dividing the device to achieve physical isolation between the positive and negative electrodes of the device, such as Figure 6 shown.

[0057] 6. Use BOE solution (buffer oxide etching solution) to remove the oxidized single crystal silicon nano-thin wall in step 4 to release the entire structure.

[0058] After the above steps are completed, the Figure 8 The shown is a gate-controlled silicon nanowire gyroscope based on SOI material.

[0059] Example 2:

[0060] The silicon nanowire gyroscope of this embodiment is different from that of embodiment 1 in that:

[0061] like Figure 10 As shown, the arrangement positions of the three triangular windows are different (two on top, one on the bottom), and the structures related to the three triangular windows are adjusted accordingly; for other structures, please refer to Example 1;

[0062] The processing technology of the silicon nanowire gyroscope is adaptively adjusted according to the different arrangement positions of the three triangular windows. The specific steps can be referred to Example 1.

[0063] The above description is only a detailed description of the preferred embodiments and principles of the present invention. For ordinary technicians in this field, based on the ideas provided by the present invention, there may be changes in the specific implementation methods, and these changes should also be considered as the scope of protection of the present invention.

Claims

1. A method for processing a gate-controlled silicon nanowire gyroscope, characterized in that: The silicon nanowire gyroscope includes an SOI silicon wafer with a silicon nitride film on the top silicon surface of the SOI silicon wafer. The top silicon wafer forms a suspended mass block and three silicon nanowires connected thereto, with the silicon nanowires distributed along the periphery of the mass block. The surfaces of the mass block and the silicon nanowires are both adhered with a silicon nitride film. When the silicon nanowire gyroscope is subjected to external angular acceleration, the mass block rotates in the direction of the angular acceleration, causing the silicon nanowires supporting the mass block to deform. The deformation causes the electrical conductance of the silicon nanowires to change, thereby outputting a changing signal. Positive and negative electrodes conductively connected to the bulk silicon are provided on the top silicon layer; The SOI silicon wafer also has an isolation channel etched from the silicon nitride film to the oxide layer to achieve physical isolation between the positive and negative electrodes; A gate is set on the suspended silicon nitride film, and the gate is used to modulate the carrier concentration of the silicon nanowire channel; The processing method comprises the following steps: S1, preparing a silicon nitride film on the top silicon surface of a (111) type SOI silicon wafer to form a dielectric mask layer; S2. Form three circularly distributed triangular patterns in the dielectric mask layer by photolithography, and etch the silicon nitride at the pattern to form three triangular windows; dry-etch the silicon at each triangular window and etch it down to the oxide layer of the SOI silicon wafer to form three vertical triangular grooves of the same depth; S3, using dry etching to sequentially etch the silicon oxide layer under the vertical triangular groove and the underlying silicon to a preset depth to obtain a triangular etched groove; S4. Remove the photoresist and perform anisotropic wet etching on the triangular etching grooves to form hexagonal etching grooves. A single-crystal silicon thin-wall structure is formed between adjacent hexagonal etching grooves. Two opposing pyramidal structures appear between the three hexagonal etching grooves. The etching grooves on the bottom silicon with a 100 crystal orientation release the two connected pyramidal structures on the top silicon to form a mass block. S5. Thermally oxidizing the silicon wafer using a self-limiting thermal oxidation process to form a single-crystal silicon nanowire at the top center of the single-crystal silicon thin-wall structure; S6. Etching the silicon nitride film at appropriate locations on the silicon wafer to form square windows, implanting boron ions into the square windows and then annealing them, and then fabricating positive and negative electrodes; S7, preparing a gate on the suspended silicon nitride film; S8. Making isolation trenches at appropriate locations on the silicon wafer to achieve physical isolation between the positive and negative electrodes; S9. Remove the oxidized single crystal silicon thin wall structure and release the entire structure.

2. The processing method according to claim 1, wherein The silicon nitride film is produced by adopting low-stress CVD film growth technology.

3. The processing method according to claim 1, wherein: The thickness of the silicon nitride film is 50 nm-5 μm.

4. The processing method according to claim 1, wherein: The depth of the vertical triangular groove is 1-100 μm.

5. The processing method according to claim 1, wherein: The preset depth of etching the bottom silicon layer is 1-100 μm.

6. The processing method according to claim 1, wherein: The gate is located directly above the silicon nanowires and each silicon nanowire is covered by the gate.

7. The processing method according to claim 6, characterized in that: The width of the gate is 1-100 μm.

8. The processing method according to claim 6, wherein: The width of the silicon nanowire is 10-800 nm.

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