Design Method of an Excitation Signal Processing Circuit for Eliminating Parasitic Capacitance Reactance

Abstract

The present invention relates to the technical field of excitation signal processing circuits, and discloses a design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance. At the rear end of an excitation capacitive sensor, a capacitor with parallel excitation is added, and the excitation signal of this capacitor is the same as that of the sensor itself. However, the excitation processing methods at the rear end are different. One path converts the AC excitation signal into a positive voltage / positive current output, and the other path converts the AC excitation signal into a negative voltage / negative current output. The two processing methods are controlled by a switch array logic. By using the symmetry principle and the summation cancellation principle of AC signals, parasitic parameters such as capacitance reactance during cable transmission are eliminated. At the same time, it can also be used as a dual-channel redundancy output, enabling dual-redundancy feedback output for DC measurement of capacitive sensors. The present invention is used to eliminate the parasitic capacitance reactance brought by the measurement output end of the sensor, realize long-distance transmission of capacitive sensors, and support dual-redundancy synchronous measurement.

Description

Technical Field

[0001] The present invention relates to the technical field of excitation signal processing circuits. Specifically, it is a design method for an excitation signal processing circuit that can eliminate parasitic capacitance reactance, which is used to eliminate the parasitic capacitance reactance brought by the measurement output end of a sensor, realize long-distance transmission of a capacitive sensor, and support dual-redundancy synchronous measurement. Background Art

[0002] The measurement of a traditional capacitive sensor uses signal excitation at one end and signal feedback at the other end, and the feedback signal is processed through integration, filtering, isolation, etc. and then converted into a DC level for acquisition and processing by the backend circuit. The backend measurement is divided into two types: DC measurement and AC measurement. The AC measurement mainly includes the mechanical bridge balance principle and the digital bridge balance principle, which are not within the scope of discussion of this invention. The DC measurement principle is as follows: One end of the capacitive sensor is excited by an AC-varying excitation signal, and the other end is converted into a DC current signal through filtering and demodulation processing. This current signal changes with the change of capacitance. The backend current sends this current signal into a computer for acquisition through current-voltage conversion, so as to obtain the acquisition output result of the capacitive sensor.

[0003] The traditional excitation backend processing circuit can neither eliminate the influence of internal voltage drop nor the influence of parasitic capacitance reactance brought by the cable. That is, a part of leakage current will be generated by the demodulation circuit due to capacitance reactance, and this leakage current will cause different output results of the capacitive sensor with the electrical drift of the device, resulting in poor measurement consistency. Especially when the transmission cable is long, it is impossible to ensure the consistency and stability of the transmission signal.

[0004] The present invention aims to design a design method for an excitation signal processing circuit that can eliminate parasitic capacitance reactance, and on the basis of the single output of the traditional excitation backend processing circuit, it is extended to bidirectional output to support dual-redundancy synchronous measurement. Summary of the Invention

[0005] The purpose of the present invention is to provide a design method for an excitation signal processing circuit that can eliminate parasitic capacitance reactance. Compared with the previous excitation signal processing circuits, it can eliminate the parasitic capacitance reactance brought by the measurement output end of the sensor, realize long-distance transmission of the capacitive sensor, and support dual-redundancy synchronous measurement.

[0006] The present invention is realized through the following technical solutions: A design method for an excitation signal processing circuit that can eliminate parasitic capacitance reactance, including:

[0007] A first parallel filter circuit and a second parallel filter circuit are arranged in the excitation signal processing circuit, and the first parallel filter circuit and the second parallel filter circuit are respectively arranged between the demodulation diode and the ground loop;

[0008] A first reference capacitor C1 and a first resistor R1 are provided in the first parallel filter circuit, and a second reference capacitor C2 and a second resistor R2 are provided in the second parallel filter circuit;

[0009] A first switch K1, a second switch K2, a third switch K3, an upper reference capacitor C0, and an equivalent lower capacitive sensor CX are provided;

[0010] The first parallel filter circuit is connected to the upper reference capacitor C0 and the second switch K2, and the second parallel filter circuit is connected to the lower equivalent capacitive sensor CX and the third switch K3;

[0011] When the first switch K1, the second switch K2, and the third switch K3 are combined according to different switching, the excitation signal processing circuit is combined into a parasitic capacitance cancellation mode and a dual-channel redundancy output mode;

[0012] The return ends of the first reference capacitor C1 and the lower equivalent capacitive sensor CX are summed through the negative terminal of the U1 summing operational amplifier provided and then an output current signal is output.

[0013] To better implement the present invention, further, an alternating sinusoidal signal with a fixed frequency is input to the driving section of the excitation signal processing circuit, and the alternating sinusoidal signal drives the upper reference capacitor C0 excitation and the equivalent lower capacitive sensor CX excitation.

[0014] To better implement the present invention, further, the method of respectively arranging the first parallel filter circuit and the second parallel filter circuit between the detection diode and the ground loop includes:

[0015] A first diode V1 and a second diode V2 are arranged beside the first parallel filter circuit, and a third diode V3 and a fourth diode V4 are arranged beside the second parallel filter circuit.

[0016] To better implement the present invention, further, the upper reference capacitor C0 outputs the negative half-wave current through the first diode V1 and conducts the positive half-wave current to the loop ground through the second diode V2;

[0017] The excitation lower equivalent capacitive sensor CX feedback signal conducts the positive half-wave current to the output through the fourth diode V4 and conducts the negative half-wave current to the loop ground through the third diode V3.

[0018] To better implement the present invention, further, an external logic is used to control the first switch K1, the second switch K2, and the third switch K3;

[0019] When the first switch K1 is open and the second switch K2 and the third switch K3 are closed, the circuit formed is the parasitic capacitance reactance elimination mode; when the first switch K1 is closed and the second switch K2 and the third switch K3 are alternately and mutually exclusively open, the circuit formed is the dual-channel redundancy output mode.

[0020] To better implement the present invention, further, in the parasitic capacitance reactance elimination mode, if the capacitance value of the upper reference capacitor C0 is adjusted to change the current signal output of the lower equivalent capacitive sensor CX;

[0021] Due to summation cancellation, the formula for the corrected capacitor CXin is CXin = CX - C0, which ensures the output consistency of the equivalent capacitive sensor CX in the parasitic capacitance reactance elimination mode.

[0022] To better implement the present invention, further, in the dual-channel redundancy output mode, the upper reference capacitor C0 and the lower equivalent capacitive sensor CX are in a parallel relationship, and the formula for the corrected capacitor CXin is CXin = CX + C0, which flexibly corrects and sets the output capacitive reactance of the equivalent capacitive sensor CX in the dual-channel redundancy output mode.

[0023] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0024] (1) Compared with the previous excitation signal processing circuit, the present invention can eliminate the parasitic capacitance reactance brought by the measurement output end of the sensor, realize the long-distance transmission of the capacitive sensor, and achieve dual-redundancy synchronous measurement through the switch combination logic.

[0025] (2) Compared with the conventional capacitive reactance excitation signal backend circuit, the present invention can effectively eliminate the voltage drop brought by the circuit, and at the same time can flexibly adjust the output parameters of the capacitive sensor; in addition, it can also eliminate the parasitic capacitance parameters of the capacitive sensor cable transmission to achieve consistent measurement; reliable measurement in different electromagnetic interference environments can be achieved by adjusting the RC filtering parameters; finally, the dual-channel DC feedback output of the capacitive sensor can also be realized through the switch array. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The present invention will be further described in conjunction with the following drawings and embodiments. All the innovative concepts of the present invention should be regarded as the disclosed content and the protection scope of the present invention.

[0027] Figure 1 It is a schematic diagram of the principle of the excitation signal processing circuit in a design method of an excitation signal processing circuit capable of eliminating parasitic capacitance reactance provided by the present invention.

[0028] Figure 2 It is a schematic diagram of a conventional method for excitation signal feedback processing provided by the present invention.

[0029] Figure 3 It is a schematic diagram of the feedback processing method for the excitation signal in the parasitic capacitance cancellation mode provided by the present invention.

[0030] Figure 4 It is a schematic diagram of the feedback processing of the reference capacitance excitation signal provided by the present invention.

[0031] Figure 5 It is a schematic diagram of the feedback processing circuit for the sensor excitation signal provided by the present invention.

[0032] Figure 6 It is a system application diagram of the feedback processing method when the excitation signal processing circuit is in the parasitic capacitance cancellation mode in the present invention.

[0033] Figure 7 It is an equivalent diagram when the excitation signal processing circuit is in the dual-channel output mode in the present invention. Specific embodiments

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will combine the accompanying drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. It should be understood that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments, and should not be regarded as a limitation of the protection scope. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative work belong to the protection scope of the present invention.

[0035] Embodiment 1:

[0036] A design method of an excitation signal processing circuit capable of eliminating parasitic capacitance in this embodiment is as follows Figure 1 As shown, the present invention relates to the design of a front-end excitation signal processing circuit mainly used for the measurement of capacitive output type sensors. Compared with the conventional excitation signal processing circuit, it can eliminate the parasitic capacitance brought by the measurement output end of the sensor, realize the long-distance transmission of the capacitive sensor, and achieve dual-redundancy synchronous measurement through switch combination logic.

[0037] The measurement of traditional capacitive sensors uses signal excitation at one end and signal feedback at the other end. The feedback signal is processed through integration, filtering, isolation, etc. and then converted into a DC level for acquisition and processing by the backend circuit. The backend measurement is divided into two types: DC measurement and AC measurement. The AC measurement mainly includes the mechanical bridge balance principle and the digital bridge balance principle, which are not within the scope of discussion in this invention. The DC measurement principle is as follows: One end of the capacitive sensor is excited by an AC-varying excitation signal, and the other end is converted into a DC current signal through filtering and demodulation processing. This current signal changes with the change of capacitance. The backend circuit sends this current signal into a computer for acquisition through current-voltage conversion, thereby obtaining the acquisition output result of the capacitive sensor.

[0038] The traditional excitation backend processing circuit can neither eliminate the influence of internal voltage drop nor the influence of parasitic capacitance introduced by the cable. That is, this demodulation circuit will generate a part of leakage current due to capacitive reactance. This leakage current will cause different output results of the capacitive sensor with the electrical drift of the device, resulting in poor measurement consistency. Especially when the transmission cable is long, it is impossible to ensure the consistency and stability of the transmitted signal.

[0039] The design idea of this invention is to add a capacitively coupled excitation capacitor at the backend of the capacitive sensor. The excitation signal of this capacitor is the same as that of the sensor itself, but the backend excitation processing methods are different. One path converts the AC excitation signal into a positive voltage / positive current output, and the other path converts the AC excitation signal into a negative voltage / negative current output. The two processing methods are controlled by a switch array logic. Through the symmetry principle and summation cancellation principle of the AC signal, parasitic parameters such as capacitive reactance during cable transmission are eliminated. At the same time, it can also be used as a dual-channel redundancy output, enabling dual-redundancy feedback output for the DC measurement of the capacitive sensor. In addition, compared with the conventional capacitive reactance excitation signal backend circuit, this invention can effectively eliminate the voltage drop caused by the circuit and can flexibly adjust the output parameters of the capacitive sensor. In addition, it can also eliminate the parasitic capacitance parameters of the capacitive sensor cable transmission, achieving consistent measurement. By adjusting the RC filtering parameters, reliable measurement in different electromagnetic interference environments can be achieved. Finally, dual-channel DC feedback output of the capacitive sensor can also be realized through the switch array.

[0040] Embodiment 2:

[0041] This embodiment is further optimized on the basis of Embodiment 1, such as Figure 1The schematic block diagram of the principle of the present invention is shown. The driving end uses an alternating sine wave signal with a fixed frequency. This driving signal simultaneously excites the reference capacitor C0 and the lower-end CX (i.e., the equivalent capacitive sensor). The upper-end reference capacitor outputs the negative half-wave current through the V1 diode and conducts the positive half-wave current to the circuit ground through the V2 diode; while the feedback signal of the excited lower-end capacitive sensor conducts the positive half-wave current to the output through the V4 diode and conducts the negative half-wave current to the circuit ground through the V3 diode. The return ends of the reference capacitor C1 and the equivalent capacitive sensor CX are summed through the negative terminal of the U1 summing operational amplifier and then output.

[0042] Among them, the parallel filter circuit composed of R1 and C1 is the first parallel filter circuit, and the parallel filter circuit composed of R2 and C2 is the second parallel filter circuit. The first parallel filter circuit and the second parallel filter circuit are arranged between the detection diode and the ground loop to filter out interference waveforms.

[0043] As Figure 1 shown, the present invention sets switches K1, K2, and K3, and the switches can be controlled by external logic. When K1, K2, and K3 are in different switch combinations, such as when K1 is open and K2 and K3 are closed, the composed circuit is the parasitic capacitance cancellation mode; when K1 is closed and K2 and K3 are alternately and mutually exclusive open, the composed circuit is the dual-channel redundancy output mode.

[0044] In the parasitic capacitance cancellation mode, if the size of the C0 capacitor is adjusted, due to the positive and negative current summation relationship between the C0 reference capacitor and the sensor capacitance backend processing circuit, the current signal output of the oil level sensor can be changed by adjusting the capacitance value of C0. Due to summation cancellation, its correction formula is CXin = CX - C0, and the consistency of the sensor output is ensured through this invention.

[0045] In the dual-channel redundancy output mode, the C0 reference capacitor and the CX sensor capacitor are in a parallel relationship, that is, the correction formula is CXin = CX + C0. Different correction methods can flexibly correct and set the output capacitive reactance of the capacitive sensor.

[0046] Other parts of this embodiment are the same as those of Embodiment 1, so they will not be described in detail.

[0047] Embodiment 3:

[0048] This embodiment is further optimized on the basis of the above Embodiment 1 or 2, such as Figure 2The figure shows a conventional schematic diagram of the excitation signal feedback processing, that is, a full-wave signal is input at one end of the equivalent capacitor CX inside the sensor, output from the positive terminal of the V1 diode, and the negative terminal is connected to the return terminal of the equivalent capacitor CX. At the same time, the return terminal is connected to the positive electrode of the V2 diode, and the full-wave signal is output as a negative half-wave rectified current signal from the positive terminal of the V1 diode in this way. Through the above method, the equivalent half-wave DC current signal can change with the change of CX, so as to realize the detection output of the capacitive sensor.

[0049] This method cannot eliminate the voltage drop of the diode, nor can it eliminate the leakage current caused by the parasitic capacitance in the cable transmission. The leakage current causes deviations in the amplitude and phase of the half-wave rectified signal it outputs, so that the DC capacitive sensor cannot achieve consistent measurement and cannot support long-distance consistent transmission.

[0050] Other parts of this embodiment are the same as those of the above-mentioned Embodiment 1 or 2, so they will not be described in detail.

[0051] Embodiment 4:

[0052] This embodiment is further optimized on the basis of any one of the above-mentioned Embodiments 1-3, such as Figure 3 The figure shows a method for processing the excitation signal feedback in the mode of eliminating parasitic capacitive reactance. C0 at the upper end of the figure is the reference capacitor, and the lower end of the figure is the CX equivalent capacitive sensor. The return terminal of the lower end CX will inevitably generate leakage current after passing through the excitation signal feedback processing circuit, and the equivalent parasitic capacitance on the cable line will also consume additional parasitic leakage current. After the above processing, a negative current signal is output, and this negative current is related to the size of CX and the change of the parasitic capacitance on the transmission cable. Similarly, the return terminal of the reference capacitor also generates leakage current and cable parasitic leakage current after passing through the feedback processing circuit. Since the internal diode combination is set in the opposite direction to the sensor excitation signal feedback processing circuit, this current is a positive current in the opposite direction. After summing operation, it is output, and the leakage current caused by the parasitic capacitive reactance can be mostly offset, that is, the influence of the parasitic capacitive reactance in the transmission process is eliminated.

[0053] Other parts of this embodiment are the same as those of any one of the above-mentioned Embodiments 1-3, so they will not be described in detail.

[0054] Embodiment 5:

[0055] This embodiment is further optimized on the basis of any one of the above-mentioned Embodiments 1-4, such as Figure 4 And as Figure 5 The figure shows a schematic diagram of the excitation signal feedback processing of the reference capacitor and a schematic diagram of the excitation signal feedback processing circuit of the sensor respectively. As Figure 4 The figure shows that a resistor R1 and a capacitor C1 are added at the negative terminal of V2, that is, the ground terminal, and the negative terminal of V1 to form a low-pass filter circuit. As Figure 5As shown in the figure, a resistor R2 and a capacitor C2 are connected in parallel at the negative terminal (i.e., the output terminal) of V4 and the negative terminal of V3, which can eliminate the high-frequency clutter signals caused by electromagnetic interference, and the low-pass cut-off frequency of this signal can be modified by the RC parameters. Figure 4 The negative current signal fed back from the rear end of the reference capacitor is reserved and output from OUT through two diodes V1 and V2, and the positive current part is grounded; Figure 5 The positive current signal fed back from the rear end of the sensor output capacitor is reserved and output from OUT through two diodes V3 and V4, and the negative current part is grounded.

[0056] The signals output after the feedback of the reference capacitor and the signals output after the feedback of the equivalent capacitor of the sensor are both affected by the voltage drop caused by the diodes and the parasitic capacitance of the cable transmission, resulting in amplitude and phase offsets. However, since the phase drifts of the former and the latter are basically the same, and the amplitude drifts just present a cancellation state, that is, the positive current and the negative current are summed up, and the feedback output obtained is the equivalent output current that eliminates the diode voltage drop and the parasitic capacitance. This current is processed further after the I / V conversion at the rear end.

[0057] Other parts of this embodiment are the same as any one of the above Embodiments 1-4, so they will not be described in detail.

[0058] Embodiment 6:

[0059] This embodiment is further optimized on the basis of any one of the above Embodiments 1-5, such as Figure 6 As shown in the figure, the present invention is applied in a measurement system. One end of a capacitive sensor is connected to a voltage Vpi with a peak value of 10V and a frequency of f, and the other end passes through an "excitation signal feedback processing circuit", and the forward voltage drop of the internal diode is defined as V D , that is, according to the capacitive reactance response formula of alternating current, the average current Ip output from the capacitive sensor end is obtained 1averag As shown in formula (1).

[0060] Ip 1average = 2πfCp(Vp 1 -V D ) (1);

[0061] Among them, f is the frequency of the excitation source, and Cp is the output equivalent capacitance of the capacitive sensor end.

[0062] After sorting out, formula (2) can be obtained:

[0063] 2πfCpV D = 2πfCpVp 1 -Ip 1average (2);

[0064] Similarly, the calculation formula obtained after the excitation feedback at the reference capacitor end is as shown in formula (3):

[0065] 2πfCpV D = 2πfCpVp 2 -Ip 2average (3);

[0066] That is, as Figure 6 shown, after passing through the summing circuit, Formula (2) and Formula (3) are combined, summed, and sorted to obtain Formula (4),

[0067] Cp = (Ip 1average -Ip 2average ) / {2πf(Vp 1 -Vp 2 )} (4);

[0068] Cp is the equivalent output of the sensor and the capacitance after passing through the excitation signal feedback processing circuit, and has nothing to do with the voltage amplitude reduction V D caused by the diode voltage drop or transmission cable. Among them, to ensure that its current signal transmission is not affected by external electromagnetic interference, the cable for current transmission uses an inner shielded cable, that is, the shield layer is independently grounded to prevent external crosstalk and electromagnetic interference.

[0069] Other parts of this embodiment are the same as any one of the above Embodiments 1-5, so they will not be described in detail.

[0070] Embodiment 7:

[0071] This embodiment is further optimized on the basis of any one of the above Embodiments 1-6. As Figure 7 shown, in Figure 1 , close K1, close K2, and open K3, that is, the reference capacitor C0 and the equivalent capacitive sensor CX are equivalently paralleled. CO can adjust the output parameters of the adjustable capacitive sensor according to needs to ensure its output consistency.

[0072] At this time, after passing through the processing circuit of the present invention, an excited output negative current signal is obtained, and this signal is denoted as the negative current signal output. Similarly, in Figure 1 , close K1, open K2, and close K3, that is, an output positive current signal excited by the equivalent capacitive sensor CX equivalently paralleled with the reference capacitor C0 is obtained, and this signal is denoted as the positive current signal output.

[0073] By controlling the periodic mutually exclusive switching of K2 and K3 through the upper computer software, the dual-channel redundancy output of the capacitive sensor can be realized. The positive and negative currents are respectively subjected to voltage conversion and AD conversion at the back end for the dual-redundancy design of the subsequent acquisition system.

[0074] Other parts of this embodiment are the same as any one of the above Embodiments 1-6, so they will not be described in detail.

[0075] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Any simple modifications and equivalent changes made to the above embodiments based on the technical essence of the present invention shall fall within the protection scope of the present invention.

Claims

1. A design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance, characterized in that, comprising: setting a first parallel filter circuit and a second parallel filter circuit in the excitation signal processing circuit, and respectively setting the first parallel filter circuit and the second parallel filter circuit between the detection diode and the ground loop; a first reference capacitor C1 and a first resistor R1 are provided in the first parallel filter circuit, and a second reference capacitor C2 and a second resistor R2 are provided in the second parallel filter circuit; setting a first switch K1, a second switch K2, a third switch K3, an upper-end reference capacitor C0 and an equivalent lower-end equivalent capacitive sensor CX; making the first parallel filter circuit connect the upper-end reference capacitor C0 and the second switch K2, and the second parallel filter circuit connect the lower-end equivalent capacitive sensor CX and the third switch K3; when the first switch K1, the second switch K2 and the third switch K3 are combined according to different switches, the excitation signal processing circuit is combined into a parasitic capacitance reactance elimination mode and a dual-channel redundancy output mode; the return ends of the first reference capacitor C1 and the lower-end equivalent capacitive sensor CX are summed through the negative terminal of the set U1 summing operational amplifier and then an output current signal is output.

2. The design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance according to claim 1, characterized in that, comprising: inputting an alternating sine wave signal with a fixed frequency at the driving section of the excitation signal processing circuit, and the alternating sine wave signal drives the upper-end reference capacitor C0 excitation and the equivalent lower-end equivalent capacitive sensor CX excitation.

3. The design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance according to claim 1, characterized in that, the method of respectively setting the first parallel filter circuit and the second parallel filter circuit between the detection diode and the ground loop includes: setting a first diode V1 and a second diode V2 beside the first parallel filter circuit, and setting a third diode V3 and a fourth diode V4 beside the second parallel filter circuit.

4. The design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance according to claim 3, characterized in that, comprising: the upper-end reference capacitor C0 outputs the negative half-wave current through the first diode V1, and conducts the positive half-wave current to the loop ground through the second diode V2; the feedback signal of the excitation lower-end equivalent capacitive sensor CX conducts the positive half-wave current to the output through the fourth diode V4, and conducts the negative half-wave current to the loop ground through the third diode V3.

5. The design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance according to claim 1, characterized in that, comprising: using an external logic to control the first switch K1, the second switch K2 and the third switch K3; when the first switch K1 is open and the second switch K2 and the third switch K3 are closed, the composed circuit is a parasitic capacitance reactance elimination mode; when the first switch K1 is closed and the second switch K2 and the third switch K3 are alternately and mutually exclusive open, the composed circuit is a dual-channel redundancy output mode.

6. The design method for an excitation signal processing circuit capable of eliminating parasitic capacitance reactance according to claim 1, characterized in that, comprising: In the parasitic capacitance cancellation mode, if the capacitance value of the upper reference capacitor C0 is adjusted, the current signal output of the lower equivalent capacitive sensor CX will change; Due to summation cancellation, the formula for its corrected capacitor CXin is CXin = CX - C0, which ensures the output consistency of the equivalent capacitive sensor CX in the parasitic capacitance cancellation mode.

7. A design method of an excitation signal processing circuit capable of eliminating parasitic capacitance according to claim 1, characterized in that it includes: In the dual-channel redundancy output mode, the upper reference capacitor C0 and the lower equivalent capacitive sensor CX are in a parallel relationship, and the formula for its corrected capacitor CXin is CXin = CX + C0, which flexibly corrects and sets the output capacitive reactance of the equivalent capacitive sensor CX in the dual-channel redundancy output mode.

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