SRAM type FPGA dynamic burn-in device and burn-in method

Abstract

The application relates to an SRAM type FPGA dynamic aging device, which comprises a computer, a high-temperature box, a power supply and an aging test board. The aging test board comprises a bottom plate, test workstations, FLASH chips, a communication module, a single-chip microcomputer and peripheral configuration circuits. The bottom plate is a printed circuit board, the test workstations are more than three, the FLASH chips correspond to the test workstations one by one, the peripheral configuration circuits correspond to the FLASH chips one by one, the excitation signal output end of the single-chip microcomputer is connected with the excitation signal input end of the test workstations, the signal output end of the test workstations is connected with the signal acquisition end of the single-chip microcomputer, the output end of the power supply is connected with the power input end of the aging test board, and the aging test board communicates with the computer through the communication module. The aging method comprises the following steps: designing and downloading FPGA circuit functions; designing and downloading single-chip microcomputer circuit functions; connecting the aging test board with other equipment; and starting the aging test. The application has the advantages of low cost, good compatibility, effective improvement of the intelligent level and reduction of the test failure rate.

Description

Technical Field

[0001] This invention relates to the curing of programmable devices, specifically to a dynamic curing device and method for SRAM-type FPGAs. Background Technology

[0002] As the primary hardware platform for modern digital system design, the main characteristic of FPGAs is that they are entirely configured and programmed by users through software to perform specific functions, and they can be repeatedly erased and rewritten. Common FPGA types on the market include SRAM, Flash, and antifuse types. Among them, SRAM FPGAs are the most widely used due to their high speed, low cost, and reprogrammability.

[0003] Aging is a common method for improving the reliability of electronic components and eliminating early failures. Typically, after a manufacturer produces a batch of products, various uncertainties can lead to differences in the reliability of individual components within the same batch. Aging tests apply continuous electrical stress to the components over a longer period. The combined effect of electrical and thermal stress accelerates various physical and chemical reactions within the components, causing potential defects such as surface contamination, poor lead soldering, oxide layer defects, and silicon wafer cracks to surface early. For defect-free components, aging tests help stabilize their electrical parameters, ensuring product quality. Therefore, aging tests are necessary for both manufacturers and users of SRAM-type FPGAs.

[0004] The existing FPGA chip aging test uses active serial or passive serial configuration, but the data storage capacity allowed is relatively small, making it unsuitable as a configuration method for large-capacity FPGAs.

[0005] In existing FPGA chip aging tests, each board typically uses one configuration chip, and multiple FPGA chips are configured simultaneously in a serial mode, forming a chain structure to complete the configuration process. This chain structure has three shortcomings: First, if an abnormality occurs during configuration, due to the serial structure, any position in the chain can trigger an anomaly, making it difficult to accurately and promptly identify the fault point. Second, if any station is damaged, a portion of the chain will be missing, affecting the use of the entire aging test board; if the damage is irreparable, the entire board must be scrapped. Third, if the number of tests is less than the number of stations, a complete chain cannot be formed, and operation cannot begin.

[0006] The current level of intelligence in aging tests is not high, mainly in the following aspects: First, it cannot achieve autonomous aging startup. Existing technology requires multiple external signal sources to input various excitation signals to the FPGA to start the aging test. Second, it cannot monitor the FPGA's operation in real time. It still requires external signal sources and oscilloscopes to manually control the excitation signal input and observe the output signal displayed on the oscilloscope to determine whether the FPGA is working properly. Third, it lacks safety monitoring of the power supply. Once the power supply malfunctions, the lack of safety protection will cause the chip to burn out.

[0007] To address the aforementioned shortcomings of existing technologies, this invention proposes a low-cost, highly compatible SRAM-based FPGA dynamic aging device and aging method that can effectively improve intelligence levels and reduce test failure rates. Summary of the Invention

[0008] The purpose of this invention is to provide a low-cost, highly compatible SRAM-type FPGA dynamic aging device and aging method that can effectively improve the level of intelligence and reduce the failure rate of tests.

[0009] To achieve the above objectives, the present invention adopts the following technical solution: an SRAM-type FPGA dynamic aging device, comprising a computer, a high-temperature chamber, a power supply, and an aging test board, characterized in that the aging test board comprises a base plate, test stations, FLASH chips, a communication module, a microcontroller, and peripheral configuration circuits. The base plate is a printed circuit board, and there are three or more test stations. Each FLASH chip corresponds to one test station, and each peripheral configuration circuit corresponds to one FLASH chip. The excitation signal output terminal of the microcontroller is connected to the excitation signal input terminal of the test station, and the signal output terminal of the test station is connected to the signal acquisition terminal of the microcontroller. The output terminal of the power supply is connected to the power input terminal of the aging test board. The aging test board is placed inside the high-temperature chamber, and the aging test board communicates with the computer through the communication module.

[0010] Furthermore, the number of test stations is 10.

[0011] Furthermore, the aging test board is connected to a computer via a communication module and a 485 communication conversion cable.

[0012] Furthermore, the output terminal of the power supply is connected to the power input terminal of the aging test board via a relay, and the control signal input terminal of the relay is connected to the voltage control signal output terminal of the microcontroller.

[0013] The method for curing an SRAM-type FPGA using one of the aforementioned dynamic curing devices includes the following steps: S1. Design and download the FPGA circuit functionality; S1.1. Designing circuit functions using ISE software Using Verilog, the hardware description language in the software ISE, and calling D flip-flops and RAM memory cells, design the circuit function to complete the aging test. S1.2 Define FPGA pins Use the ISE software to define the pins for the clock port, input port, and output port; S1.3. Software Simulation Use the software ISE to perform simulation and verify whether the designed circuit functions normally. If it does, proceed to the next step; otherwise, return to step S1.1. S1.4. Download Circuit Function Use the SPI configuration method to generate a configuration file, and download the configuration file to each Flash chip on the old refinement test board; S2. Design and download the microcontroller circuit functions; S2.1. Design the circuit function of the microcontroller using the MDK software. S2.1.1. Configuration Process The microcontroller sends signals to the configuration pins prog and init of the FPGA chip, acquires the signal of the configuration pin done of the FPGA chip, and compares the level of the done pin. If it is high, the configuration is complete; otherwise, the configuration is reconfigured. S2.1.2. Formal Work Process The microcontroller sends signals to the clock port and input pins of the FPGA chip and acquires signals from the output pins of the FPGA chip. S2.2. Functional Simulation Use an oscilloscope to connect to the pins assigned to the microcontroller during the configuration and operation processes to verify whether the required excitation signal and output signal are normal. If they are normal, proceed to the next step; otherwise, return to step S2.1. S2.3. Downloading the microcontroller circuit function Use a programmer to download the functions of a microcontroller circuit. S3. Connect the aging test plate to other equipment; Place the FPGA chip to be aged in the test station, select a power supply that is compatible with the FPGA chip to be aged, connect the aging test board to the power supply and the computer respectively, and place the aging test board in the high temperature chamber. S4. Initiate the aging test; S4.1. Start the configuration process using a software serial port debugging assistant. Place the FPGA chip at the test station and control the FPGA chip and the corresponding Flash chip in the test station to complete the configuration; Enter the command in the serial port debugging assistant. This command, through the communication module, controls the microcontroller to send signals to the configuration pins prog and init of the FPGA chip. Wait 20 seconds for the configuration process to complete, and the serial port debugging assistant will receive the configuration result. If the configuration is successful, the result will be displayed as 1; if the configuration fails, the result will be displayed as 0. You need to check whether the software settings and hardware connections are correct and repeat the above steps until the configuration is successful. The serial port debugging assistant will display the configuration results of all stations on the aging test board. Based on the displayed results, troubleshoot the abnormal stations. Repeat the above process until the FPGA chips and corresponding Flash chips in all test stations are configured. S4.2. Start the formal working process using a software serial port debugging assistant. After successful configuration, input the command into the serial port debugging assistant. This command controls the microcontroller to send excitation signals to the clock port and input port defined by the FPGA, and collects the signal at the output port of the microcontroller. By comparing the signals, it is determined whether the designed FPGA circuit function has been implemented. The serial port debugging assistant receives the implementation result of the circuit function. If the implementation is successful, the result is displayed as 1; if the implementation fails, the result is displayed as 0. It is necessary to check whether the software settings and hardware connections are correct, and repeat the above steps until the implementation is successful. The serial port debugging assistant displays the implementation results of all test stations on the aging test board. Based on the displayed results, troubleshoot the abnormal stations. S4.3 Verify FPGA aging function Connect an oscilloscope to the clock port, input pin, and output pin of the FPGA chip respectively, observe the trend of waveform changes, and verify whether the FPGA aging function of the design meets expectations; if it meets expectations, proceed to the next step; otherwise, return to step S4.1. S4.4 Monitoring the FPGA aging process After the FPGA aging test starts normally, input the working command through the software serial port debugging assistant every 1-3 hours. After receiving the result display, determine whether the current aging test is normal. If an abnormality occurs, stop the aging test and troubleshoot the fault point. S4.5. Monitor the power supply voltage of the aging test board. The power supply voltage of the aging test board is monitored in real time by a microcontroller. If the voltage exceeds the threshold, the power supply line is cut off.

[0014] This invention adopts the SPI configuration method, that is, selects a FLASH chip with an SPI interface as the configuration chip to store the data required for the normal operation of the FPGA chip, which meets the storage requirements of large-capacity FPGA aging test, and therefore can be adapted to the aging of most FPGA chips.

[0015] This invention changes the serial mode to a parallel mode, that is, each FPGA chip is equipped with a separate FLASH chip and a separate peripheral configuration circuit, so that each station can work independently, effectively avoiding test abnormalities caused by mutual interference and reducing the test failure rate.

[0016] This invention adds a microcontroller to provide excitation signal input to the FPGA and collect the FPGA's output signal, thereby realizing automatic real-time monitoring; the microcontroller, when used with a communication module, can realize autonomous startup function; the microcontroller can also monitor the power supply voltage of the aging test board in real time.

[0017] Compared to the serial mode, although this invention increases the manufacturing cost due to the increased number of FLASH chips, it effectively eliminates the risk of entire board scrapping due to damage at a single workstation during subsequent use. Overall, it reduces the cost over the entire lifecycle of the test board. This invention is low-cost, highly compatible, and effectively improves the level of intelligence and reduces the test failure rate. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the structure of the present invention; Figure 2 This is a schematic diagram of the aging test plate structure of the present invention.

[0019] In the diagram: 1-Computer; 2-High Temperature Chamber; 3-Power Supply; 4-Aging Test Board; 4.1-Base Plate; 4.2-Test Station; 4.3-FLASH Chip; 4.4-Communication Module; 4.5-Microcontroller; 4.6-Peripheral Configuration Circuit; 5-Relay. Detailed Implementation

[0020] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments, but these embodiments should not be construed as limiting the present invention.

[0021] As shown in the figure, an SRAM-type FPGA dynamic aging device includes a computer 1, a high-temperature chamber 2, a power supply 3, and an aging test board 4. The aging test board 4 includes a base plate 4.1, test stations 4.2, FLASH chips 4.3, a communication module 4.4, a microcontroller 4.5, and peripheral configuration circuits 4.6. The base plate 4.1 is a printed circuit board. There are more than three test stations 4.2. Each FLASH chip 4.3 corresponds to one test station 4.2, and each peripheral configuration circuit 4.6 corresponds to one FLASH chip 4.3. The excitation signal output terminal of the microcontroller 4.5 is connected to the excitation signal input terminal of the test station 4.2, and the signal output terminal of the test station 4.2 is connected to the signal acquisition terminal of the microcontroller 4.5. The output terminal of the power supply 3 is connected to the power input terminal of the aging test board 4. The aging test board 4 is placed inside the high-temperature chamber 2 and communicates with the computer 1 through the communication module 4.4.

[0022] A preferred embodiment is that, in the above scheme, there are 10 test stations 4.2.

[0023] A preferred embodiment is that, in the above scheme, the aging test board 4 is connected to the computer 1 via the communication module 4.4 and the 485 communication conversion cable.

[0024] A preferred embodiment is as follows: In the above scheme, the output terminal of the power supply 3 is connected to the power input terminal of the aging test board 4 through the relay 5, and the control signal input terminal of the relay 5 is connected to the voltage control signal output terminal of the microcontroller 4.5.

[0025] The method for curing an SRAM-type FPGA using one of the aforementioned dynamic curing devices includes the following steps: S1. Design and download the FPGA circuit functionality; S1.1. Designing circuit functions using ISE software Using Verilog, the hardware description language in the software ISE, and calling D flip-flops and RAM memory cells, design the circuit function to complete the aging test. S1.2 Define FPGA pins Use the ISE software to define the pins for the clock port, input port, and output port; S1.3. Software Simulation Use the software ISE to perform simulation and verify whether the designed circuit functions normally. If it does, proceed to the next step; otherwise, return to step S1.1. S1.4. Download Circuit Function Use the SPI configuration method to generate configuration files, and download the configuration files to each Flash chip 4.3 of the old refinement test board 4; S2. Design and download the microcontroller circuit functions; S2.1. Design the circuit function of a microcontroller 4.5 using the MDK software. S2.1.1. Configuration Process The microcontroller 4.5 sends signals to the configuration pins prog and init of the FPGA chip, acquires the signal of the configuration pin done of the FPGA chip, and compares the level of the pin done. If it is high, the configuration is complete; otherwise, the configuration is reconfigured. S2.1.2. Formal Work Process The microcontroller 4.5 sends signals to the clock port and input pins of the FPGA chip and acquires signals from the output pins of the FPGA chip. S2.2. Functional Simulation Use an oscilloscope to connect to the pins assigned to the microcontroller during the configuration and operation processes to verify whether the required excitation signal and output signal are normal. If they are normal, proceed to the next step; otherwise, return to step S2.1. S2.3. Download the microcontroller 4.5 circuit function Use a programmer to download the functions of the microcontroller 4.5 circuit; S3. Connect the aging test plate to other equipment; Place the FPGA chip to be aged in the test station 4.2, select a power supply 3 that is compatible with the FPGA chip to be aged, connect the aging test board 4 to the power supply 3 and the computer 1 respectively, and place the aging test board 4 in the high temperature chamber 2. S4. Initiate the aging test; S4.1. Start the configuration process using a software serial port debugging assistant. Place the FPGA chip in test station 4.2, and control the FPGA chip in test station 4.2 to complete the configuration with the corresponding Flash chip 4.3; Enter the command in the serial port debugging assistant. This command, through communication module 4.4, controls the microcontroller 4.5 to send signals to the configuration pins prog and init of the FPGA chip. After waiting for 20 seconds, the configuration process ends, and the serial port debugging assistant receives the configuration result. If the configuration is successful, the result is displayed as 1; if the configuration fails, the result is displayed as 0. You need to check whether the software settings and hardware connections are correct, and repeat the above steps until the configuration is successful. The serial port debugging assistant displays the configuration results of all stations on the aging test board. Based on the displayed results, specifically troubleshoot the abnormal stations. Repeat the above process until all FPGA chips in test stations 4.2 and their corresponding Flash chips 4.3 are configured. S4.2. Start the formal working process using a software serial port debugging assistant. After successful configuration, input the command into the serial port debugging assistant. This command controls the microcontroller 4.5 via computer 1 to send excitation signals to the clock port and input port defined by the FPGA, and collects signals at the output port of the microcontroller 4.5. By comparing the signals, it is determined whether the designed FPGA circuit function has been implemented. The serial port debugging assistant receives the implementation result of the circuit function. If the implementation is successful, the result is displayed as 1; if the implementation fails, the result is displayed as 0. It is necessary to check whether the software settings and hardware connections are correct, and repeat the above steps until the implementation is successful. The serial port debugging assistant displays the implementation results of all test stations 4.2 on the aging test board 4. Based on the displayed results, troubleshoot the abnormal stations. S4.3 Verify FPGA aging function Connect an oscilloscope to the clock port, input pin, and output pin of the FPGA chip respectively, observe the trend of waveform changes, and verify whether the FPGA aging function of the design meets expectations; if it meets expectations, proceed to the next step; otherwise, return to step S4.1. S4.4 Monitoring the FPGA aging process After the FPGA aging test starts normally, input the working command through the software serial port debugging assistant every 1-3 hours. After receiving the result display, determine whether the current aging test is normal. If an abnormality occurs, stop the aging test and troubleshoot the fault point. S4.5. Monitor the power supply voltage of aging test board 4. The power supply voltage of the aging test board 4 is monitored in real time by a single-chip microcomputer 4.5. If the voltage exceeds the threshold, the power supply line is cut off.

[0026] Example 1 The FPGA chip to be aged is model XC6SLX45-2CSG324I. S1. Design and download the FPGA circuit functionality; S1.1. Designing circuit functions using ISE software Using Verilog, the hardware description language in the software ISE, and calling D flip-flops and RAM memory cells, design the circuit function to complete the aging test. S1.2 Define FPGA pins Use the ISE software to define the pins for the clock port, input port, and output port; S1.3. Software Simulation Simulation was performed using the ISE software, and the designed circuit functioned correctly. S1.4. Download Circuit Function Use the SPI configuration method to generate configuration files, and download the configuration files to each Flash chip 4.3 of the old refinement test board 4; S2. Design and download the microcontroller circuit functions; S2.1. Design the circuit function of a microcontroller 4.5 using the MDK software. S2.1.1. Configuration Process The microcontroller 4.5 sends signals to the configuration pins prog and init of the FPGA chip, acquires the signal of the configuration pin done of the FPGA chip, compares the level of the done pin, and displays a high level, indicating that the configuration is complete. S2.1.2. Formal Work Process The microcontroller 4.5 sends signals to the clock port and input pins of the FPGA chip and acquires the signals from the output pins of the FPGA chip. S2.2. Functional Simulation Using an oscilloscope, the pins assigned to the microcontroller during configuration and operation were connected to the microcontroller. It was verified that the applied excitation signal and the output signal were normal. S2.3. Download the microcontroller 4.5 circuit function Use a programmer to download the functions of the microcontroller 4.5 circuit; S3. Connect the aging test plate to other equipment; Place the FPGA chip to be aged in the test station 4.2, select a power supply 3 that is compatible with the FPGA chip to be aged. There are two power supplies with voltages set to 3.3V and 1.2V respectively. Connect the aging test board 4 to the power supply 3 and the computer 1 respectively, and place the aging test board 4 in the high temperature chamber 2. S4. Initiate the aging test; S4.1. Start the configuration process using a software serial port debugging assistant. Place the FPGA chip in test station 4.2, and control the FPGA chip in test station 4.2 to complete the configuration with the corresponding Flash chip 4.3; Enter the command in the serial port debugging assistant. This command, through communication module 4.4, controls the microcontroller 4.5 to send signals to the configuration pins prog and init of the FPGA chip. After waiting for 20 seconds, the configuration process ends, and the serial port debugging assistant receives the configuration result. If the configuration is successful, the result is displayed as 1; if the configuration fails, the result is displayed as 0. You need to check whether the software settings and hardware connections are correct, and repeat the above steps until the configuration is successful. The serial port debugging assistant displays the configuration results of all stations on the aging test board. Based on the displayed results, specifically troubleshoot the abnormal stations. Repeat the above process until all FPGA chips in test stations 4.2 and their corresponding Flash chips 4.3 are configured. S4.2. Start the formal working process using a software serial port debugging assistant. After successful configuration, input the command into the serial port debugging assistant. This command controls the microcontroller 4.5 via computer 1 to send excitation signals to the clock port and input port defined by the FPGA, and collects signals at the output port of the microcontroller 4.5. By comparing the signals, it is determined whether the designed FPGA circuit function has been implemented. The serial port debugging assistant receives the implementation result of the circuit function. If the implementation is successful, the result is displayed as 1; if the implementation fails, the result is displayed as 0. It is necessary to check whether the software settings and hardware connections are correct, and repeat the above steps until the implementation is successful. The serial port debugging assistant displays the implementation results of all test stations 4.2 on the aging test board 4. Based on the displayed results, troubleshoot the abnormal stations. S4.3 Verify FPGA aging function Using an oscilloscope, connect the clock port, input pin, and output pin of the FPGA chip respectively to observe the waveform trend and verify whether the FPGA aging function meets expectations. The verification shows that the signals of the clock port, input pin, and output pin of the FPGA chip are all normal. S4.4 Monitoring the FPGA aging process After the FPGA aging test starts normally, every 2 hours, input the working command through the software serial port debugging assistant, and judge the current aging test to be normal based on the received result; S4.5. Monitor the power supply voltage of aging test board 4. The power supply voltage of the aging test board 4 was monitored in real time by a single-chip microcomputer 4.5, and none of the voltage exceeded the voltage threshold.

[0027] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A method for curing SRAM-type FPGAs, applied to a dynamic curing device for SRAM-type FPGAs, the device comprising a computer (1), a high-temperature chamber (2), a power supply (3), and a curing test board (4), characterized in that: The aging test board (4) includes a base plate (4.1), test stations (4.2), FLASH chips (4.3), communication modules (4.4), microcontrollers (4.5), and peripheral configuration circuits (4.6). The base plate (4.1) is a printed circuit board. There are more than three test stations (4.2). The FLASH chips (4.3) correspond one-to-one with the test stations (4.2). The peripheral configuration circuits (4.6) correspond one-to-one with the FLASH chips (4.3). The excitation signal output terminal of the microcontroller (4.5) is connected to the excitation signal input terminal of the test station (4.2). The signal output terminal of the test station (4.2) is connected to the signal acquisition terminal of the microcontroller (4.5). The output terminal of the power supply (3) is connected to the power input terminal of the aging test board (4). The aging test board (4) is placed in a high-temperature chamber (2). The aging test board (4) communicates with the computer (1) through the communication module (4.4). Includes the following steps: S1. Design and download the FPGA circuit function; S1.

1. Design the circuit function using the ISE software. Using Verilog, the hardware description language in the software ISE, and calling D flip-flops and RAM memory cells, design the circuit function to complete the aging test. S1.2 Define FPGA pins Use the ISE software to define the pins for the clock port, input port, and output port; S1.

3. Software Simulation Use the software ISE to perform simulation and verify whether the designed circuit functions normally. If it does, proceed to the next step; otherwise, return to step S1.

1. S1.

4. Download Circuit Function The configuration file is generated using the SPI configuration method and downloaded to each Flash chip (4.3) of the old refinement test board (4). S2. Design and download the microcontroller circuit functions; S2.

1. Design the circuit function of the microcontroller (4.5) using the MDK software. S2.1.

1. Configuration Process The microcontroller (4.5) sends signals to the configuration pins prog and init of the FPGA chip, collects the signal of the configuration pin done of the FPGA chip, and compares the level of the pin done. If it is high, the configuration is complete; otherwise, the configuration is reconfigured. S2.1.

2. Formal Work Process The microcontroller (4.5) sends signals to the clock and input pins of the FPGA chip and collects the signals from the output pins of the FPGA chip. S2.

2. Functional Simulation Use an oscilloscope to connect to the pins assigned to the microcontroller during the configuration and operation processes to verify whether the required excitation signal and output signal are normal. If they are normal, proceed to the next step; otherwise, return to step S2.

1. S2.

3. Downloading the microcontroller (4.5) circuit function Use a programmer to complete the download of the microcontroller (4.5) circuit function; S3. Connect the aging test board to other devices; Place the FPGA chip to be aged in the test station (4.2), select a power supply (3) that is compatible with the FPGA chip to be aged, connect the aging test board (4) to the power supply (3) and the computer (1) respectively, and place the aging test board (4) in the high temperature chamber (2). S4. Initiate the aging test; S4.

1. Start the configuration process using a software serial port debugging assistant. Place the FPGA chip in the test station (4.2), and control the FPGA chip in the test station (4.2) to complete the configuration with the corresponding Flash chip (4.3); Input the command in the serial port debugging assistant. This command, through the communication module (4.4), controls the microcontroller (4.5) to send signals to the configuration pins prog and init of the FPGA chip. Wait 20 seconds for the configuration process to end, and the serial port debugging assistant will receive the configuration result. If the configuration is successful, the result will be displayed as 1. If the configuration fails, the result will be displayed as 0. Check whether the software settings and hardware connections are correct and repeat the operation until the configuration is successful. The serial port debugging assistant displays the configuration results of all stations on the old tempering test board. Based on the displayed results, check the abnormal stations. Repeat the configuration process until the FPGA chips and corresponding Flash chips (4.3) in all test stations (4.2) are configured. S4.

2. Start the formal working process using a software serial port debugging assistant. After successful configuration, input the command in the serial port debugging assistant. The command controls the microcontroller (4.5) through the computer (1) to send excitation signals to the clock pin and input port defined by the FPGA, and collects the signal at the output port of the microcontroller (4.5). By comparing the signals, it is determined whether the FPGA circuit function is implemented. The serial port debugging assistant receives the implementation result of the circuit function. If the implementation is successful, the result is displayed as 1. If the implementation fails, the result is displayed as 0. It is necessary to check whether the software settings and hardware connections are correct and repeat until the implementation is successful. In the serial port debugging assistant, the implementation results of all test stations (4.2) on the old test board (4) are displayed. The abnormal stations are specifically investigated according to the displayed results. S4.3 Verify FPGA aging function Connect an oscilloscope to the clock pin, input pin, and output pin of the FPGA chip respectively, observe the trend of the waveform changes, and verify whether the FPGA aging function of the design meets expectations; if it meets expectations, proceed to the next step; otherwise, return to step S4.

1. S4.4 Monitoring the FPGA aging process After the FPGA aging test starts normally, input the working command through the software serial port debugging assistant every 1-3 hours. After receiving the result display, determine whether the current aging test is normal. If an abnormality occurs, stop the aging test and troubleshoot the fault point. S4.

5. Monitor the power supply voltage of the aging test board (4). The power supply voltage of the aging test board (4) is monitored in real time by a microcontroller (4.5). If the voltage exceeds the threshold, the power supply line is cut off.

2. The method for aging an SRAM-type FPGA according to claim 1, characterized in that: The number of test stations (4.2) is 10.

3. A method for aging an SRAM-type FPGA according to claim 1 or 2, characterized in that: The aging test board (4) is connected to the computer (1) via a communication module (4.4) and a 485 communication conversion cable.

4. A method for aging an SRAM-type FPGA according to claim 1 or 2, characterized in that: The output terminal of the power supply (3) is connected to the power input terminal of the aging test board (4) through the relay (5), and the control signal input terminal of the relay (5) is connected to the voltage control signal output terminal of the microcontroller (4.5).

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