Circuit path simplification method and system

Abstract

The present invention provides a circuit path simplification method and system. An initial path sequence obtaining step obtains a plurality of initial path sequences. Each initial path sequence includes a plurality of element tags and a plurality of line tags, and the element tags and the line tags are alternately arranged with each other. A line tag searching step searches for identical line tags to generate line tag confirmation results. An element tag comparing step compares whether two element tags arranged in adjacent columns of the identical line tags are identical according to the line tag confirmation results. When the two element tags are identical, a merging step is performed to generate a merged element tag and a merged line tag. When the two element tags are not identical, an arrangement step is performed to generate an arranged element tag and the merged line tag. In this way, the plurality of initial path sequences are simplified into simplified path sequences.

Description

Technical Field

[0001] This invention relates to an electronic data processing technology, and more particularly to a circuit path simplification method and system thereof. Background Technology

[0002] As circuit complexity increases, determining whether two electronic components are connected, or judging the bias voltage or current flowing through a component, becomes inconvenient in circuit diagrams. This process is not only time-consuming but also prone to human error. Using computer software to assist in this process requires converting the circuit diagram into text data for computer processing. While commercial computer software has data conversion formats and internal processing procedures, these are usually trade secrets and cannot be publicly disclosed. Academic circuit representations, such as Simulation Program with Integrated Circuit Emphasis (SPICE), can show the connections between electronic components in a circuit diagram, but these connections are less intuitive and cannot be quickly identified during the search process.

[0003] When the circuit between two electronic components is located, multiple paths are usually found. These paths may also appear on paths between other electronic components. Such parallel circuit relationships can be used to determine voltage / current division or signal shunting on components. However, currently, a significant amount of time still needs to be spent manually locating parallel relationships within the circuit diagram. This manual search becomes difficult when the circuit is complex and contains a large number of electronic components.

[0004] In view of this, developing a method and system that can display whether there is a parallel relationship between circuits and simplify multiple paths is a goal and direction that must be vigorously researched and developed. Summary of the Invention

[0005] Therefore, the purpose of this invention is to provide a circuit path simplification method and system, which uses an initial path sequence formed by component labels and line labels to simply present the connection relationship of the circuit path, and then merges the line labels and arranges the component labels based on the same line labels in multiple initial path sequences, thereby simplifying multiple initial path sequences into a simplified path sequence.

[0006] According to an embodiment of the present invention, a circuit path simplification method is provided to simplify multiple initial path sequences corresponding to a circuit diagram, wherein the circuit diagram includes multiple electronic components and multiple lines. The circuit path simplification method includes an initial path sequence acquisition step, a line label lookup step, and a component label comparison step. The initial path sequence acquisition step drives a processing unit to acquire the multiple initial path sequences corresponding to the circuit diagram from a storage unit. Each initial path sequence includes multiple component labels corresponding to a portion of the multiple electronic components and multiple line labels corresponding to a portion of the multiple lines, and the multiple component labels and multiple line labels are arranged alternately. The line label lookup step drives the processing unit to search for a common line label in the multiple initial path sequences to generate a line label confirmation result. The component label comparison step drives the processing unit to compare whether two adjacent component labels listed under a line label in two initial path sequences are the same, based on the line label confirmation result, to simplify the multiple initial path sequences. When two component labels are the same, the processing unit performs a merging step. The merging step merges the two element labels of two initial path sequences to generate a merged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The merged element label and the merged line label are arranged to form a simplified path sequence. When the two element labels are different, the driving operation processing unit performs an arrangement step. The arrangement step arranges the two element labels of two initial path sequences to generate an arranged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The arranged element label and the merged line label are arranged to form another simplified path sequence.

[0007] According to another embodiment of the present invention, a circuit path simplification system is provided for simplifying multiple initial path sequences corresponding to a circuit diagram, wherein the circuit diagram includes multiple electronic components and multiple circuits. The circuit path simplification system includes a storage unit and a processing unit. The storage unit stores the multiple initial path sequences corresponding to the circuit diagram. Each initial path sequence includes multiple component labels corresponding to a portion of the multiple electronic components and multiple line labels corresponding to a portion of the multiple circuits, and the multiple component labels and multiple line labels are arranged alternately. The processing unit is connected to the storage unit and obtains the multiple initial path sequences, and the processing unit is configured to perform a line label lookup step and a component label comparison step. The line label lookup step searches for a common line label in the multiple initial path sequences to generate a line label confirmation result. The component label comparison step compares two adjacent component labels listed under a line label in two initial path sequences based on the line label confirmation result to simplify the multiple initial path sequences. When two component labels are the same, the processing unit performs a merging step. The merging step merges the two element labels of two initial path sequences to generate a merged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The merged element label and the merged line label are arranged to form a simplified path sequence. When the two element labels are different, the processing unit performs an arrangement step. The arrangement step arranges the two element labels of two initial path sequences to generate an arranged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The arranged element label and the merged line label are arranged to form another simplified path sequence.

[0008] Therefore, the circuit path simplification method and system of the present invention finds the same line label in all initial path sequences, then merges the same component labels to generate merged component labels, or arranges different component labels to generate arranged component labels, and merges the same line labels to generate merged line labels, thereby simplifying multiple initial path sequences into simplified path sequences. Attached Figure Description

[0009] Figure 1 This is a schematic flowchart illustrating a circuit path simplification method according to a first embodiment of the present invention;

[0010] Figure 2 This is a schematic diagram illustrating the application of the circuit path simplification method of the present invention to multiple initial path sequences;

[0011] Figure 3 This is another schematic diagram illustrating the application of the circuit path simplification method of the present invention to multiple initial path sequences;

[0012] Figure 4 This is yet another schematic diagram illustrating the application of the circuit path simplification method of the present invention to multiple initial path sequences; and

[0013] Figure 5 This is a schematic diagram illustrating a circuit path simplification system according to a second embodiment of the present invention.

[0014] [List of Labels in the Attached Image]

[0015] 100: Circuit Path Simplification Method

[0016] 110: Line tag confirmation result

[0017] 200: Circuit Path Simplification System

[0018] 210: Storage unit

[0019] 220: Processing Unit

[0020] 211: Circuit Diagram

[0021] 212,I1,I2,I3,I4,I5,I6,I7,I8,I9,I 10 ,I 11 Initial path sequence

[0022] E1, E2, E3, E4, E5, E6, E7: Component Labels

[0023] P1, P2, P3: Line Labels

[0024] M E1 M E2 M E3 M E4 M E5 M E6 : Merged component labels

[0025] M P1 M P2 M P3 M P4 Merged line labels

[0026] A E1 A E2 A E3 A E4 A E5 : Arranged component labels

[0027] Q1: First symbol

[0028] Q2: Second symbol

[0029] S1, S2, S3: Simplified path sequence

[0030] C1, C2, C3: Simplified circuit diagram

[0031] S02: Steps for obtaining the initial path sequence

[0032] S04, S12: Procedures for finding line tags

[0033] S06, S14: Component Label Comparison Steps

[0034] S062, S142: Merging Steps

[0035] S064, S144: Arrangement steps Detailed Implementation

[0036] Please refer to the above as well. Figure 1 and Figure 2 ,in Figure 1 This is a schematic flowchart illustrating a circuit path simplification method 100 according to a first embodiment of the present invention; and Figure 2 This is a schematic diagram illustrating the application of the circuit path simplification method 100 of the present invention to multiple initial path sequences I1, I2, I3, I4, and I5. As shown in the figure, the circuit path simplification method 100 includes an initial path sequence acquisition step S02, a line label search step S04, and a component label comparison step S06, and is used to simplify the initial path sequences I1, I2, I3, I4, and I5 of the corresponding circuit diagram into a simplified path sequence S1.

[0037] In step S02, the initial path sequence acquisition step drives the arithmetic processing unit to retrieve the initial path sequence I1, I2, I3, I4, I5 corresponding to the circuit diagram from the storage unit. The circuit diagram contains multiple electronic components and multiple lines. The initial path sequence I1, I2, I3, I4, I5 includes multiple component labels E1, E2, E3, E4, E5, E6, E7 corresponding to the aforementioned electronic components and multiple line labels P1, P2, P3 corresponding to the aforementioned lines. Specifically, Figure 2The initial path sequence I1 contains component labels E1, E2, E3 and line labels P1, P2, P3, which are arranged alternately from front to back (i.e., from left to right). Adjacent component labels E1 and line labels P1 represent the electrical connection between the electronic component corresponding to component label E1 and the line corresponding to line label P1, and other initial path sequences follow the same pattern. Furthermore, the aforementioned circuit diagram can be drawn using drawing software (Allegro) and converted into an XML data file, which can contain all electronic component data and the line data connecting each pair of electronic components. All combinations of electronic components and lines in the circuit diagram are identified manually or by software, and the electronic component and line data in the XML data file are rearranged to generate data based on JavaScript Object Notation (JSON) format (i.e., the initial path sequences I1, I2, I3, I4, I5).

[0038] The route label search step S04 drives the processing unit to search for identical route labels in all initial path sequences I1, I2, I3, I4, and I5, generating at least one route label confirmation result 110. Figure 2 It can be seen that since the initial path sequences I1, I2, I3, I4, and I5 all have the same line labels P1, P2, and P3, the processing unit generates multiple line label confirmation results 110 corresponding to line labels P1, P2, and P3.

[0039] In the component label comparison step S06, the processing unit compares the two component labels E1 adjacent to line label P1 in the two initial path sequences I1 and I2 based on the line label confirmation result 110 of the corresponding line label P1. It should be noted that the processing unit includes all initial path sequences with line label P1 in the comparison process; in other words, the processing unit can also periodically compare the multiple component labels E1, E2, E3, E4, E5, E6, and E7 adjacent to line labels P1, P2, and P3 in all initial path sequences I1, I2, I3, I4, and I5 based on the line label confirmation result 110. When the two component labels are the same, the processing unit executes the merging step S062. The merging step S062 merges the two component labels of the two initial path sequences to generate a merged component label, and merges the line labels of the two initial path sequences to generate a merged line label. When the two component labels are different, the processing unit executes the arrangement step S064. In step S064, the two element labels of the two initial path sequences are arranged to generate arranged element labels, and the line labels of the two initial path sequences are merged to generate merged line labels.

[0040] For example, in all initial path sequences I1, I2, I3, I4, and I5, multiple element labels E1 preceding line label P1 are identical. The processing unit executes merging step S062. Merging step S062 drives the processing unit to merge the multiple element labels E1 preceding line label P1 to generate the merged element label M. E1 Furthermore, the line labels P1 of all initial path sequences I1, I2, I3, I4, and I5 are merged to generate the merged line label M. P1 The processing unit will merge the component label M. E1 Listed under the merged line label M P1 Previously, similarly, in all initial path sequences I1, I2, I3, I4, and I5, the multiple component labels E2 located after line label P1 are identical, and the processing unit also executes the merging step S062. Merging step S062 drives the processing unit to merge the multiple component labels E2 located after line label P1 to generate the merged component label M. E2 The processing unit will merge the component label M. E2 Listed under the merged line label M P1 after.

[0041] If, taking line label P2 as the center, multiple component labels E2 preceding line label P2 are identical in all initial path sequences I1, I2, I3, I4, and I5, the processing unit generates a merged component label M. E2 Furthermore, the line labels P2 of all initial path sequences I1, I2, I3, I4, and I5 are merged to generate the merged line label M. P2 The processing unit will merge the component label M. E2 Listed under the merged line label M P2 Before.

[0042] Specifically, among all the initial path sequences I1, I2, I3, I4, I5, the component labels E3, E4, E5, E6, and E7 located after line label P2 are different from each other. The processing unit executes the arrangement step S064. Arrangement step S064 drives the processing unit to arrange the component labels E3, E4, E5, E6, and E7 in sequence to generate the arranged component label A. E1 The processing unit will arrange the component label A. E1 Listed under the merged line label M P2 after.

[0043] If, taking line label P3 as the center, the component labels E3, E4, E5, E6, and E7 preceding line label P3 in all initial path sequences I1, I2, I3, I4, and I5 are all different, the processing unit executes arrangement step S064. Arrangement step S064 drives the processing unit to sequentially arrange component labels E3, E4, E5, E6, and E7 to generate the arranged component label A. E1 The line labels P3 of all initial path sequences I1, I2, I3, I4, and I5 are merged to generate the merged line label M. P3 The processing unit will arrange the component label A. E1 Listed under the merged line label M P3 Previously. Finally, the processing units are arranged in sequence and merged, with the component label M... E1 Merged line label M P1 Merged component label M E2 Merged line label M P2 After arrangement, component label A E1 and the merged line label M P3 This results in a simplified path sequence S1.

[0044] Furthermore, the processing unit merges the line label M. P1 A first symbol Q1 is introduced. The first symbol Q1 is located before line label P1. The first symbol Q1 indicates a series connection, that is, the electronic component corresponding to line label P1 is connected to the electronic component corresponding to line label E1, and simultaneously indicates that the electronic component corresponding to component label E1 is connected via the electronic component corresponding to line label P1 and line label E2. The processing unit then processes the merged line label M... P2 A second symbol Q2 is introduced. The second symbol Q2 is located before line label P2. The second symbol Q2 indicates parallel connection, meaning the electronic components corresponding to the parallel element labels E3, E4, E5, E6, and E7 corresponding to line label P2. It also indicates that the electronic component corresponding to element label E2 is connected via the electronic components corresponding to the parallel element labels E3, E4, E5, E6, and E7 corresponding to line label P2, and the combined line label M... P3 And so on.

[0045] It is worth noting that the data of the merged component labels is equivalent to the data of the pre-merger component labels; this means that the merged component label M E1 The corresponding JSON data is equivalent to the JSON data corresponding to component label E1, and other merged component labels follow the same principle, without further explanation. Therefore, the processing unit can convert the simplified path sequence S1 of the corresponding circuit diagram into the simplified circuit diagram C1. Figure 2As shown in the simplified circuit diagram C1, the electronic component corresponding to component label E1 and the electronic component corresponding to component label E2 are connected in series with each other via the line corresponding to line label P1. The electronic component corresponding to component label E2 and the electronic components corresponding to each of component labels E3, E4, E5, E6, and E7 are connected in parallel with each other via the line corresponding to line label P2. All component labels E3, E4, E5, E6, and E7 are connected in parallel to the line corresponding to line label P3. Therefore, the circuit path simplification method 100 of the present invention can find the same line labels P1, P2, and P3 in all initial path sequences I1, I2, I3, I4, and I5, and then generate merged component labels M based on merging the same component labels E1 and E2. E1 M E2 Alternatively, different component labels E3, E4, E5, E6, and E7 can be arranged to produce the arranged component label A. E1 Furthermore, identical line labels P1, P2, and P3 are merged to generate merged line label M. P1 M P2 M P3 This simplifies all initial path sequences I1, I2, I3, I4, and I5 into a simplified path sequence S1, making it easier for users to understand the connection relationships between components and lines in the simplified circuit diagram C1. Therefore, even when the circuit in the diagram is complex, users can still easily view and determine the voltage dividers / current dividers or signal dividers on the electronic components using the simplified path sequence S1.

[0046] Please refer to the above as well. Figure 1 and Figure 3 ,in Figure 3 This is another schematic diagram illustrating the application of the circuit path simplification method 100 of the present invention to multiple initial path sequences I6, I7. As shown, the line tag search step S04 drives the arithmetic processing unit to search for the same line tag in the two initial path sequences I6, I7 corresponding to another circuit diagram, thereby generating a line tag confirmation result 110. Figure 3 As can be seen, since the initial path sequences I6 and I7 both contain the same line labels P1 and P2, the processing unit generates line label confirmation results 110 for the corresponding line labels P1 and P2, respectively. The following only details the line label confirmation result 110 for the corresponding line label P1; other line label confirmation results 110 will not be elaborated upon.

[0047] In the component label comparison step S06, the processing unit compares the two component labels E1, which are adjacent to each other before line label P1 in the two initial path sequences I6 and I7, based on the line label confirmation result 110 of the corresponding line label P1. It also compares the two component labels E2 and E3, which are adjacent to each other after line label P1 in the two initial path sequences I6 and I7. Since the two component labels E1 before line label P1 in the two initial path sequences I6 and I7 are identical, the processing unit executes the merging step S062. The merging step S062 drives the processing unit to merge the two component labels E1 before line label P1 to generate the merged component label M. E1 Furthermore, the line labels P1 of the initial path sequences I6 and I7 are merged to generate the merged line label M. P4 The processing unit will merge the component label M. E1 Listed under the merged line label M P4 Previously, in the initial path sequences I6 and I7, the component labels E2 and E3 located after line label P1 were different. The processing unit executed arrangement step S064. Arrangement step S064 drove the processing unit to sequentially arrange component label E2 and line label P2 to generate the arranged component label A. E2 The component label E3, circuit label P3, component label E4, and circuit label P2 are arranged in sequence to generate the arranged component label A. E3 The processing unit will arrange the component label A. E2 Listed under the merged line label M P4 Then, arrange the component label A. E3 Listed in the arranged component label A E2 Then, the simplified path sequence S2 is formed.

[0048] In addition, the processing unit merges the line label M P4 A second symbol Q2 is introduced. This second symbol Q2 precedes line label P1. Q2 indicates parallel connection, meaning the electronic component corresponding to component label E1 is connected in parallel with the electronic components corresponding to component labels E2 and E3 via the line corresponding to line label P1. The processing unit introduces a first symbol Q1 before line label P3, indicating series connection, meaning the electronic component corresponding to component label E3 is connected in series with the electronic component corresponding to component label E4 via the line corresponding to line label P3. Therefore, the processing unit can convert the simplified path sequence S2 corresponding to another circuit diagram into a simplified circuit diagram C2. Figure 3As shown in the simplified circuit diagram C2, the electronic component corresponding to component label E1 is connected in parallel to the electronic components corresponding to component labels E2 and E3 after the line corresponding to line label P1. The electronic component corresponding to component label E3 is connected in series to the electronic component corresponding to component label E4 after the line corresponding to line label P3, and the electronic components corresponding to component labels E2 and E4 are connected in series to the line corresponding to line label P2.

[0049] Please refer to the above as well. Figure 1 and Figure 4 ,in Figure 4 This illustrates the application of the circuit path simplification method 100 of the present invention to multiple initial path sequences I8, I9, I... 10 I 11 Another schematic diagram. As shown in the figure, the line label search step S04 drives the arithmetic processing unit to the initial path sequence I8, I9, I... of the corresponding circuit diagram. 10 I 11 The system searches for matching line tags and generates a line tag confirmation result 110. Figure 4 It can be seen that, due to the initial path sequence I8, I9, I 10 I 11 All lines have the same line labels P1, P2, and P3. Therefore, the processing unit generates line label confirmation results 110 for the corresponding line labels P1, P2, and P3 respectively. The following only describes the line label confirmation results 110 for the corresponding line labels P1 and P2 in detail; the line label confirmation result 110 for the corresponding line label P3 will not be described in detail.

[0050] If we take line label P1 as the center, the component label comparison step S06 drives the calculation and processing unit to compare the initial path sequence I8, I9, I10 based on the line label confirmation result 110 of the corresponding line label P1. 10 I 11 Check if the four element labels E1 preceding line label P1 are the same, and compare the two element labels E2 and two element labels E3 following line label P1 to see if they are the same. In the initial path sequence I8, I9, I... 10 I 11 The four element labels E1 located before line label P1 are all identical. The processing unit executes the merging step S062. Merging step S062 drives the processing unit to merge the four element labels E1 located before line label P1 to generate the merged element label M. E1 Furthermore, the processing unit merges the initial path sequences I8, I9, and I... 10 I 11 The merged line label M is generated from the line label P1. P4 The processing unit is located in the merged line label M. P4The second symbol Q2 is introduced, and the merged line label M is added. P4 Listed under the merged component label M E1 after.

[0051] In the initial path sequence I8, I9, I 10 I 11 The two element tags E2 and E3 located after line tag P1 are identical. The processing unit executes the merging step S062. Merging step S062 drives the processing unit to merge the two element tags E2 to generate the merged element tag M. E2 Furthermore, the merged component label E3 generates the merged component label M. E3 Next, due to the merged component label M E2 With the merged component label M E3 Since they are different, the processing unit executes arrangement step S064. Arrangement step S064 drives the processing unit to arrange and merge the component labels M. E2 With the merged component label M E3 And the generated element label A after arrangement E4 .

[0052] If we take line label P2 as the center, the component label comparison step S06 drives the calculation and processing unit to compare the initial path sequence I8, I9, I20 based on the line label confirmation result 110 of the corresponding line label P2. 10 I 11 The system checks whether the two element labels E2 and E3, which are adjacent to each other before line label P2, are identical, and also checks whether the two element labels E4 and E5, which are adjacent to each other after line label P2, are identical. The simplified process for element labels E2 and E3 is as described above, so it will not be repeated here.

[0053] In the initial path sequence I8, I9, I 10 I 11 The two element tags E4 and E5 located after line tag P2 are identical. The processing unit executes the merging step S062. Merging step S062 drives the processing unit to merge the two element tags E4 to generate the merged element tag M. E4 Furthermore, the merged component label E5 generates the merged component label M. E5 The processing unit merges the initial path sequences I8, I9, and I... 10 I 11 The merged line label M is generated from the line label P2. P2 The processing unit is located in the merged line label M. P2 A second symbol Q2 is introduced. Then, due to the merged component label M... E4 With the merged component label ME5 Since they are different, the processing unit executes arrangement step S064. Arrangement step S064 drives the processing unit to arrange and merge the component labels M. E4 With the merged component label M E5 And the generated element label A after arrangement E5 The processing unit will merge the line tag M P2 Listed in the arranged component label A E4 A E5 Between. Finally, the processing units are arranged in sequence and merged, with the component label M. E1 Merged line label M P4 After arrangement, component label A E4 Merged line label M P2 After arrangement, component label A E5 Merged line label M P3 and the merged component label M E6 This results in the simplified path sequence S3.

[0054] Therefore, the processing unit can convert the simplified path sequence S3 corresponding to another circuit diagram into a simplified circuit diagram C3. Figure 4 As shown in the simplified circuit diagram C3, the electronic component corresponding to component label E1 is connected in parallel to the electronic components corresponding to component labels E2 and E3 after the line corresponding to line label P1. The electronic components corresponding to component labels E2 and E3 are connected in parallel to the electronic components corresponding to component labels E4 and E5 via the line corresponding to line label P2. The electronic components corresponding to component labels E4 and E5 are connected in parallel to the line corresponding to line label P2, and are connected in series to the electronic component corresponding to component label E6 via the line corresponding to line label P3.

[0055] Please refer to the following: Figure 1 and Figure 5 ,in Figure 5This is a schematic diagram illustrating a circuit path simplification system 200 according to a second embodiment of the present invention. As shown, the circuit path simplification system 200 is used to simplify a plurality of initial path sequences 212 corresponding to a circuit diagram 211, and includes a storage unit 210 and a processing unit 220. The storage unit 210 stores the circuit diagram 211 and the plurality of initial path sequences 212 corresponding to the circuit diagram 211. The processing unit 220 is electrically connected to the storage unit 210 and obtains the plurality of initial path sequences 212. The processing unit 220 is configured to implement the line tag lookup step S12, the component tag comparison step S14, the merging step S142, and the arrangement step S144, which are the same as the steps corresponding to the circuit path simplification method 100 in the first embodiment, and will not be described again. In addition, the processing unit 220 may be a digital signal processor (DSP), a microprocessor (MPU), a central processing unit (CPU), or other electronic processor, but the present invention is not limited thereto.

[0056] Although the present invention has been disclosed above with reference to embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A circuit path simplification method for simplifying multiple initial path sequences corresponding to a circuit diagram, the circuit diagram comprising multiple electronic components and multiple circuits, characterized in that, This circuit path simplification method includes the following steps: An initial path sequence acquisition step drives a processing unit to acquire the plurality of initial path sequences corresponding to the circuit diagram from a storage unit, wherein each initial path sequence includes a plurality of component labels corresponding to a portion of the plurality of electronic components and a plurality of line labels corresponding to a portion of the plurality of lines, and the plurality of component labels and the plurality of line labels are arranged alternately with each other. A route label lookup step drives the processing unit to search for one of the same route labels in the plurality of initial path sequences to generate a route label confirmation result; and A component label comparison step drives the processing unit to compare whether two component labels listed adjacent to one of the line labels in the two initial path sequences are the same based on the line label confirmation result, so as to simplify the multiple initial path sequences; When the two element labels are the same, the processing unit is driven to perform a merging step. The merging step merges the two element labels of the two initial path sequences to generate a merged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The merged element label and the merged line label are arranged to form a simplified path sequence. When the two element labels are different, the processing unit is driven to perform an arrangement step. The arrangement step arranges the two element labels of the two initial path sequences to generate an arranged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The arranged element label and the merged line label are arranged to form another simplified path sequence.

2. The circuit path simplification method as described in claim 1, characterized in that, An adjacent element label and a circuit label indicate that the electronic component corresponding to the element label is electrically connected to the circuit corresponding to the circuit label.

3. The circuit path simplification method as described in claim 1, characterized in that, In the component label comparison step, When two element labels preceding one of the line labels in the two initial path sequences are the same, the merging step drives the arithmetic processing unit to merge the two element labels preceding one of the line labels. and When two element labels following one of the line labels in the two initial path sequences are the same, the merging step drives the arithmetic processing unit to merge the two element labels following one of the line labels.

4. The circuit path simplification method as described in claim 1, characterized in that, In the component label comparison step, When two element labels preceding one of the line labels in the two initial path sequences are the same, the merging step drives the arithmetic processing unit to merge the two element labels preceding one of the line labels. and When the two element labels following one of the line labels in the two initial path sequences are different, the arrangement step drives the operation processing unit to arrange the two element labels following one of the line labels.

5. The circuit path simplification method as described in claim 1, characterized in that, In the component label comparison step, When the two element labels preceding one of the line labels in the two initial path sequences are different, the arrangement step drives the operation processing unit to arrange the two element labels preceding one of the line labels; and When two element labels following one of the line labels in the two initial path sequences are the same, the merging step drives the arithmetic processing unit to merge the two element labels following one of the line labels.

6. The circuit path simplification method as described in claim 1, characterized in that, In the component label comparison step, When the two element labels preceding one of the line labels in the two initial path sequences are different, the arrangement step drives the operation processing unit to arrange the two element labels preceding one of the line labels; and When the two element labels following one of the line labels in the two initial path sequences are different, the arrangement step drives the operation processing unit to arrange the two element labels following one of the line labels.

7. The circuit path simplification method as described in claim 1, characterized in that, The processing unit introduces one of a first symbol and a second symbol into the merged line label. The first symbol and the second symbol are located before one of the line labels. The first symbol indicates that an electronic component corresponding to a component label listed before one of the line labels is connected in series with an electronic component corresponding to another component label listed after one of the line labels via a line corresponding to one of the line labels. The second symbol indicates that an electronic component corresponding to a component label listed before one of the line labels is connected in parallel with at least two electronic components corresponding to at least two component labels listed after one of the line labels via a line corresponding to one of the line labels.

8. A circuit path simplification system for simplifying multiple initial path sequences corresponding to a circuit diagram, the circuit diagram comprising multiple electronic components and multiple circuits, characterized in that, This circuit path simplification system includes: A storage unit stores the plurality of initial path sequences corresponding to the circuit diagram, wherein each initial path sequence includes a plurality of component labels for a corresponding portion of the plurality of electronic components and a plurality of line labels for a corresponding portion of the plurality of lines, the plurality of component labels and the plurality of line labels being arranged alternately with each other; as well as A processing unit is connected to the storage unit and obtains the plurality of initial path sequences, and the processing unit is configured to implement the following steps: A route label lookup step involves searching for one identical route label among the multiple initial path sequences to generate a route label confirmation result; and A component label comparison step involves comparing two component labels listed adjacent to one of the line labels in the initial path sequences based on the line label confirmation result to see if they are the same, thereby simplifying the multiple initial path sequences. When the two element labels are the same, the processing unit performs a merging step, which merges the two element labels of the two initial path sequences to generate a merged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The merged element label and the merged line label are arranged to form a simplified path sequence. When the two element labels are different, the processing unit performs an arrangement step, which arranges the two element labels of the two initial path sequences to generate an arranged element label, and merges one of the line labels of the two initial path sequences to generate a merged line label. The arranged element label and the merged line label are arranged to form another simplified path sequence.

9. The circuit path simplification system as described in claim 8, characterized in that, An adjacent element label and a circuit label indicate that the electronic component corresponding to the element label is electrically connected to the circuit corresponding to the circuit label.

10. The circuit path simplification system as described in claim 8, characterized in that, The processing unit introduces one of a first symbol and a second symbol into the merged line label. The first symbol and the second symbol are located before one of the line labels. The first symbol indicates that an electronic component corresponding to a component label listed before one of the line labels is connected in series with an electronic component corresponding to another component label listed after one of the line labels via a line corresponding to one of the line labels. The second symbol indicates that an electronic component corresponding to a component label listed before one of the line labels is connected in parallel with at least two electronic components corresponding to at least two component labels listed after one of the line labels via a line corresponding to one of the line labels.

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