Vertical decoder and related memory device and method

Abstract

Embodiments of the present application relate to vertical decoders and related memory devices and methods. A memory device can include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate. The decoder can be configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder can include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells. In some cases, the decoder can include a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction (e.g., away from a surface of the substrate), and the doped material can be configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

Description

[0001] Related application information

[0002] This application is a divisional application of the application patent application with the application date of October 31, 2019, the application number “201980078610.4”, and the invention name “VERTICAL DECODER AND RELATED MEMORY DEVICES AND METHODS”.

[0003] Cross reference to related applications

[0004] This patent application claims priority to PCT Application No. PCT / US2019 / 059037, filed October 31, 2019, to Redaelli et al., entitled “VERTICAL DECODER,” which claims priority to U.S. Patent Application No. 16 / 206,006, filed November 30, 2018, to Redaelli et al., entitled “VERTICAL DECODER,” each of which is assigned to its assignee and the entire contents of each of which are hereby expressly incorporated by reference. TECHNICAL FIELD

[0005] The technical field relates to a vertical decoder. BACKGROUND

[0006] The following relates generally to operating a memory array and more specifically to a vertical decoder.

[0007] Memory devices are widely used to store information in various electronic devices such as computers, cameras, digital displays, and the like. Information is stored by programming different states of a memory device. For example, binary devices have two states, which are typically represented by a logical “1” or a logical “0.” In other systems, more states can be stored. To access stored information, components of an electronic device can read or sense the stored states in a memory device. To store information, components of an electronic device can write or program states in a memory device.

[0008] There are a variety of types of memory devices, including magnetic hard disks, random access memory (RAM), read only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), and the like. Memory devices can be volatile or non-volatile. Non-volatile memory elements can maintain their stored logic state for extended periods of time even in the absence of an external power source. Volatile memory elements can lose their stored state over time unless they are periodically refreshed by an external power source.

[0009] Improvements in memory devices can generally include increasing memory cell density, increasing read / write speeds, increasing reliability, increasing data retention, reducing power consumption, or reducing manufacturing costs, among other metrics. Improved solutions for conserving space in a memory array, increasing memory cell density, or reducing overall power usage of a memory array can be desired. SUMMARY

[0010] A memory device is described. The memory device can include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate and configured to apply a voltage to an access line of the array of memory cells as part of an access operation. The decoder can include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells, and a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction away from a surface of the substrate, the doped material configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

[0011] A memory device is described. The memory device can include a substrate, and a decoder coupled with the substrate and configured to select a memory cell as part of an access operation. The decoder can include a first conductive line configured to carry a voltage for selecting the memory cell as part of the access operation, and a doped material extending between the first conductive line and a contact coupling the decoder with the memory cell and configured to selectively couple the first conductive line with the contact as part of the access operation.

[0012] A memory device is described. The memory device can include a substrate, an array of memory cells coupled with the substrate and comprising a first set of access lines and a second set of access lines, a first decoder coupled with the substrate and the array of memory cells, the first decoder configured to apply a first voltage to a first access line of the first set as part of an access operation, the first decoder including a first conductive line configured to carry the first voltage for the first access line as part of the access operation, and a doped material extending between the first conductive line and one of the first set of access lines in a first direction perpendicular to a surface of the substrate, the doped material configured to selectively couple the first conductive line with the first access line as part of the access operation. The memory device can include a second decoder coupled with the substrate and the array of memory cells, the second decoder configured to apply a second voltage to a second access line of the second set as part of the access operation.

[0013] A method is described. The method can include applying, as part of an access operation of a memory cell, a first voltage for selecting the memory cell to a first conductive line of a decoder, coupling, as part of the access operation, the first conductive line and an access line associated with the memory cell based at least in part on applying the first voltage and using a doped material of the decoder extending between the first conductive line and the access line, and applying, as part of the access operation, the first voltage to the memory cell based at least in part on coupling the first conductive line of the decoder and the access line.

[0014] An apparatus is described. The apparatus can include a decoder configured to apply, as part of an access operation of a memory cell, a voltage, the decoder including a first conductive line configured to carry, as part of the access operation, the voltage for selecting the memory cell, and a doped material coupled with the first conductive line and a contact, the doped material configured to selectively couple the first conductive line and the contact. The apparatus can include a controller operable, as part of the access operation of the memory cell, to select the memory cell by applying a first voltage to the first conductive line of the decoder, couple, based at least in part on selecting the memory cell, the first conductive line of the decoder and an access line associated with the memory cell, and apply, based at least in part on coupling the first conductive line of the decoder and the access line, the first voltage to the memory cell. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 An example memory device as disclosed herein is described.

[0016] Figure 2 An example of a portion of a memory array supporting a vertical decoder as disclosed herein is described.

[0017] Figure 3 An example of a top view of a decoder as disclosed herein is described.

[0018] Figure 4 An example of a cross-sectional view of a portion of a memory array supporting a vertical decoder as disclosed herein is described.

[0019] Figure 5 And 6 An example of a memory array supporting a vertical decoder as disclosed herein is described.

[0020] Figure 7A And 7BExamples of memory device configurations that support vertical decoders as disclosed herein are illustrated.

[0021] Figure 8 Block diagrams of devices that support vertical decoders as disclosed herein are shown.

[0022] Figure 9 and 10 Flow diagrams illustrating one or more methods that support vertical decoders as disclosed herein are shown. DETAILED DESCRIPTION

[0023] Some memory devices can include decoders coupled with a memory array. In some cases, the decoders can include one or more doped materials formed in a particular orientation to reduce the array size of a die used by the decoders. For example, the decoders can include doped materials that extend in a direction different from (e.g., perpendicular to) a surface of a substrate. In some cases, the decoders can also include conductive lines. The doped materials can extend from the conductive lines of the decoders to access lines associated with the memory array. In accordance with the teachings herein, the decoders can be coupled with the substrate and configured to apply a voltage to the access lines of the memory array. In some cases, the conductive lines can be configured to carry the voltage applied to the access lines, and the doped materials can couple the first conductive lines of the decoders with the access lines of the memory array.

[0024] In some cases, the memory array can be an example of a self-selecting memory array. In some cases, the self-selecting memory array can be fabricated in three dimensions and can include vertical memory cells. To conserve space and resources, decoders that include vertical doped materials can be implemented as part of or in the self-selecting memory array. In some examples, the decoders can be examples of row decoders implemented to bias one or more word lines or examples of column decoders implemented to bias one or more bit lines or both. The decoders can be positioned above the memory array, below the memory array, or both. In such cases, the size of the memory array can be reduced based on the placement and / or orientation of one or more decoders. Accordingly, these and other techniques and advantages described herein can improve the size and density of the memory array.

[0025] The features of the disclosure introduced above are further described below in the context of a memory array. Then, particular examples for operating a memory array in relation to a vertical decoder are described in some examples. These and other features of the disclosure are further illustrated by and described with reference to device diagrams and flowcharts in relation to techniques for vertical decoders.

[0026] Figure 1 An example memory device 100 as disclosed herein is illustrated. The memory device 100 can also be referred to as an electronic memory apparatus.Figure 1 is a schematic representation of various components and features of the memory device 100. As such, it should be appreciated that the components and features of the memory device 100 are shown in a manner to illustrate functional interrelationships between the components and features, rather than their actual physical location within the memory device 100. In Figure 1 In the illustrative example of FIG. 1, the memory device 100 includes a three- dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 is programmable to store two states represented as a logical 0 and a logical 1. In some examples, the memory cells 105 can be configured to store more logical states. In some examples, the memory cells 105 can include self-selecting memory cells. Although some elements included in the 3D memory array 102 are labeled with numerical designators, other corresponding elements are not labeled, but are the same or will be understood to be similar, in an attempt to increase visibility and clarity of the depicted features. Figure 1 In the illustrative example of FIG. 1, the memory device 100 includes a three- dimensional (3D) memory array 102. The 3D memory array 102 includes memory cells 105 that are programmable to store different states. In some examples, each memory cell 105 is programmable to store two states represented as a logical 0 and a logical 1. In some examples, the memory cells 105 can be configured to store more logical states. In some examples, the memory cells 105 can include self-selecting memory cells. Although some elements included in the 3D memory array 102 are labeled with numerical designators, other corresponding elements are not labeled, but are the same or will be understood to be similar, in an attempt to increase visibility and clarity of the depicted features.

[0027] The 3D memory array 102 can include two or more two-dimensional (2D) memory arrays 103 formed on top of each other. This can increase the number of memory cells that can be placed or produced on a single die or substrate compared to 2D arrays, which in turn can reduce production costs or increase performance of the memory device, or both. The memory array 102 can include two levels of memory cells 105 and thus can be considered a 3D memory array; however, the number of levels is not limited to two. Each level can be aligned or positioned such that the memory cells 105 can be aligned with each other (completely, overlapping, or approximately) across each level, forming a memory cell stack 145. In some cases, the memory cell stack 145 can include multiple self-selecting memory cells that are laid on top of each other while both share an access line, as explained below. In some cases, the self-selecting memory cells can be multi-level self-selecting memory cells configured to store more than one bit of data using multi-level storage technology.

[0028] In some examples, each row of memory cells 105 is connected to an access line 110, and each column of memory cells 105 is connected to a bit line 115. The access lines 110 and the bit lines 115 can be substantially perpendicular to each other and can produce a memory cell array. As Figure 1As shown in the middle, two memory cells 105 in the memory cell stack 145 can share a common conductive line (e.g., bit line 115). That is, the bit line 115 can be in electronic communication with the bottom electrode of the upper memory cell 105 and the top electrode of the lower memory cell 105. Other configurations can be possible, e.g., a third layer can share an access line 110 with a lower layer. In general, one memory cell 105 can be located at the intersection of two conductive lines (e.g., access line 110 and bit line 115). This intersection can be referred to as the address of the memory cell. The target memory cell 105 can be the memory cell 105 located at the intersection of the energized access line 110 and bit line 115; that is, the access line 110 and bit line 115 can be energized in order to read from or write to the memory cell 105 at their intersection. Other memory cells 105 in electronic communication with (e.g., connected to) the same access line 110 or bit line 115 can be referred to as unaddressed memory cells 105.

[0029] As discussed above, electrodes can be coupled to memory cells 105 and access lines 110 or bit lines 115. The term electrode can refer to an electrical conductor, and in some cases, can function as an electrical contact to a memory cell 105. An electrode can include a trace, wire, conductive line, conductive layer, or the like that provides an electrically conductive path between elements or components of a memory device 100. In some examples, a memory cell 105 can include a chalcogenide material positioned between a first electrode and a second electrode. One side of the first electrode can be coupled to an access line 110 and the other side of the first electrode is coupled to the chalcogenide material. Additionally, one side of the second electrode can be coupled to a bit line 115 and the other side of the second electrode is coupled to the chalcogenide material. The first electrode and the second electrode can be the same material (e.g., carbon) or different materials.

[0030] Operations (e.g., read and write) can be performed on memory cells 105 by activating or selecting access lines 110 and bit lines 115. In some examples, access lines 110 can also be referred to as word lines 110, and bit lines 115 can also be referred to as digit lines 115. References to access lines, word lines, and bit lines, or the like, can be interchangeable without loss of understanding or operation. Activating or selecting a word line 110 or bit line 115 can include applying a voltage to the respective line. Word lines 110 and bit lines 115 can be made of an electrically conductive material, such as a metal (e.g., copper (Cu), aluminum (Al), gold (Au), tungsten (W), titanium (Ti)), a metal alloy, carbon, an electrically conductive doped semiconductor, or other electrically conductive material, alloy, compound, or the like.

[0031] Accessing memory cells 105 can be controlled by row decoder 120 and column decoder 130. For example, row decoder 120 can receive a row address from memory controller 140 and activate the appropriate word line 110 based on the received row address. Similarly, column decoder 130 can receive a column address from memory controller 140 and activate the appropriate bit line 115. For example, memory array 102 can include a plurality of word lines 110 labeled WL_1 through WL_M and a plurality of digit lines 115 labeled DL_1 through DL_N, where M and N depend on the array size. Thus, by activating a word line 110 and a bit line 115 (e.g., WL_2 and DL_3), a memory cell 105 at their intersection can be accessed. As discussed in greater detail below, accessing memory cells 105 can be controlled by row decoder 120 and column decoder 130 that can include one or more doped materials that extend in a direction away from a surface of a substrate to which memory array 102 is coupled.

[0032] After access, memory cell 105 can be read or sensed by sense component 125 to determine the stored state of memory cell 105. For example, a voltage can be applied to memory cell 105 (using the corresponding word line 110 and bit line 115) and the presence of a resulting current can depend on the applied voltage and threshold voltage of memory cell 105. In some cases, more than one voltage can be applied. Further, if the applied voltage does not result in current flow, other voltages can be applied until current is detected by sense component 125. By evaluating the voltage that results in current flow, the stored logic state of memory cell 105 can be determined. In some cases, the voltage can be ramped in magnitude until current flow is detected. In other cases, predetermined voltages can be sequentially applied until current is detected. Likewise, a current can be applied to memory cell 105 and the magnitude of the voltage that produces the current can depend on the resistance or threshold voltage of memory cell 105.

[0033] In some examples, a memory cell that can include a memory storage element can be programmed by providing an electrical pulse to the cell. The pulse can be provided via a first access line (e.g., word line 110) or a second access line (e.g., bit line 115) or a combination thereof. In some cases, after the pulse is provided, ions can migrate within the memory storage element depending on the polarity of the memory cell 105. Thus, the concentration of ions relative to the first side or the second side of the memory storage element can be based at least in part on the polarity of the voltage between the first access line and the second access line. In some cases, the asymmetric shape of the memory storage element can cause ions to more aggregate at the portion of the element that has more area. A particular portion of the memory storage element can have a higher resistivity and thus can generate a threshold voltage that is higher than other portions of the memory storage element. This description of ion migration represents an example of a mechanism of a self-selecting memory cell for achieving the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms of a self-selecting memory cell for achieving the results described herein.

[0034] The sensing component 125 can include various transistors or amplifiers in order to detect and amplify the difference in the signal (this can be referred to as latching). The detected logic state of the memory cell 105 can then be output as an output 135 by the column decoder 130. In some cases, the sensing component 125 can be part of the column decoder 130 or the row decoder 120. Alternatively, the sensing component 125 can be connected to or in electronic communication with the column decoder 130 or the row decoder 120. One of ordinary skill in the art will appreciate that a sensing component can be associated with a column decoder or a row decoder without losing its functional purpose.

[0035] A memory cell 105 can be set or written and can store at least one logic value in the memory cell 105 by similarly activating the relevant word line 110 and bit line 115. The column decoder 130 or the row decoder 120 can accept data (e.g., input / output 135) to be written to the memory cell 105. In the case of a self-selecting memory cell that includes a chalcogenide material, the memory cell 105 can be written to store a logic state in the memory cell 105 by applying a first voltage to the memory cell 105 as part of an access operation based on coupling a first conductive line of the decoder (e.g., row decoder 120 or column decoder 130) with an access line (e.g., word line 110 or bit line 115).

[0036] The memory controller 140 can control the operation (e.g., read, write, rewrite, refresh, discharge) of the memory cells 105 through various components (e.g., the row decoder 120, the column decoder 130, and the sensing component 125). In some cases, one or more of the row decoder 120, the column decoder 130, and the sensing component 125 can be co-located with the memory controller 140. The memory controller 140 can generate row and column address signals in order to activate the desired word lines 110 and bit lines 115. The memory controller 140 can also generate and control various voltages or currents used during the operation of the memory device 100.

[0037] The memory controller 140 can be configured to select the memory cell 105 by applying a first voltage to a first conductive line of a decoder (e.g., the row decoder 120 or the column decoder 130). In some cases, the memory controller 140 can be configured to couple the first conductive line of the decoder with an access line (e.g., the word line 110 or the bit line 115) associated with the memory cell 105 based on selecting the memory cell 105. The memory controller 140 can be configured to apply the first voltage to the memory cell 105 based at least in part on coupling the first conductive line of the decoder with the access line.

[0038] In some examples, the memory controller 140 can be configured to apply a second voltage to a second conductive line of the decoder as part of an access operation. In some cases, the second voltage can cause the doped material to selectively couple the first conductive line of the decoder with the access line associated with the memory cell 105. The application of the first voltage to the memory cell 105 can be based on the application of the second voltage to the second conductive line. For example, the memory controller 140 can select the memory cell 105 based on the intersection of the first voltage and the second voltage. In some cases, the signal applied to the memory cell 105 as part of the access operation can have a positive polarity or a negative polarity.

[0039] In some examples, the memory controller 140 can receive a command including an instruction to perform an access operation on the memory cell 105 and identify an address of the memory cell 105 based on receiving the command. In some cases, the application of the second voltage to the second conductive line can be based on identifying the address. If the access operation is a read operation, the memory controller 140 can be configured to output a logic state stored in the memory cell 105 based on applying the first voltage to the memory cell 105. If the access operation is a write operation, the memory controller 140 can store a logic state in the memory cell 105 based on applying the first voltage to the memory cell 105.

[0040] Figure 2 An example of a 3D memory array 200 that supports a vertical decoder as disclosed herein is illustrated. The memory array 200 can be a referenceFigure 1 An example of a portion of the memory array 102 is depicted. The memory array 200 can include a first array or level 205 of memory cells located over a substrate 204 and a second array or level 210 of memory cells located on top of the first array or level 205. The memory array 200 can also include word lines 110-a and 110-b and bit lines 115-a, which can be as described with reference to Figure 1 An example of a word line 110 and a bit line 115 is depicted. The memory cells of the first level 205 and the second level 210 can each have one or more self-selecting memory cells (e.g., self-selecting memory cell 220-a and self-selecting memory cell 220-b, respectively). Although Figure 2 Some elements included in the figures can be labeled with a digital identifier, other corresponding elements are not labeled with a digital identifier, but are identical or understood to be similar, in order to try to increase the visibility and clarity of the depicted features.

[0041] The self-selecting memory cells of the first level 205 can include a first electrode 215-a, a self-selecting memory cell 220-a (e.g., including a chalcogenide material), and a second electrode 225-a. Additionally, the self-selecting memory cells of the second level 210 can include a first electrode 215-b, a self-selecting memory cell 220-b (e.g., including a chalcogenide material), and a second electrode 225-b. In some examples, the self-selecting memory cells of the first level 205 and the second level 210 can have a common conductive line such that the corresponding self-selecting memory cells of each level 205 and 210 can share a bit line 115 or a word line 110 as described with reference to Figure 1 A bit line 115 or a word line 110 is depicted. For example, the first electrode 215-b of the second level 210 and the second electrode 225-a of the first level 205 can be coupled to the bit line 115-a such that the bit line 115-a is shared by vertically adjacent self-selecting memory cells. According to the teachings herein, if the memory array 200 includes more than one level, a decoder can be located above or below each level. For example, a decoder can be positioned above the first level 205 and the second level 210.

[0042] The architecture of the memory array 200 can be referred to in some cases as a cross-point architecture, where memory cells are formed at topological cross-points between word lines and bit lines, as described with reference to Figure 2The cross-point architecture can provide relatively high density data storage at lower production costs compared to other memory architectures. For example, the cross-point architecture can have memory cells that are area scaled and thus have increased memory cell density compared to other architectures. For example, the architecture can have a 4F2memory cell area compared to other architectures, such as architectures with three-terminal selection components, that have a 6F2memory cell area, where F is the minimum feature size. For example, DRAM can use transistors, which are three-terminal devices, as the selection component for each memory cell and can have a larger memory cell area compared to cross-point architectures.

[0043] While Figure 2 Examples of the memory array 200 show two memory levels, but other configurations are possible. In some examples, a single memory level of self-selecting memory cells, which can be referred to as two-dimensional memory, can be constructed over the substrate 204. In some examples, three or four memory levels of memory cells can be configured in a manner similar to one in a three-dimensional cross-point architecture.

[0044] In some examples, one or more of the memory levels can include self-selecting memory cells 220 that include a chalcogenide material. For example, the self-selecting memory cells 220 can include a chalcogenide glass, such as, for example, an alloy of selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), and silicon (Si). In some examples, a chalcogenide material having primarily selenium (Se), arsenic (As), and germanium (Ge) can be referred to as a SAG alloy. In some examples, a SAG alloy can include silicon (Si) and this chalcogenide material can be referred to as a SiSAG alloy. In some examples, the chalcogenide glass can include additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0045] In some examples, the self-selecting memory cells 220 that include a chalcogenide material can be programmed to a logical state by applying a first voltage. By way of example, when a particular self-selecting memory cell 220 is programmed, the elements within the cell separate, causing ion migration. Depending on the polarity of the voltage applied to the memory cell, the ions can migrate toward a particular electrode. For example, in the self-selecting memory cells 220, the ions can migrate toward a negative electrode. The memory cell can then be read by applying a voltage to sense across the cell. The threshold voltage seen during a read operation can be based on the ion distribution in the memory cell and the polarity of the read pulse.

[0046] For example, if a memory cell has a given ion distribution, a threshold voltage detected during the read operation can be different for a first read voltage having a first polarity than for a second read voltage having a second polarity. Depending on the polarity of the memory cell, this concentration of migrated ions can represent a logic "1" or a logic "0" state. This description of ion migration represents an example of a mechanism for a self-selecting memory cell to achieve the results described herein. This example of a mechanism should not be considered limiting. The present disclosure also includes other examples of mechanisms for a self-selecting memory cell to achieve the results described herein.

[0047] In some cases, as part of an access operation of a self-selecting memory cell 220, a first voltage can be applied to a first conductive line of a decoder. After applying the first voltage, the first conductive line can be coupled with an access line (e.g., word line 110-a, word line 110-b, or bit line 115-a) associated with the self-selecting memory cell 220. For example, the first conductive line can be coupled with the access line based on a doped material of the decoder extending between the first conductive line and the access line in a first direction.

[0048] In some examples, the first voltage can be applied to the self-selecting memory cell 220 based on coupling the first conductive line of the decoder with the access line. The decoder can include one or more doped materials extending between the first conductive line and an access line of the memory array 200 of memory cells in a first direction away from a surface of the substrate 204. In some cases, the decoder can be coupled with the substrate 204.

[0049] Figure 3 An example of a top view of a decoder 300 as disclosed herein is illustrated. The decoder 300 can be an example of the row decoder 120 or the column decoder 130 described with reference to FIG. 1. The decoder 300 can include a doped material 310 extending in a direction away from a surface of a substrate (not shown). The decoder 300 can be an example of a final stage decoder of a memory array. Figure 1 An example of a row decoder 120 or a column decoder 130 described. The decoder 300 can include a doped material 310 extending in a direction away from a surface of a substrate (not shown). The decoder 300 can be an example of a final stage decoder of a memory array.

[0050] The decoder 300 can include at least a first conductive line 305. In some cases, the decoder 300 can include a plurality of first conductive lines 305. The first conductive line 305 can be configured to carry a voltage applied to an access line (not shown) of an array of memory cells. For example, each first conductive line 305 can receive a signal from an access line within the decoder 300. The first conductive line 305 can extend in a second direction.

[0051] In some cases, the decoder 300 can include a doped material 310 that can extend between the first conductive line 305 and an access line (not shown). For example, the doped material 310 can extend in a direction away from a surface of a substrate (e.g., a first direction). In some cases, the direction can be perpendicular or orthogonal to a plane defined by the surface of the substrate. For example, a second direction can be perpendicular to the first direction along which the first conductive line 305 extends. The doped material 310 can be configured to selectively couple the first conductive line 305 of the decoder 300 with an access line. In some cases, the doped material 310 can comprise a semiconductor material, such as polysilicon. In some cases, polysilicon can be deposited at a lower temperature than other materials, thereby increasing compatibility between polysilicon material of the decoder 300 and a memory array.

[0052] The decoder 300 can also include a contact 315. The contact 315 can extend between the doped material 310 and other conductive lines of the decoder 300 or an access line of a memory cell array. In some cases, the doped material 310 can selectively couple the first conductive line 305 of the decoder 300 with the contact 315. The contact 315 can also extend between a conductive material 320 and a second conductive line (not shown).

[0053] In some examples, the decoder 300 can include at least one conductive material 320. The conductive material 320 can be coupled with the doped material 310. In some cases, the conductive material 320 can be configured to carry a second voltage (e.g., a voltage different from a voltage applied to an access line) for causing the doped material 310 to selectively couple the first conductive line 305 with an access line of a memory array (e.g., a memory cell array). In such cases, the one or more conductive materials 320 can receive a signal from an access line associated with the memory array. In some cases, the access line can be an example of a word line. Each conductive material 320 can be in contact with an access line of the memory array.

[0054] In some cases, the decoder 300 can include one or more transistors. For example, the doped material 310 and the conductive material 320 can comprise a transistor. The transistor can selectively couple the first conductive lines 305 with access lines of a memory array. In such cases, the conductive material 320 can be an example of a gate of the transistor and the doped material 310 can be an example of a source of the transistor, a drain of the transistor, or both. In some cases, the conductive material 320 can contact an oxide of the doped material 310. The transistor can be an example of an nMOS transistor or a pMOS transistor. In some cases, a polysilicon transistor as a decoder can allow for greater degrees of freedom compared to a polysilicon transistor as a selector in a back end of a memory array. For example, a polysilicon transistor in a front end of a memory array can allow for the use of higher thermal budgets for dopant activation, thereby reducing device engineering complexity. In some cases, a gate oxide can be positioned between the conductive material 320 and the doped material 310.

[0055] In some examples, if the decoder 300 includes the doped material 310 extending in a direction away from a surface of a substrate, a size and dimensions of the decoder 300 can be optimized. For example, when implementing a vertical decoder, a distance 325 between two conductive materials 320 can be reduced. In some examples, the distance 325 between the conductive materials 320 can be 120 nm. In some cases, when implementing a vertical decoder, a width 330 of the conductive materials 320 can also be reduced. For example, the width 330 of the conductive materials 320 can be 120 nm. A combined distance 335 of the distance 325 and the width 330 can be 240 nm. In such cases, when implementing a vertical decoder, the combined distance 335 can be reduced.

[0056] In some cases, when implementing a vertical decoder, a distance 340 between two first conductive lines 305 can be increased. For example, the distance 340 between the first conductive lines 305 can be 120 nm. In some cases, when implementing a vertical decoder, a width 345 of the first conductive lines 305 can be reduced. For example, the width 345 of the first conductive lines 305 can be 120 nm. A combined distance 350 of the distance 340 and the width 345 can be 240 nm. In such cases, when implementing a vertical decoder, the combined distance 350 can be reduced. For example, an area of an nMOS transistor can be 0.015 um2. 2 As described in further detail below, the decoder 300 can be viewed via a perspective line 355.

[0057] Figure 4An example illustrates a cross-sectional view of a portion of a memory array 400 supporting a vertical decoder as disclosed herein. The portion of the memory array 400 can include a decoder 402, which can include doped materials 410-a, 410-b, 410-c, and / or 410-d extending in a direction away from a surface 435 of a substrate 425. The decoder 402 can be an example of a decoder 300 as described with reference to Figure 3 An example illustrates a cross-sectional view of a portion of a memory array 400 supporting a vertical decoder as disclosed herein. The portion of the memory array 400 can include a decoder 402, which can include doped materials 410-a, 410-b, 410-c, and / or 410-d extending in a direction away from a surface 435 of a substrate 425. The decoder 402 can be an example of a decoder 300 as described with reference to Figure 3 An example illustrates a cross-sectional view of a portion of a memory array 400 supporting a vertical decoder as disclosed herein. The portion of the memory array 400 can include a decoder 402, which can include doped materials 410-a, 410-b, 410-c, and / or 410-d extending in a direction away from a surface 435 of a substrate 425. The decoder 402 can be an example of a decoder 300 as described with reference to

[0058] The portion of the memory array 400 can include a substrate 425, which can be an example of a substrate 204 as described with reference to Figure 2 In some examples, the decoder 402 can be coupled with the substrate 425. The substrate 425 can be above or below the decoder 402. In some cases, the decoder 402 can be configured to apply a voltage to an access line (e.g., a word line or a digit line) of a memory cell array as part of an access operation. The decoder 402 can also include a first conductive line 405, which can be an example of a first conductive line 305 as described with reference to Figure 3 In some cases, the first conductive line 405 can be directly coupled with the doped material 410-a.

[0059] In some cases, the decoder 402 can include doped materials 410-a through 410-d. The doped materials 410-a through 410-d can be polysilicon materials. In some examples, the doped materials 410-a through 410-d can extend between the first conductive line 405 and an access line (e.g., a word line or a digit line) of a memory cell array in a direction away from a surface 435 of a substrate 425. For example, the doped materials 410-a through 410-d can extend orthogonally from a plane bounded by the surface 435 of the substrate 425.

[0060] In some examples, the doped material 410 can include a first doped region 440 and a second doped region 445. For example, the first doped region 440 can be a first distance from the surface 435 of the substrate 425, and the second doped region 445 can be a second distance from the surface 435 of the substrate 425. In such cases, the first and second distances from the surface 435 of the substrate 425 can be different. In some cases, the first and second doped regions 440 and 445 can include similar doped materials. In other examples, the first and second doped regions 440 and 445 can include different doped materials. For example, the first doped region 440 can include polysilicon and the second doped region 445 can include a different semiconductor material.

[0061] Decoder 402 may include one or more contacts 415, said one or more contacts 415-a and 415-b, which may be used as a reference. Figure 3 An example of contact 315 is described. Contact 415-a may extend between doped material 410-a and the access lines of the memory cell array. In such cases, contact 415-a may be directly coupled to doped material 410-a. In some cases, doped material 410-a may selectively couple the first conductive line 405 of decoder 402 to contact 415-a.

[0062] Decoder 402 may also include conductive material 420, which may be coupled to doped materials 410-a and 410-b and may be as shown in the reference. Figure 3 Examples of conductive material 320 described. Conductive material 420 may be configured to carry a second voltage for causing doped material 410-a to selectively couple the first conductive line 405 to the access line or contact 415-a. In some cases, conductive material 420 may be directly coupled to the surface of doped material 410-a. For example, conductive material 420 may be coupled to the surface of doped material 410-a. Conductive material 420 may contact the oxide of doped material 410-a. In some examples, conductive material 420 may extend in a direction parallel to the surface of substrate 425. Doped material 410-a may extend in a direction perpendicular to the surface of conductive material 420.

[0063] In some cases, decoder 402 may include a second conductive line 430. The second conductive line 430 may be coupled to a contact 415-b. For example, contact 415-b may extend between the second conductive line 430 and conductive material 420. The second conductive line 430 may carry a second voltage for causing doped material 410-a to couple the first conductive line 405 of decoder 402 to the access line. In some cases, contact 415-b may carry the second voltage from the second conductive line 430 to the conductive material 420 as part of an access operation. The second conductive line 430 may extend in a direction parallel to the surface of substrate 425. In this case, doped material 410-a may extend in a direction perpendicular to the surface of the second conductive line 430. In some cases, the first conductive line 405 may be an example of a global word line or a global digital line of decoder 402, and the second conductive line 430 may be an example of a local word line or a local digital line of decoder 402.

[0064] Figure 5An example of a memory array 500 supporting a vertical decoder as disclosed herein is illustrated. The memory array 500 can include decoders 502-a and 502-b, a substrate 525, a memory cell array 535, and access lines 530-a (e.g., a first set of access lines) and 530-b (e.g., a second set of access lines). The decoders 502-a and 502-b and the substrate 525 can be examples of decoders and substrates as described with reference to Figures 2 to 4 The memory array 500 can include a memory cell array 535 coupled with the substrate 525. In some cases, the access lines 530-a can comprise word lines or digit lines. In some examples, the access lines 530-b can comprise bit lines or digit lines or word lines. In other examples, the memory array 500 can be an example of a cross-point architecture, a pillar architecture, or a planar architecture. The memory array 500 can be an example of an electrical schematic.

[0065] The decoders 502-a and 502-b can each be an example of a vertical decoder as described herein. The decoder 502-a can be an example of a first decoder (e.g., a row decoder) coupled with the substrate 525 and the memory cell array 535. In some cases, the decoder 502-a can include a plurality of nMOS transistors. In some cases, the decoder 502-a can include a conductive line 505-a (e.g., a first conductive line), a doped material 510-a, a contact 515-a, a contact 515-b, and a conductive material 520-a, which can be examples of a first conductive line, a doped material, a contact, and a conductive material as described with reference to Figure 3 and 4 In some examples, the decoder 502-a can be positioned above the memory cell array 535 (not shown), below the memory cell array 535, or both. The decoder 502-b can be an example of a second decoder (e.g., a column decoder) coupled with the substrate 525 and the memory cell array 535. In some cases, the decoder 502-b can include a plurality of pMOS transistors. In some cases, the decoder 502-b can include a conductive line 505-b (e.g., a second conductive line), a doped material 510-b, a contact 515-c, a contact 515-d, and a conductive material 520-b, which can be examples of a first conductive line, a doped material, a contact, and a conductive material as described with reference to

[0066] The decoder 502-a can apply a first voltage to an access line (e.g., a first access line) of the access lines 530-a as part of an access operation. The conductive line 505-a can carry the first voltage for the access operation. In some cases, the conductive line 505-a can be coupled to an access line of the access lines 530-a based on the first voltage being applied. For example, the contact 515-a can carry a signal from another conductive line to cause the first conductive line 505-a to be coupled with the access line 530-a. The contact 515-b can couple the doped material 510-a with the access line 530-a. In some cases, the access line 530-a can be selected based on the first conductive line 505-a and the conductive material 520-a being activated. The first voltage can also be applied to a memory cell of the memory cell array 535 based on the conductive line 505-a being coupled to the access line of the access lines 530-a. In some cases, a logical state stored in a memory cell of the memory cell array 535 can be output based on the first voltage being applied. In such cases, the access operation can be a read operation. In some examples, a logical state can be stored in a memory cell of the memory cell array 535 based on the first voltage being applied. In such cases, the access operation can be a write operation.

[0067] The doped material 510-a can extend between one of the conductive line 505-a and the access line 530-a (or the contact 515-b) in a direction perpendicular to a surface of the substrate 525. That is, the doped material 510-a can extend in a direction perpendicular to a surface of the conductive material 520-a. In some cases, the conductive line 505-a and the access line 530-a can be selectively coupled via the doped material 510-a.

[0068] In some cases, the memory array 500 can include a decoder 502-b, which can be an example of a second decoder (e.g., a column decoder). In some cases, the decoder 502-b can include a plurality of pMOS transistors. For example, the decoder 502-b can be coupled with the substrate 525 and the memory cell array 535. In some cases, the decoder 502-b can include a conductive line 505-b (e.g., a second conductive line), a doped material 510-b, a contact 515-c, a contact 515-d, and a conductive material 520-b. In some examples, the decoder 502-b can be positioned above the memory cell array 535, below the memory cell array 535 (not shown), or both.

[0069] In some cases, fabrication techniques to form memory array 500 can include different masking steps to form each of the different lengths of contacts 515-d (e.g., the distance between doped material 510-b and access line 530-b). In some examples, the contact scheme can be an example of a staggered configuration. For example, the length of contacts 515-d can increase as the distance between contacts 515-d and memory cell array 535 increases. In such cases, bottom access line 530-b can extend further than top access line 530-b. The contact scheme can be implemented via additional conductive layers (not shown). In some examples, a single masking step after deposition can be implemented to obtain the contact scheme (e.g., the staggered configuration).

[0070] In some examples, decoder 502-b can apply a second voltage to an access line (e.g., a second access line) of access lines 530-b as part of an access operation. Conductive line 505-b can carry the second voltage for selecting a memory cell of memory cell array 535 as part of the access operation. Contacts 515-d can couple doped material 510-b with access line 530-b. In some cases, access line 530-b can be selected based on activating conductive line 505-b and conductive material 520-b. In some cases, contacts 515-c can carry a signal from another conductive line to cause first conductive line 505-b to couple with access line 530-b. A memory cell included in memory cell array 535 can be selected based on an intersection of activated access lines 530-a and 530-b. For example, an intersection of the first voltage and the second voltage can select a memory cell. In such cases, a signal applied to a memory cell of memory cell array 535 can have a positive or negative polarity.

[0071] In some cases, doped material 510-b can extend between one of conductive line 505-b and access line 530-b (or contacts 515-d) in a direction perpendicular to a surface of substrate 525. Conductive line 505-b and access line 530-b can be coupled via doped material 510-b.

[0072] Figure 6Examples of a memory array supporting a vertical decoder as disclosed herein are described. The memory array 600 can include a first decoder 602-a, a second decoder 602-b, a substrate 625, a memory cell array 635, and access lines 630-a (e.g., a first set of access lines) and 630-b (e.g., a second set of access lines). The memory array 600 can include the memory cell array 635 coupled with the substrate 625. In some cases, the access lines 630-a can comprise word lines or digit lines. In some examples, the access lines 630-b can comprise bit lines or word lines. In other examples, the memory array 600 can be an example of a cross-point architecture, a pillar architecture, or a planar architecture. The memory array 600 can be an example of a memory array as described with reference to Figure 5 Examples of the memory array 500 are described.

[0073] The first decoder 602-a can be an example of a vertical decoder as described herein. The first decoder 602-a can be coupled with the substrate 625 and the memory cell array 635. In some cases, the first decoder 602-a can include a plurality of nMOS transistors or a plurality of pMOS transistors. In some cases, the first decoder 602-a can include a conductive line 605-a (e.g., a first conductive line), a doped material 610-a, a contact 615-a, a contact 615-b, and a conductive material 620-a, which can be examples of a conductive line, a doped material, a contact, and a conductive material as described with reference to Figures 3 to 5 Examples of the first conductive line, the doped material, the contact, and the conductive material are described.

[0074] The first decoder 602-a can apply a first voltage to an access line (e.g., a first access line) of the access lines 630-a as part of an access operation. The conductive line 605-a can carry the first voltage for the access operation (e.g., through the contact 615-b). The doped material 610-a can extend between the conductive line 605-a and one of the access lines 630-a in a direction perpendicular to a surface of the substrate 625. The conductive line 605-a and the access line 630-a can be coupled via the doped material 610-a. For example, the contact 615-a can carry a signal from another conductive line to cause the first conductive line 605-a and the access line 630-a to be coupled.

[0075] In some cases, the memory array 600 can include a second decoder 602-b, which can be an example of a planar decoder. In some cases, the second decoder 602-b can include a plurality of pMOS transistors or nMOS transistors. For example, the second decoder 602-b can be coupled with the substrate 625 and the memory cell array 635. In some cases, the second decoder 602-b can include a conductive line 605-b (e.g., a second conductive line), a doped material 610-b, a contact 615-c, a contact 615-d, and a conductive material 620-b, which can be examples of a conductive line, a doped material, a contact, and a conductive material as described with reference to Figures 3 to 5Examples of the first conductive line, the doped material, the contact, and the conductive material described.

[0076] In some examples, the second decoder 602-b can apply a second voltage to an access line (e.g., a second access line) of the access lines 630-b as part of an access operation. The conductive line 605-b can carry the second voltage for selecting a memory cell of the memory cell array 635 as part of the access operation. In some cases, the doped material 610-b can extend parallel to a surface of the substrate 625. The doped material 610-b can include a plurality of doped regions configured to couple the first conductive line 605-b with the access line 630-b based at least in part on a signal applied to one or more of the conductive material 620-b. The contact 615-c can couple the first conductive line 605-b with a first doped region of the doped material 610-b and the contact 615-d can couple the access line 630-b with a second doped region of the doped material 610-b.

[0077] The doped material 610-b can extend along a direction parallel to a surface of the substrate 625. In such cases, the doped material 610-b can extend along a direction perpendicular to a surface of the doped material 610-a. The conductive line 605-b and the access line 630-b can be coupled via the doped material 610-b. In some cases, the memory array 600 can include a first decoder 602-a including a doped material 610-a extending along a direction perpendicular to a surface of the substrate 625 and a second decoder 602-b including a doped material 610-b extending along a direction parallel to a surface of the substrate 625.

[0078] Figure 7A An example of a memory device configuration 700-a supporting a vertical decoder as disclosed herein is illustrated. The memory device configuration 700-a can include a decoder 705-a, a memory cell array 710-a, and a substrate 715-a, which can be as described with reference to Figures 3 to 6 Examples of a decoder, a memory cell array, and a substrate described. In some cases, the memory cell array 710-a can be positioned between the substrate 715-a and the decoder 705-a.

[0079] Figure 7B An example of a memory device configuration 700-b supporting a vertical decoder as disclosed herein is illustrated. The memory device configuration 700-b can include a decoder 705-b, a memory cell array 710-b, and a substrate 715-b, which can be as described with reference to Figures 3 to 6 Examples of a decoder, a memory cell array, and a substrate described. In some cases, the decoder 705-b can be positioned between the memory cell array 710-b and the substrate 715-b.

[0080] Figure 8A block diagram 800 of a device 805 that supports a vertical decoder as disclosed herein. In some examples, the device 805 can be an example of a memory array. The device 805 can be an example of a portion of a memory controller (e.g., as described with reference to the memory controller 140). The device 805 can include a selection component 810, a coupling component 815, a voltage component 820, a command component 825, and a logic state component 830. Each of these components can communicate, directly or indirectly, with one another (e.g., via one or more buses). Figure 1 The selection component 810 can apply a first voltage for selecting a memory cell to a first conductive line of a decoder as part of an access operation of the memory cell. In some examples, the selection component 810 can select the memory cell based at least in part on an intersection of the first voltage and a second voltage, where a signal applied to the memory cell as part of the access operation has a positive polarity or a negative polarity.

[0081] The selection component 810 can apply a first voltage for selecting a memory cell to a first conductive line of a decoder as part of an access operation of the memory cell. In some examples, the selection component 810 can select the memory cell based at least in part on an intersection of the first voltage and a second voltage, where a signal applied to the memory cell as part of the access operation has a positive polarity or a negative polarity.

[0082] The coupling component 815 can couple the first conductive line and an access line associated with the memory cell as part of the access operation based at least in part on applying the first voltage and using a doped material of the decoder extending between the first conductive line and the access line in a first direction.

[0083] The voltage component 820 can apply the first voltage to the memory cell as part of the access operation based at least in part on coupling the first conductive line of the decoder and the access line. In some examples, the voltage component 820 can apply a second voltage to a second conductive line of the decoder as part of the access operation, the second voltage to cause the doped material to selectively couple the first conductive line of the decoder and the access line associated with the memory cell, where applying the first voltage to the memory cell is based at least in part on applying the second voltage to the second conductive line.

[0084] The command component 825 can receive a command including an instruction to perform an access operation on a memory cell. In some examples, the command component 825 can identify an address of the memory cell based at least in part on receiving the command, where applying the second voltage to the second conductive line is based at least in part on identifying the address.

[0085] The logic state component 830 can output a logic state stored in the memory cell based at least in part on applying the first voltage to the memory cell. In this case, the access operation is a read operation. In some examples, the logic state component 830 can store a logic state in the memory cell based at least in part on applying the first voltage to the memory cell. In this case, the access operation is a write operation.

[0086] Figure 9A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to Figure 8 A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to Figure 1 A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to

[0087] At 905, as part of an access operation to a memory cell, the memory controller can apply a first voltage for selecting the memory cell to a first conductive line of a decoder. The operations of 905 can be performed according to the methods described herein. In some examples, portions of the operations of 905 can be performed by a selection component as described with reference to Figure 8 A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to

[0088] At 910, as part of the access operation, the memory controller can couple the first conductive line to an access line associated with the memory cell based at least in part on applying the first voltage and using a doped material of the decoder extending between the first conductive line and the access line in a first direction. The operations of 910 can be performed according to the methods described herein. In some examples, portions of the operations of 910 can be performed by a coupling component as described with reference to Figure 8 A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to

[0089] At 915, as part of the access operation, the memory controller can apply the first voltage to the memory cell based at least in part on coupling the first conductive line of the decoder to the access line. The operations of 915 can be performed according to the methods described herein. In some examples, portions of the operations of 915 can be performed by a voltage component as described with reference to Figure 8 A flow diagram illustrating a method 900 that supports vertical decoders as disclosed herein is shown. The operations of method 900 can be implemented by a memory controller or its components as described herein. For example, the operations of method 900 can be performed by a memory controller as described with reference to

[0090] Figure 10 A flow diagram illustrating a method 1000 that supports vertical decoders as disclosed herein is shown. The operations of method 1000 can be implemented by a memory controller or its components as described herein. For example, the operations of method 1000 can be performed by a memory controller as described with reference to Figure 8 A flow diagram illustrating a method 1000 that supports vertical decoders as disclosed herein is shown. The operations of method 1000 can be implemented by a memory controller or its components as described herein. For example, the operations of method 1000 can be performed by a memory controller as described with reference to Figure 1 A flow diagram illustrating a method 1000 that supports vertical decoders as disclosed herein is shown. The operations of method 1000 can be implemented by a memory controller or its components as described herein. For example, the operations of method 1000 can be performed by a memory controller as described with reference to

[0091] At 1005, as part of an access operation to a memory cell, the memory controller can apply a first voltage for selecting the memory cell to a first conductive line of a decoder. The operations of 1005 can be performed according to the methods described herein. In some examples, portions of the operations of 1005 can be performed by a selection component as described with reference to Figure 8 FIG. 9.

[0092] At 1010, the memory controller can couple the first conductive line with an access line associated with the memory cell as part of the access operation based at least in part on applying the first voltage and using a doped material of the decoder extending between the first conductive line and the access line in a first direction. The operations of 1010 can be performed according to the methods described herein. In some examples, portions of the operations of 1010 can be performed by a coupling component as described with reference to Figure 8 FIG. 9.

[0093] At 1015, the memory controller can apply the first voltage to the memory cell as part of the access operation based at least in part on coupling the first conductive line of the decoder with the access line. The operations of 1015 can be performed according to the methods described herein. In some examples, portions of the operations of 1015 can be performed by a voltage component as described with reference to Figure 8 FIG. 9.

[0094] At 1020, the memory controller can apply a second voltage to a second conductive line of the decoder as part of the access operation, the second voltage for causing the doped material to selectively couple the first conductive line of the decoder with the access line associated with the memory cell, wherein applying the first voltage to the memory cell is based at least in part on applying the second voltage to the second conductive line. The operations of 1020 can be performed according to the methods described herein. In some examples, portions of the operations of 1020 can be performed by a voltage component as described with reference to Figure 8 FIG. 9.

[0095] In some examples, an apparatus as described herein can perform one or several methods, such as method 1000. The apparatus can include features, means, or instructions for applying, as part of an access operation for a memory cell, a first voltage for selecting the memory cell to a first conductive line of a decoder as a memory cell (e.g., a non-transitory computer-readable medium storing instructions executable by a processor). The apparatus can include features, means, or instructions for coupling, as part of the access operation, the first conductive line of the decoder with an access line associated with the memory cell based at least in part on applying the first voltage and using a doped material of the decoder extending between the first conductive line and the access line, including features, means, or instructions for applying, as part of the access operation, the first voltage to the memory cell based at least in part on coupling the first conductive line of the decoder with the access line (e.g., a non-transitory computer-readable medium storing instructions executable by a processor).

[0096] Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for applying, as part of the access operation, a second voltage to a second conductive line of the decoder, the second voltage for causing the doped material to selectively couple the first conductive line of the decoder with the access line associated with the memory cell, where applying the first voltage to the memory cell is based at least in part on applying the second voltage to the second conductive line. Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for selecting the memory cell based at least in part on an intersection of the first voltage and the second voltage, where a signal applied to the memory cell as part of the access operation has a positive polarity or a negative polarity.

[0097] Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for receiving a command including an instruction to perform an access operation for a memory cell. Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for identifying an address of the memory cell based at least in part on receiving the command, where applying the second voltage to the second conductive line is based at least in part on identifying the address. Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for outputting a logical state stored in the memory cell based at least in part on applying the first voltage to the memory cell. Some examples of the method 1000 and apparatus described herein can further include operations, features, means, or instructions for storing a logical state in the memory cell based at least in part on applying the first voltage to the memory cell.

[0098] It should be noted that the methods described above describe possible implementations, and that the operations and the steps can be rearranged or otherwise modified and that other implementations are possible. Furthermore, portions from two or more methods can be combined.

[0099] In some examples, an apparatus or device can perform aspects of the functions described herein. The device can include a substrate, an array of memory cells coupled with the substrate, and a decoder coupled with the substrate and configured to apply a voltage to an access line of the array of memory cells as part of an access operation. In some examples, the decoder can include a first conductive line configured to carry the voltage applied to the access line of the array of memory cells, and a doped material extending between the first conductive line and the access line of the array of memory cells in a first direction away from a surface of the substrate, the doped material configured to selectively couple the first conductive line of the decoder with the access line of the array of memory cells.

[0100] In some examples, the device can include a contact extending between the doped material and the access line of the array of memory cells, where the doped material selectively couples the first conductive line of the decoder with the contact. In some examples, the doped material is directly coupled with the first conductive line.

[0101] In some examples, the decoder can include a conductive material coupled with the doped material and configured to carry a second voltage for causing the doped material to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. In some examples, the conductive material is directly coupled with a surface of the doped material. In some examples, the conductive material extends in a second direction parallel to the surface of the substrate.

[0102] In some examples, the decoder can include a second conductive line configured to carry the second voltage for causing the doped material to selectively couple the first conductive line of the decoder with the access line of the array of memory cells. In some examples, the decoder can include a contact extending between the second conductive line and the conductive material, the contact configured to carry the second voltage from the second conductive line to the conductive material as part of the access operation.

[0103] In some examples, the doped material and the conductive material comprise a transistor configured to selectively couple a first conductive line of a decoder and an access line of an array of memory cells. In some examples, the doped material extends orthogonally from a plane defined by a surface of a substrate. In some examples, the doped material has a first doped region and a second doped region, where the first doped region is a first distance from the surface of the substrate and the second doped region is a second distance from the surface of the substrate different from the first distance. In some examples, the doped material is polysilicon. In some examples, the array of memory cells comprises self-selecting memory cells.

[0104] In some examples, an apparatus or device can perform aspects of the functions described herein. The device can include a substrate and a decoder coupled with the substrate and configured to select a memory cell as part of an access operation. In some examples, the decoder can include a first conductive line configured to carry a voltage for selecting a memory cell as part of an access operation and a doped material extending between the first conductive line and a contact coupling the decoder with the memory cell and configured to selectively couple the first conductive line with the contact as part of the access operation.

[0105] In some examples, the first conductive line is directly coupled with the doped material. In some examples, the decoder can include a conductive material coupled with the doped material and configured to carry a second voltage for causing the doped material to selectively couple a first conductive line of the decoder with a memory cell. In some examples, the conductive material extends parallel to a plane defined by a surface of a substrate.

[0106] In some examples, the decoder can include a second conductive line configured to carry a second voltage for causing the doped material to selectively couple a first conductive line of the decoder with an access line of a memory cell. In some examples, the doped material is polysilicon and extends orthogonally from a plane defined by a surface of a substrate.

[0107] In some examples, an apparatus or device can perform aspects of the functions described herein. The device can include a substrate, a memory cell array coupled with the substrate and comprising a first set of access lines and a second set of access lines, a first decoder coupled with the substrate and the memory cell array, the first decoder configured to apply a first voltage to a first access line of the first set as part of an access operation, and a second decoder coupled with the substrate and the memory cell array, the second decoder configured to apply a second voltage to a second access line of the second set as part of the access operation. In some examples, the first decoder can include a first conductive line configured to carry the first voltage for the first access line as part of the access operation, and a doped material extending between the first conductive line and one of the first set of access lines in a first direction perpendicular to a surface of the substrate, the doped material configured to selectively couple the first conductive line with the first access line as part of the access operation.

[0108] In some examples, the second decoder can include a second conductive line configured to carry the second voltage for selecting a memory cell of the memory cell array as part of the access operation, and a second doped material extending between the second conductive line and one of the second set of access lines of the memory cell array in a first direction perpendicular to a surface of the substrate, the second doped material configured to selectively couple the second conductive line with the second access line of the memory cell array as part of the access operation.

[0109] In some examples, the second decoder can include a second conductive line configured to carry the second voltage for selecting a memory cell of the memory cell array as part of the access operation, and a second doped material extending in a second direction parallel to a surface of the substrate, the second doped material configured to selectively couple the second conductive line with the second access line of the memory cell array as part of the access operation.

[0110] In some examples, the first decoder is positioned between the substrate and the memory cell array. In some examples, the memory cell array is positioned between the substrate and the first decoder. In some examples, the first decoder comprises a plurality of nMOS transistors and the second decoder comprises a plurality of pMOS transistors. In some examples, the first set of access lines comprises word lines. In some examples, the memory cell array comprises a cross-point architecture, a pillar architecture, or a planar architecture.

[0111] In some examples, an apparatus or device can perform aspects of the functionality described herein. The device can include a decoder configured to apply a voltage as part of an access operation of a memory cell. The decoder can include a first conductive line configured to carry a voltage for selecting a memory cell as part of an access operation, a doped material coupled with the first conductive line and a contact, the doped material configured to selectively couple the first conductive line with the contact, and a controller. In some examples, the controller can be operable to select a memory cell by applying a first voltage to a first conductive line of a decoder as part of an access operation of a memory cell, couple the first conductive line of the decoder with an access line associated with the memory cell based at least in part on selecting the memory cell, and apply the first voltage to the memory cell based at least in part on coupling the first conductive line of the decoder with the access line.

[0112] In some examples, the controller can be operable to apply a second voltage to a second conductive line of the decoder as part of the access operation, the second voltage for causing the doped material to selectively couple the first conductive line of the decoder with the access line associated with the memory cell, where applying the first voltage to the memory cell is based at least in part on applying the second voltage to the second conductive line.

[0113] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some drawings can illustrate signals as single signals; however, it will be understood by one of ordinary skill in the art that the signals can represent a bus of signals, where the bus can have a variety of bit widths.

[0114] The terms "in electronic communication," "in conductive contact," "connected," and "coupled" can refer to a relationship between components in which the components support signal flow between them. Components are considered to be in electronic communication (or in conductive contact or connected or coupled) with each other if there is any conductive path between the components that can support signal flow between the components at any given time. The conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other can be open or closed based on the operation of the device that includes the connected components at any given time. The conductive path between connected components can be a direct conductive path between the components or the conductive path between connected components can be an indirect conductive path that can include intervening components such as switches, transistors, or other components. In some cases, signal flow between connected components can be interrupted for a period of time using, for example, one or more intervening components such as switches or transistors.

[0115] The term "coupled" refers to a condition prior to which an open circuit relationship exists between components from which signals cannot be passed between the components via a conductive path, and after which a closed circuit relationship exists between the components from which signals can be passed between the components via a conductive path. When a component (e.g., a controller) couples other components together, the component initiates a change that allows signals to flow between the other components via a conductive path through which signals were not previously allowed to flow.

[0116] As used herein, the term "substantially" means, in reference to a given property, characteristic, parameter or other metric, that the given property, characteristic, parameter or other metric is at least close to a desired amount or level, and that variations, if any, are minimal, where typically specific values or ranges are provided elsewhere herein.

[0117] As used herein, the term "electrode" can refer to an electrical conductor and, in some cases, can function as an electrical contact to other components of a memory cell or memory array. An electrode can include a trace, metal line, conductive line, conductive layer, or the like that provides an electrically conductive path between elements or components of the memory array 102.

[0118] Devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate can be a silicon-on-insulator (SOI) substrate (such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or sub-regions of the substrate can be controlled by doping using various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed during initial formation or growth of the substrate by ion implantation or by any other doping means.

[0119] The description set forth herein, in connection with the appended drawings, describes and discloses embodiments that encompass one or more features. The term "embodiment" as used herein means "serving as an example, instance, or illustration" and not "preferred" or "comprising preferred aspects only." The implementations are presented for purposes of providing an understanding of the described technology. However, it is apparent that these technologies can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the concepts of the described embodiments.

[0120] In the drawings, like reference numerals can be used to denote similar components throughout the several views. Further, various components of the same type can be distinguished by following the convention of using a leading prime superscript to indicate variations. If only the first reference numeral is used in the specification, the description can be applicable to any one of the similar components having the same first reference numeral irrespective of the second reference numeral.

[0121] Information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof.

[0122] The various illustrative blocks and modules described in connection with the disclosure herein can be implemented or performed with a general-purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor can be a microprocessor, but in the alternative, the processor can be any processor, controller, microcontroller, or state machine. A processor can also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration).

[0123] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Other examples and implementations are within the scope of the disclosure and appended claims. For example, due to the nature of software, functions described above can be implemented using software executed by a processor, hardware, firmware, hardwiring, or combinations of any of these. Features implementing functions can also be physically located at various positions, including being distributed such that portions of functions are implemented at different physical locations. Also, as used herein including in the claims, “or” as used in a list of items prefaced by “at least one of’ indicates a disjunctive list such that, for example, a list of “at least one of A, B, or C” means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Also, as used herein, the phrase “based on” shall not be construed as a reference to a closed set of conditions. For example, an instance step described as being “based on” condition A can be based on both conditions A and B without departing from the scope of the present disclosure. In other words, as used herein, the phrase “based on” shall be construed in the same manner as the phrase “based at least in part on.”

[0124] Computer-readable media includes both non-transitory computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A non-transitory storage medium can be any available medium that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, non-transitory computer-readable media can include RAM, ROM, electrically erasable programmable read only memory (EEPROM), compact disk (CD) ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other non-transitory medium that can be used to carry or store desired program elements in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, include CD, laser disc, optical disc, digital versatile disc (DVD), floppy disk and Blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above are also included within the scope of computer-readable media.

[0125] The description herein is presented to enable a person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other variations without departing from the scope of the disclosure. Thus, the disclosure is not to be limited to the examples and designs described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device, comprising: an array of memory cells; and a first decoder coupled with the array of memory cells, the first decoder comprising: a first conductive line; a first doped material extending in a first direction between the first conductive line and a first contact coupled with an access line of the array of memory cells; and a second decoder coupled with a substrate, the second decoder comprising: a second conductive line; and a second doped material extending between the second conductive line and a second contact, wherein a length of the second contact is different than a length of the first contact.

2. The memory device of claim 1, wherein the first decoder is configured to apply a voltage to the access line of the array of memory cells as part of an access operation.

3. The memory device of claim 2, wherein the first conductive line is configured to carry the voltage applied to the access line of the array of memory cells.

4. The memory device of claim 1, wherein the first doped material is configured to selectively couple the first conductive line of the first decoder with the access line of the array of memory cells.

5. The memory device of claim 1, wherein the first decoder is coupled with the substrate, and wherein the first doped material extends in the first direction away from a surface of the substrate.

6. The memory device of claim 1, wherein the first conductive line is directly coupled with an oxide of the first doped material.

7. The memory device of claim 1, wherein the first doped material has a first doped region and a second doped region, wherein the first doped region is a first distance from a surface of the substrate and the second doped region is a second distance from the surface of the substrate.

8. The memory device of claim 7, wherein the first doped region comprises a third doped material and the second doped region comprises a fourth doped material that is the same as the third doped material.

9. The memory device of claim 1, wherein each memory cell of the array of memory cells comprises a chalcogenide material.

10. A memory device, comprising: a first decoder coupled with a substrate and configured to select a memory cell as part of an access operation, the first decoder comprising: a first conductive line; a first doped material extending between the first conductive line and a first contact, the first contact coupling the first decoder with the memory cell; and a second decoder coupled with the substrate, the second decoder comprising: a second conductive line; and a second doped material extending between the second conductive line and a second contact, wherein a length of the second contact is different than a length of the first contact.

11. The memory device of claim 10, wherein the first conductive line is configured to carry a voltage for selecting the memory cell as part of the access operation.

12. The memory device of claim 10, wherein the first doped material is configured to selectively couple the first conductive line with the first contact as part of the access operation.

13. The memory device of claim 10, wherein the first doped material extends orthogonally from a plane bounded by a surface of the substrate.

14. The memory device of claim 10, further comprising: a third decoder coupled with the substrate, the third decoder comprising: a third conductive line; and a third doped material extending between the third conductive line and a third contact, wherein a length of the third contact is different than the length of the second contact.

15. The memory device of claim 10, further comprising: a third doped material extending between a third conductive line and a third contact, wherein the first contact, the second contact, and the third contact are configured in a staggered configuration.

16. The memory device of claim 10, wherein the memory cells comprise a chalcogenide material.

17. A memory device, comprising: an array of memory cells; and a first decoder coupled with a substrate and the array of memory cells, the first decoder comprising: a first conductive line; and a first doped material extending between the first conductive line and a first contact coupled with an access line of a first set of access lines in a first direction perpendicular to a surface of the substrate; and a second decoder coupled with the substrate and coupled with the array of memory cells, the second decoder comprising: a second conductive line; and a second doped material extending between the second conductive line and a second contact, wherein a length of the second contact is different than a length of the first contact.

18. The memory device of claim 17, wherein the first decoder is configured to apply a first voltage to a first access line of the first set of access lines as part of an access operation.

19. The memory device of claim 18, wherein the first conductive line is configured to carry the first voltage for the first access line as part of the access operation.

20. The memory device of claim 18, wherein the first doped material is configured to selectively couple the first conductive line with the first access line as part of the access operation.

21. The memory device of claim 17, wherein the second decoder is configured to apply a second voltage to a second access line of a second set of access lines as part of an access operation.

22. The memory device of claim 17, wherein the array of memory cells is positioned between the substrate and the first decoder and the second decoder.

23. The memory device of claim 17, wherein the first decoder and the second decoder are positioned between the array of memory cells and the substrate.

24. The memory device of claim 17, wherein each memory cell of the array of memory cells comprises a chalcogenide material.

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