Memory cell arrangement and method thereof

Abstract

Aspects relate to a memory cell arrangement including: a plurality of ferroelectric memory cells; and control circuitry configured to cause a write of one or more first memory cells via a write operation, the write operation including: supplying a set of write signals to the plurality of ferroelectric memory cells to provide a write voltage drop at each of the one or more first memory cells to switch a corresponding polarization state, the set of write signals causing an interference voltage drop at one or more second memory cells not intended to be written, the interference voltage drop causing interference to the one or more second memory cells and maintaining a corresponding polarization state; and wherein the control circuitry is further configured to supply a set of anti-interference signals to the plurality of ferroelectric memory cells, the set of anti-interference signals providing an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the set of write signals.

Description

TECHNICAL FIELD

[0001] Aspects relate to a memory cell arrangement and a method thereof, such as a method of operating a memory cell arrangement. BACKGROUND ART

[0002] Generally, various computer memory technologies have been developed in the semiconductor industry. The basic building block of a computer memory can be referred to as a memory cell. A memory cell can be an electronic circuit configured to store at least one piece of information (e.g., bit by bit). The information stored in a memory cell can be obtained by determining which of the possible memory states the memory cell is in. Currently, various types of memory cells can be used to store data. For example, one type of memory cell can include a thin film of a ferroelectric material, whose polarization state can be changed in a controlled manner to store data in the memory cell, e.g., in a non-volatile manner. Memory cells can be integrated with one or more logic circuits on, for example, a wafer or a chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] In the drawings, the same reference numerals generally refer to the same parts throughout the different views. The drawings are not necessarily drawn to scale; rather, emphasis is generally placed on illustrating the principles of the invention.

[0004] In the following description, various aspects of the invention are described with reference to the following drawings, in which:

[0005] Figure 1 Schematically shows a capacitive memory structure according to various aspects;

[0006] Figure 2 Schematically shows an equivalent circuit diagram of a memory cell including a capacitive memory structure according to various aspects;

[0007] Figure 3 Shows a schematic diagram of a memory cell arrangement according to various aspects;

[0008] Figure 4A Shows a memory cell arrangement in schematic form according to various aspects;

[0009] Figure 4B Shows a graph associated with a set of write signals according to various aspects;

[0010] Figure 4C Shows a memory cell arrangement in schematic form according to various aspects;

[0011] Figure 4D Shows a graph associated with a set of anti-interference signals according to various aspects;

[0012] Figure 5A , Figure 5B , Figure 5C and Figure 5D each show a memory cell arrangement according to various aspects in schematic form;

[0013] Figure 6A , Figure 6B , Figure 6C and Figure 6D each show a memory cell arrangement according to various aspects in schematic form;

[0014] Figure 7A and Figure 7B each show a memory cell arrangement according to various aspects in schematic form; and

[0015] Figure 8 shows a schematic flow chart of a method of writing one or more memory cells according to various aspects. DETAILED DESCRIPTION

[0016] The following detailed description refers to the accompanying drawings, which illustrate by way of illustration specific details and aspects in which the present invention may be practiced. The aspects are described in sufficient detail to enable those skilled in the art to practice the present invention. Without departing from the scope of the present invention, other aspects may be utilized and structural, logical, and electrical changes may be made. The aspects are not necessarily mutually exclusive, as some aspects may be combined with one or more other aspects to form new aspects. The aspects are described in connection with methods and are also described in connection with devices (e.g., memory cell arrangements, memory cells, or control circuits). However, it will be understood that aspects described in connection with methods may be similarly applied to devices and vice versa.

[0017] In the semiconductor industry, the integration of non-volatile memory technology can be useful for system-on-chip (SoC) products such as microcontrollers (MCUs). According to various aspects, the non-volatile memory can be integrated near the processor cores of a processor. As another example, one or more non-volatile memories can be used as part of a mass storage device. In some aspects, the non-volatile memory technology can be based on at least one field-effect transistor (FET) structure. In some aspects, a memory cell can include a field-effect transistor structure and a capacitive memory structure (also referred to herein as a memory capacitor) coupled to the field-effect transistor structure. The amount of charge stored in the capacitive memory structure can affect the threshold voltage of the field-effect transistor structure. The threshold voltage of the field-effect transistor structure can define the memory state in which the memory cell resides. In some aspects, the capacitive memory structure can be a ferroelectric capacitor structure (FeCAP) coupled to the gate electrode of the field-effect transistor structure to provide a ferroelectric field-effect transistor (FeFET) structure. Because a ferroelectric material (or more generally, a spontaneously polarizable material) can have at least two stable polarization states, it can be used to non-volatilely change the threshold voltage of the field-effect transistor; thus, it can be used to transform the field-effect transistor into a non-volatile field-effect transistor-based memory structure. In other aspects, the non-volatile memory technology can be based on at least one capacitive memory structure. The capacitive memory structure can be or can include a ferroelectric capacitor structure. The ferroelectric material can transform the ferroelectric capacitor structure into a non-volatile capacitor-based memory structure, for example, by controlling the amount of charge stored in the capacitor structure. The amount of charge stored in the capacitive memory structure can be read out by a suitable electronic readout circuit (e.g., by a charge-voltage converter) by determining the switching current of the capacitive memory structure.

[0018] The terms "spontaneously polarizable," "capable of spontaneous polarization," or "spontaneous polarization" can be used herein to refer to the polarization ability of a material that exceeds dielectric polarization. The coercivity of a material can be a measure of the reverse polarization electric field strength required to eliminate the remanent polarization, if any.

[0019] According to various aspects, by way of example, a memory cell, a layer can include or can be made of a polarizable material, e.g., a spontaneously polarizable material (e.g., antiferroelectric and / or ferroelectric material). An antiferroelectric material can exhibit hysteresis in polarization (voltage-dependent), however, in the absence of a voltage drop across the antiferroelectric material, there is no remaining polarization. A ferroelectric material can exhibit hysteresis in polarization (voltage-dependent), however, in the absence of a voltage drop across the ferroelectric material, a remaining polarization still exists. The spontaneous polarization (e.g., remaining or non-remaining spontaneous polarization) can be evaluated, e.g., by analyzing one or more hysteresis measurements (e.g., hysteresis curves) in a plot of polarization P versus electric field E, where the material is polarized in opposite directions. The polarization capabilities of the material (dielectric polarization, spontaneous polarization, and remanent characteristics of polarization) can be analyzed using capacitance spectroscopy, e.g., by static (C-V) and / or time-resolved measurements, or by polarization-voltage (P-V) or positive-negative reversal (PUND) measurements.

[0020] The term "spontaneously polarizable material" or "spontaneously polarizing material" can be used herein to refer to a material that has a polarization capability in addition to its dielectric polarization capability. A spontaneously polarizable material can be or can include a spontaneously polarizable material that exhibits remanence, e.g., a ferroelectric material, and / or a spontaneously polarizable material that does not exhibit remanence, e.g., an antiferroelectric material.

[0021] The term "remanently polarized" or "remanent polarization" with respect to a layer, a portion, a structure, a memory cell (by way of example) can be understood as a layer that exhibits a remanent polarization capability (e.g., in addition to a dielectric polarization capability and / or a non-remanent polarization capability). In some aspects, a remanently polarized layer, a remanently polarized structure, a remanently polarized memory cell, a remanently polarized portion (by way of example only) can include a material that has a remanent polarization (i.e., exhibits remanence of spontaneous polarization), e.g., a ferroelectric material. In other aspects, a remanently polarized layer, a remanently polarized structure, a remanently polarized memory cell, a remanently polarized portion (by way of example only) can include a material that is spontaneously polarized and does not exhibit remanence, e.g., an antiferroelectric material under additional conditions where measures are implemented to create an internal electric field within the antiferroelectric material. The internal electric field within the antiferroelectric material can be caused (e.g., applied, generated, maintained, by way of example) in various ways, e.g., by implementing a floating node that can be charged to a voltage different from zero volts, e.g., by implementing a charge storage layer, e.g., by using a doped layer, e.g., by using an electrode layer that adapts the electron work function to create an internal electric field, by way of example only.

[0022] Typically, remanent polarization (also referred to as ferroelectricity or remanence) can exist in a material layer if the material layer can retain polarization when the applied electric field (E) is reduced to zero. Thus, a specific value of the electric polarization (P) of the material layer can be detected. Illustratively, when the electric field is reduced to zero, the polarization remaining in the material can be referred to as remanent polarization (also referred to herein as residual polarization). The remanence of a material can be a measure of the residual polarization in the material in the absence of an applied electric field. Typically, ferroelectricity and antiferroelectricity can be concepts that describe the remanent polarization of a material, similar to ferromagnetism and antiferromagnetism which are used to describe remanent magnetization in magnetic materials.

[0023] In the following, various aspects of memory cells and / or capacitive memory structures are described with reference to exemplary types of memory cells and / or capacitive memory structures. It should be understood that, generally, a memory structure as described herein (e.g., a spontaneous polarization memory structure) can be a functional component that allows for the provision of various types of memory cells, e.g., Figure 1 the capacitive memory cells exemplarily shown in Figure 2 , e.g., the field-effect transistor-based capacitive memory cells exemplarily shown in CAP , or any other type of memory cell. According to various aspects, a memory structure can include one or more electrodes and at least one memory layer coupled to the one or more electrodes, the memory layer including a spontaneous polarization material. In some aspects, the memory structure can be or can include any type of capacitive memory structure (C

[0024] ). A capacitive memory structure per se can be understood as a memory cell. For example, an array of capacitive memory structures can be arranged as memory cells and addressed via control lines. In other aspects, a capacitive memory structure can be used in combination with a transistor to serve as a memory cell, e.g., the gate of an FET is coupled to an electrode of the capacitive memory structure, or the capacitive memory structure is included (e.g., integrated) in the gate structure of an FET.

[0025] In some aspects, a memory cell circuit (e.g., including one memory cell) or a memory cell arrangement (e.g., including an array of multiple memory cells) can operate based on one or more write operations (e.g., programming and / or erasing operations) and / or one or more read operations. For example, during a write operation, a predetermined voltage can be provided to a wire (also referred to as a control line or a driver line), where the wire can be connected to a corresponding terminal of a memory cell (e.g., each memory cell) to allow a desired operation. The wire can be referred to as, for example, a word line, a source line, and / or a bit line.

[0026] One method of programming and / or erasing multiple memory cells can be a “one-third (1 / 3) voltage scheme”. Such a 1 / 3 voltage scheme can achieve that only one-third of the programming voltage (the programming voltage can also be referred to as the write voltage) is substantially exceeded at the terminals corresponding to one or more memory cells intended to be written (e.g., programmed or erased). All memory cells not intended to be written can experience a voltage that is at least substantially equal to or less than one-third of the programming voltage. The programming voltage can be defined by the type and / or design of the memory cell. In some aspects, the programming voltage can be in the range from about 1V to about 10V. The programming voltage can be determined by one or more electrical measurements. Various timings can be used to provide the corresponding voltages, e.g., to provide a desired write voltage and / or a desired read voltage.

[0027] Various aspects can be based on the recognition that performing a write operation on one or more memory cells in a memory cell arrangement (illustratively, one or more “actively addressed” memory cells, also referred to herein as active memory cells) can also have an impact on other memory cells in the memory cell arrangement that are not the (intentional) objects of the write operation (memory cells that are not written and not intended to be written, but are “passively affected” other memory cells, also referred to herein as passive memory cells).

[0028] Providing one or more write voltages to a (active) memory cell intended to be written may inherently cause one or more voltage drops at a (passive) memory cell not intended to be written. Illustratively, the active memory cell and the passive memory cell may share one or more control lines (e.g., may be connected to one or more same control lines), such that supplying one or more (write) voltages to the active memory cell may inherently include supplying one or more voltages to the passive memory cell. One or more voltages supplied to the passive memory cell during the writing of the active memory cell may provide a corresponding voltage drop at the passive memory cell (e.g., a voltage drop across the corresponding spontaneous polarization memory layer). Such a voltage drop may be referred to herein as an "interference voltage drop". An interference voltage drop may be understood as a voltage drop (unintentionally) provided at another memory cell of a memory cell arrangement during a write operation performed on a memory cell of the memory cell arrangement.

[0029] An interference voltage drop may have a negative impact on the characteristics of a memory cell and, illustratively, may cause interference to the memory cell. The impact of an interference voltage drop on a memory cell may depend on the type of the memory cell (e.g., n-type or p-type) and the memory state in which the memory cell is located (e.g., HVT state or LVT state), as described in further detail below.

[0030] For example, an interference voltage drop may increase the magnitude of the remanent polarization associated with a memory cell (e.g., the remanent polarization of a spontaneous polarization memory layer), resulting in a so-called "imprint" or "imprint effect". The imprint may cause the memory state in which the memory cell is located to be superior to any other possible memory state (e.g., more energetically favorable). The presence of an imprinted memory state may be harmful to future write operations performed on the memory cell. For example, a larger voltage drop may be required to switch the memory state of an imprinted memory cell.

[0031] As another example, an interference voltage drop may reduce the magnitude of the remanent polarization associated with a memory cell (e.g., the remanent polarization of a spontaneous polarization memory layer). The overall polarization of a memory layer may be defined by the individual contributions of the grains forming the layer. A memory layer in a polarized state may be understood as a combination (e.g., sum or superposition) of the individual polarizations of the grains forming the memory layer that define that polarized state. Some grains of the memory layer may be in an unstable polarized state, e.g., may be in a state unstable to switching. An interference voltage drop may cause an undesired switching (in other words, an undesired flip) of the polarization state of the weakly polarized grains of the memory layer, thereby reducing the overall polarization. The reduction of the overall polarization may be harmful to the reading of the memory cell, e.g., in the case where the magnitude of the polarization of the memory layer is no longer sufficient to define the desired threshold voltage associated with that memory state.

[0032] Hereinafter, a decrease in the magnitude of the remanent polarization (e.g., of a memory layer) may simply be referred to as a decrease in remanent polarization. In a similar manner, an increase in the magnitude of the remanent polarization (e.g., of a memory layer) may simply be referred to as an increase in remanent polarization.

[0033] The effect of the interference voltage drop on the memory cells accumulates over time. Illustratively, consecutive write operations performed on memory cells of a memory cell arrangement may provide consecutive interference voltage drops on other memory cells, thereby providing an increasingly large decrease or an increasingly large increase in the magnitude of the remanent polarization associated with said other memory cells.

[0034] Aspects may relate to an anti-interference operation to be performed on memory cells of a memory cell arrangement, such as an anti-interference operation performed on one or more other memory cells that are disturbed during the writing of one or more memory cells of the memory cell arrangement. The anti-interference operation may be configured to compensate for (e.g., counteract, reduce, or eliminate) the effect of interference caused by the writing of another memory cell at a memory cell. Illustratively, the anti-interference operation may be configured to compensate for a decrease in remanent polarization (e.g., by partially polarizing the memory cell) or an increase in remanent polarization (e.g., by partially depolarizing the memory cell) associated with the disturbed memory cell. In aspects, the anti-interference operation may include providing an anti-interference voltage drop at one or more memory cells of the memory cell arrangement that have been disturbed during the writing of one or more other memory cells of the memory cell arrangement. The anti-interference voltage drop may be configured to counteract the effect of the interference voltage drop experienced by one or more memory cells during the writing of one or more other memory cells.

[0035] Aspects relate to a control circuit configured to perform write operations and anti-interference operations on memory cells of a memory cell arrangement. The anti-interference operation may include supplying a set of anti-interference signals (e.g., which includes one or more anti-interference voltages) to the memory cells of the memory cell arrangement to compensate for the effect of a previously performed write operation. The anti-interference operation may cause a controlled (weak) polarization or (weak) depolarization of the spontaneously polarizable memory layer of the memory cells disturbed in the previous write operation, e.g., without switching the memory state in which the memory cells are located and only compensating for the polarization or depolarization of the previously experienced interference.

[0036] The anti-interference operation may illustratively include providing an anti-interference voltage drop at one or more memory cells of the memory cell arrangement to weakly polarize or weakly depolarize the corresponding memory layer, thereby compensating for the (respective) depolarization or polarization of the memory layer caused by a (previous) write operation (e.g., a previous write operation for writing to one or more other memory cells of the memory cell arrangement).

[0037] According to various aspects, a memory cell arrangement may include: a plurality of ferroelectric memory cells; and a control circuit configured to cause a write of one or more first memory cells among the plurality of ferroelectric memory cells via a write operation, wherein the write operation includes: supplying a set of write signals to the plurality of ferroelectric memory cells to provide a write voltage drop at each of the one or more first memory cells, thereby causing each of the one or more first memory cells to enter one of at least two memory states by switching a respective polarization state of each of the one or more first memory cells, the set of write signals causing (e.g., inadvertently providing) an interference voltage drop at one or more second memory cells among the plurality of ferroelectric memory cells that are not intended to be written, wherein the interference voltage drop causes interference to the one or more second memory cells and maintains a respective polarization state of each of the one or more second memory cells; and wherein the control circuit is further configured to supply a set of anti-interference signals to the plurality of ferroelectric memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the set of write signals.

[0038] According to various aspects, a memory cell arrangement may include: a first set of ferroelectric memory cells and a second set of ferroelectric memory cells, wherein the memory cells in the first set of memory cells correspond to a first word line, and wherein the memory cells in the second set of memory cells correspond to a second word line; and a control circuit configured to: cause a write of one or more memory cells in the first set of memory cells via a write operation, wherein the write operation includes supplying a set of write signals to the first set of memory cells and the second set of memory cells, wherein the set of write signals provides a write voltage drop at each of the one or more memory cells in the first set of memory cells that are intended to be written, thereby causing the one or more memory cells to enter one of at least two memory states by switching a respective polarization state of each of the one or more memory cells, wherein the set of write signals causes interference at the memory cells in the second set of memory cells that are not intended to be written; and wherein the control circuit is further configured to supply a set of anti-interference signals to the first set of memory cells and the second set of memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at each memory cell in the second set of memory cells to at least partially compensate for the interference caused by the set of write signals.

[0039] According to various aspects, a memory cell arrangement may include: a plurality of memory cells, each memory cell including a respective ferroelectric memory layer, and control circuitry configured to: cause a write operation of one or more first memory cells among the plurality of memory cells, wherein the write operation of the one or more first memory cells causes interference to one or more second memory cells among the plurality of memory cells that are not written, and compensate for the interference caused by the write operation of the one or more first memory cells by polarizing or at least partially depolarizing the ferroelectric memory layers of the one or more second memory cells.

[0040] According to various aspects, a memory cell arrangement may include: a first ferroelectric memory cell and a second ferroelectric memory cell, and control circuitry configured to: cause a write operation of the first memory cell, wherein the write operation of the first memory cell causes interference to the second memory cell, and compensate for the interference caused by the write operation of the first memory cell by polarizing or at least partially depolarizing the second memory cell (at least partially).

[0041] According to various aspects, a method of operating a memory cell arrangement is provided, the memory cell arrangement including a plurality of memory cells, each memory cell including a (respective) ferroelectric memory layer, the method including: causing a write operation of one or more first memory cells among the plurality of memory cells by a write operation, wherein the write operation includes supplying a set of write signals to the plurality of memory cells, wherein the set of write signals provides a write voltage drop at the one or more first memory cells to cause the one or more first memory cells to enter one of at least two memory states by polarizing the respective ferroelectric memory layers, wherein the set of write signals causes an interference voltage drop at one or more second memory cells among the plurality of memory cells that are not written, the interference voltage drop causing interference to the one or more second memory cells; and supplying a set of anti-interference signals to the plurality of memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to compensate for the interference caused by the set of write signals.

[0042] According to various aspects, a method of operating a memory cell arrangement is provided, the memory cell arrangement including a plurality of ferroelectric memory cells, the method including: partially polarizing or partially depolarizing one or more second memory cells among the plurality of ferroelectric memory cells to compensate for the corresponding partial depolarization or partial polarization caused by a write operation of one or more first memory cells among the plurality of ferroelectric memory cells.

[0043] The term "switching" can be used herein to describe a change in polarization, such as a change in the polarization of a ferroelectric memory layer. For example, the polarization of a ferroelectric memory layer can be switched such that the polarization changes from pointing in a first direction to pointing in an opposite (second) direction, e.g., the sign of the polarization changes from positive to negative or from negative to positive, while the absolute value of the polarization can remain substantially unchanged in some respects. The term "switching" can also be used herein to describe a change in the memory state of a memory cell. For example, in the case where a memory cell is in a first memory state (e.g., the LVT state), the memory state of the memory cell can be switched such that after the switching, the memory cell can be in a second memory state different from the first memory state (e.g., the HVT state). Thus, the term "switching" can be used herein to describe a change in the memory state of a memory cell from a first memory state to a second memory state. The term "flipping" and its variants can be used herein in the same manner as the term "switching" and its variants.

[0044] The term "voltage" can be used herein relative to "one or more write voltages", "one or more anti-disturbance voltages", "one or more disturbance voltages", "one or more gate voltages", "base voltage", "one or more source / drain voltages", etc. As an example, the term "gate voltage" can be used herein to denote the voltage provided to, for example, the gate node or gate terminal of a transistor or a memory cell. As another example, the term "base voltage" can be used herein to denote the reference voltage and / or reference electric potential of a circuit. In terms of a circuit, the base voltage can also be referred to as the ground voltage, ground electric potential, virtual ground voltage, or zero volts (0V). The base voltage of a circuit can be defined by the power supply used to operate the electronic circuit. As another example, the term "source / drain voltage" can be used herein to denote the voltage provided at, for example, the source / drain node or source / drain terminal of a transistor or a memory cell.

[0045] The voltage provided at a node of a circuit can be defined relative to the base voltage of the circuit (referred to as V B) is defined by the corresponding electric potential applied to the node. In addition, the voltage drop provided at a certain component (e.g., at a memory cell, at a capacitive memory structure, at a field effect transistor structure, etc.) can describe the difference between two voltages / electric potentials provided at that component (e.g., directly or indirectly provided). For example, the voltage drop provided at a component can include the difference between two voltages / electric potentials provided at two different nodes or terminals of that component. As another example, the voltage drop provided at a component can include the difference between two voltages / electric potentials provided at two different positions in a circuit, which results in a voltage drop across that component (e.g., via one or more additional components). For example, the voltage drop associated with two different nodes of a circuit can be defined by the corresponding voltages / electric potentials applied at these two nodes. As an example, the gate-source voltage drop associated with a gate structure (e.g., the gate structure of a transistor or a memory cell) can be defined by the corresponding voltages / electric potentials applied at the corresponding gate node and source node of the gate structure. The gate-source voltage drop can also be referred to as the gate-source voltage V GS . In the case where the source voltage is zero, such as that used in a conventional driving scheme for writing and / or reading a field effect transistor-based memory cell, the gate-source voltage drop and the gate-source voltage V GS can be referred to as the gate voltage V G .

[0046] In some aspects, two voltages can be compared with each other by relative terms such as "greater", "higher", "lower", "smaller", or "equal", for example. It should be understood that in some aspects, the comparison can include the sign (positive or negative) of the voltage value, or in other aspects, the comparison of the absolute voltage value (also referred to as the magnitude or amplitude, e.g., the magnitude or amplitude of a voltage pulse) can be considered. As an example, a memory cell based on an n-type or p-type field effect transistor can have a first threshold voltage (also referred to as the low threshold voltage (V L-th )) and a second threshold voltage (also referred to as the high threshold voltage (V H-th ). In the case of a memory cell based on an n-type field effect transistor (n-FET), with respect to the voltage value and the absolute voltage value, the high threshold voltage V H-th can be greater than the low threshold voltage V L-th (e.g., only as a numerical example, V L-th can be 1V, while V H-th can be 3V), or only with respect to the voltage value, the high threshold voltage V H-th can be greater than the low threshold voltage V L-th (e.g., only as a numerical example, V L-th can be -1V, while V H-th can be 1V, or V L-th can be -2V, while VH-th can be 0 V, or V L-th can be -3 V, while V H-th can be -1 V). In the case of a memory cell based on a p-type field-effect transistor (p-FET), the high threshold voltage V H-th can be lower than the low threshold voltage V with respect to the voltage value L-th and higher than the low threshold voltage V with respect to the absolute voltage value L-th (e.g., by way of numerical example only, V L-th can be -1 V, while V H-th can be -3 V), or only with respect to the voltage value, the high threshold voltage V H-th can be lower than the low threshold voltage V L-th (e.g., by way of numerical example only, V L-th can be 1 V, while V H-th can be -1 V, or V L-th can be 2 V, while V H-th can be 0 V, or V L-th can be 3 V, while V H-th can be 1 V).

[0047] Figure 1 illustrates the schematic functionality of a capacitive memory structure 100 in accordance with various aspects. The capacitive memory structure 100 can include one or more electrodes 102, 106 (e.g., one or more electrode layers, such as Figure 1 the first electrode 102 and the second electrode 106 in the configuration of CAP .) and a memory element 104 coupled to the one or more electrodes 102, 106. The memory element 104 can include or can be a memory layer disposed between two electrode layers 102, 106. The memory element 104 can include or can be composed of a ferroelectric material. Accordingly, the capacitive memory structure 100 can have a capacitance C associated therewith

[0048] In some aspects, the capacitive memory structure 100 itself can be used as a memory cell in a memory cell arrangement. In other aspects, the capacitive memory structure 100 can be coupled to or integrated in another device, such as a field effect transistor, and the combination of the capacitive memory structure 100 and the other device can be used as a memory cell in a memory cell arrangement. A memory element that includes or consists of a ferroelectric material may be referred to as a ferroelectric memory element. A memory layer that includes or consists of a ferroelectric material may be referred to as a ferroelectric memory layer (e.g., in the case of a remanent polarization material, referred to as a remanent polarization memory layer). According to various aspects, the memory element 104 can include one or more memory layers. As an example, the ferroelectric memory element 104 can include one or more ferroelectric memory layers. Hereinafter, a reference to a memory layer (e.g., memory layer 104) can be understood to apply to a ferroelectric memory layer (e.g., a ferroelectric memory layer or an antiferroelectric memory layer).

[0049] At least one memory element 104 can include any type of ferroelectric material, such as a ferroelectric material, an antiferroelectric material, a ferroelectric-like material, an antiferroelectric-like material, etc. At least one memory element 104 can be a memory layer of the capacitive memory structure 100 to store information, for example, through at least two remanent polarization states of the at least one memory element 104. Programming of the capacitive memory structure 100 (illustratively, storing information therein) can be performed by providing an electric field at the capacitive memory structure, such as an electric field between the first electrode 102 and the second electrode 106 (e.g., the potential difference between a first node and a second node associated with the first electrode 102 and the second electrode 106, respectively, to provide a voltage drop across the memory element 104), so as to set or change the remanent polarization state of the at least one memory element 104.

[0050] The capacitive memory structure 100 including the memory element 104 can be used to implement a storage function. Features and functions described herein with reference to a memory cell (e.g., with reference to a FeFET) can be implemented in the capacitive memory structure 100 (e.g., in a FeCAP) in the same or similar manner, and the capacitive memory structure 100 can act as a memory cell.

[0051] In various aspects, the polarization state of the memory element 104 can be switched by the capacitor structure. The polarization state of the memory element 104 can also be read out by the capacitor structure. The polarization state of the memory element 104 can define the memory state. As an example, the polarization state of the spontaneous polarization memory layer 104 can determine the amount of charge stored in the capacitor structure. The amount of charge stored in the capacitor structure can be used to define the memory state (e.g., a first amount of charge stored in the capacitor structure, such as less than 500 μC (but not limited to such a value), can define a first memory state, such as an LVT state, and a second amount of charge stored in the capacitor structure, such as greater than 500 μC (but not limited to such a value), can define a second memory state, such as an HVT state). For example, a memory cell including the capacitive memory structure 100 can be operated without including a field effect transistor structure in the memory cell, for example, without basing the operation on a change in the threshold voltage of the field effect transistor structure.

[0052] Figure 2 FIG. 2 shows an equivalent circuit of a memory cell 200 including a field effect transistor structure 200a and a capacitive memory structure 200b according to various aspects. The capacitive memory structure 200b may be as described with reference to FIG. Figure 1 The capacitive memory structure 100 shown is configured as described, for example, including one or more electrodes 102, 106 and a memory element 104 coupled to the one or more electrodes 102, 106 (e.g., including a first electrode 102, a second electrode 106, and a spontaneous polarization memory layer 104 disposed between the first electrode 102 and the second electrode 106). In some aspects, the field effect transistor structure 200a (e.g., the gate stack 208 of the field effect transistor structure 200a, also referred to as a gate structure) can be coupled to the capacitive memory structure 200b. In other aspects, the capacitive memory structure 200b can be integrated into the field effect transistor structure 200a, for example, integrated within the gate stack 208 of the field effect transistor structure 200a.

[0053] The field effect transistor structure 200a may include a gate structure 208, wherein the gate structure 208 may include a gate isolation 204 and a gate electrode 206. The gate structure 208 is illustratively shown as a planar gate stack; however, it is understood that Figure 2 The planar configuration shown is one example, and other field effect transistor designs may include a gate structure 208 having a non-planar shape, such as a trench gate transistor design, a vertical field effect transistor design, or other designs.

[0054] The gate structure 208 may define a channel region 202, which is disposed, for example, in a semiconductor portion (e.g., in a semiconductor layer, in a semiconductor die, etc.). The gate structure 208 may allow controlling the electrical behavior of the channel region 202 (e.g., the resistance R), and for example, may control (e.g., allow, increase, prevent, decrease, etc.) the current in the channel region 202. In some aspects, the gate structure 208 may, for example, allow controlling (e.g., allowing or preventing) the source / drain current I from the first source / drain region of the field-effect transistor structure 200a to the second source / drain region of the field-effect transistor structure 200a SD (The source / drain is disposed in or adjacent to the channel, but not shown in Figure 2 ). The channel region 202 and the source / drain regions may be formed, for example, by doping one or more semiconductor materials or by using an intrinsically doped semiconductor material within and / or on a layer

[0055] Regarding the operation of the field-effect transistor structure 200a, a voltage may be provided at the gate electrode 206 to control the current I in the channel region 202 SD , and the current I in the channel region 202 SD is caused by the voltage provided through the source / drain regions. The gate electrode 206 may include a conductive material (e.g., a metallic material). In some aspects, the gate electrode 206 may be coupled to the capacitive memory structure 200b (e.g., may be coupled to an electrode of the capacitive memory structure, such as the first electrode 102). According to various aspects, the gate isolation 204 may be configured to provide electrical isolation between the gate electrode 206 and the channel region 202, and is also configured to affect the channel region 202 via the electric field generated by the gate electrode 206. As an example, the gate isolation 204 may include one or more electrically insulating layers

[0056] As an example, the gate electrode 206 of the field-effect transistor structure 200a may be conductively connected (e.g., ohmically) to the first electrode of the capacitive memory structure 200b. As another example, the first electrode of the capacitive memory structure 200b may be in direct physical contact with the gate electrode 206 of the field-effect transistor structure 200a. As another example, the capacitive memory structure 200b and the field-effect transistor structure 200a may share a common electrode, which serves as the gate electrode of the field-effect transistor structure 200a and the electrode of the capacitive memory structure 200b

[0057] As Figure 2 shown in the equivalent circuit of FET , a first capacitor CFET , the capacitor originates from more or less conductive regions (channel region 202 and gate electrode 206) separated from each other by gate isolation 204. The channel region 202 can be considered as the first capacitor electrode, the gate electrode 206 can be considered as the second capacitor electrode, and the gate isolation 204 can be considered as the dielectric between the two capacitor electrodes. In some aspects, the field effect transistor structure 200a and the capacitive memory structures 100, 200b can be coupled (e.g., electrically connected) to each other to provide a capacitive voltage divider, as Figure 2 shown by the equivalent circuit in. The channel or body node of the field effect transistor structure 200a can provide or be connected to the first node, the electrodes of the capacitive memory structures 100, 200b can provide or be connected to the second node, and the intermediate conductive part (electrode, layer, etc.) can provide or be connected to the floating intermediate node.

[0058] According to various aspects, a ferroelectric material can be used as part of the capacitive memory structure of a memory cell (e.g., as part of the capacitive memory structure 100, or as part of the capacitive memory structure 200b of the memory cell 200). The ferroelectric material can be an example of the material of the memory layer (e.g., memory layer 104). Illustratively, the ferroelectric material can be used to store data in an integrated circuit in a non-volatile manner. The term "ferroelectric" can be used herein, for example, to describe a material that exhibits a hysteretic charge-voltage relationship (Q-V). Doped or substituted hafnium oxide (HfO2), doped or substituted zirconium oxide (ZrO2), or more generally, transition metal oxides (TMO) and their mixtures can exhibit a large remanent polarization under certain process conditions (e.g., Hf 0.5 Zr 0.5 O2 can have strong ferroelectric properties). However, the choice of the memory layer material is not limited to ferroelectric materials.

[0059] The material of the memory layer (e.g., as part of the capacitive memory structure 100 and / or the memory cell 200) can be or can include at least one of the following: doped transition metal oxides, undoped transition metal oxides, doped transition metal nitrides, undoped transition metal nitrides, doped metal nitrides (e.g., aluminum nitride) and / or undoped metal nitrides. For example, the material of the memory layer can be or can include hafnium oxide (ferroelectric hafnium oxide, HfO2), zirconium oxide (ferroelectric zirconium oxide, ZrO2) and / or a (ferroelectric) mixture of hafnium oxide and zirconium oxide. Ferroelectric hafnium oxide can include any form of hafnium oxide that can exhibit ferroelectric properties. Ferroelectric zirconium oxide can include any form of zirconium oxide that can exhibit ferroelectric properties. This can include, for example, a solid solution of hafnium oxide, zirconium oxide, hafnium oxide and zirconium oxide (e.g., but not limited to, a 1:1 mixture) or hafnium oxide and / or zirconium oxide doped or substituted with one or more of the following elements (non-exhaustive list): silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, zirconium, any rare earth element or any other dopant (also referred to as a dopant) suitable for providing or maintaining ferroelectricity in hafnium oxide or zirconium oxide. By way of example only, the ferroelectric material can be doped at a concentration from about 2 mole % to about 6 mole %. As another example, the material of the memory layer can be or can include scandium nitride.

[0060] According to various aspects, a memory cell (e.g., memory cells 100, 200) can have at least two different memory states associated therewith, e.g., having two different conductivities or two different stored charge amounts, and these two different conductivities or two different stored charge amounts can be determined (e.g., measured) to determine which of the at least two different memory states the memory cell is in. According to various aspects, the memory state in which the memory cell is located can be a "programmed state" or an "erased state". For example, the programmed state can be a conductive state or a state having a positive stored charge (e.g., associated with logic "1"), while the erased state can be a non-conductive state or a state having a negative stored charge (e.g., associated with logic "0"). However, the definitions of the programmed state and the erased state can be arbitrarily selected.

[0061] The remanent polarization of the memory layer can define the memory state in which the memory cell is located. According to various aspects, when the memory layer is in a first polarization state, the memory cell can be in a first memory state, and when the memory layer is in a second polarization state (e.g., opposite to the first polarization state), the memory cell can be in a second memory state.

[0062] The threshold voltage of a field effect transistor structure (e.g., field effect transistor structure 200a) can vary with the amount and / or polarity of charge stored in a capacitive memory structure, e.g., based on the polarization state of a memory layer of the capacitive memory structure. A first threshold voltage, e.g., a low threshold voltage V L-th , can be associated with a first polarization state (e.g., associated with a first amount and / or polarity of stored charge), and a second threshold voltage, e.g., a high threshold voltage V H-th , can be associated with a second polarization state (e.g., associated with a second amount and / or polarity of stored charge). Illustratively, a first memory state can be associated with the first threshold voltage (e.g., the first memory state can be referred to as an LVT state), and a second memory state can be associated with the second threshold voltage (e.g., the second memory state can be referred to as an HVT state).

[0063] According to various aspects, writing a memory cell or performing a write operation on a memory cell can include an operation or process of modifying the memory state in which the memory cell is located from (e.g., a first) memory state to another (e.g., a second) memory state. According to various aspects, writing a memory cell can include programming the memory cell (e.g., performing a programming operation on the memory cell), where the memory state in which the memory cell is located after programming can be referred to as a "programmed state". For example, programming an n-type FET-based memory cell can modify the state in which the memory cell is located from an HVT state to an LVT state, while programming a p-type FET-based memory cell can modify the state in which the memory cell is located from an LVT state to an HVT state. According to various aspects, writing a memory cell can include erasing the memory cell (e.g., performing an erase operation on the memory cell), where the memory state in which the memory cell is located after erasing can be referred to as an "erased state". For example, erasing an n-type FET-based memory cell can modify the state in which the memory cell is located from an LVT state to an HVT state, while erasing a p-type FET-based memory cell can modify the state in which the memory cell is located from an HVT state to an LVT state.

[0064] Reading out a memory cell including a field effect transistor structure (e.g., reading out memory cell 200) can include providing a read voltage drop at the memory cell and measuring the current output from the memory cell (e.g., the source-drain current). The memory state in which the memory cell is located can be determined based on the measured current. In the case where the memory cell is in a non-conductive state (e.g., in an HVT state), a first (relatively low) amount of current can be measured, while in the case where the memory cell is in a conductive state (e.g., in an LVT state), a second (relatively high) amount of current can be measured.

[0065] Figure 3 An exemplary configuration of a memory cell arrangement 300 according to various aspects is schematically shown. The memory cell arrangement 300 may include a plurality of memory cells 302, such as a plurality of ferroelectric memory cells 302. In Figure 3 a simplified representation, only two memory cells (a first memory cell 302w and a second memory cell 302d) are shown to illustrate the principle of the anti-interference operation. However, it should be understood that the memory cell arrangement 300 may include any number of memory cells (e.g., to achieve a desired storage size). The memory cells 302 (e.g., at least one or each of the memory cells 302) may be configured with respect to Figure 1 and Figure 2 the capacitive memory structure 100 and / or the memory cell 200 described. Illustratively, each memory cell 302 may include a corresponding ferroelectric memory layer.

[0066] Various aspects may be based on the recognition that in the memory cell arrangement 300, the addressing (e.g., writing) of one or more memory cells 302 may also have an impact on other memory cells 302 that are not intended to be written. Illustratively, the addressing of an “active” memory cell may affect the characteristics (e.g., the remanent polarization) of other “passive” memory cells that are not the intended target of the write operation. Hereinafter, the writing of the (first) memory cell 302w and the interference of another (second) memory cell 302d (the interfered memory cell 302d) may be referred to. The addressing of the memory cell 302w may “interfere” with another memory cell 302d and, over time, cause an undesired polarization or depolarization of another memory cell (e.g., the memory layer of another memory cell 302d). However, it should be understood that the aspects described herein may be correspondingly applicable to the writing of more than one memory cell 302w (e.g., the simultaneous writing of two, three, four, five, or more than five memory cells 302w) and the interference (and anti-interference) of more than one memory cell 302d (e.g., the simultaneous interference of two, three, four, five, or more than five memory cells 302d). The interference of “passive” memory cells related to the writing of “active” memory cells will be described in more detail with reference to Figures 4A to 4D

[0067] ​In various aspects, the memory cell arrangement 300 may be configured to perform an anti-interference operation (e.g., after a write operation, e.g., less than 1 minute later, or less than 10 seconds later, or less than 500 ms later), where anti-interference is provided at a memory cell 302d that is affected by the write of another memory cell 302w (or other memory cells) during a write operation. The anti-interference operation may be configured to at least partially address the undesired polarization or depolarization of the passive memory cell 302d by providing a corresponding depolarization or polarization of the passive memory cell 302d (e.g., of the corresponding memory layer).

[0068] According to various aspects, the memory cell arrangement 300 may include control circuitry 304 configured to perform and / or direct one or more write operations associated with writing to the memory cells 302 of the memory cell arrangement 300. The control circuitry 304 may also be configured to perform and / or direct one or more anti-interference operations on the memory cells 302 of the memory cell arrangement 300. Examples of write operations and anti-interference operations will be described in more detail with respect to Figures 4A to 4D Simply put, the control circuitry 304 may be configured to provide a set of write signals 306w to the memory cells 302 of the memory cell arrangement 300 to cause a write to one or more memory cells 302 (e.g., memory cell 302w), and the circuitry 304 may be configured to supply a set of anti-interference signals 306c to the memory cells 302 of the memory cell arrangement 300 to address interference at one or more memory cells 302 (e.g., at memory cell 302d). As an example, the control circuitry 304 may include or may control one or more voltage supply circuits. The one or more voltage supply circuits may be used to supply control voltages (e.g., write voltages and anti-interference voltages) to control lines of the memory cell arrangement 300 ( Figure 3 not shown), e.g., to supply voltages to respective control nodes of the memory cells 302 ( Figure 3 not shown). According to various aspects, the control circuitry 304 may define a base voltage V B , e.g., a ground voltage (e.g., 0V) (the base voltage V B may also be referred to herein as the base voltage V ref ).

[0069] The control circuit 304 can be configured to cause a write operation of one or more (first) memory cells 302w of the plurality of memory cells 302. The write operation can include supplying a set of write signals 306w to the plurality of memory cells 302 (e.g., a set of voltages, e.g., one or more voltages supplied to one or more memory cells 302w intended to be written, one or more voltages supplied to one or more other memory cells 302d not intended to be written, as described in further detail below). The set of write signals 306w can provide a write voltage drop at one or more (first) memory cells 302w intended to be written, thereby causing the memory cells 302w to enter one of at least two memory states by switching the respective polarization states of each of the one or more first memory cells (e.g., by polarizing the respective memory layer, e.g., the respective spontaneous polarization memory layer). The write voltage drop can be understood as the voltage drop provided at the memory cell 302w that has a sufficient magnitude (in other words, sufficient amplitude) to switch the polarization state (and thus the memory state) in which the memory cell 302w is (or was prior to the provision of the write voltage drop), e.g., switching the polarization from a positive remanent polarization to a negative remanent polarization, or vice versa. The write voltage drop can include a voltage drop that provides an electric field equal to or greater than the coercive field at the memory cell 302w for switching the polarization of the memory cell.

[0070] Each aspect can be based on the recognition that the set of write signals 306w can cause an (interference) voltage drop at one or more other (e.g., second) memory cells 302d of the plurality of memory cells 302 that are not intended to be written. The interference voltage drop can cause interference at the other (passive) memory cells 302d. As an example, the interference caused by the interference voltage drop can include a reduction in the remanent polarization associated with the passive memory cell 302d (e.g., a reduction in the remanent polarization of the respective memory layer). Illustratively, the interference voltage drop can at least partially depolarize each passive memory cell 302d, e.g., the respective memory layer of the passive memory cell 302d. As another example, the interference caused by the interference voltage drop can include an increase in the remanent polarization associated with the passive memory cell 302d (e.g., an increase in the remanent polarization of the respective memory layer). Illustratively, the interference voltage drop can at least partially polarize each passive memory cell 302d, e.g., the respective memory layer of the passive memory cell 302d (illustratively, can cause a polarization imprint). Generally, the interference caused by the interference voltage drop can include a change in the magnitude of the remanent polarization associated with each respective one of the one or more passive (second) memory cells 302d.

[0071] The interference voltage drop can be understood as the voltage drop at the memory cell 302d, which causes a partial change in the polarization state of the memory cell 302d without fully switching the polarization state. The interference voltage drop can maintain the respective polarization states of each of one or more second memory cells 302d. Illustratively, the interference voltage drop may not switch the respective memory states of the passive memory cells 302d. For example, the interference voltage drop (provided by the voltage included in the write signal set 306w) may have an amplitude insufficient to switch the polarization state of the passive memory cell 302d. In various aspects, the amplitude of the interference voltage drop can be less than the amplitude of the write voltage drop (e.g., the amplitude of the interference voltage drop can be a fraction of the amplitude of the write voltage drop, such as one-half, one-third, or one-sixth, by way of example).

[0072] The increase or decrease in the residual polarization associated with the passive memory cell 302d provided by the interference voltage drop can depend on the memory state of the passive memory cell 302. Illustratively, in the case where the passive memory cell 302d is in a memory state associated with polarization oriented in a first direction, an interference voltage drop providing an electric field oriented in the first direction across the memory layer will increase the residual polarization of the memory cell. An interference voltage drop providing an electric field oriented in a second direction (opposite to the first direction) across the memory layer, conversely, will decrease the residual polarization of the memory cell. Accordingly, in the case where the passive memory cell 302d is in a memory state associated with polarization oriented in the second direction, the electric field in the second direction will increase the residual polarization, while the electric field in the first direction will decrease the residual polarization of the memory cell.

[0073] As an example, in the case where the passive memory cell 302d has a positive residual polarization (e.g., the memory cell is in the LVT state), an interference voltage drop with a positive polarity (e.g., for an n-type memory cell) can increase the residual polarization of the memory cell 302d, and an interference voltage drop with a negative polarity can decrease the residual polarization of the memory cell 302d. As another example, in the case where the passive memory cell 302d is in a memory state associated with negative residual polarization (e.g., in the HVT state), an interference voltage drop with a negative polarity (e.g., for an n-type memory cell) can increase the residual polarization of the memory cell 302d, and an interference voltage drop with a positive polarity can decrease the residual polarization of the memory cell 302d. In both cases, as described above, a deterioration in the storage characteristics of the memory cell can be observed.

[0074] In various aspects, the presence of interference voltage drops at memory cells 302d that are not intended to be written may be related to a write signal set 306w that includes, for example, one or more suppression voltages provided at those memory cells 302d. Illustratively, in addition to merely holding the memory cells 302d that are not intended to be written at a base voltage V B (e.g., 0V), the write operation may further include supplying one or more suppression voltages (e.g., having different magnitudes relative to the base voltage V B ) to those memory cells 302d. The one or more suppression voltages may be configured to ensure that the memory state of the passive memory cells 302d is not switched during the write operation. However, as described above, the one or more suppression voltages may interfere with the passive memory cells 302d.

[0075] According to various aspects, the control circuit 304 may be configured to perform an anti-interference operation to at least partially compensate for the interference caused to the passive memory cells 302d. The control circuit 304 may be configured to provide an anti-interference signal set 306c to the plurality of memory cells 302 (e.g., including one or more voltages provided at the memory cells 302w that were written in a previous write operation and one or more voltages provided at the memory cells 302d that were interfered with in a previous write operation). The anti-interference signal set 306c may provide an anti-interference voltage drop at the passive memory cells 302d (e.g., a corresponding anti-interference voltage drop at each of the one or more second memory cells 302d) to at least partially compensate for the interference caused by the write signal set 306w.

[0076] The anti-interference signal set 306c may be configured according to the write signal set 306w (e.g., configured to vary with the write signal set 306w). Illustratively, the anti-interference signal set 306c may be configured to provide, during the write operation, at the passive memory cells 302d, (corresponding) anti-interference voltage drops having opposite polarities relative to the interference voltage drops provided at those memory cells.

[0077] will be further described in detail with respect to Figures 4A to 4D and an exemplary configuration of the memory cell arrangement, the supply of the write signal set 306w and the anti-interference signal set 306c having exemplary voltage values.

[0078] Figure 4A and Figure 4C schematically shows during the write operation according to various aspects ( Figure 4A ) and during the anti-interference operation ( Figure 4C) memory cell arrangement 400. The memory cell arrangement 400 may include a plurality of (spontaneously polarized) memory cells 402. The memory cell arrangement 400 may be an exemplary configuration of the memory cell arrangement 300, and the memory cells 402 may be an exemplary configuration of the memory cells 302 described with respect to Figure 3 described memory cell 302.

[0079] The memory cells 402 may be arranged, for example, in a matrix architecture. The memory cells 402 may be arranged in n columns and m rows, where m and n are integers equal to or greater than 1. Figure 4A and Figure 4C shows four columns (e.g., the first to fourth columns) and two rows (e.g., the first row and the second row) of the memory cell arrangement 400, with each column including two memory cells 402, which is only an example. The memory cell arrangement 400 may include any suitable number of memory cells 402, which are arranged in any suitable number n of columns and any suitable number m of rows.

[0080] At least one (e.g., more than one or each) of the plurality of memory cells 402 may include one or more control nodes. As an example, each memory cell 402 may include at least a second control node 404s, a third control node 404d, and a first control node 404w to control the electrical behavior (e.g., the current between the second control node 404s and the third control node 404d) of the second control node 404s and the third control node 404d of the memory cell 402.

[0081] According to various aspects, at least one (e.g., more than one or each) of the plurality of memory cells 402 may be a field-effect transistor (FET)-based memory cell, for example, may include a field-effect transistor structure, and may include two source / drain regions and a gate region (also referred to as a gate structure) to control the current between the two source / drain regions. As an example, the memory cell 402 may include a gate node 404w, a source node 404s, and a drain node 404d. The gate node 404w may be coupled to the gate region of the memory cell 402. The source node 404s may be coupled to the source region of the memory cell 402. The drain node 404d may be coupled to the drain region of the memory cell 402.

[0082] It should be understood that, in some aspects, multiple memory cells 402 (e.g., at least one or each memory cell 402) may include only a capacitive memory structure without a field effect transistor structure, as described above. In such a configuration, the control node of the memory cell 402 may be coupled to one or more electrodes of the capacitive memory structure. As an example, in such a configuration of the memory cell 402, the memory cell arrangement 400 may include a cross arrangement, where each electrode of the memory cell 402 is connected to a corresponding control line.

[0083] According to various aspects, the memory cell arrangement 400 may include multiple control lines (e.g., multiple word lines WL, multiple bit lines BL, and multiple source lines SL) coupled to the memory cells 402. The control lines may be used to supply voltage to the control nodes of the memory cells 402. The multiple control lines may be arranged in any suitable manner defined by the desired architecture of the memory cell arrangement 400 (e.g., by the desired matrix setting of the memory cells 402). As an example, the first control node 404w of each memory cell 402 may be connected to a corresponding word line WL, the second control node 404s of each memory cell 302 may be connected to a corresponding source line SL, and the third control node 404d of each memory cell 302 may be connected to a corresponding bit line BL. Each memory cell 402 of the multiple memory cells 402 may be explicitly assigned to one word line WL, one source line SL, and one bit line BL (in other words, assigned to a source line / bit line pair).

[0084] In the case where the memory cell 402 includes a field effect transistor structure, the corresponding source / drain regions of the field effect transistor structure may be connected to the source line / bit line pair corresponding to the memory cell 402. For example, one of the two source / drain regions of the field effect transistor structure may be connected to the bit line BL in the corresponding source line / bit line pair, while the other of the two source / drain regions of the field effect transistor structure may be connected to the source line SL in the corresponding source line / bit line pair. The portion of the memory cell 402 connected to the corresponding word line WL may depend on the architecture of the memory cell 402. As an example, in the case where the memory cell 402 includes a capacitive memory structure coupled to the field effect transistor structure, the capacitive structure may be connected to the corresponding word line WL. As another example, in the case where the memory cell 402 includes a capacitive memory structure included (e.g., integrated) in the gate structure of the field effect transistor structure, the gate structure may be connected to the corresponding word line WL.

[0085] Multiple memory cells 402 may be arranged such that a control line may be shared by more than one memory cell 402 (e.g., shared by memory cells 402 disposed in the same row or the same column of the memory cell arrangement 400). Each source line / bit line pair may be coupled to each memory cell 402 in the same column of memory cells 402, and each word line WL may be coupled to each memory cell 402 in the same row of memory cells 402.

[0086] In accordance with various aspects, at least one (e.g., more than one or each) memory cell 402 may include an additional (e.g., fourth) control node. In such a case, the memory cell 402 may be assigned to an additional (e.g., fourth) control line, e.g., assigned to an additional word line WL (not shown). A four-terminal memory cell (also referred to as a four-node memory cell or a four-terminal device) may be, for example, a ternary memory cell (e.g., a ternary content addressable memory (TCAM) cell).

[0087] In various aspects, the memory cells 402 of the memory cell arrangement 400 may be logically (and in some aspects, spatially) divided into one or more sets 406 (in other words, one or more groups) of memory cells 402, e.g., two sets 406(1), 406(2) in the Figure 4A and Figure 4C configuration. A set of memory cells may be understood to form one or more memory cells 402 of a standard cell for storing information. In some aspects, a set of memory cells 402 may be understood as a “word,” as is known in the art, e.g., a set of memory cells 402 (each representing an “information bit”) that may be addressed as a unit (exemplarily, together, in parallel). In the Figure 4A and Figure 4C configuration, a set of memory cells may include memory cells 402 disposed adjacent to each other in the memory cell arrangement 400; however, it should be understood that a set of memory cells may also include memory cells 402 that are not adjacent to each other (e.g., may be formed by memory cells that are not adjacent to each other), as long as the memory cells 402 of the set may be addressed as a unit (as another example, a set of memory cells may include every two memory cells 402 in the same row, or every three memory cells 402 in the same row).

[0088] Depending on the desired architecture, e.g., depending on the desired processing of data stored in the memory cell arrangement 400, the set of memory cells can include any suitable number of memory cells 402. As a numerical example, the set of memory cells can include one, two, four, eight, sixteen, thirty-two, or sixty-four memory cells 402 (e.g., providing a one-bit word, two-bit word, four-bit word, eight-bit word, sixteen-bit word, thirty-two-bit word, or sixty-four-bit word, respectively).

[0089] The memory cells 402 in the set of memory cells can correspond to the same word line WL (e.g., the respective gate nodes 404w of each memory cell 402 in the set of memory cells can be connected to the same word line WL). This can provide for addressing the memory cells 402 of the set 406 as a single unit (e.g., by providing a common control signal, such as a common voltage, at the respective gate nodes 404w). In some aspects, more than one set of memory cells can correspond to the same word line WL, e.g., multiple sets of memory cells can be addressed via the same word line WL. In such a configuration, depending on the logic architecture of the memory cell arrangement 400, the sets of memory cells corresponding to the same word line WL can still be considered separate sets of memory cells (e.g., as separate words).

[0090] The memory cells 402 in different sets of memory cells can share the same source line / bit line pair, e.g., memory cells 402 of different sets arranged along the same column can correspond to the same source line SL and the same bit line BL. In Figure 4A and Figure 4C the configuration of, at least one (e.g., more than one or each) memory cell 402 of the first set 406(1) and at least one (e.g., more than one or each) memory cell 402 of the second set 406(2) can correspond to the same source line / bit line pair (the same bit line BL(1) and the same source line SL(1), the same bit line BL(2) and the same source line SL(2), etc.).

[0091] Memory cells 402 of different sets 406 connected to the same control line can be such that supplying one or more voltages to one or more memory cells of one set 406 inherently includes supplying one or more voltages to one or more memory cells of another set 406, e.g., providing the above-mentioned interference during a write operation.

[0092] Hereinafter, with respect to Figure 4A and Figure 4BDescribe a write operation where the memory cell 402w at position (1,1) in the memory cell 402 array is considered the memory cell to be written. However, it should be understood that the aspects described herein related to the memory cell 402w can be correspondingly applied to each memory cell intended to be written (e.g., the same write voltage drop can be provided at each memory cell intended to be written). In some aspects, one or more (first) memory cells intended to be written can be part of the same memory cell set (e.g., the first set 406(1), e.g., the same word).

[0093] A set of write signals (e.g., the set of write signals 306w) can include one or more voltages V1, V2, V3, V4 supplied to the control lines of the memory cell arrangement 400 (and thus to the corresponding control nodes of the memory cells 402). The set of write signals can include one or more voltages V1, V3 that are supplied to the control lines corresponding to one or more (first) memory cells intended to be written (e.g., supplied to the first word line WL(1), the first source line SL(1), and the first bit line BL(1) corresponding to the memory cell 402w intended to be written in the Figure 4A configuration). The set of write signals can include one or more voltages V2, V4 that are supplied to the control lines corresponding to other memory cells 402 of the memory cell arrangement 400, illustratively corresponding to the control lines of one or more (second) memory cells 402 (one or more passive, disturbed memory cells 402d) of the memory cell arrangement 400 that are not written (and not intended to be written) during the write operation.

[0094] One or more voltages V1, V3 supplied to the control lines corresponding to one or more (first) memory cells intended to be written can be configured (e.g., selected) to provide a write voltage drop at those memory cells 402w. One or more voltages V2, V4 supplied to the control lines corresponding to one or more (second) memory cells 402d not intended to be written can be configured to provide a voltage drop that does not switch the memory state in which those memory cells 402d are located.

[0095] Figure 4BIllustrated is a graph 410w associated with a set of write signals according to various aspects. The graph 410w shows exemplary voltage values of voltages V1, V2, V3, V4 supplied to the control lines of the memory cell arrangement 400 for writing one or more (first) memory cells (e.g., memory cell 402w). The graph 410w shows exemplary voltage values for transitioning the memory cell 402w to a first memory state, such as an erase operation 412w (to write a logic “0”), and exemplary voltage values for transitioning the memory cell 402w to a second memory state, such as a program operation 414w (to write a logic “1”). In Figure 4B (and below with respect to Figure 4D ), a scheme based on a 1 / 3 relationship between voltages is described. However, it should be understood that the 1 / 3 relationship is merely an example of a possible ratio between voltages provided at different control lines, and other relationships are possible (e.g., as other examples, a 1 / 2 relationship or a 1 / 6 relationship).

[0096] The set of write signals can include a first voltage V1 supplied to a (first) word line WL(1) corresponding to the memory cell 402w intended to be written (e.g., corresponding to one or more first memory cells 402w intended to be written). In some aspects, the first voltage V1 can be supplied to each memory cell 402 in the set of memory cells to which the memory cell 402w to be written belongs. Illustratively, the set of memory cells can include one or more (first) memory cells 402w intended to be written, and one or more (second) memory cells not intended to be written. The same (first) voltage can be provided to the memory cells of the set, and writing to the memory cells not intended to be written can be prevented by providing appropriate (inhibiting) voltages at the corresponding bit lines and source lines. In some aspects, the first voltage V1 can be provided to each memory cell corresponding to the first word line, such as also to memory cells belonging to other sets, the writing of which can be prevented by providing appropriate (inhibiting) voltages at the corresponding bit lines and source lines (e.g., see Figure 5A and Figure 5C ).

[0097] The set of write signals can include a second voltage V2 supplied to a (second) word line WL(2) corresponding to one or more (second) memory cells 402d not intended to be written. Illustratively, the second voltage V2 can be supplied to each word line WL in the set of memory cells not intended to be written.

[0098] The write signal set may include a third voltage V3 that is supplied to one or more source line / bit line pairs corresponding to memory cells 402w intended to be written (e.g., corresponding to one or more first memory cells). The third voltage V3 may also be provided at each memory cell 402 in the same column as the memory cell 402w intended to be written, e.g., also provided to memory cells 402d not intended to be written (e.g., memory cells 402d in another set of memory cells). Writing to those memory cells 402d may be prevented by providing an appropriate (second) voltage V2 at the corresponding word line WL(2).

[0099] The write signal set may include a fourth voltage V4 that is supplied to one or more source line / bit line pairs corresponding to one or more (second) memory cells 402d not to be written that do not share the corresponding source line / bit line pair with the memory cell 402w intended to be written (e.g., not sharing with one of one or more first memory cells). The fourth voltage V4 may be provided at memory cells in the same set as the memory cell 402w intended to be written, as well as at memory cells in other sets of memory cells.

[0100] To write to the memory cell 402w, the write voltage drop (e.g., the magnitude of the write voltage drop) may correspond to the absolute value of the magnitude of the write voltage V W . The polarity of the voltage drop may define which memory state the memory cell 402w can be written to. The write voltage V W may be understood as the magnitude to be provided for switching the polarization state (and thus the memory state) of the memory cell 402w.

[0101] In the Figure 4A and Figure 4B illustrated configuration, the absolute value of the difference between the first voltage V1 and the third voltage V3 may correspond to the write voltage V W . As an example, to write a "0" (e.g., in the case of an n-type memory cell 402w), the third voltage V3 may correspond to the write voltage V W , and the first voltage V1 may correspond to the base voltage V B . As an example, to write a "1" (e.g., in the case of an n-type memory cell 402w), the first voltage V1 may correspond to the write voltage V W , and the third voltage V3 may correspond to the base voltage V B . Illustratively, at least one of the first voltage V1 or the third voltage V3 may include the base voltage V B , while the other of the first voltage V1 or the third voltage V3 may include the write voltage VW It should be understood that other voltages may be provided as the first voltage V1 and the third voltage V3, as long as the magnitude of the provided write voltage drop is equal to or greater than the absolute value of the write voltage V W .

[0102] To prevent the writing of memory cells 402d that are not intended to be written, the voltage supplied to the corresponding control lines (as part of the set of write signals) can be configured such that the voltage drop at those memory cells is less than the write voltage V W , for example such that the voltage drop at those memory cells is approximately 1 / 3 of the write voltage V W , as an exemplary ratio.

[0103] The absolute value of the difference between the second voltage V2 and the fourth voltage V4 can be in the range of 0 to 1 / 3 of the write voltage V W . As an example (during the writing of "0"), the second voltage V2 can include a voltage corresponding to 2 / 3 of the write voltage V W , while the fourth voltage V4 can include a voltage corresponding to 1 / 3 of the write voltage V W . As another example (during the writing of "1"), the second voltage V2 can include a voltage corresponding to 1 / 3 of the write voltage V W , while the fourth voltage V4 can include a voltage corresponding to 2 / 3 of the write voltage V W .

[0104] Accordingly, the absolute value of the difference between the second voltage V2 and the third voltage V3 can be in the range of 0 to 1 / 3 of the write voltage V W . As an example (during the writing of "0"), the second voltage V2 can include a voltage corresponding to 2 / 3 of the write voltage V W , while the third voltage V3 can include the write voltage V W . As another example (during the writing of "1"), the second voltage V2 can include a voltage corresponding to 1 / 3 of the write voltage V W , while the third voltage V3 can include the base voltage V B .

[0105] In Figure 4A and Figure 4B the configuration shown, the absolute value of the difference between the first voltage V1 and the second voltage V2 can be 2 / 3 of the write voltage V W . Such a ratio, combined with the voltages V3, V4 provided at the source line / bit line pair, can cause the memory cells 402d that are not intended to be written to not be written in practice. As an example, in the case where the first voltage V1 includes the base voltage V B , the second voltage V2 can include a voltage corresponding to the write voltage V WTwo-thirds of the voltage. As another example, when the first voltage V1 includes the write voltage V W in the case of, the second voltage V2 may include a voltage corresponding to one-third of the write voltage V W .

[0106] Providing voltages according to the above scheme can ensure that memory cells 402d that are not intended to be written experience a voltage drop that does not switch the corresponding memory state (illustratively, a voltage drop that maintains the corresponding memory state), however, as described above, such a voltage drop may interfere with the memory cells. Illustratively, in this scheme, the absolute value of the magnitude of the interfering voltage drop can be in the range from 0 to approximately one-third of the write voltage V W , which is not sufficient to switch the polarization state, but is sufficient to affect the memory cell 402d. As another example, the absolute value of the magnitude of the interfering voltage drop can be in the range from 0 to approximately one-half of the write voltage V W .

[0107] Hereinafter, anti-interference operations are described with respect to Figure 4C and Figure 4D , considering the write operation shown above (e.g., writing to the memory cell 402w at position (1,1)). However, it should be understood that the aspects described herein can be correspondingly applied to other write operations in which other or additional memory cells have been written.

[0108] The anti-interference signal set (e.g., anti-interference signal set 306c) can include one or more anti-interference voltages VC1, VC2, VC3, VC4, which are supplied to the control lines of the memory cell arrangement 400 (and thus to the corresponding control nodes of the memory cells 402). The anti-interference signal set can include one or more voltages VC1, VC3, which are supplied to the control lines corresponding to one or more (first) memory cells written during the write operation (e.g., the first word line WL(1), the first source line SL(1), and the first bit line BL(1) corresponding to the memory cell 402w in the configuration of Figure 4C ). The write signal set can include one or more voltages VC2, VC4, which are supplied to the control lines corresponding to other memory cells 402 of the memory cell arrangement 400, illustratively the control lines corresponding to one or more (second) memory cells 402 (one or more passive, interfered memory cells 402d) that are not written during the write operation.

[0109] One or more anti-interference voltages VC1, VC2, VC3, VC4 can be configured (e.g., selected) based on one or more voltages V1, V2, V3, V4 supplied during a previous write operation. Illustratively, one or more anti-interference voltages VC1, VC2, VC3, VC4 can be configured to provide an anti-voltage drop that at least partially compensates for the interference voltage drop caused by one or more voltages V1, V2, V3, V4 supplied during a previous write operation.

[0110] The anti-interference voltage drop at one or more disturbed memory cells 402d can have an opposite polarity relative to the corresponding interference voltage drop at those memory cells 402d. Illustratively, the anti-interference voltage drop can be configured to compensate for the interference caused by the interference voltage drop by at least partially polarizing or depolarizing the disturbed memory cells 402d, e.g., by at least partially polarizing or depolarizing the corresponding self-polarizing memory layers of the disturbed memory cells.

[0111] In various aspects, the anti-interference voltage drop at one or more disturbed memory cells 402d can have the same magnitude as the corresponding interference voltage drop at those memory cells 402d (illustratively, a magnitude with the same absolute value but opposite polarity relative to the magnitude of the corresponding interference voltage drop). As an example, the absolute value of the magnitude of the anti-interference voltage drop can be in the range of 0 to 1 / 2 (half) of the write voltage V W , e.g., in the range of 0 to 1 / 3 of the write voltage V according to a 1 / 3 scheme W . This can ensure that the interference can be compensated without switching the memory state in which those memory cells 402d are located. Illustratively, the anti-interference voltage drop can be configured to change (e.g., increase or decrease) the magnitude of the remaining polarization associated with each disturbed memory cell 402 (e.g., the magnitude of the remaining polarization of the corresponding self-polarizing memory layer) without switching the corresponding memory state (illustratively, without causing a sign inversion of the remaining polarization of the self-polarizing memory layer).

[0112] Figure 4D Graph 410c associated with a set of anti-interference signals according to various aspects is shown. Graph 410c shows exemplary voltage values of the voltages VC1, VC2, VC3, VC4 supplied to the control lines of the memory cell arrangement 400 for anti-interference operations. Graph 410c shows exemplary voltage values for compensating for the interference caused by an erase operation (anti-interference "0" 412c) and for compensating for the interference caused by a programming operation (anti-interference "1" 414c). In Figure 4DIn it, a scheme based on a 1 / 3 relationship between voltages during a previous write operation is described. However, it should be understood that the 1 / 3 relationship is merely an example, and in the case of different relationships (e.g., as another example, 1 / 2) between the voltages V1, V2, V3, V4 provided in the write operation, the anti-interference voltage can be adjusted accordingly.

[0113] The set of anti-interference signals can include a first anti-interference voltage VC1 supplied to a (first) word line WL(1) corresponding to the memory cells 402w written in the write operation (e.g., corresponding to one or more first memory cells 402w). The first anti-interference voltage VC1 can be supplied to each memory cell 402 in the set of memory cells to which the memory cells 402w written in the write operation belong. In some aspects, the first anti-interference voltage VC1 can be provided to each memory cell corresponding to the first word line WL(1).

[0114] The set of anti-interference signals can include a second anti-interference voltage VC2 supplied to a (second) word line WL(2) corresponding to one or more (second) memory cells 402d not written during the write operation. Illustratively, the second anti-interference voltage VC2 can be supplied to the word line WL corresponding to the set of memory cells not written in the previous write operation.

[0115] The set of anti-interference signals can include a third anti-interference voltage VC3 supplied to one or more source line / bit line pairs corresponding to the memory cells 402w written in the write operation (e.g., corresponding to one or more first memory cells). The third anti-interference voltage VC3 can also be supplied at each memory cell 402 disposed in the same column as the memory cells 402w written in the write operation.

[0116] The set of anti-interference signals can include a fourth anti-interference voltage VC4 supplied to one or more source line / bit line pairs corresponding to one or more (second) memory cells 402d not written, where the one or more (second) memory cells 402d do not share the corresponding source line / bit line pair with the memory cells 402w written in the write operation (e.g., with one of the one or more first memory cells). The fourth anti-interference voltage VC4 can be provided at the memory cells in the same set as the memory cells 402w written in the write operation, as well as at the memory cells in other sets of memory cells.

[0117] In various aspects, the first anti-interference voltage VC1 and the second anti-interference voltage VC2 (e.g., the anti-interference voltage supplied to the word line during the anti-interference operation) can be equal to each other. The first anti-interference voltage VC1 and the second anti-interference voltage VC2 can include a voltage corresponding to 1 / 3 of the write voltage V W Combined with the voltages supplied at the source line and the bit line, such voltage values can provide a desired anti-interference voltage drop (e.g., a 1 / 3 anti-interference voltage drop) at the memory cell.

[0118] To provide the desired anti-interference voltage drop, the difference between the first anti-interference voltage VC1 and the third anti-interference voltage VC3 can be in the range of 0 to 1 / 3 of the write voltage. Accordingly, the difference between the second anti-interference voltage VC2 and the third anti-interference voltage VC3 can be in the range of 0 to 1 / 3 of the write voltage. As an example, in the case of anti-interference after erasure, the first and second anti-interference voltages VC1, VC2 can include a voltage corresponding to 1 / 3 of the write voltage V W and the third anti-interference voltage VC3 can include a voltage corresponding to the base voltage V B As another example, in the case of anti-interference after programming, the first and second anti-interference voltages VC1, VC2 can include a voltage corresponding to 1 / 3 of the write voltage V W and the third anti-interference voltage VC3 can include a voltage corresponding to 2 / 3 of the write voltage V W

[0119] Similarly, to provide the desired anti-interference voltage drop, the difference between the first anti-interference voltage VC1 and the fourth anti-interference voltage VC4 can be in the range of 0 to 1 / 3 of the write voltage. Accordingly, the difference between the second anti-interference voltage VC2 and the fourth anti-interference voltage VC4 can be in the range of 0 to 1 / 3 of the write voltage. For example, in the case of anti-interference after erasure, the first and second anti-interference voltages VC1, VC2 can include a voltage corresponding to 1 / 3 of the write voltage V W and the fourth anti-interference voltage VC4 can include a voltage corresponding to 2 / 3 of the write voltage V W As another example, in the case of anti-interference after programming, the first and second anti-interference voltages VC1, VC2 can include a voltage corresponding to 1 / 3 of the write voltage V W and the fourth anti-interference voltage VC4 can include a voltage corresponding to 2 / 3 of the write voltage V W

[0120] It should be understood that other voltages can be provided as the first to fourth anti-interference voltages VC1, VC2, VC3, VC4 as long as the provided anti-interference voltage drop is in the range of 0 to 1 / 3 of the write voltage V W ​​​

[0121] According to the scheme described with respect to Figure 4B and Figure 4D interference at memory cells that are part of the same set of memory cells 402w being written (or intended to be written) during a write operation may not be compensated. Illustratively, in the configuration of Figures 4A to 4D memory cells of the first memory cell set 406(1) may experience the same voltage drop (e.g., having the same polarity and the same magnitude, e.g., 1 / 3 of the write voltage V W ) during a write operation and during an anti-interference operation. Illustratively, interference for portions of memory cells of other memory cell sets (e.g., the second set 406(2)) may be compensated while interference for portions of memory cells in the same set as the memory cells being written is not compensated. However, these memory cells may be written during a subsequent write operation (e.g., during the immediately subsequent write operation), such as during the write of a word, such that the interference effect may be negligible.

[0122] In addition, according to the scheme described with respect to Figure 4B and Figure 4D memory cells 402w being written during a write operation experience a voltage drop during an anti-interference operation for other memory cells 402d. Illustratively, anti-interference voltages VC1, VC2, VC3, VC4 may provide an "intentional interference" voltage drop (e.g., a voltage drop having an opposite polarity and a smaller magnitude relative to the write voltage drop) at the memory cells 402w being written during a write operation. In various aspects, such an "intentional interference" voltage drop may at least partially depolarize the spontaneous polarization memory layer of the written memory cells 402w, e.g., by switching the polarization state of weakly polarized grains. In various aspects, this may cause the memory state of the written memory cells 402w to be defined only by stable grains, thereby increasing the reliability of data retention.

[0123] Figure 5A , Figure 5B , Figure 5C and Figure 5D show successive write operations ( Figure 5B and Figure 5D ) with corresponding anti-interference operations ( Figure 5A and Figure 5C ) in a memory cell arrangement 500 according to various aspects. The memory cell arrangement 500 may be Figure 3The exemplary configuration of the memory cell arrangement 300 described in the foregoing, for example, includes a plurality of (spontaneously polarized) memory cells 502 (e.g., each memory cell includes a field effect transistor structure coupled to a capacitive memory structure) arranged in a matrix arrangement together with corresponding word lines WL, bit lines BL, and source lines SL. Each memory cell 502 may include a corresponding gate node 504w, source node 504s, and drain node 504d. The memory cells 502 may be related to Figures 3 to 4D Exemplary configurations of memory cells 302, 402 are described.

[0124] exist Figures 5A to 5D In the configuration of , the memory cell arrangement 500 may include multiple sets 506d of memory cells 502, for example, four sets 506(1), 506(2), 506(3), 506(4), each set including one or more memory cells 502. The first set 506(1) and the third set 506(3) may correspond to the first word line WL(1), and the second set 506(2) and the fourth set 506(4) may correspond to the second word line WL(2). The memory cells 502 of the first set 506(1) and the second set 506(2) may share the same bit lines BL(1), BL(2) and source lines SL(1), SL(2). The memory cells 502 of the third set 506(3) and the fourth set 506(4) may share the same bit lines BL(3), BL(4) and source lines SL(3), SL(4).

[0125] exist Figure 5A and Figure 5C , a write to a memory cell 502w of a first set 506(1) and a corresponding disturbance to other memory cells 502d of the memory cell arrangement 500 are shown.

[0126] exist Figure 5A , a logic "0" is shown written into the memory cell 502w at the position (1,1) in the memory cell arrangement 500. As described above with respect to Figure 4B As described above, writing may include providing a corresponding voltage (as part of a write signal set) to a control line of the memory cell arrangement 500. As an example, a base voltage V may be provided at the first word line WL(1). B , a write voltage V may be provided at the first bit line BL(1) and the first source line SL(1) W , a write voltage V corresponding to the write voltage V may be provided on the other bit lines BL(2), BL(3), BL(4) and the source lines SL(2), SL(3), SL(4) W 1 / 3 of the voltage, and can provide a voltage corresponding to the write voltage V WTwo-thirds of the voltage. Figure 5A The write in can correspond to writing a "0" in the first word of the memory cell arrangement 500.

[0127] In Figure 5A In the write shown, a write voltage drop (-V W ) can be provided at the memory cell 502w to be written, and a disturbance voltage drop (which has a positive or negative polarity depending on the voltage provided at the corresponding control line) can be provided at other memory cells. For example, a disturbance voltage drop with a positive polarity (+V D ) can be provided at the memory cells at positions (2, 2), (2, 3), and (2, 4) in the memory cell arrangement 500, and a disturbance voltage drop with a negative polarity (-V D ) can be provided at the memory cells at positions (1, 2), (1, 3), (1, 4), and (2, 1) in the memory cell arrangement 500.

[0128] Figure 5B Shows the anti-disturbance operation corresponding to Figure 5A the write operation. The anti-disturbance can include providing a corresponding anti-disturbance voltage (as part of a set of anti-disturbance signals) to the control lines of the memory cell arrangement 500, as described above with respect to Figure 4D . As an example, a voltage corresponding to one-third of the write voltage V W can be provided at the word lines WL(1), WL(2), a base voltage V B can be provided at the first bit line BL(1) and the first source line SL(1), a voltage corresponding to two-thirds of the write voltage V W can be provided at the other bit line BL(2) and source line SL(2) corresponding to the set 506(1) including the memory cell 502w to be written, and a voltage corresponding to one-third of the write voltage V W can be provided at the other bit lines BL(3), BL(4) and source lines SL(3), SL(4).

[0129] In Figure 5B the anti-disturbance shown, the memory cells in the memory cell sets 506(3), 506(4) that do not share bit lines and source lines with the set 506(1) including the memory cell 502w to be written do not experience a voltage drop (e.g., the generated voltage drop is 0V). Thus, the disturbance at these memory cells of the sets 506(3), 506(4) is not compensated during the anti-disturbance operation, but is "automatically" compensated during subsequent write operations, as discussed in further detail below.

[0130] In Figure 5BIn the anti-interference shown, memory cells in memory cell set 506(2) that share bit lines and source lines with a set 506(1) including the memory cell 502w being written experience an anti-interference voltage drop. For example, the cell at position (2,1) has a positive polarity, while the cell at position (2,2) has a negative polarity. Memory cells in set 506(1) including the memory cell 502w being written (the memory cell being written and other memory cells in the set) experience a (further) interference voltage drop. For example, as described above, the cell at position (1,1) has a positive polarity, while the cell at position (1,2) has a negative polarity.

[0131] In Figure 5C and Figure 5D a write of another memory cell 502w of the first set 506(1) and corresponding interference of other memory cells 502d of the memory cell arrangement 500 are shown.

[0132] In Figure 5C a write of a logic "1" in the memory cell 502w at position (1,2) in the memory cell arrangement 500 is shown (e.g., after a "0" has been written in the memory cell at position (1,1) as described in Figure 5A ). As described above with respect to Figure 4B the write may include providing corresponding voltages to the control lines of the memory cell arrangement 500. As an example, a write voltage V W may be provided at the first word line WL(1), a base voltage V B may be provided at the second bit line BL(2) and the second source line SL(2), a voltage corresponding to 1 / 3 of the write voltage V W may be provided at another word line WL(2), and voltages corresponding to 2 / 3 of the write voltage V W may be provided at the other bit lines BL(1), BL(3), BL(4) and source lines SL(1), SL(3), SL(4). Figure 5A and Figure 5C The writes in may correspond to writing "01" in the first word of the memory cell arrangement.

[0133] In Figure 5C the shown write, a write voltage drop (+V W ) may be provided at the memory cell 502w to be written, and interference voltage drops may be provided at other memory cells 502d. For example, interference voltage drops with a positive polarity (+V D ) may be provided at memory cell positions (1,1), (1,3), (1,4), (2,2), which may cancel out in Figure 5AThe disturbance at the memory cells of the third set 506(3) during writing is shown. A voltage with negative polarity (-V D ) interference voltage drop, which can offset the Figure 5A Disturbance at memory cells of the fourth set 506(4) during writing is shown. Illustratively, disturbance at memory cells of the sets 506(3), 506(4) that do not share bit lines and source lines with the set 506(1) including the memory cell 502w being written can be automatically compensated by writing a "0" and a "1" (or a "1" and then a "0"), so that further measures for those memory cells can be omitted.

[0134] Figure 5D Shows the corresponding Figure 5C The anti-disturbance operation of the write operation of the memory cell arrangement 500 may include providing a corresponding anti-disturbance voltage to the control line of the memory cell arrangement 500, as described above with respect to Figure 4D As described. As an example, a write voltage V may be provided at word lines WL(1) and WL(2). W A voltage of 1 / 3 of the write voltage V can be provided at the bit line BL(2) and the source line SL(2) corresponding to the write voltage V W , a voltage of 2 / 3 of that of the memory cell 502w to be written may be provided at the first bit line BL(1) and the first source line SL(1) corresponding to the set 506(1) including the memory cell 502w to be written. B , and a write voltage V corresponding to the write voltage V may be provided on the other bit lines BL(3), BL(4) and the source lines SL(3), SL(4) W 1 / 3 of the voltage. Figure 5B As mentioned, also in Figure 5D In the anti-disturbance shown, the memory cells of the sets 506(3), 506(4) do not experience a voltage drop because the disturbance is inherently compensated.

[0135] exist Figure 5D In the illustrated anti-disturbance, memory cells of the set 506(2) of memory cells that share bit lines and source lines with the set 506(1) including the memory cell 502w being written experience an anti-disturb voltage drop, e.g., having a positive polarity for the cell at position (2,1) and a negative polarity for the cell at position (2,2). The memory cells of the set 506(1) including the memory cell 502w being written (the memory cell being written as well as the other memory cells of the set) experience a (further) disturb voltage drop, e.g., having a positive polarity for the cell at position (1,1) and a negative polarity for the cell at position (1,2), as described above.

[0136] Figure 6A and Figure 6B illustrates a write operation for writing more than one memory cell of the same set to a memory state (e.g., an HVT state) and a corresponding anti-disturbance operation. Figure 6C and Figure 6D illustrates a write operation for writing more than one memory cell of the same set to a memory state (e.g., an LVT state) and a corresponding anti-disturbance operation.

[0137] In Figures 6A to 6D are shown write operations and anti-disturbance operations related to the memory cell arrangement 600. The memory cell arrangement 600 may be configured with respect to the memory cell arrangement 500 described in Figures 5A to 5D and may include a plurality of (spontaneously polarized) memory cells 602 (e.g., each including a field effect transistor structure coupled to a capacitive memory structure) arranged in a matrix arrangement together with corresponding word lines WL, bit lines BL, and source lines SL. Each memory cell 602 may include a corresponding gate node 604w, source node 604s, and drain node 604d. The memory cell arrangement 600 may include a plurality of sets 606 of memory cells 602, such as four sets 606(1), 606(2), 606(3), 606(4), each set including one or more memory cells 602.

[0138] In Figure 6A and Figure 6C are shown the writing of a plurality of memory cells 602w of the first set 606(1) and the corresponding disturbance of other memory cells 602d of the memory cell arrangement 600. In Figure 6A and Figure 6C are shown the writing of two memory cells 602w, however, it should be understood that the aspects described herein may be applied to the writing of more than two (e.g., each) memory cells 602 in the set 606.

[0139] In Figure 6A is shown the writing of a logic "0" to the memory cells 602w of the first set 606 (at positions (1,1) and (1,2) in the arrangement 600). As described above with respect to Figure 4B the writing may include providing a corresponding voltage (as part of a set of write signals) to the control lines of the memory cell arrangement 600. As an example, a base voltage V may be provided at the first word line WL(1) B and write voltages V may be provided at the bit lines BL(1), BL(2) and source lines SL(1), SL(2) corresponding to the first set 606 W, a voltage corresponding to 1 / 3 of the write voltage V can be provided at other bit lines BL(3), BL(4) and source lines SL(3), SL(4) of the memory cell arrangement 600, and a voltage corresponding to 2 / 3 of the write voltage V can be provided at other word lines WL(2) of the memory cell arrangement 600. W The write in W can correspond to writing "00..." in the first word of the memory cell arrangement 600. Figure 6A In the write shown in

[0140] In Figure 6A the write shown, a write voltage drop (-V W ) can be provided at the memory cell 602w to be written, and a disturbance voltage drop can be provided at other memory cells. For example, a disturbance voltage drop with a positive polarity (+V D ) can be provided at the memory cells at positions (2,3) and (2,4) in the memory cell arrangement 600, and a disturbance voltage drop with a negative polarity (-V D ) can be provided at the memory cells at positions (1,3), (1,4), (2,1) and (2,2).

[0141] Figure 6B shows an anti-disturbance operation corresponding to the write operation of Figure 6A . The anti-disturbance can include providing a corresponding anti-disturbance voltage (as part of a set of anti-disturbance signals) to the control lines of the memory cell arrangement 600, as described above with respect to Figure 4D . As an example, a voltage corresponding to 1 / 3 of the write voltage V can be provided at the word lines WL(1), WL(2), a base voltage V W can be provided at the bit lines BL(1), BL(2) and source lines SL(1), SL(2) corresponding to the first set 606, and a voltage corresponding to 1 / 3 of the write voltage V can be provided at other bit lines BL(3), BL(4) and source lines SL(3), SL(4). B W

[0142] In Figure 6B ​​In the anti-interference shown, memory cells in memory cell sets 606(3) and 606(4) that do not share bit lines and source lines with the first set 606(1) do not experience a voltage drop (e.g., the generated voltage drop is 0V). The interference at these memory cells in sets 606(3) and 606(4) can be "automatically" compensated during subsequent write operations, as described above and as discussed in further detail below. Memory cells in the second memory cell set 606(2) that share bit lines and source lines with the first set 606(1) experience an anti-interference voltage drop, e.g., with a positive polarity. The written memory cells 602w in the first set 606(1) experience an (intentional) interference voltage drop, e.g., with a positive polarity.

[0143] In Figure 6C it is shown that a logical "1" is written into the memory cells 602w of the first set 606 (at positions (1,1) and (1,2) in the arrangement 600). As an example, a base voltage V B can be provided at the bit lines BL(1), BL(2) and source lines SL(1), SL(2) corresponding to the first set 606, a write voltage V W can be provided at the first word line WL(1), a voltage corresponding to 1 / 3 of the write voltage V W can be provided at the other word line WL(2), and voltages corresponding to 2 / 3 of the write voltage V W can be provided at the other bit lines BL(3), BL(4) and source lines SL(3), SL(4) of the memory cell arrangement 600. Figure 6A The write in

[0144] In Figure 6C the shown write, a write voltage drop (V W ) can be provided at the memory cells 602w to be written, and interference voltage drops can be provided at other memory cells. For example, interference voltage drops with a positive polarity (+V D ) can be provided at the memory cells at positions (1,3) and (1,4) in the memory cell arrangement 600, and interference voltage drops with a negative polarity (-V D ) can be provided at the memory cells at positions (2,3) and (2,4), which will compensate for the interference experienced by those memory cells during the write of "00..." shown in Figure 6A . Interference voltage drops with a positive polarity (+V D ) can also be provided at the memory cells at positions (2,1) and (2,2) in the memory cell arrangement 600.

[0145] Figure 6Dillustrates an anti - interference operation corresponding to Figure 6C a write operation. The anti - interference can include providing a corresponding anti - interference voltage to a control line of the memory cell array 600. As an example, a base voltage V B can be provided at word lines WL(1), WL(2), and a voltage corresponding to 1 / 3 of the write voltage V W can be provided at bit lines BL(1), BL(2) and source lines SL(1), SL(2) corresponding to the first set 606, and a base voltage V B can be provided at other bit lines BL(3), BL(4) and source lines SL(3), SL(4).

[0146] In Figure 6D the anti - interference shown, memory cells of memory cell sets 606(3), 606(4) that do not share bit lines and source lines with the first set 606(1) do not experience a voltage drop, as described above (and can compensate for the corresponding interference when writing a "0" in the first set 606(1)). Memory cells of the second set 606(2) experience an anti - interference voltage drop, for example, with a negative polarity. The written memory cells 602w of the first set 606(1) experience an (intentional) interference voltage drop, for example, with a negative polarity.

[0147] In various aspects, as an alternative or additional method of preventing or reducing the interference effect on memory cells in a memory cell array that are not intended to be written (e.g., memory cells 302 of memory cell array 300), dedicated access transistors can be provided. Illustratively, each word line of the memory cell array can have a corresponding access transistor configured to allow or block current flow in the corresponding word line (e.g., the first word line has a corresponding first access transistor, the second word line has a second access transistor, etc.). From a different perspective, the access transistor can be configured to allow or block the provision of a voltage on the corresponding word line. The access transistor can be controlled (e.g., via a corresponding control signal provided by a control circuit of the memory cell array, such as control circuit 304) to allow or block the provision of a voltage at the gate node of the memory cell (e.g., at the gate nodes of the memory cells of a memory cell set). The access transistor can be configured to allow current to flow in the corresponding word line in a first state (open state) and block current from flowing in the corresponding word line in a second state (closed state).

[0148] In various aspects, a memory cell arrangement can include corresponding access transistors for each set of memory cells. Illustratively, each access transistor can correspond to a portion of a word line (rather than the entire word line, e.g., corresponding to the portion corresponding to the respective set) to allow or block current flow in the respective portion. Further illustratively, the word line WL can be understood as a global word line that is divided into one or more local word lines (one local word line for each set of memory cells corresponding to that global word line), and each local word line can have a corresponding access transistor. A portion of the (global) word line can be understood as a local word line. The access transistors of the local word lines corresponding to the same global word line can be connected in parallel with each other (see Figure 7A and Figure 7B ). A portion of the word line can include a connection to the respective control node (e.g., gate node) of the memory cells of the respective set of memory cells. In such a configuration, the access transistors can be configured (e.g., controlled) to allow or block addressing (e.g., writing or anti-disturbance) of the memory cells of the respective set of memory cells. This can prevent interference with the memory cells of the sets that are not being written during a write operation, illustratively by "disconnecting" such sets from the set being written.

[0149] Figure 7A and Figure 7B FIGS. show a respective write operation in a memory cell arrangement 700 including a plurality of access transistors 710 according to various aspects. The memory cell arrangement 700 can be an exemplary configuration of the memory cell arrangement 300 described with respect to Figure 3 In the configuration of Figure 7A and Figure 7B , the memory cell arrangement can include a plurality of (spontaneously polarized) memory cells 702, and the memory cells 702 include a field effect transistor structure coupled to a capacitive memory structure. However, it should be understood that a configuration including access transistors can also be provided for a memory cell arrangement including other types of memory cells (e.g., based only on a capacitive memory structure, as shown in Figure 1 ). The plurality of memory cells 702 can be an exemplary configuration of the memory cells 302 of the memory cell arrangement 300.

[0150] The memory cells 702 can be arranged in a matrix arrangement together with respective word lines WL, bit lines BL, and source lines SL. Each memory cell 702 can include a corresponding gate node 704w, source node 704s, and drain node 704d. The memory cell arrangement 700 can include a plurality of sets 706 of memory cells 702, e.g., four sets 706(1), 706(2), 706(3), 706(4), each set including one or more memory cells 702.

[0151] The memory cell arrangement 700 may include a plurality of access transistors 710, for example, each access transistor 710 corresponds to a respective set 706 of memory cells 702 (e.g., four access transistors 710(1), 710(2), 710(3), 710(4) in the configuration of Figure 7A and Figure 7B ), for example, each access transistor 710 corresponds to a respective local word line of the global word lines WL(1), WL(2) of the memory cell arrangement 700. The memory cell arrangement 700 may include one or more additional control lines (referred to herein as access lines AL) corresponding to the plurality of access transistors 710. The access transistors 710 corresponding to a set of memory cells 702 sharing the same source line / bit line pair may correspond to (e.g., be connected to) the same access line AL. In the configuration of Figure 7A and Figure 7B , the (first and second) access transistors 710(1), 710(2) corresponding to the first set 706(1) and the second set 706(2) of memory cells 702 may correspond to the first access line AL(1), and the (third and fourth) access transistors 710(3), 710(4) corresponding to the third set 706(3) and the fourth set 706(4) of memory cells 702 may correspond to the second access line AL(2). Illustratively, access lines AL may be provided to transfer control signals to the access transistors 710 to which they are connected, for example, at the respective gate nodes of the access transistors 710. As shown in Figure 7A and Figure 7B , the access transistors 710 corresponding to the same global word lines WL(1), WL(2) may be connected in parallel with each other (e.g., at the respective source nodes), for example, the first access transistor 710(1) and the third access transistor 710(3) corresponding to the first word line WL(1) may be connected in parallel with each other, and the second access transistor 710(2) and the fourth access transistor 710(4) corresponding to the second word line WL(2) may be connected in parallel with each other. The parallel connection may provide addressing of the desired set of memory cells corresponding to a certain global word line while being able to "disconnect" other sets of memory cells corresponding to that word line.

[0152] In various aspects, each access transistor 710 may include a field effect transistor structure, which, for example, has a source node, a drain node, and a gate node to control the electrical behavior of the source node and the drain node (in a manner similar to that for Figure 2The field effect transistor structure is described in a similar manner). The control signal provided at the gate node can allow or block the flow of current between the source node and the drain node, thus illustratively "connecting" or "disconnecting" the corresponding memory cell set from the associated word line or word line portion. Illustratively, the (first) control signal can be configured to short-circuit the source node and the drain node of the access transistor in such a way that the voltage provided at the source node can be transferred to the drain node (illustratively, such that the voltage provided at the global word line can be transferred to the local word line). The (second) control signal can be configured to disconnect the connection between the source node and the drain node of the access transistor in such a way that the voltage provided at the source node is not transferred to the drain node (illustratively, isolating the local word line and the corresponding memory cell set).

[0153] Figure 7A and Figure 7B shows the writing of the memory cell 702w of the first memory cell set 706(1). In this case, the (first) control signal can be provided at the (first) access line AL(1) corresponding to the (first) access transistor 710(1) associated with the (first) set 706(1) including the memory cell 702w to be written. The first control signal can be configured to turn on the access transistor coupled to the first access line AL(1), for example, to enable current to flow in the corresponding word line or word line portion. Illustratively, the gate-source voltage drops at the first and second access transistors 710(1), 710(2) provided by the first control signal and the voltages at the respective source nodes of the first and second access transistors 710(1), 710(2) can allow a voltage to be provided on the local word line corresponding to the first memory cell set 706(1) and inherently on the local word line corresponding to the second memory cell set 706(2). In another case, for example, if the access transistor remains closed (off), the corresponding local word line can remain electrically floating, for example, at a voltage that is substantially the base voltage.

[0154] A (second) control signal may be provided at a (second) access line AL(2) corresponding to access transistors 710(3), 710(4) associated with one or more other sets 706(3), 706(4) of memory cells that are not to be written during a write operation. The second control signal may be configured to turn off the access transistors coupled to the second access line AL(2), e.g., to prevent current from flowing in a corresponding word line or word line section. Illustratively, the gate-source voltage drop provided by the second control signal at the third and fourth access transistors 710(3), 710(4) and the voltage at the respective source nodes of the third and fourth access transistors 710(3), 710(4) may prevent a voltage from being provided at local word lines corresponding to the third and fourth sets 706(3), 706(4) of memory cells.

[0155] As an exemplary scenario for writing a “1” in the memory cells 702w of the first set 706(1), as Figure 7A shown, a base voltage V may be provided at each bit line BL and source line SL of the memory cell arrangement 700. B A write voltage V may be provided at the source nodes of access transistors 710(1), 710(3) corresponding to the first word line WL(1), W and a first control signal at the first access transistor 710(1) may allow the write voltage V to be provided at a word line section corresponding to the first set 710(1) of memory cells 702, W while a second control signal at the third access transistor 710(3) may prevent the write voltage V from being provided at a word line section corresponding to the third set 710(3) of memory cells 702. W A base voltage V may be provided at the source nodes of access transistors 710(2), 710(4) corresponding to the second word line WL(2), B and a first control signal (and gate-source voltage drop) at the second access transistor 710(2) may allow the base voltage V to be provided at a word line section corresponding to the second set 710(2) of memory cells 702, B while a second control signal at the fourth access transistor 710(3) may prevent the base voltage V from being provided at a word line section corresponding to the fourth set 710(2) of memory cells. B . Figure 7A The write in may provide a write of “11...” in the first word of the memory cell arrangement 700.

[0156] In Figure 7A the scenario described, the memory cells 702w to be written experience a write voltage drop (magnitude +V W), e.g., with a positive polarity. Other memory cells 702 that are not intended to be written do not experience any voltage drop (e.g., 0V), such that interference at those memory cells can be prevented. Illustratively, a base voltage V is provided at the nodes of the memory cells 702 of the second set 706(2) B , such that these memory cells do not experience any voltage drop, and access transistors 710(3), 710(4) can enable the suppression voltage to be unused during writing, such that interference with other memory cells can be reduced or prevented. The access transistors 710 can "disconnect" (in other words, decouple) the memory cells not intended to be written from the memory cells intended to be written, such that interference voltage drops can be prevented.

[0157] In Figure 7B an exemplary scheme for writing a "0" in the memory cells 702w of the first set 706(1) is shown. A base voltage V can be provided at the source nodes of the access transistors 710(1), 710(3) corresponding to the first word line WL(1) B , and the first control signal at the first access transistor 710(1) can allow the base voltage V to be provided at the word line portion corresponding to the first set 706(1) of memory cells 702 B , while the second control signal at the third access transistor 710(3) can prevent the base voltage V from being provided at the word line portion corresponding to the third set 710(3) of memory cells 702 B . A voltage corresponding to 2 / 3 of the write voltage V W can be provided at the source nodes of the access transistors 710(2), 710(4) corresponding to the second word line WL(2), and the first control signal (and gate-source voltage drop) at the second access transistor 710(2) can allow a voltage corresponding to 2 / 3 of the write voltage V W to be provided at the word line portion corresponding to the second set 710(2) of memory cells 702, while the second control signal at the fourth access transistor 710(3) can prevent a voltage corresponding to 2 / 3 of the write voltage V W from being provided at the word line portion corresponding to the fourth set 710(4) of memory cells. The write voltage V W can be provided at the bit lines BL(1), BL(2) and source lines SL(1), SL(2) corresponding to the first set 706(1) of memory cells 702, and the base voltage V B can be provided at the bit lines BL(3), BL(4) and source lines SL(3), SL(4) corresponding to the sets 706(3), 706(4) of memory cells 702 that do not share bit lines and source lines with the first set 706(1). Figure 7BWriting in can enable writing "00..." to be provided in the first word of the memory cell arrangement 700.

[0158] Under the scheme described in Figure 7B , the memory cell 702w intended to be written experiences a write voltage drop (with an amplitude of -V W ), for example, with a negative polarity. Memory cells 702 in the sets 706(3) and 706(4) that do not share bit lines and source lines with the first set 706(1) and are not intended to be written do not experience any voltage drop (e.g., 0V), so that interference at these memory cells can be prevented. Memory cells 702 in the set 706(2) that do not share bit lines and source lines with the first set 706(1) and are not intended to be written may experience an interference voltage drop (with an amplitude of 1 / 3 of the write voltage V W ), as described above, which can be compensated for by an anti-interference operation. In this configuration, the access transistors 710(3) and 710(4) can prevent interference at memory cells 702 in the sets 706(3) and 706(4) that do not share bit lines and source lines with the set including the written memory cell 702w, thus reducing the overall harmful impact on the memory cell arrangement 700.

[0159] Figure 8 Fig. shows a schematic flowchart of a method 800 for operating a memory cell arrangement (e.g., the memory cell arrangements 300, 400, 500, 600, 700 described with respect to Figures 3 to 7B ). Illustratively, the method 800 can be a method for writing one or more (first) memory cells of a memory cell arrangement and compensating for interference at one or more other (second) memory cells of the memory cell arrangement.

[0160] The method 800 can include, at 810, by a write operation (e.g., with respect to Figure 4A , Figure 4C , Figure 5A , Figure 5C , Figure 6A , Figure 6C , Figure 7A , Figure 7BThe described write operation causes the writing of one or more (first) memory cells. The write operation can include supplying a set of write signals (e.g., set of write signals 306w) to the memory cells of the memory cell arrangement to provide a write voltage drop at one or more first memory cells, thereby causing one or more first memory cells to enter one of at least two memory states by switching the corresponding polarization state of each of the one or more first memory cells (e.g., by polarizing the corresponding spontaneous polarization memory layer). The set of write signals can cause an interference voltage drop at one or more other (second) memory cells in the memory cell arrangement that are not intended to be written. As described above, the interference voltage drop can cause interference to one or more second memory cells.

[0161] The method can include, at 820, supplying a set of anti-interference signals (e.g., set of anti-interference signals 306c) to the memory cells of the memory cell arrangement. The set of anti-interference signals can provide an anti-interference voltage drop at one or more second memory cells to at least partially compensate for the interference caused by the set of write signals.

[0162] Various examples are provided below, which can include one or more aspects described above with reference to the memory cells (e.g., capacitive memory structure 100, memory cell 200), the memory cell arrangement (e.g., memory cell arrangements 300, 400, 500, 600, 700), and the method (e.g., method 800). It is contemplated that aspects described with respect to the memory arrangement can also be applied to the method, and vice versa.

[0163] Example 1 is a memory cell arrangement comprising: a plurality of spontaneous polarization memory cells; and control circuitry configured to cause the writing of one or more first memory cells among the plurality of spontaneous polarization memory cells by a write operation, wherein the write operation includes: supplying a set of write signals to the plurality of spontaneous polarization memory cells to provide a write voltage drop at each of the one or more first memory cells, thereby causing each of the one or more first memory cells to enter one of at least two memory states by switching the corresponding polarization state of each of the one or more first memory cells, the set of write signals causing an interference voltage drop at one or more second memory cells in the plurality of spontaneous polarization memory cells that are not intended to be written, wherein the interference voltage drop causes interference to the one or more second memory cells and maintains the corresponding polarization state of each of the one or more second memory cells; and wherein the control circuitry is further configured to supply a set of anti-interference signals to the plurality of spontaneous polarization memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the set of write signals.

[0164] In Example 2, the memory cell arrangement of Example 1 may optionally further include: the memory cell arrangement includes a plurality of word lines, and one or more first memory cells correspond to a first word line among the plurality of word lines, and one or more second memory cells correspond to a second word line among the plurality of word lines.

[0165] In Example 3, the memory cell arrangement of Example 1 or 2 may optionally further include: the memory cell arrangement includes a plurality of source line / bit line pairs, and at least one memory cell among the one or more first memory cells and at least one other memory cell of the one or more second memory cells correspond to the same source line / bit line pair among the plurality of source line / bit line pairs.

[0166] In Example 4, the memory cell arrangement of any one of Examples 1 to 3 may optionally further include: the interference caused by the interference voltage drop includes a change in the magnitude of the remanent polarization associated with a respective one of the one or more second memory cells. Illustratively, the interference caused by the interference voltage drop at the one or more second memory cells may include a decrease or an increase in the magnitude of the remanent polarization associated with a respective one of the one or more second memory cells (e.g., a decrease or an increase in the magnitude of the remanent polarization of the respective ferroelectric memory layer).

[0167] In Example 5, the memory cell arrangement of any one of Examples 1 to 4 may optionally further include: the interference voltage drop is configured to either partially polarize or partially depolarize each of the one or more second memory cells. Illustratively, the interference voltage drop may be configured to at least partially polarize the respective ferroelectric memory layer of the one or more second memory cells, or at least partially depolarize the respective ferroelectric memory layer of the one or more second memory cells.

[0168] In Example 6, the memory cell arrangement of any one of Examples 1 to 5 may optionally further include: the anti-interference signal set is configured to compensate for the interference caused by the interference voltage drop by partially polarizing or partially depolarizing a respective one of the one or more second memory cells. Illustratively, the anti-interference voltage drop may be configured to compensate for the interference caused by the interference voltage drop by at least partially polarizing the respective ferroelectric memory layer of the one or more second memory cells or by at least partially depolarizing the respective ferroelectric memory layer of the one or more second memory cells.

[0169] In Example 7, the memory cell arrangement of any one of Examples 1 to 6 may optionally further include: an anti-interference voltage drop configured to change (e.g., increase or decrease) the magnitude of the corresponding remaining polarization associated with one or more second memory cells, e.g., the magnitude of the polarization of the spontaneous polarization memory layer of one or more second memory cells, without switching the corresponding memory states of the one or more second memory cells.

[0170] In Example 8, the memory cell arrangement of any one of Examples 1 to 7 may optionally further include: the corresponding anti-interference voltage drop at the corresponding second memory cell of the one or more second memory cells has a polarity opposite to that of the corresponding interference voltage drop at the corresponding second memory cell.

[0171] In Example 9, the memory cell arrangement of any one of Examples 1 to 8 may optionally further include: the magnitude of the corresponding anti-interference voltage drop at the corresponding second memory cell of the one or more second memory cells has the same absolute value and opposite polarity with respect to the magnitude of the corresponding interference voltage drop at the corresponding second memory cell.

[0172] In Example 10, the memory cell arrangement of any one of Examples 1 to 9 may optionally further include: the interference voltage drop is configured (e.g., has such a magnitude that) not to switch the corresponding memory states of the one or more second memory cells (illustratively, configured to maintain the corresponding memory states of the one or more second memory cells).

[0173] In Example 11, the memory cell arrangement of any one of Examples 1 to 10 may optionally further include: the anti-interference voltage drop is configured (e.g., has such a magnitude that) not to switch the corresponding memory states of the one or more second memory cells (illustratively, configured to maintain the corresponding memory states of the one or more second memory cells).

[0174] In Example 12, the memory cell arrangement of any one of Examples 1 to 11 may optionally further include: the absolute value of the magnitude of the write voltage drop corresponds to the absolute value of the magnitude of the write voltage, and the absolute value of the magnitude of the interference voltage drop is in the range of 0 to approximately half of the write voltage (as another example, 0 to approximately one-third of the write voltage).

[0175] In Example 13, the memory cell arrangement of Example 12 may optionally further include: the absolute value of the magnitude of the anti-interference voltage drop is in the range of 0 to approximately half of the write voltage (as another example, 0 to approximately one-third of the write voltage).

[0176] In Example 14, the memory cell arrangement of any one of Examples 1 to 13 may optionally further include: each of the plurality of memory cells is explicitly assigned to one word line and one source line / bit line pair.

[0177] In Example 15, the memory cell arrangement of any one of Examples 1 to 14 may optionally further include: each of the plurality of ferroelectric memory cells includes a ferroelectric memory layer, and the material of the ferroelectric memory layer includes at least one of the following: doped transition metal oxides, undoped transition metal oxides, doped transition metal nitrides, undoped transition metal nitrides, doped metal nitrides, and / or undoped metal nitrides.

[0178] In Example 16, the memory cell arrangement of any one of Examples 1 to 15 may optionally further include: each of the plurality of ferroelectric memory cells includes a first electrode, a second electrode, and a ferroelectric memory layer disposed between the first electrode and the second electrode.

[0179] In Example 17, the memory cell arrangement of Example 16 may optionally further include: the first electrode, the second electrode, and the ferroelectric memory layer form a capacitive memory structure.

[0180] In Example 18, the memory cell arrangement of any one of Examples 1 to 17 may optionally further include: each of the plurality of ferroelectric memory cells includes a field effect transistor structure, and the field effect transistor structure includes two source / drain regions and a gate structure.

[0181] In Example 19, the memory cell arrangements of Examples 17 and 18 may optionally further include: the gate structure is coupled to the capacitive memory structure, or the capacitive memory structure is integrated in the field effect transistor structure.

[0182] In Example 20, the memory cell arrangement of Example 18 or 19 may optionally further include: one of the two source / drain regions of the field effect transistor structure is connected to the bit line in the corresponding source line / bit line pair, the other of the two source / drain regions of the field effect transistor structure is connected to the source line in the corresponding source line / bit line pair, and at least one of the capacitive structure or the gate structure of the field effect transistor structure is connected to the corresponding word line.

[0183] In Example 21, the memory cell arrangement of any one of Examples 1 to 20 may optionally further include: at least two memory states include a first memory state and a second memory state, and each of the plurality of ferroelectric memory cells has a first threshold voltage in the first memory state and a second threshold voltage in the second memory state.

[0184] In Example 22, the memory cell arrangement of any one of Examples 2 to 21 may optionally further include: the write signal set includes a first voltage supplied to a first word line corresponding to one or more first memory cells, and a second voltage supplied to a second word line corresponding to one or more second memory cells.

[0185] In Example 23, the memory cell arrangement of Example 22 may optionally further include: the absolute value of the difference between the first voltage and the second voltage is two-thirds of the write voltage.

[0186] In Example 24, the memory cell arrangement of Example 22 or 23 may optionally further include: the write signal set further includes a third voltage supplied to one or more source line / bit line pairs corresponding to one or more first memory cells, and the absolute value of the difference between the first voltage and the third voltage corresponds to the write voltage.

[0187] In Example 25, the memory cell arrangement of Example 24 may optionally further include: the control circuit defines a base voltage, and at least one of the first voltage or the third voltage includes the base voltage.

[0188] In Example 26, the memory cell arrangement of Example 24 or 25 may optionally further include: the absolute value of the difference between the second voltage and the third voltage is in the range of 0 to one-third of the write voltage.

[0189] In Example 27, the memory cell arrangement of any one of Examples 22 to 26 may optionally further include: the write signal set further includes a fourth voltage supplied to one or more source line / bit line pairs corresponding to one or more second memory cells that do not share a corresponding source line / bit line pair with one of the one or more first memory cells.

[0190] In Example 28, the memory cell arrangement of Example 27 may optionally further include: the absolute value of the difference between the second voltage and the fourth voltage is in the range of 0 to one-third of the write voltage.

[0191] In Example 29, the memory cell arrangement of any one of Examples 2 to 28 may optionally further include: the anti-interference signal set includes a first anti-interference voltage supplied to a first word line corresponding to one or more first memory cells and a second anti-interference voltage supplied to a second word line corresponding to one or more second memory cells.

[0192] In Example 30, the memory cell arrangement of Example 29 may optionally further include: the first anti-interference voltage has the same voltage value as the second anti-interference voltage.

[0193] In Example 31, the memory cell arrangement of Example 29 or 30 may optionally further include: the anti-interference signal set further includes a third anti-interference voltage supplied to one or more source line / bit line pairs corresponding to one or more first memory cells, and the absolute value of the difference between the first anti-interference voltage and the third anti-interference voltage is in the range of 0 to one-third of the write voltage.

[0194] In Example 32, the memory cell arrangement of Example 31 may optionally further include: the anti-interference signal set further includes a fourth anti-interference voltage supplied to one or more source line / bit line pairs corresponding to one or more second memory cells that do not share the corresponding source line / bit line pair with one of the one or more first memory cells.

[0195] In Example 33, the memory cell arrangement of Example 31 or 32 may optionally further include: the absolute value of the difference between the first anti-interference voltage and the third anti-interference voltage is in the range of 0 to one-third of the write voltage.

[0196] In Example 34, the memory cell arrangement of any one of Examples 2 to 33 may optionally further include: the first word line has a corresponding first access transistor configured to allow or block the flow of current in the first word line, and the second word line has a corresponding second access transistor configured to allow or block the flow of current in the second word line.

[0197] The first access transistor may be configured to allow or block the voltage on the first word line (e.g., allow or block the voltage to be applied to the memory cells corresponding to the first word line), and the second access transistor may be configured to allow or block the voltage on the second word line (e.g., allow or block the voltage to be applied to the memory cells corresponding to the second word line).

[0198] Example 35 is a memory cell arrangement that includes: a first set of ferroelectric memory cells and a second set of ferroelectric memory cells, where the memory cells in the first set of memory cells correspond to a first word line, and where the memory cells in the second set of memory cells correspond to a second word line; and a control circuit configured to: cause a write of one or more memory cells in the first set of memory cells by a write operation, where the write operation includes supplying a set of write signals to the first set of memory cells and the second set of memory cells, where the set of write signals provides a write voltage drop at each of the one or more memory cells in the first set of memory cells intended to be written, thereby causing the one or more memory cells to enter one of at least two memory states by switching the respective polarization states of each of the one or more memory cells, where the set of write signals causes interference at the memory cells in the second set of memory cells not intended to be written; and where the control circuit is further configured to supply a set of anti-interference signals to the first set of memory cells and the second set of memory cells, where the set of anti-interference signals provides an anti-interference voltage drop at each memory cell in the second set of memory cells to at least partially compensate for the interference caused by the set of write signals.

[0199] In Example 36, optionally, the memory cell arrangement of Example 35 may further include one, some, or all of the features of any one of Examples 1 to 34, where appropriate.

[0200] Example 37 is a memory cell arrangement that includes: a plurality of memory cells, each memory cell including a respective ferroelectric memory layer, and a control circuit configured to: cause a write of one or more first memory cells among the plurality of memory cells, where writing the one or more first memory cells causes interference to one or more second memory cells among the plurality of memory cells not written, and compensate for the interference caused by writing the one or more first memory cells by polarizing or at least partially depolarizing the ferroelectric memory layers of the one or more second memory cells.

[0201] In Example 38, optionally, the memory cell arrangement of Example 37 may further include: one, some, or all of the features of any one of Examples 1 to 34.

[0202] Example 39 is a memory cell arrangement that includes: a first ferroelectric memory cell and a second ferroelectric memory cell, and a control circuit configured to: cause a write of the first memory cell, where writing the first memory cell causes interference at the second memory cell, and at least partially compensate for the interference caused by writing the first memory cell by at least partially polarizing or at least partially depolarizing the second memory cell.

[0203] In Example 40, optionally, the memory cell arrangement of Example 39 may further include one or some or all of the features of any one of Examples 1 to 34, where appropriate.

[0204] Example 41 is a method of operating a memory cell arrangement including a plurality of memory cells, each memory cell including a ferroelectric memory layer. The method includes: causing a write of one or more first memory cells among the plurality of memory cells through a write operation, where the write operation includes supplying a set of write signals to the plurality of memory cells, and the set of write signals provides a write voltage drop at the one or more first memory cells to cause one or more first memory cells to enter one of at least two memory states by polarizing the corresponding ferroelectric memory layer, and the set of write signals causes an interference voltage drop at one or more second memory cells that are not written among the plurality of memory cells, and the interference voltage drop causes interference to the one or more second memory cells; and supplying a set of anti-interference signals to the plurality of memory cells, where the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to compensate for the interference caused by the set of write signals.

[0205] Example 42 is a method of operating a memory cell arrangement including a plurality of ferroelectric memory cells. The method includes: partially polarizing or partially depolarizing one or more second memory cells among the plurality of ferroelectric memory cells to compensate for the corresponding partial depolarization or partial polarization caused by a write operation on one or more first memory cells among the plurality of ferroelectric memory cells.

[0206] In Embodiment 43, the method of Example 42 may optionally further include: the write operation includes supplying a set of write signals to the plurality of ferroelectric memory cells to provide a write voltage drop at each of the one or more first memory cells, so that each of the one or more first memory cells enters one of at least two memory states by switching the corresponding polarization state of each of the one or more first memory cells, the set of write signals causes an interference voltage drop at one or more second memory cells that are not intended to be written among the plurality of ferroelectric memory cells, where the interference voltage drop causes interference to the one or more second memory cells and maintains the corresponding polarization state of each of the one or more second memory cells, and the partial polarization or partial depolarization of the one or more second memory cells includes supplying a set of anti-interference signals to the plurality of ferroelectric memory cells, where the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the set of write signals.

[0207] The terms "at least one" and "one or more" can be understood to include any integer greater than or equal to one, i.e., one, two, three, four, [...], etc. The term "plurality" or "pluralities" can be understood to include any integer greater than or equal to two, i.e., two, three, four, five, [...], etc. The phrase "at least one of..." with respect to a group of elements can be used herein to denote at least one element of the group consisting of these elements. For example, the phrase "at least one of..." with respect to a group of elements can be used herein to denote a selection: one of the listed elements, one of a plurality of listed elements, a plurality of individually listed elements, or a plurality of several listed elements.

[0208] The term "connected" can be used herein with respect to nodes, terminals, integrated circuit elements, etc., to denote an electrical connection, which can include a direct connection or an indirect connection, where the indirect connection can include only additional structures in the current path that do not affect the basic function of the circuit or device. The term "conductively connected" used herein to describe an electrical connection between one or more terminals, nodes, regions, contacts, etc. can be understood to be a conductive connection having, for example, ohmic behavior, such as provided by a metal or a degenerated semiconductor in the absence of a p-n junction in the current path. The term "conductively connected" can also be referred to as "electroplated connection".

[0209] The term "region" used with respect to a "source region", "drain region", "channel region", etc. can be used herein to denote a continuous region of a semiconductor portion (e.g., a semiconductor wafer or a portion of a semiconductor wafer, a semiconductor layer, a fin, a semiconductor nanosheet, a semiconductor nanowire, etc.). In some aspects, the continuous region of the semiconductor portion can be provided by a semiconductor material having only one major doping type.

[0210] The term "metal material" can be used herein to describe a metal (e.g., a pure or substantially pure metal), a mixture of more than one metal, a metal alloy, an intermetallic material, a conductive metal compound (e.g., a nitride), etc. Illustratively, the term "metal material" can be used herein to describe a material having a typical electrical conductivity of a metal (e.g., a conductivity greater than 10 6 S / m at a temperature of 20 °C). The term "metal material" can be used herein to describe a material having a Fermi level within at least one energy band.

[0211] In various aspects, reference may be made to the position of a memory cell within a memory cell arrangement. The notation may be based on a matrix configuration of memory cells within the memory cell arrangement. Illustratively, a memory cell in position (1,1) may be the memory cell in the upper left corner (as shown in the figure) of the memory cell arrangement, a memory cell in position (1,2) may be the memory cell immediately to the right of the memory cell in position (1,1), and so on. A memory cell in position (1,1) may be a memory cell in the first row and the first column of the memory cell arrangement, a memory cell in position (1,2) may be a memory cell in the first row and the second column of the memory cell arrangement, and so on.

[0212] Although the invention has been particularly shown and described with reference to specific aspects, those skilled in the art will appreciate that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Accordingly, the scope of the invention is represented by the appended claims, and all changes within the meaning and range of equivalents of the claims are included therein.

Claims

1. A memory device, the memory device comprising: a plurality of ferroelectric memory cells; and control circuitry configured to cause a write of one or more first memory cells among the plurality of ferroelectric memory cells through a write operation, wherein the write operation includes: supplying a set of write signals to the plurality of ferroelectric memory cells to provide a write voltage drop at each of the one or more first memory cells, thereby causing each of the one or more first memory cells to enter one of at least two memory states by switching a respective polarization state of each of the one or more first memory cells, the set of write signals causing an interference voltage drop at one or more second memory cells among the plurality of ferroelectric memory cells that are not intended to be written, wherein the interference voltage drop causes interference to the one or more second memory cells and maintains a respective polarization state of each of the one or more second memory cells; and wherein the control circuitry is further configured to supply a set of anti-interference signals to the plurality of ferroelectric memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the interference voltage drop.

2. The memory device according to claim 1, wherein the memory device includes a plurality of word lines, and wherein the one or more first memory cells correspond to a first word line among the plurality of word lines, and the one or more second memory cells correspond to a second word line among the plurality of word lines.

3. The memory device according to claim 1, wherein the memory device includes a plurality of source line / bit line pairs, and wherein at least one memory cell among the one or more first memory cells and at least one memory cell among the one or more second memory cells correspond to the same source line / bit line pair among the plurality of source line / bit line pairs.

4. The memory device according to claim 1, wherein the interference caused by the interference voltage drop includes a change in the magnitude of the remanent polarization associated with a respective one of the one or more second memory cells.

5. The memory device according to claim 4, wherein the interference voltage drop is configured to either partially polarize or partially depolarize each of the one or more second memory cells.

6. The memory device according to claim 4, wherein the set of anti-interference signals is configured to compensate for the interference caused by the interference voltage drop by partially polarizing or partially depolarizing a respective one of the one or more second memory cells.

7. The memory device according to claim 6, wherein each memory cell among the plurality of ferroelectric memory cells includes a ferroelectric memory layer, and The anti-interference voltage drop is configured to change the magnitude of the remanent polarization of the corresponding ferroelectric memory layer in the one or more second memory cells without switching the corresponding memory states of the one or more second memory cells.

8. The memory device according to claim 1, wherein the corresponding anti-interference voltage drop at the corresponding second memory cell among the one or more second memory cells has a polarity opposite to that of the corresponding interference voltage drop at the corresponding second memory cell.

9. The memory device according to claim 1, wherein the magnitude of the corresponding anti-interference voltage drop at the corresponding second memory cell among the one or more second memory cells has the same absolute value and opposite polarity as the magnitude of the corresponding interference voltage drop at the corresponding second memory cell.

10. The memory device according to claim 1, wherein the absolute value of the magnitude of the write voltage drop corresponds to the absolute value of the magnitude of the write voltage, and wherein the absolute value of the magnitude of the interference voltage drop ranges from zero to approximately half of the write voltage.

11. The memory device according to claim 1, wherein each of the plurality of ferroelectric memory cells includes a ferroelectric memory layer, and wherein the material of the ferroelectric memory layer includes at least one of the following: doped transition metal oxides, undoped transition metal oxides, doped transition metal nitrides, undoped transition metal nitrides, doped metal nitrides, and / or undoped metal nitrides.

12. The memory device according to claim 1, wherein each of the plurality of ferroelectric memory cells includes a first electrode, a second electrode, and a ferroelectric memory layer disposed between the first electrode and the second electrode.

13. The memory device according to claim 12, wherein the first electrode, the second electrode, and the ferroelectric memory layer form a capacitive memory structure.

14. The memory device according to claim 13, wherein each of the plurality of ferroelectric memory cells includes a field effect transistor structure, the field effect transistor structure including two source / drain regions and a gate structure, and wherein the gate structure is coupled to the capacitive memory structure, or wherein the capacitive memory structure is integrated in the field effect transistor structure.

15. The memory device according to claim 1, wherein the at least two memory states include a first memory state and a second memory state, and wherein each of the plurality of ferroelectric memory cells has a first threshold voltage in the first memory state and a second threshold voltage in the second memory state.

16. The memory device according to claim 2, wherein the first word line has a corresponding first access transistor configured to allow or block current flow in the first word line, and The second word line has a corresponding second access transistor configured to allow or block current flow in the second word line.

17. The memory device according to claim 16, wherein the corresponding first access transistor corresponds to a first set of memory cells of the plurality of ferroelectric memory cells, and wherein the corresponding second access transistor corresponds to a second set of memory cells of the plurality of ferroelectric memory cells.

18. A method of operating a memory device, the memory device including a plurality of ferroelectric memory cells, the method comprising: Partially polarizing or partially depolarizing one or more second memory cells of the plurality of ferroelectric memory cells to compensate for a corresponding partial depolarization or partial polarization caused by a write operation on one or more first memory cells of the plurality of ferroelectric memory cells; and wherein the write operation includes supplying a set of write signals to the plurality of ferroelectric memory cells to provide a write voltage drop at each of the one or more first memory cells, thereby causing each of the one or more first memory cells to enter one of at least two memory states by switching a corresponding polarization state of each of the one or more first memory cells, the set of write signals causing an interference voltage drop at one or more second memory cells of the plurality of ferroelectric memory cells that are not intended to be written, wherein the interference voltage drop causes interference to the one or more second memory cells and maintains a corresponding polarization state of each of the one or more second memory cells.

19. The method according to claim 18, wherein partially polarizing or partially depolarizing the one or more second memory cells includes supplying a set of anti-interference signals to the plurality of ferroelectric memory cells, wherein the set of anti-interference signals provides an anti-interference voltage drop at the one or more second memory cells to at least partially compensate for the interference caused by the interference voltage drop.

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