Self-cooling semiconductor resistor and method of manufacturing the same

Abstract

The application relates to the technical field of semiconductors, and discloses a self-refrigeration semiconductor resistor and a manufacturing method thereof. The resistor comprises a plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, a first polysilicon gate on each N-type well region, a second polysilicon gate on each P-type well region, and a metal interconnection layer. The plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in a row direction and a column direction, an N-type deep doped region is formed in each N-type well region, and a P-type deep doped region is formed in each P-type well region. The first polysilicon gate is N-type deep doped and does not have a gate insulating layer between the first polysilicon gate and the semiconductor substrate. The second polysilicon gate is P-type deep doped and does not have a gate insulating layer between the second polysilicon gate and the semiconductor substrate. The metal interconnection layer connects the plurality of first polysilicon gates and the plurality of second polysilicon gates into an S-shaped structure. In the application, the heat flow direction is from the inside of the resistor to the surface, so that heat dissipation refrigeration is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a self-cooling semiconductor resistor and a manufacturing method thereof. BACKGROUND

[0002] Chip is called the "food" of modern industry, and is an important basic component of information technology industry. The development of mobile phones, computers, automobiles, industrial control, Internet of Things, big data, artificial intelligence and other fields cannot be separated from chip. In use, in addition to the designed function, heat will be generated, and the heat needs to be dissipated efficiently to maintain the internal devices of the chip to work at a safe temperature, which is an important issue to ensure product safety and reliability. With the increase of chip size and speed, this issue is becoming more and more challenging, and innovative ideas and methods need to be introduced.

[0003] Peltier effect refers to the phenomenon of heat absorption and heat release at the junction of different conductors when current flows through a loop composed of different conductors. The existing design is based on the Peltier effect of metal, which has weak cooling effect on one hand, and is incompatible with the existing semiconductor CMOS process on the other hand, and also needs an additional cooling mode, which brings inconvenience to the application. Therefore, a self-cooling Peltier resistor is needed to achieve better process compatibility and cooling effect. SUMMARY

[0004] The present application aims to provide a self-cooling semiconductor resistor and a manufacturing method thereof, and a Peltier device compatible with the existing CMOS process, which can be applied to various chips and help improve the overall performance of the chip.

[0005] The present application discloses a self-cooling semiconductor resistor, comprising:

[0006] A plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, the plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in row direction and column direction, an N-type deep doped region is formed in each of the N-type well regions, and a P-type deep doped region is formed in each of the P-type well regions;

[0007] A first polysilicon gate on each of the N-type well regions, the first polysilicon gate is N-type deep doped and does not have a gate insulating layer between the first polysilicon gate and the semiconductor substrate;

[0008] A second polysilicon gate on each of the P-type well regions, the second polysilicon gate is P-type deep doped and does not have a gate insulating layer between the second polysilicon gate and the semiconductor substrate; and

[0009] A metal interconnection layer, the metal interconnection layer connects the plurality of first polysilicon gates and the plurality of second polysilicon gates into an S-shaped structure.

[0010] In one preferred embodiment, further comprising: a shallow trench isolation region surrounding the plurality of N-type well regions and the plurality of P-type well regions.

[0011] In one preferred embodiment, further comprising: a sidewall formed around the first polysilicon gate and the second polysilicon gate.

[0012] In one preferred embodiment, further comprising: a silicide formed on the first polysilicon gate and the second polysilicon gate.

[0013] In one preferred embodiment, when the self-cooling semiconductor resistor is in operation, the current flows through the first polysilicon gate, the N-type deep doped region, the P-type deep doped region, the second polysilicon gate in sequence and circulates in sequence, the heat flows from the N-type deep doped region to the first polysilicon gate, and the heat flows from the P-type deep doped region to the second polysilicon gate.

[0014] The present application also discloses a method for manufacturing a self-cooling semiconductor resistor, comprising:

[0015] forming a plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, the plurality of N-type well regions and the plurality of P-type well regions are arranged alternately in a row direction and a column direction;

[0016] forming a polysilicon gate on each of the N-type well regions and each of the P-type well regions, the polysilicon gate and the semiconductor substrate do not have a gate insulating layer therebetween;

[0017] forming an N-type deep doped region on each of the N-type well regions and doping the polysilicon gate on each of the N-type well regions as a first N-type deep doped polysilicon gate;

[0018] forming a P-type deep doped region on each of the P-type well regions and doping the polysilicon gate on each of the P-type well regions as a second P-type deep doped polysilicon gate; and

[0019] forming a metal interconnection layer, the metal interconnection layer connects the plurality of first polysilicon gates and the plurality of second polysilicon gates as an S-shaped structure.

[0020] In one preferred embodiment, before the step of forming a polysilicon gate on each of the N-type well regions and each of the P-type well regions, further comprising:

[0021] forming a gate insulating layer on the semiconductor substrate;

[0022] removing part of the gate insulating layer on the semiconductor substrate; and

[0023] depositing polysilicon, the polysilicon on the part of the semiconductor substrate forms the polysilicon gate.

[0024] In a preferred embodiment, before the step of forming a plurality of N-type well regions and a plurality of P-type well regions in the semiconductor substrate, further comprising: forming a shallow trench isolation region surrounding the plurality of N-type well regions and the plurality of P-type well regions.

[0025] In a preferred embodiment, before the step of forming a metal interconnection layer, further comprising: forming a sidewall around the first polysilicon gate and the second polysilicon gate.

[0026] In a preferred embodiment, before the step of forming a metal interconnection layer, further comprising: forming a silicide on the first polysilicon gate and the second polysilicon gate.

[0027] In the embodiment of the present application, the heat flow direction is from the inside of the resistor to the surface, so as to achieve heat dissipation refrigeration. Because the Seebeck coefficient of N+ / P+ of semiconductor material is relatively large, about 30 times larger than that of metal material, only 1 / 30 of the current is needed to achieve the same effect as the metal-based Peltier device.

[0028] Compared with the existing CMOS process, the present application only needs to increase one photolithography and etching process to remove the gate insulating layer between the polysilicon gate and the semiconductor substrate, and in the polysilicon patterning process and the P-type and N-type ion implantation process, only the design of the pattern in the layout needs to be modified, without the need to increase additional photolithography process. The embodiment of the present application is fully compatible with the existing CMOS process, without introducing special materials and processes, and has sufficient feasibility. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1 A top view of the self-cooling semiconductor resistor in an embodiment of the present application is shown.

[0030] Figure 2 A cross-sectional view of the self-cooling semiconductor resistor in an embodiment of the present application is shown. Figure 1 along the direction of AA' is shown.

[0031] Figure 3 A cross-sectional view of the self-cooling semiconductor resistor in an embodiment of the present application is shown. Figure 1 along the direction of BB' is shown.

[0032] Figure 4 A flowchart of the manufacturing method of the self-cooling semiconductor resistor in an embodiment of the present application is shown.

[0033] Figure 5(a) shows a top view of the N / P-type well regions and the N+ / P+ deep doped regions of the self-cooling semiconductor resistor in an embodiment of the present application.

[0034] Figure 5(b) shows a schematic diagram of the formation of a gate insulating layer on a semiconductor substrate in a self-cooling semiconductor resistor fabrication method according to an embodiment of this application.

[0035] Figure 5(c) shows a schematic diagram of the formation of polycrystalline silicon on a semiconductor substrate in a self-cooling semiconductor resistor fabrication method according to an embodiment of this application.

[0036] Figure 5(d) shows a schematic diagram of forming a polysilicon gate on a semiconductor substrate in a method for fabricating a self-cooling semiconductor resistor according to an embodiment of this application.

[0037] Figure 5(e) shows a schematic diagram of N-type ion implantation in a self-cooling semiconductor resistor fabrication method according to an embodiment of this application.

[0038] Figure 5(f) shows a schematic diagram of P-type ion implantation in a self-cooling semiconductor resistor fabrication method according to an embodiment of this application. Detailed Implementation

[0039] In the following description, many technical details are presented to help the reader better understand this application. However, those skilled in the art will understand that the technical solutions claimed in this application can be implemented even without these technical details and various variations and modifications based on the following embodiments.

[0040] Several different embodiments are given below according to different features of the present invention. Specific elements and arrangements in the present invention are for simplification, but the present invention is not limited to these embodiments. For example, the description of forming a first element on a second element may include embodiments where the first element and the second element are in direct contact, as well as embodiments where additional elements are formed between the first element and the second element, such that the first element and the second element are not in direct contact. Furthermore, for the sake of brevity, the present invention uses repeated element symbols and / or letters in different examples, but this does not imply a specific relationship between the various embodiments and / or structures. It should be understood that when a layer is "on" other layers or substrates, it may mean directly on other layers or substrates, or that other layers are sandwiched between other layers or substrates.

[0041] This application discloses a self-cooling semiconductor resistor. Figure 1 A top view of a self-cooling semiconductor resistor 100 in one embodiment is shown. Figure 2 It shows Figure 1 A cross-sectional view of the self-cooling semiconductor resistor 100 along the AA' direction. Figure 3 It shows Figure 1 A cross-sectional view of the self-cooling semiconductor resistor 100 along the BB' direction. (Combined with...) Figures 1 to 3As shown, the resistor comprises a plurality of N-type well regions (Nwell) 107 and a plurality of P-type well regions (Pwell) 108 in the semiconductor substrate 101, a first polysilicon gate 102 on each of the N-type well regions 107, a second polysilicon gate 103 on each of the P-type well regions 108, a via 104, and a metal interconnection layer 105. As shown in FIG. 5(a), the plurality of N-type well regions 107 and the plurality of P-type well regions 108 are arranged alternately in a row direction and a column direction, an N-type deep doped region 109 is formed in each of the N-type well regions 107, and a P-type deep doped region 110 is formed in each of the P-type well regions 108.

[0042] In one embodiment, the first polysilicon gate 102 is N-type deep doped and does not have a gate insulating layer between the first polysilicon gate 102 and the semiconductor substrate 101. The second polysilicon gate 103 is P-type deep doped and does not have a gate insulating layer between the second polysilicon gate 103 and the semiconductor substrate 101. The metal interconnection layer 105 connects the plurality of first polysilicon gates 102 and the plurality of second polysilicon gates 103 into an S-shaped structure.

[0043] In one embodiment, continuing to refer to FIG. 5(a), Figure 2 As shown, the resistor 100 further comprises a shallow trench isolation region 106 between the N-type deep doped region 109 and the P-type deep doped region 110.

[0044] In one embodiment, continuing to refer to FIG. 5(a), Figure 2 and Figure 3 As shown, the resistor 100 further comprises a side wall 111 formed around the first polysilicon gate 102 and the second polysilicon gate 103.

[0045] In one embodiment, continuing to refer to FIG. 5(a), Figure 2 and Figure 3 As shown, the resistor 100 further comprises a silicide 112 formed on the first polysilicon gate 102 and the second polysilicon gate 103.

[0046] In one embodiment, continuing to refer to FIG. 5(a), Figure 3 As shown, the resistor 100 further comprises a shallow trench isolation region 114 surrounding the plurality of N-type well regions 107 and the plurality of P-type well regions 108.

[0047] Referring to FIG. 5(a), Figure 3As shown, in the working process of the self-cooling semiconductor resistor in the embodiment, the through hole 104 is connected to the power supply voltage, and the current flows through the first polysilicon gate 102, the N-type deep doped region 109, the P-type deep doped region 110, and the second polysilicon gate 103 in sequence, and then flows to the next first polysilicon gate 102, and the process is repeated. The first polysilicon gate 102 and the N-type deep doped region 109 are both N-type doped, and the carrier is an electron e - . The flow direction of the carrier e - is from the N-type deep doped region 109 to the first polysilicon gate 102. Then, the current flows from the N-type deep doped region 109 to the P-type deep doped region 110, and from the P-type deep doped region 110 to the second polysilicon gate 103. The P-type deep doped region 110 and the second polysilicon gate 103 are both P-type doped, and the carrier is a hole h + . The flow direction of the carrier h + is from the P-type deep doped region 110 to the second polysilicon gate 103. Inside the resistor 100, the direction of heat flow is the flow direction of the carrier, so the direction of heat flow is from the N-type deep doped region 109 to the first polysilicon gate 102, and from the P-type deep doped region 110 to the second polysilicon gate 103, that is, from the inside of the resistor to the surface, thereby achieving heat dissipation and refrigeration.

[0048] In practical applications, the cooling effect achieved by the present application depends on the size of the working current flowing through the resistor, which can range from microamperes to hundreds of milliamperes. Compared with ordinary resistors, the present application reduces the operating temperature of the resistor and the chip without increasing additional power consumption, improves the reliability of the chip, and increases the safe working interval of the chip.

[0049] Another embodiment of the present application also discloses a manufacturing method of a self-cooling semiconductor resistor, Figure 4 a flowchart of the manufacturing method of the self-cooling semiconductor resistor is shown, and Figures 5(a) to 5(f) the manufacturing method in the embodiment will be described in detail. The method comprises the following steps:

[0050] Step 401, as shown in FIG. 5(a), a semiconductor substrate 101 is provided, and a plurality of N-type well regions 107 and a plurality of P-type well regions 108 are formed in the semiconductor substrate 101. The plurality of N-type well regions 107 and the plurality of P-type well regions 108 are arranged alternately in the row direction and the column direction.

[0051] Step 402: A polysilicon gate is formed on each of the N-type well regions and each of the P-type well regions, wherein no gate insulating layer exists between the polysilicon gate and the semiconductor substrate. Specifically, referring to FIG5(b), a gate insulating layer 510 is formed on the semiconductor substrate 101, a patterned photoresist (not shown) is formed on the gate insulating layer 510, and the gate insulating layer 510 is etched to remove a portion of the gate insulating layer 510 on the semiconductor substrate 101. Referring to FIG5(c), polysilicon 530 is deposited on this portion of the semiconductor substrate 101. Referring to FIG5(d), the polysilicon 530 is etched to form a polysilicon gate 540. It should be understood that in this embodiment, the polysilicon deposited on the unetched gate insulating layer 510 is used to form the gate of the transistor (not shown), and the polysilicon deposited on the etched gate insulating layer 510 is used to form the polysilicon gate 540 of the resistor 100.

[0052] Step 403, referring to FIG. 5(e), a patterned photoresist 550 is deposited on the semiconductor substrate 101, covering the P-type well region 108 and exposing the N-type well region 107. N-type ion implantation is performed to form an N-type deeply doped region 109 on each N-type well region 107. Simultaneously, the polysilicon gate on each N-type well region 107 is doped with a first polysilicon gate 102 that is N-type deeply doped. Afterwards, the patterned photoresist 550 is removed.

[0053] Step 404, referring to FIG. 5(f), a patterned photoresist 560 is deposited on the semiconductor substrate 101, covering the N-type well region 107 and exposing the P-type well region 108. P-type ion implantation is performed to form a P-type deeply doped region 110 in each P-type well region 108. Simultaneously, a second polysilicon gate 103 with P-type deep doping is formed on the polysilicon gate of each P-type well region 108. Afterwards, the patterned photoresist 560 is removed. Following step 404, the structure shown in FIG. 5(a) is formed.

[0054] Step 405, refer to Figure 2 and Figure 3 As shown, vias 104 are formed on the first polysilicon gate 102 and the second polysilicon gate 103. Next, a metal interconnect layer 105 is formed, which connects the plurality of first polysilicon gates 102 and the plurality of second polysilicon gates 103 into an S-shaped structure, as shown in the diagram. Figure 1 As shown.

[0055] In one embodiment, prior to the step of forming a plurality of N-type well regions 107 and a plurality of P-type well regions 108 in a semiconductor substrate, the method further includes: forming a shallow trench isolation region 114, the shallow trench isolation region 114 surrounding the plurality of N-type well regions and the plurality of P-type well regions, the structure of which is referenced. Figure 3 As shown.

[0056] In one embodiment, the step of forming the metal interconnect layer 105 is preceded by forming a sidewall 111 around the first polysilicon gate 102 and the second polysilicon gate 103, as shown in Figure 3

[0057] In one embodiment, the step of forming the metal interconnect layer 105 is preceded by forming a silicide 112 on the first polysilicon gate 102 and the second polysilicon gate 103, as shown in Figure 3

[0058] The first embodiment is a product embodiment corresponding to the present embodiment, and technical details in the first embodiment can be applied to the present embodiment, and technical details in the present embodiment can be applied to the first embodiment.

[0059] It should be noted that the relational terms herein such as first and second and the like are used solely to distinguish one from another entity or action, without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises... a" does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element. The application file contains at least one photograph executed in color. Copies of this application with color photographs will be provided by the Patent and Trademark Office upon request and payment of the necessary fee. The term "performing an action based on a certain element" means at least performing the action based on the element, including two cases: performing the action based on the element only, and performing the action based on the element and other elements. The expressions "a plurality of", "a plurality of times", "a plurality of kinds" and the like include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0060] All documents mentioned in this specification are hereby incorporated by reference in their entirety to provide additional description of the application. In addition, it should be appreciated that various modifications, adaptations, and alternative embodiments thereof can be made within the scope and spirit of the present disclosure. The application is not limited to the exemplary embodiments set forth herein but can be practiced with modification and alteration within the scope and spirit of the present disclosure. Accordingly, the specification is to be regarded in an illustrative manner and all such modifications of practice of the application are intended to be included within the scope of the disclosure.

[0061] ​​In some cases, the actions or steps recited in the claims can be performed in a different order and still accomplish desirable results. Additionally, the processes depicted in the figures do not necessarily require the particular order shown, or sequential order to achieve desirable results.

Claims

1. A self-cooled semiconductor resistor, characterized by, Comprising: a plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, the plurality of N-type well regions and the plurality of P-type well regions being arranged in a row direction and a column direction in an alternating manner, an N-type deep doped region being formed in each of the N-type well regions, a P-type deep doped region being formed in each of the P-type well regions; a first polysilicon gate on each of the N-type well regions, the first polysilicon gate being N-type deep doped and not having a gate insulating layer between the first polysilicon gate and the semiconductor substrate; a second polysilicon gate on each of the P-type well regions, the second polysilicon gate being P-type deep doped and not having a gate insulating layer between the second polysilicon gate and the semiconductor substrate; and a metal interconnection layer connecting a plurality of the first polysilicon gates and a plurality of the second polysilicon gates into an S-shaped structure. Further comprising:

2. The self refrigerating semiconductor resistor according to claim 1, characterized in that a shallow trench isolation region surrounding the plurality of N-type well regions and the plurality of P-type well regions. Further comprising:

3. The self refrigerating semiconductor resistor according to claim 1, characterized in that a sidewall formed around the first polysilicon gate and the second polysilicon gate. Further comprising:

4. The self refrigerating semiconductor resistor of claim 1, wherein, a silicide formed on the first polysilicon gate and the second polysilicon gate. When the self-cooling semiconductor resistor is in operation, an electric current flows through the first polysilicon gate, the N-type deep doped region, the P-type deep doped region, the second polysilicon gate in sequence and circulates in sequence, a heat flow flows from the N-type deep doped region to the first polysilicon gate, and a heat flow flows from the P-type deep doped region to the second polysilicon gate.

5. The self refrigerating semiconductor resistor of claim 1, wherein, Comprising:

6. A method of manufacturing a self-cooled semiconductor resistor, characterized by, forming a plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, the plurality of N-type well regions and the plurality of P-type well regions being arranged in a row direction and a column direction in an alternating manner; forming a polysilicon gate on each of the N-type well regions and each of the P-type well regions, the polysilicon gate not having a gate insulating layer between the polysilicon gate and the semiconductor substrate; forming an N-type deep doped region on each of the N-type well regions and doping the polysilicon gate on each of the N-type well regions as a first polysilicon gate which is N-type deep doped; forming a P-type deep doped region on each of the P-type well regions and doping the polysilicon gate on each of the P-type well regions as a second polysilicon gate which is P-type deep doped; and forming a metal interconnection layer connecting a plurality of the first polysilicon gates and a plurality of the second polysilicon gates into an S-shaped structure. Before the step of forming a polysilicon gate on each of the N-type well regions and each of the P-type well regions, further comprising: forming a gate insulating layer on the semiconductor substrate; 7. The method of claim 6, wherein the self-cooled semiconductor resistor is formed by the steps of: removing part of the gate insulating layer on the semiconductor substrate; and depositing polysilicon, the polysilicon on the part of the semiconductor substrate forming a polysilicon gate. Before the step of forming a plurality of N-type well regions and a plurality of P-type well regions in a semiconductor substrate, further comprising: forming a shallow trench isolation region surrounding the plurality of N-type well regions and the plurality of P-type well regions. Before the step of forming a metal interconnection layer, further comprising: forming a sidewall around the first polysilicon gate and the second polysilicon gate.

8. The method of claim 6, wherein the self-cooled semiconductor resistor is formed by the steps of: Before the step of forming a metal interconnection layer, further comprising: forming a silicide on the first polysilicon gate and the second polysilicon gate.

9. The method of claim 6, wherein the self-cooled semiconductor resistor is formed by the steps of: ​ 10. The method of claim 6, wherein the self-cooled semiconductor resistor is formed by the steps of: ​

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