Semiconductor device and method of manufacturing the same

Abstract

The application discloses a semiconductor device and a preparation method thereof. The semiconductor device comprises a substrate of a first conductive type and an epitaxial layer arranged on the substrate; the semiconductor device further comprises a plurality of semiconductor units, a plurality of gate trenches and a plurality of shielding layers arranged in the epitaxial layer; the plurality of semiconductor units comprises a plurality of first semiconductor units and a plurality of second semiconductor units, and the second semiconductor units are circumferentially arranged around the first semiconductor units; the first semiconductor unit comprises a body region of a second conductive type, a body region contact region of the second conductive type and a source region of the first conductive type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from a surface of the epitaxial layer to a surface of the body region; the second semiconductor unit comprises a shielding region of the second conductive type; the shielding region extends from the surface of the epitaxial layer to the substrate, and the shielding region is in contact with the shielding layer, so that the phenomenon that the shielding layer has a hole flow-out state and cannot backflow is eliminated, and normal conduction of the device is ensured.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor device and a method for fabricating the same. Background Technology

[0002] With the development of semiconductor power devices, semiconductor power devices have evolved from planar structures to trench structures in order to increase current density and reduce resistance.

[0003] For trench-type semiconductor devices, it is necessary to reduce the electric field in the gate oxide layer at the trench corners to ensure reliability. One approach is to add a P-type masking layer structure at the bottom of the gate trench, using the PN junction formed at the bottom of the gate trench to protect the trench corners. However, in this approach, if the distance between the P-type masking layer and the P-type substrate is too small and the P-type masking layer at the bottom of the gate trench is floating, holes flow from the P-type masking layer to the P-type substrate during turn-off and cannot flow back. This results in a larger depletion region when the device is turned on, increasing the resistance and losses during conduction, thus preventing normal operation. Summary of the Invention

[0004] This application provides a semiconductor device and a method for fabricating the same, to eliminate the phenomenon that holes flow out of the P-type masking layer and cannot flow back.

[0005] To address the aforementioned technical problems, the first technical solution provided in this application is: to provide a semiconductor device, comprising: a substrate of a first conductivity type and an epitaxial layer disposed on the substrate; the semiconductor device further comprising: a plurality of semiconductor units, a plurality of gate trenches, and a plurality of shielding layers disposed in the epitaxial layer; the gate trenches are disposed between any two of the semiconductor units, and the shielding layers extend from the bottom of the gate trenches toward the substrate;

[0006] The plurality of semiconductor units include: a plurality of first semiconductor units and a plurality of second semiconductor units, wherein the second semiconductor units are configured to be arranged circumferentially around the plurality of first semiconductor units;

[0007] The first semiconductor unit includes: a body region of a second conductivity type, a body region contact region of a second conductivity type, and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region;

[0008] The second semiconductor unit includes: a shielding region of a second conductivity type; the shielding region extends from the surface of the epitaxial layer toward the substrate, and the shielding region is in contact with the shielding layer.

[0009] To solve the above-mentioned technical problems, the second technical solution provided in this application is: to provide a semiconductor device, including: a substrate of a first conductivity type and an epitaxial layer disposed on the substrate, and a plurality of unit cells disposed on the epitaxial layer;

[0010] The unit cell includes: a plurality of semiconductor units disposed in the epitaxial layer, a gate trench, and a shielding layer; the gate trench is disposed between any two semiconductor units, and the shielding layer extends from the bottom of the gate trench toward the substrate;

[0011] The plurality of semiconductor units include: a plurality of first semiconductor units and a second semiconductor unit, wherein a plurality of first semiconductor units are arranged circumferentially around a second semiconductor unit;

[0012] The first semiconductor unit includes: a body region of a second conductivity type, a body region contact region of a second conductivity type, and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region;

[0013] The second semiconductor unit includes: a shielding region of a second conductivity type; the shielding region extends from the surface of the epitaxial layer toward the substrate, and the shielding region is in contact with the shielding layer.

[0014] To address the aforementioned technical problems, the third technical solution provided in this application is: a method for fabricating a semiconductor device, comprising:

[0015] Provide a substrate of the first conductivity type;

[0016] An epitaxial layer is formed on the substrate;

[0017] A plurality of semiconductor units are disposed on the epitaxial layer; a shielding layer is disposed between any two semiconductor units; and a gate trench is disposed on the shielding layer.

[0018] The plurality of semiconductor units includes: a plurality of first semiconductor units and a plurality of second semiconductor units, wherein the second semiconductor units are configured to circumferentially surround the plurality of first semiconductor units; the first semiconductor units include: a body region of a second conductivity type, a body region contact region of a second conductivity type, and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region; the second semiconductor units include: a shielding region of a second conductivity type; the shielding region extends from the surface of the epitaxial layer to the substrate, and the shielding region is in contact with the shielding layer.

[0019] The beneficial effects of this application are as follows: Unlike the prior art, this application discloses a semiconductor device and its fabrication method. The semiconductor device includes a substrate of a first conductivity type and an epitaxial layer disposed on the substrate. The semiconductor device also includes: a plurality of semiconductor units, a plurality of gate trenches, and a plurality of shielding layers disposed in the epitaxial layer. The gate trenches are disposed between any two semiconductor units, and the shielding layers extend from the bottom of the gate trenches toward the substrate. The plurality of semiconductor units include: a plurality of first semiconductor units and a plurality of second semiconductor units, wherein the second semiconductor units are configured to have a plurality of first semiconductor units disposed circumferentially around them. The first semiconductor unit includes: a body region of a second conductivity type, a body region contact region of a second conductivity type, and a source region of a first conductivity type. The body region extends from the epitaxial layer toward the substrate. The body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region. The second semiconductor unit includes: a shielding region of a second conductivity type. The shielding region extends from the surface of the epitaxial layer toward the substrate and contacts the shielding layer, connecting the shielding layer at the bottom of the gate trench to the source region through the shielding region, thereby eliminating the phenomenon that holes flow out of the shielding layer and cannot flow back in the floating state, ensuring the normal conduction of the device. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1a This is a schematic diagram of a SiC trench MOSFET structure with a P-type masking layer added to the bottom of the gate trench in the prior art;

[0022] Figure 1b This is a schematic diagram of the structure in the prior art where a P-type shielding layer is grounded through a main junction;

[0023] Figure 2a This is a schematic diagram of the layout structure of the semiconductor device provided in the embodiments of this application;

[0024] Figure 2b yes Figure 2a The diagram shows the structure of the semiconductor device as viewed from the surface of the epitaxial layer.

[0025] Figure 3 yes Figure 2a The diagram shows a cross-sectional view of the semiconductor device along line AA.

[0026] Figure 4 yes Figure 2a A schematic cross-sectional view of the semiconductor device along line BB;

[0027] Figure 5 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application;

[0028] Figure 6 yes Figure 5 The diagram shows the structure of step S02.

[0029] Figure 7a yes Figure 5 The flowchart of step S03 is shown below;

[0030] Figure 7b yes Figure 7a The diagram shows the structure of step S031.

[0031] Figure 8 yes Figure 7a The diagram shows the structure of step S032.

[0032] Figure 9 yes Figure 7a The diagram shows the structure of step S033.

[0033] Figure 10 yes Figure 7a The diagram shows the structure of step S034.

[0034] Figure 11 yes Figure 7a The diagram shows the structure of step S036.

[0035] Figure 12 yes Figure 5 The diagram shows the structure of step S04.

[0036] Figure 13 yes Figure 5 The diagram shows the structure of the intermediate process in step S05.

[0037] Figure 14 yes Figure 5 A schematic diagram of the structure of step S05 is shown;

[0038] Figure 15 yes Figure 5 The diagram shows the structure of the intermediate process in step S06.

[0039] Figure 16 yes Figure 5 The diagram shows the structure of step S06.

[0040] Figure 17 yes Figure 5 The diagram shows the structure of the intermediate process in step S07.

[0041] Figure 18 yes Figure 5The diagram shows the structure of step S07.

[0042] Figure 19 yes Figure 5 The diagram shows the structure of the intermediate process in step S08.

[0043] Figure 20 yes Figure 5 The diagram shows the structure of step S08. Detailed Implementation

[0044] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0045] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0046] The terms "first," "second," and "third" in this application are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the stated features. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movement of components in a specific posture (as shown in the figures). If the specific posture changes, the directional indications also change accordingly. The terms "comprising" and "having," and any variations thereof, in the embodiments of this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or components inherent to these processes, methods, products, or devices.

[0047] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0048] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] Compared to silicon (Si), third-generation semiconductor silicon carbide (SiC) has a wider bandgap and a higher electric field strength. Therefore, at the same breakdown voltage, SiC power devices require only one-tenth the epitaxial layer thickness of Si power devices, and the doping concentration is one hundred times higher. This significantly reduces drift region resistance, making it the core material for next-generation power electronic devices. Currently, SiC power devices are used in wind power generation, new energy vehicles, and charging piles. It should be noted that Si or SiC is the substrate material for power devices.

[0050] Similar to the development of Si power devices, SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) have also evolved from planar structures to trench structures, increasing current density, reducing power device resistance, and improving performance. While trench structures further reduce resistance, they also introduce reliability issues. This is because SiC has a high breakdown electric field, and the gate oxide layer (gate oxide) of SiC power devices experiences a large voltage during breakdown, potentially causing gate oxide leakage and threshold voltage drift. The curvature effect at the trench corners further concentrates the electric field, leading to even greater reliability problems. Therefore, when designing trench-type SiC MOSFETs, it is necessary to reduce the electric field in the gate oxide layer at the trench corners. To reduce the electric field, James A. Cooper proposed a structure that adds a P-type masking layer 12 at the bottom of the gate trench 11, utilizing the PN junction formed at the bottom of the gate trench 11 to protect the trench corners. Figure 1a As shown, Figure 1a This is a schematic diagram of a SiC trench MOSFET structure with a P-type masking layer added to the bottom of the gate trench in the prior art. However, although this structure protects the gate oxide 13, it introduces a JFET resistor between the P-type masking layer 12 and the P-type base layer 14, resulting in an increase in the semiconductor unit resistance. When the spacing between the P-type masking layer 12 and the P-type base layer 14 is too small, the device is at risk of pinch-off and loses its normal output characteristics. In addition, when the spacing between the P-type masking layer 12 and the P-type base layer 14 is too small and the P-type masking layer 12 at the bottom of the gate trench 11 is in a floating state, holes flow from the P-type masking layer 12 to the P-type base layer 14 during the turn-off process and cannot flow back, resulting in a larger depletion region when the device is turned on, thereby increasing the resistance and loss during conduction and preventing normal operation.

[0051] To address the issue of holes flowing from the P-type shielding layer 12 to the P-type base layer 14 and failing to return, the P-type shielding layer 12 at the bottom of the trench 11 needs to be grounded. The existing method connects the P-type shielding layer 12 to the main junction 15 outside the active region on both sides of the trench 11, and grounding is achieved through the source bar 16 on the main junction 15, such as... Figure 1b As shown, Figure 1b This is a schematic diagram of a P-type shielding layer grounded through a main junction in the prior art. However, in this grounding method, the trench 11 is relatively long. An excessively long trench cannot effectively reduce the series resistance of the P-type shielding layer 12. The potential of the P-type shielding layer 12 in the middle region of the trench 11 is not zero, resulting in an increase in conduction resistance similar to that in a floating state.

[0052] It is understandable that, in addition to SiC MOSFETs, MOSFETs with substrates made of other materials also suffer from the aforementioned problems. Therefore, this application provides a semiconductor device to offer a novel grounding method, eliminating the phenomenon of holes flowing out of the P-type masking layer and being unable to return.

[0053] Please see Figures 2a-4 , Figure 2a This is a schematic diagram of the layout structure of the semiconductor device provided in the embodiments of this application. Figure 2b yes Figure 2a The diagram shown is a schematic representation of the semiconductor device as viewed from the surface of the epitaxial layer. Figure 3 yes Figure 2a The diagram shows a cross-sectional view of the semiconductor device along line AA. Figure 4 yes Figure 2a The diagram shows a cross-sectional view of the semiconductor device along line BB.

[0054] The semiconductor device includes a substrate 21, a gate oxide 22, a gate electrode 23, a dielectric layer 24, a source layer 25, and a drain layer 26.

[0055] The substrate 21 includes a first conductivity type substrate 214 and an epitaxial layer 215 disposed on the substrate 214, which are stacked sequentially. The doping concentration of the epitaxial layer 215 is 1×10⁻⁶. 15 cm -3 Up to 2×10 16 cm -3 The thickness of the epitaxial layer 215 is 5 μm to 60 μm. The substrate 214 can be made of SiC, or other materials such as Si, Ga2O3, GaN, or diamond. Optionally, the first conductivity type is N-type; that is, both the substrate 214 and the epitaxial layer 215 are N-type.

[0056] The epitaxial layer 215 is provided with a plurality of semiconductor units 211, a plurality of gate trenches 213 and a plurality of shielding layers 212. The gate trenches 213 are disposed between any two semiconductor units 211, and the shielding layers 212 extend from the bottom of the gate trenches 213 toward the substrate 214; that is, the semiconductor units 211 are spaced apart, and the shielding layers 212 are located between any two semiconductor units 212.

[0057] The plurality of semiconductor units 211 includes a plurality of first semiconductor units 2111 and a plurality of second semiconductor units 2112. The second semiconductor units 2112 are configured to have a plurality of first semiconductor units 2111 arranged circumferentially around them, that is, each second semiconductor unit 2112 has a plurality of first semiconductor units 2111 arranged circumferentially around it. The top surfaces of the plurality of semiconductor units 211 are flush.

[0058] The first semiconductor unit 2111 includes a body region 2111a of a second conductivity type, a body region contact region 2111b of a second conductivity type, and a source region 2111c of a first conductivity type. The body region 2111a extends from the epitaxial layer 215 toward the substrate 214, and the body region contact region 2111b and the source region 2111c extend from the surface of the epitaxial layer 215 to the surface of the body region 2111a; in other words, the body region contact region 2111b and the source region 2111c are located on the surface of the body region 2111a away from the substrate 214. The source region 2111c is disposed around the entire circumference of the body region contact region 2111b. The thickness of the body region 2111a is 0.8 μm to 2 μm, and the doping concentration of the body region 2111a is 5 × 10⁻⁶. 16 cm -3 Up to 5×10 18 cm -3 The thickness of the body contact region 2111b is 0.3 μm to 1 μm, and the doping concentration of the body contact region 2111b is 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The thickness of the source region 2111c is 0.3 μm to 1 μm, and the doping concentration of the source region 2111c is 1 × 10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 Optionally, the second conductivity type is P-type; that is, the body region 2111a and the body contact region 2111b are P-type doped, and the source region 2111c is N-type doped.

[0059] The top surface of the body contact region 2111b is flush with the top surface of the source region 2111c; wherein, the top surface of the body contact region 2111b refers to the surface of the body contact region 2111b away from the substrate 214, and the top surface of the source region 2111c refers to the surface of the source region 2111c away from the substrate 214. The surface of the body region 2111a away from the substrate 214 is a plane and parallel to the substrate 214. The projections of the body contact region 2111b and the source region 2111c onto the body region 2111a completely coincide with the body region 2111a.

[0060] In this embodiment, the source region 2111c and the body region contact region 2111b are concentrically arranged, and the center of the body region contact region 2111b corresponds to the center of the body region 2111a. In other embodiments, the center of the body region contact region 2111b is offset from the center of the body region 2111a, so that the source region 2111c is present in the circumference of the body region contact region 2111b.

[0061] The second semiconductor unit 2112 includes a shielding region 2112a of a second conductivity type, which extends from the surface of the epitaxial layer 215 toward the substrate 214. In this embodiment, the second semiconductor unit 2112 is a shielding region 2112a of a second conductivity type, that is, the second semiconductor unit 2112 has no other structure besides the shielding region 2112a of the second conductivity type; in other embodiments, the second semiconductor unit 2112 includes other structures besides the shielding region 2112a of the second conductivity type, which are designed according to specific needs. Optionally, the second conductivity type is P-type, and the shielding region 2112a is P-type doped.

[0062] The shielding layer 212 is lower than the two adjacent semiconductor cells 211 to form a gate trench 213 between the two adjacent semiconductor cells 211. In other words, the top surface of the shielding layer 212 is lower than the bottom surface of the two adjacent semiconductor cells 211 to form a gate trench 213 between the two adjacent semiconductor cells 211. The top surface of the shielding layer 212 serves as the bottom surface of the gate trench 213. From the perspective of Figure 2, the shape of the gate trench 213 is the same as the shape of the shielding layer 212. The bottom surface of the semiconductor cell 211 refers to the surface of the semiconductor cell 211 closest to the substrate 214, and the top surface of the shielding layer 212 refers to the surface of the shielding layer 212 furthest from the substrate 214. The thickness of the shielding layer 212 is 1.3 μm to 3 μm, and the doping concentration of the shielding layer 212 is 1 × 10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The width of the gate trench 213 is 0.5 μm to 2 μm, and the depth of the gate trench 213 is 0.8 μm to 3 μm.

[0063] Gate oxide 22 is disposed on the inner surface of gate trench 213, and the thickness of gate oxide 22 is 30nm to 80nm. By providing a shielding layer 212 at the bottom of gate trench 213, the reliability of gate oxide 22 in trench semiconductor devices is improved, meeting industrial and automotive-grade reliability requirements. Gate 23 is disposed within gate trench 213; optionally, the material of gate 23 is polysilicon.

[0064] A dielectric layer 24 is disposed on the first surface of the substrate 21 and covers the gate 23. The thickness of the dielectric layer 24 is 0.5 μm to 1.5 μm. The dielectric layer 24 has an opening corresponding to the semiconductor cell 211 (not shown). A source layer 25 is disposed on the surface of the dielectric layer 24 away from the substrate 21 and forms an ohmic contact with the semiconductor cell 211 through the opening in the dielectric layer 24; the thickness of the source layer 25 is 1 μm to 2 μm. A drain layer 26 is disposed on the second surface of the substrate 21.

[0065] In this embodiment, the shielding region 2112a of the second conductivity type is in contact with the shielding layer 212. The shielding layer 212 at the bottom of the gate trench 213 is connected to the source layer 25 through the shielding region 2112a of the second conductivity type, thereby achieving grounding. This eliminates the phenomenon that holes flow out of the shielding layer 212 in the floating state and cannot return, thus avoiding the phenomenon of increased device on-resistance, improving switching speed, reducing switching losses, and ensuring normal device conduction.

[0066] Referring to Figure 2, in this embodiment, multiple semiconductor units 211 are arranged in a two-dimensional array. Odd-numbered rows or columns include multiple spaced-apart first semiconductor units 2111. Even-numbered rows or columns include multiple first semiconductor units 2111 and multiple second semiconductor units 2112, with the first semiconductor units 2111 and second semiconductor units 2112 alternating, i.e., arranged in the order of first semiconductor unit 2111, second semiconductor unit 2112, first semiconductor unit 2111, second semiconductor unit 2112, and first semiconductor unit 2111. In other words, the distance between any two adjacent first semiconductor units 2111 is equal, and the distance between a first semiconductor unit 2111 and a second semiconductor unit 2112 is equal to the distance between two adjacent first semiconductor units 2111. The arrangement of the multiple semiconductor units 211 shown in Figure 2 improves the robustness of the device, increases the short-circuit time, and facilitates the design of external protection circuits.

[0067] It should be noted that the distribution density of the second semiconductor cell 2112 can be adjusted as needed, as long as the shielding layer 212 at the bottom of the gate trench 213 can be connected to the source layer 25 through the shielding region 2112a of the second conductivity type. This application does not limit it to the distribution density shown in FIG2. The distribution density of the second semiconductor cell 2112 can adjust the short-circuit capability of the semiconductor device, thereby realizing the adjustment functions of on-resistance, switching loss and short-circuit capability.

[0068] The distance between two adjacent first semiconductor units 2111 and the distance between the first semiconductor unit 2111 and the second semiconductor unit 2112 are designed according to specific needs, so that the shielding layer 212 at the bottom of the gate trench 213 can be connected to the source layer 25 through the shielding area 2112a of the second conductivity type.

[0069] The shielding layer 212 includes a first masking strip 2121 located between two adjacent rows of semiconductor cells 211 and a second masking strip 2122 located between two adjacent columns of semiconductor cells 211. Multiple first masking strips 2121 and multiple second masking strips 2122 are intersected and interconnected. By configuring the shielding layer 212 as described above, the shielding layer 212 between two adjacent first semiconductor cells 2111 located in the circumferential direction of the second semiconductor cell 2112 can also be connected to the source layer 25 through the shielding region 2112a.

[0070] Optionally, the bottom surface of the shielding layer 212 is flush with the bottom surface of the shielding region 2112a. The side surface of the shielding layer 212 contacts the side surface of the shielding region 2112a. By making the bottom surface of the shielding layer 212 flush with the bottom surface of the shielding region 2112a of the second conductivity type, the shielding layer 212 and the shielding region 2112a have the largest contact area, ensuring the reliability of the shielding layer 212's connection to the source layer 25 through the shielding region 2112a. Here, the bottom surface of the shielding layer 212 refers to the surface of the shielding layer 212 near the substrate 214; the bottom surface of the shielding region 2112a refers to the surface of the shielding region 2112a near the substrate 214. It is understood that the bottom surface of the shielding layer 212 may not be flush with the bottom surface of the shielding region 2112a, as long as the shielding layer 212 can be connected to the source layer 25 through the shielding region 2112a.

[0071] Optionally, the multiple semiconductor units 211 may have the same shape and size.

[0072] Optionally, the surface of each semiconductor unit 211 can be a polygon such as a square, hexagon, octagon, or dodecagon. It should be noted that, for the same area, the longer the side length of the polygon, the greater the density of the gate trench 213, the greater the current, and the smaller the resistance.

[0073] Continue reading Figure 2a and Figure 2b A plurality of unit cells M are disposed on the epitaxial layer 215. Each unit cell M includes a plurality of semiconductor units 211, a plurality of gate trenches 213, and a plurality of shielding layers 212 disposed on the epitaxial layer 215. The gate trenches 213 are disposed between any two semiconductor units 211, and the shielding layers 212 extend from the bottom of the gate trenches 213 toward the substrate 214. The plurality of semiconductor units 211 include a plurality of first semiconductor units 2111 and a second semiconductor unit 2112, with a plurality of first semiconductor units 2111 arranged circumferentially around the second semiconductor unit 2112. The specific structures of the first semiconductor units 2111 and the second semiconductor units 2112 and their positional relationships are described above. Adjacent unit cells M share a plurality of first semiconductor units 2111 on their adjacent side.

[0074] By making the above-mentioned configuration of the first semiconductor unit 2111, the second semiconductor unit 2112, and the shielding layer 212, the reliability of the device is improved and meets the industrial and automotive-grade reliability requirements; the switching characteristics of the device are guaranteed to conduct normally, and the switching losses are reduced; the robustness of the device is improved, the short-circuit time is increased, and the design of external protection circuits is facilitated.

[0075] Please see Figures 5-20 , Figure 5 This is a schematic flowchart of a semiconductor device fabrication method provided in an embodiment of this application. Figure 6 yes Figure 5 The diagram shown is a structural schematic of step S02. Figure 7a yes Figure 5 The flowchart of step S03 shown is as follows. Figure 7b yes Figure 7a The diagram shown is a structural schematic of step S031. Figure 8 yes Figure 7a The diagram shown is a structural schematic of step S032. Figure 9 yes Figure 7a The diagram shows the structure of step S033. Figure 10 yes Figure 7a The diagram shows the structure of step S034. Figure 11 yes Figure 7a The diagram shown is a structural schematic of step S036. Figure 12 yes Figure 5 The diagram shows the structure of step S04. Figure 13 yes Figure 5 The diagram shows the structure of the intermediate process in step S05. Figure 14 yes Figure 5 The diagram shown is a structural schematic of step S05. Figure 15 yes Figure 5 The diagram shows the structure of the intermediate process in step S06. Figure 16yes Figure 5 The diagram shown is a structural schematic diagram of step S06. Figure 17 yes Figure 5 The diagram shows the structure of the intermediate process in step S07. Figure 18 yes Figure 5 The diagram shows the structure of step S07. Figure 19 yes Figure 5 The diagram shows the structure of the intermediate process in step S08. Figure 20 yes Figure 5 The diagram shows the structure of step S08.

[0076] This application also provides a method for fabricating a semiconductor device to prepare the semiconductor device provided in the above embodiments. Specifically, the method is described in detail with SiC as the material of the substrate 21.

[0077] Step S01: Provide a substrate of a first conductivity type.

[0078] In one embodiment, the first conductivity type is N-type; the substrate 214 is N-type and the material is SiC.

[0079] Step S02: Form an epitaxial layer on the substrate.

[0080] Specifically, a SiCN-type epitaxial layer 215 is grown on a selected SiC N-type substrate 214 using a low-pressure chemical vapor deposition (LPCVD) apparatus, with a doping concentration ranging from 1×10⁻⁶. 15 cm -3 Up to 2×10 16 cm -3 With a thickness of 5μm to 60μm, the structure is as follows: Figure 6 As shown.

[0081] Step S03: A plurality of semiconductor units are disposed on the epitaxial layer; a shielding layer is disposed between any two semiconductor units; and a gate trench is disposed on the shielding layer.

[0082] Specifically, a plurality of semiconductor cells 211, a shielding layer 212, and a gate trench 213 are formed on the epitaxial layer 215 using a mask. The plurality of semiconductor cells 211 include a plurality of first semiconductor cells 2111 and a plurality of second semiconductor cells 2112. The second semiconductor cells 2112 are configured to have a plurality of first semiconductor cells 2111 arranged circumferentially around them. Each first semiconductor cell 2111 includes a body region 2111a of a second conductivity type, a body region contact region 2111b of a second conductivity type, and a source region 2111c of a first conductivity type. The body region 2111a extends from the epitaxial layer 215 toward the substrate 214, and the body region contact region 2111b and the source region 2111c extend from the surface of the epitaxial layer 215 to the surface of the body region 2111a. The second semiconductor cells 2112 include a shielding region 2112a of a second conductivity type, which extends from the surface of the epitaxial layer 215 toward the substrate 214. The shielding area 2112a is in contact with the shielding layer 212.

[0083] The specific steps for setting multiple semiconductor units 211, shielding layer 212, and gate trench 213 on epitaxial layer 215 include:

[0084] Step S031: High-temperature implantation is performed on the epitaxial layer to form multiple spaced-apart body regions of the second conductivity type.

[0085] In one embodiment, the second conductivity type is P-type. A repeating body region 2111a of the second conductivity type is implanted into the N-type epitaxial layer 215 using a high-temperature implantation device, with a doping concentration ranging from 5 × 10⁻⁶. 16 cm -3 Up to 5×10 18 cm -3 The thickness ranges from 0.8 μm to 2 μm, and the structure is shown in Figure 7.

[0086] Step S032: Perform a second high-temperature implantation on the epitaxial layer to form a body region contact region of the second conductivity type on the top surface of the body region of the second conductivity type.

[0087] Specifically, a second conductivity type body region contact region 2111b is formed in the middle region of the top surface of the second conductivity type body region 2111a using a high-temperature injection device, with a doping concentration range of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The thickness ranges from 0.3 μm to 1 μm, and the structure is as follows: Figure 8 As shown.

[0088] Step S033: Under MeV energy, implantation is performed on the epitaxial layer to form a pre-shielding layer and a shielding region of the second conductivity type; the first side of the pre-shielding layer is in contact with a body region of the second conductivity type, and the second side of the pre-shielding layer is in contact with the shielding region of the second conductivity type or another body region of the second conductivity type, with the first side and the second side being arranged opposite to each other.

[0089] Specifically, at MeV energy, a second conductivity type shielding region 2112a with a square distribution is implanted, and a pre-shielding layer 212a is formed at the location of the gate trench 213 but not yet etched, with a doping concentration range of 1×10⁻⁶. 18 cm -3 Up to 1×10 20 cm -3 The thickness ranges from 1.3 μm to 3 μm, and the structure is as follows: Figure 9 As shown.

[0090] Step S034: Perform high-temperature implantation on the epitaxial layer again to form a source region of the first conductivity type on the top surface of the body region of the second conductivity type, and the source region contacts the body region.

[0091] Specifically, a ring-shaped source region 2111c of the first conductivity type is formed by implantation using a high-temperature implantation device. The ring-shaped source region 2111c is located outside the contact region 2111b of the bulk region, and the doping concentration ranges from 1×10⁻⁶. 19 cm -3 Up to 1×10 20 cm -3 The thickness ranges from 0.3 μm to 1 μm, and the structure is as follows: Figure 10 As shown.

[0092] Step S035: Activate the contact region between the source region and the bulk region.

[0093] Specifically, impurities in the source region 2111c and the contact region 2111b of the body region are activated using a high-temperature annealing device at a temperature of 1600°C to 1850°C for 5 minutes to 1 hour.

[0094] Step S036: Etch the prepared shielding layer to form the shielding layer and gate trench.

[0095] Specifically, using an inductively coupled plasma (ICP) device, the pre-shielding layer 212a in the space before the body region 2111a of the second conductivity type and the space between the shielding region 2112a of the second conductivity type and the body region 2111a of the second conductivity type is etched to form a cross-shaped gate trench 213. The trench width ranges from 0.5 μm to 2 μm, and the trench depth ranges from 0.8 μm to 3 μm, as shown in the figure. Figure 11 As shown.

[0096] Step S04: Form gate oxide on the inner surface of the gate trench.

[0097] Specifically, gate oxide 22 is formed using thermal oxidation or low-pressure chemical vapor deposition (LPCVD) equipment, with a thickness ranging from 30 nm to 80 nm, and a structure as follows: Figure 12 As shown.

[0098] Step S05: Form a gate in the gate trench.

[0099] Specifically, polycrystalline silicon is deposited using a low-pressure chemical vapor deposition (LPCVD) system with a thickness ranging from 0.3 μm to 1.5 μm, and the structure is as follows: Figure 13 As shown; the polysilicon on the mesa is etched using an inductively coupled plasma (ICP) device to form the gate 23, with the structure as shown. Figure 14 As shown.

[0100] Step S06: Form a dielectric layer on the surface of the substrate.

[0101] Specifically, silicon oxide is deposited using a low-pressure chemical vapor deposition (LPCVD) apparatus to form a preparative dielectric layer 24a with a thickness ranging from 0.5 μm to 1.5 μm, and the structure is as follows: Figure 15 As shown. The dielectric layer 24 is etched using an inductively coupled plasma (ICP) device to form an ohmic contact hole 241, as shown in the diagram. Figure 16 As shown.

[0102] Step S07: Form the source layer.

[0103] Specifically, Ti / Ni is deposited on the surface of dielectric layer 24 using metal evaporation equipment, with a thickness ranging from [missing information]. to to Structure as Figure 17 As shown. The device was annealed using a rapid annealing furnace (RTA) to form a 25-ohm source layer contact at temperatures ranging from 700°C to 980°C for 100 to 300 seconds. An Al layer was then deposited on the device using a metal evaporation apparatus, with a thickness ranging from 1 μm to 2 μm, as shown in the diagram. Figure 18 As shown, metal Al is etched using inductively coupled plasma (ICP) equipment or wet etching to form the gate 23 and source layer 25 metal pads.

[0104] Step S08: Form the drain layer.

[0105] Specifically, Ti / Ni is deposited on the back of the device using metal evaporation equipment, with a thickness of [missing information]. Structure as Figure 19As shown, the device is annealed using a rapid annealing furnace (RTA) to form a 26-ohm drain layer contact at temperatures ranging from 700°C to 980°C for 100 to 300 seconds. A Ti / Ni / Ag layer is then deposited onto the device using a metal evaporation apparatus to form a drain metal pad with a thickness ranging from 1 μm to 2 μm, as shown in the diagram. Figure 20 As shown.

[0106] This application also provides a specific preparation method embodiment, as follows:

[0107] (1) Using LPCVD, a doping concentration of 8×10⁻⁶ was grown on a 350 μm SiC N-type substrate 214. 15 cm -3 A 10μm thick SiC N-type epitaxial layer 215.

[0108] (2) After patterning the mask using a photolithography machine and ICP equipment, Al atoms were repeatedly implanted into the SiC N-type epitaxial layer 215 at 500℃ using a high-temperature ion implantation device to form a P-type bulk region 2111a with a side length of 5μm and a repeating spacing of 1.0μm; the implantation energies were 450keV, 280keV, and 120keV, and the implantation doses were 2×10⁻⁶. 13 cm -2 1×10 13 cm -2 3×10 13 cm -2 .

[0109] (3) After patterning the mask using a photolithography machine and ICP equipment, Al atoms were repeatedly implanted into the SiC N-type epitaxial layer 215 at 500℃ using a high-temperature ion implantation device to form a square P-type bulk contact region 2111b with a side length of 2μm in the middle of the bulk region 2111a. The implantation energies were 180keV, 120keV, 80keV, 60keV, and 30keV, and the implantation doses were 3×10⁻⁶. 14 cm -2 2×10 14 cm -2 4×10 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 .

[0110] (4) After patterning the mask using a photolithography machine and ICP equipment, a P-type shielding region 2112a with an outer side length of 5 μm square distribution is formed by implantation. Simultaneously, a pre-shielding layer 212a with a width of 1 μm is formed at the gate trench 213 location where etching has not yet occurred. The implantation energies are 1.1 MeV, 930 keV, 750 keV, 580 keV, 360 keV, 180 keV, 80 keV, and 30 keV, respectively, and the implantation doses are 4 × 10⁻⁶. 14 cm -2 2×10 14 cm -2 4×10 14 cm -2 2×10 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 2×10 14 cm -2 .

[0111] (5) After patterning the mask using a photolithography machine and ICP equipment, N atoms are implanted multiple times at 500℃ using a high-temperature ion implantation device to form a ring-shaped N-type source region 2111c. The ring-shaped N-type source region 2111c is located outside the P-type bulk contact region 2111b. The implantation energies are 200keV, 100keV, and 30keV, and the implantation doses are 5×10⁻⁶. 14 cm -2 2×10 14 cm -2 3×10 14 cm -2 .

[0112] (6) Sputtering on the wafer surface The carbon film was then annealed at 1650℃ for 30 minutes in a high-temperature annealing furnace under an Ar atmosphere of 20 mTorr to activate the doped atoms.

[0113] (7) After mask patterning, the shielding layer 212a is etched using ICP equipment to form a gate trench 213 with a width of 1.0 μm and a depth of 1.0 μm.

[0114] (8) Using a wet oxidation method, oxidize at 1000℃ for 1 hour to form a sacrificial oxide layer of about 20 nm;

[0115] (9) Use BOE to rinse the wafer for 10 minutes to remove the sacrificial oxide layer generated above.

[0116] (10) A 100nm layer of SiO2 was deposited using LPCVD to form gate oxide 22;

[0117] (11) Using LPCVD, a thickness of 0.8 μm and a doping concentration of 1×10⁻⁶ were grown. 20 cm -3 N-type heavily doped polycrystalline silicon; the doping element can be a P atom.

[0118] (12) The polysilicon on the mesa is removed by ICP etching, and the polysilicon in the gate trench 213 is retained to form the gate 23.

[0119] (13) A 1.0 μm thick SiO2 layer is grown on the wafer using LPCVD to form a dielectric layer 24. Then, using photoresist as a mask, part of the dielectric layer 24 on the mesa is removed by ICP etching to form an ohmic contact hole 241.

[0120] (14) A layer of thickness is deposited on the wafer using an evaporation deposition device. The Ti / Ni layer is then annealed at 950°C using an RTA device to form a 25-ohm source layer contact.

[0121] (15) Remove the residual Ni on the photoresist by stripping.

[0122] (16) Using photoresist as a mask, ICP etching is used to remove part of the SiO2 and open the contact hole in the gate 23 region.

[0123] (17) A layer of Al with a thickness of 2 μm is deposited on the wafer using a metal vapor deposition equipment.

[0124] (18) Use an ICP device to remove part of the Al metal to form the source layer 25 and the gate 23Pad.

[0125] (19) Ti / Ni was deposited on the back of the device using a metal evaporation deposition apparatus, with a thickness of [missing information]. Then, the drain layer is annealed at 950°C using an RTA device to form a 26-ohm drain contact.

[0126] (20) A 2μm thick Ti / Ni / Ag layer is deposited on the device using a metal evaporation equipment to form a drain layer 26 metal Pad.

[0127] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A semiconductor device, characterized in that, Comprising: a substrate of a first conductivity type and an epitaxial layer disposed on the substrate; the semiconductor device further comprises: a plurality of semiconductor units disposed in the epitaxial layer, a plurality of gate trenches and a plurality of shielding layers; the gate trenches are disposed between any two semiconductor units, and the shielding layers extend from the bottom of the gate trenches to the substrate; the plurality of semiconductor units comprises: a plurality of first semiconductor units and a plurality of second semiconductor units, wherein the second semiconductor units are configured to be circumferentially arranged around the plurality of first semiconductor units; the first semiconductor unit comprises: a body region of a second conductivity type, a body contact region of the second conductivity type, and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region; the second semiconductor unit comprises: a shielding region of the second conductivity type; the shielding region extends from the surface of the epitaxial layer to the substrate, and the shielding region is in contact with the shielding layer; wherein the plurality of semiconductor units are arranged in a two-dimensional array; an odd row or an odd column comprises a plurality of first semiconductor units arranged at intervals; an even row or an even column comprises a plurality of first semiconductor units and a plurality of second semiconductor units, and the first semiconductor units and the second semiconductor units are arranged alternately; the shielding layer comprises a first shielding strip located between two adjacent rows of semiconductor units and a second shielding strip located between two adjacent columns of semiconductor units; a plurality of first shielding strips and a plurality of second shielding strips are arranged in a cross shape and are connected to each other.

2. The semiconductor device according to claim 1, wherein The bottom surface of the shielding layer is flush with the bottom surface of the shielding region.

3. The semiconductor device of claim 1, wherein The top surface of the shielding layer is lower than the bottom surface of the semiconductor unit.

4. The semiconductor device of claim 1, wherein The source region is arranged around the body contact region; the second semiconductor unit is a shielding region of the second conductivity type.

5. The semiconductor device of claim 4, wherein, The source region and the body contact region are concentrically arranged, and the center of the body contact region corresponds to the center of the body region.

6. The semiconductor device of claim 1, wherein The material of the substrate is one of SiC, Si, Ga2O3, GaN, and diamond.

7. The semiconductor device of claim 1, wherein The shapes and sizes of the plurality of semiconductor units are the same; and / or, the shape of the surface of the semiconductor unit is a square, a hexagon, an octagon, or a dodecagon.

8. The semiconductor device of claim 1, wherein Further comprising: gate oxide, disposed on the inner surface of the gate trench; gate, disposed in the gate trench; dielectric layer, disposed on the surface of the epitaxial layer and covering the gate; the dielectric layer has an opening corresponding to the semiconductor unit; source layer, disposed on the surface of the dielectric layer away from the epitaxial layer and forming ohmic contact with the semiconductor unit through the opening; drain layer, disposed on the surface of the substrate away from the epitaxial layer.

9. The semiconductor device of claim 1, wherein, The thickness of the body region is 0.8-2 μm; the thickness of the body contact region is 0.3-1 μm; the thickness of the source region is 0.3-1 μm; the thickness of the shielding layer is 1.3-3 μm; the width of the gate trench is 0.5-2 μm, and the depth of the gate trench is 0.8-3 μm.

10. A semiconductor device, characterized by comprising: Comprising: A substrate of a first conductivity type and an epitaxial layer disposed on the substrate, and a plurality of cells disposed on the epitaxial layer; The cell comprises: a plurality of semiconductor units disposed in the epitaxial layer, a gate trench and a shielding layer; the gate trench is disposed between any two semiconductor units, and the shielding layer extends from the bottom of the gate trench to the substrate; The plurality of semiconductor units comprises: a plurality of first semiconductor units and one second semiconductor unit, wherein a plurality of first semiconductor units are circumferentially arranged around the second semiconductor unit; The first semiconductor unit comprises: a body region of a second conductivity type, a body region contact region of a second conductivity type and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region; The second semiconductor unit comprises: a shielding region of a second conductivity type; the shielding region extends from the surface of the epitaxial layer to the substrate, and the shielding region is in contact with the shielding layer; Wherein, the plurality of semiconductor units are arranged in a two-dimensional array; the second semiconductor unit is circumferentially surrounded by the first semiconductor unit, and adjacent two cells share a plurality of first semiconductor units on their adjacent sides. The shielding layer comprises a first shielding strip between adjacent two rows of semiconductor units and a second shielding strip between adjacent two columns of semiconductor units; a plurality of first shielding strips and a plurality of second shielding strips are cross arranged and connected to each other.

11. A method of manufacturing a semiconductor device, characterized by, Comprise: a substrate of a first conductivity type is provided; an epitaxial layer is disposed on the substrate; a plurality of semiconductor units are disposed on the epitaxial layer; and a shielding layer is disposed between any two semiconductor units; and a gate trench is disposed on the shielding layer; Wherein, the plurality of semiconductor units comprises: a plurality of first semiconductor units and a plurality of second semiconductor units, wherein the second semiconductor unit is configured to circumferentially surround a plurality of first semiconductor units; the first semiconductor unit comprises: a body region of a second conductivity type, a body region contact region of a second conductivity type and a source region of a first conductivity type; the body region extends from the epitaxial layer to the substrate; the body region contact region and the source region extend from the surface of the epitaxial layer to the surface of the body region; the second semiconductor unit comprises: a shielding region of a second conductivity type; the shielding region extends from the surface of the epitaxial layer to the substrate, and the shielding region is in contact with the shielding layer; the plurality of semiconductor units are arranged in a two-dimensional array; an odd row or an odd column comprises a plurality of first semiconductor units arranged at intervals; an even row or an even column comprises a plurality of first semiconductor units and a plurality of second semiconductor units, and the first semiconductor units and the second semiconductor units are arranged alternately; the shielding layer comprises a first shielding strip between adjacent two rows of semiconductor units and a second shielding strip between adjacent two columns of semiconductor units; a plurality of first shielding strips and a plurality of second shielding strips are cross arranged and connected to each other.

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