Display panel

Abstract

The application provides a display panel, which comprises a substrate, a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure and a gate electrode which are arranged on the substrate in a stack, and the first boss has at least one sidewall. By arranging the semiconductor structure on the sidewall of the first boss, the length of a channel can be shortened by using an existing process, and the volume of a thin film transistor can be reduced, so that the integration of the thin film transistor in the display panel can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel. BACKGROUND

[0002] Integrating pixel driving circuit, gate driving circuit, source driving circuit, time sequence controller and other circuits on a glass substrate (system on glass, SOG) can greatly improve the integration of the display panel, reduce the dependence on integrated circuit chips, and reduce the cost. Realizing SOG requires improving the integration, maximum working frequency and current density of the thin film transistor in the existing display panel, which requires the thin film transistor to have a shorter channel length, higher mobility and smaller volume.

[0003] In summary, the existing display panel has the problem that the existing process cannot reduce the channel length and volume of the thin film transistor. Therefore, it is necessary to provide a display panel to improve this defect. SUMMARY

[0004] The display panel provided by the embodiments of the present application can reduce the channel length and volume of the thin film transistor, increase the on-state current of the thin film transistor, and improve the integration of the thin film transistor in the display panel.

[0005] The display panel provided by the embodiments of the present application comprises:

[0006] a substrate;

[0007] a first ohmic contact structure disposed on the substrate;

[0008] a first protrusion disposed on a side of the first ohmic contact structure away from the substrate, the first protrusion having at least one sidewall;

[0009] a second ohmic contact structure disposed on a side of the first protrusion away from the first ohmic contact structure;

[0010] a semiconductor structure disposed on at least the sidewall and in contact with the first ohmic contact structure and the second ohmic contact structure, respectively; and

[0011] a gate disposed on a side of the semiconductor structure away from the substrate.

[0012] According to an embodiment of the present application, the first ohmic contact structure has a first sidewall adjacent to the sidewall, and the semiconductor structure is in contact with the first sidewall.

[0013] According to an embodiment of the present application, the first ohmic contact structure comprises:

[0014] a body portion disposed between the first protrusion and the substrate; and

[0015] a protrusion connected to the body portion, a projection of the protrusion on the substrate does not overlap with a projection of the first protrusion on the substrate, and the semiconductor structure is in contact with a side surface of the protrusion away from the substrate.

[0016] According to an embodiment of the present application, comprising:

[0017] a first portion disposed on the substrate and / or the first ohmic contact structure;

[0018] a second portion disposed on the sidewall and connected to the first portion; and

[0019] a third portion disposed on a side of the second ohmic contact structure away from the first protrusion and connected to the second portion.

[0020] According to an embodiment of the present application, an angle between the sidewall and a plane where the substrate is located is between 45 degrees and 90 degrees.

[0021] According to an embodiment of the present application, the first protrusion has two oppositely disposed sidewalls, and the semiconductor structure and the gate on a side of the semiconductor structure away from the substrate are disposed on both of the sidewalls.

[0022] The semiconductor structure on both of the sidewalls is in contact with the first ohmic contact structure and the second ohmic contact structure.

[0023] According to an embodiment of the present application, the semiconductor structure is continuously disposed on both of the sidewalls of the first protrusion and the second ohmic contact structure.

[0024] According to an embodiment of the present application, a projection of the gate on the substrate covers a projection of the semiconductor structure on the substrate.

[0025] According to an embodiment of the present application, the display panel comprises:

[0026] a third ohmic contact structure disposed on the substrate;

[0027] a second protrusion disposed on a side of the third ohmic contact structure away from the substrate; and

[0028] a fourth ohmic contact structure disposed on a side of the second protrusion away from the first ohmic contact structure, and the semiconductor structure is disposed on a sidewall of the second protrusion and in contact with the third ohmic contact structure and the fourth ohmic contact structure respectively;

[0029] The display panel further includes a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected to the first ohmic contact structure and the third ohmic contact structure, and the other of the source electrode and the drain electrode is electrically connected to the second ohmic contact structure and the fourth ohmic contact structure.

[0030] According to an embodiment of the present application, the semiconductor structure is continuously arranged on the first protrusion and the second protrusion and in a region between the first protrusion and the second protrusion.

[0031] According to an embodiment of the present application, a projection of the gate electrode on the substrate covers a projection of the semiconductor structure on the substrate.

[0032] According to an embodiment of the present application, the display panel further includes a gate insulating layer and an interlayer dielectric layer, the gate insulating layer is arranged at least between the gate electrode and the semiconductor structure and covers the second ohmic contact structure and the first ohmic contact structure, and the interlayer dielectric layer is arranged at a side of the gate insulating layer away from the substrate and covers the gate electrode.

[0033] The display panel further includes a source electrode and a drain electrode, both of which are arranged at a side of the interlayer dielectric layer away from the substrate, one of the source electrode and the drain electrode contacts the first ohmic contact structure through the interlayer dielectric layer and the gate insulating layer, and the other of the source electrode and the drain electrode contacts the second ohmic contact structure through the interlayer dielectric layer and the gate insulating layer.

[0034] According to an embodiment of the present application, the display panel further includes a light shielding structure, the light shielding structure is arranged at a side of the first ohmic contact structure close to the substrate, and the semiconductor structure includes a connection between the first ohmic contact structure and the second ohmic contact structure.

[0035] A projection of the light shielding structure on the substrate covers a projection of the channel portion on the substrate.

[0036] The display panel provided by the embodiments of the present application includes a substrate and a first ohmic contact structure, a second ohmic contact structure, a semiconductor structure and a gate electrode arranged in layers on the substrate, the first protrusion has at least one sidewall, the semiconductor structure is arranged on the sidewall of the first protrusion and contacts the first ohmic contact structure and the second ohmic contact structure respectively, the existing process can be used to shorten the channel length of the thin film transistor and reduce the volume of the thin film transistor, so that the integration of the thin film transistor in the display panel can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] To more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0038] Figure 1 A planar schematic diagram of a first type of thin-film transistor provided in an embodiment of this application;

[0039] Figure 2 A schematic cross-sectional view of the first thin-film transistor provided in the embodiments of this application along the BB direction;

[0040] Figure 3 A schematic cross-sectional view of the first thin-film transistor provided in the embodiments of this application along the AA direction;

[0041] Figure 4 A planar schematic diagram of a second type of thin-film transistor provided in an embodiment of this application;

[0042] Figure 5 A schematic cross-sectional view of the second type of thin-film transistor provided in the embodiments of this application along the BB direction;

[0043] Figure 6 A schematic cross-sectional view of the second type of thin-film transistor provided in the embodiments of this application along the AA direction;

[0044] Figure 7 A planar schematic diagram of a third type of thin-film transistor provided in the embodiments of this application;

[0045] Figure 8 A schematic cross-sectional view of a third type of thin-film transistor along the BB direction provided in an embodiment of this application;

[0046] Figure 9 A cross-sectional schematic diagram along the AA direction for a third type of thin-film transistor provided in an embodiment of this application;

[0047] Figure 10 This is a planar schematic diagram of a fourth type of thin-film transistor provided in an embodiment of this application;

[0048] Figure 11 A schematic cross-sectional view of the fourth type of thin-film transistor provided in the embodiments of this application along the BB direction;

[0049] Figure 12 A cross-sectional schematic diagram along the AA direction for a fourth type of thin-film transistor provided in an embodiment of this application;

[0050] Figures 13a to 13gThis is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. Detailed Implementation

[0051] The following descriptions of the embodiments are based on the accompanying illustrations and are used to illustrate specific embodiments in which this application can be implemented. Directional terms used in this application, such as [up], [down], [front], [back], [left], [right], [inner], [outer], [side], etc., are only for reference to the accompanying drawings. Therefore, the directional terms used are for illustrative and understanding purposes and not for limiting the application. In the figures, structurally similar units are represented by the same reference numerals.

[0052] The present application will be further described below with reference to the accompanying drawings and specific embodiments.

[0053] This application provides a display panel that can reduce the channel length and volume of thin-film transistors (TFTs) using existing processes, increase the on-state current of TFTs, and improve the integration density of TFTs within the display panel.

[0054] The display panel includes a substrate 10 and a plurality of thin-film transistors 20 disposed on the substrate 10. The thin-film transistors 20 can be applied in at least one circuit module of the display panel, such as a pixel driving circuit, a gate driving circuit, a source driving circuit, and a timing controller.

[0055] It should be noted that "deposited on the substrate 10" can refer to being in direct contact with the substrate 10 or to being in indirect contact with the substrate 10.

[0056] Combination Figure 1 and Figure 3 The above, Figure 1 This is a planar schematic diagram of the first type of thin-film transistor provided in the embodiments of this application. Figure 2 This is a schematic cross-sectional view of the first type of thin-film transistor provided in an embodiment of this application along the BB direction. Figure 3 This is a cross-sectional schematic diagram of a first type of thin-film transistor along the AA direction provided in an embodiment of this application. The display panel may further include a buffer layer 11, which is disposed on the surface of the substrate 10 near the thin-film transistor 20, and the thin-film transistor 20 is disposed on the buffer layer 11.

[0057] Furthermore, the display panel includes a first ohmic contact structure 21, a first boss 23, a second ohmic contact structure 22, a semiconductor structure 24, and a gate 25.

[0058] The first ohmic contact structure 21 is disposed on the substrate 10. For example, the first ohmic contact structure 21 may be disposed on the side surface of the buffer layer 11 facing away from the substrate 10.

[0059] The material of the first ohmic contact structure 21 is N-type heavily doped amorphous silicon material, and the first ohmic contact structure 21 may be doped with elemental impurities such as phosphorus or arsenic.

[0060] The first boss 23 is disposed on the side of the first ohmic contact structure 21 opposite to the substrate 10.

[0061] The material of the first protrusion 23 can be an inorganic insulating material or an organic insulating material. For example, the material of the first protrusion 23 can be commonly used inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride. The material of the first protrusion 23 can also be any one or a combination of two or more of the following materials: acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyacrylate, polycarbonate, polyimide, and polystyrene.

[0062] The second ohmic contact structure 22 is disposed on the side of the first boss 23 opposite to the first ohmic contact structure 21.

[0063] The material of the second ohmic contact structure 22 is N-type heavily doped amorphous silicon material, and the second ohmic contact structure 22 may be doped with elemental impurities such as phosphorus or arsenic.

[0064] Furthermore, the first boss 23 has at least one sidewall 230, and the semiconductor structure 24 is disposed on at least the sidewall 230 and contacts the first ohmic contact structure 21 and the second ohmic contact structure 22 respectively.

[0065] In one embodiment, the first boss 23 may have a first surface 231 and a second surface 232 disposed opposite to each other, the first surface 231 may be disposed parallel to the second surface 232, and the second surface 232 may be disposed on the side of the first surface 231 away from the substrate 10.

[0066] The first surface 231 can directly contact the side of the first ohmic contact structure 21 that is away from the substrate 10, and the second ohmic contact structure 22 can be disposed on the side of the second surface 232 that is away from the substrate 10, and can directly contact the second surface 232.

[0067] The sidewall 230 is disposed between the first surface 231 and the second surface 232, and is connected to the first surface 231 and the second surface 232 respectively. The sidewall 230 is disposed in an inclined state and forms a certain angle with the first surface 231 and the second surface 232.

[0068] The semiconductor structure 24 is disposed along the sidewall 230 and extends to contact the first ohmic contact structure 21 and the second ohmic contact structure 22, respectively.

[0069] The semiconductor structure 24 is made of undoped polycrystalline silicon. The channel portion 240 in the semiconductor structure 24, which is disposed opposite to the sidewall 230, can serve as the channel of the thin film transistor 20. The length L of the channel portion 240 extending along the sidewall 230 is the channel length of the thin film transistor.

[0070] The gate 25 is disposed on the side of the semiconductor structure 24 opposite to the substrate 10.

[0071] like Figure 2 As shown, the display panel further includes a gate insulating layer 13, which is disposed on the side of the semiconductor structure 24 away from the substrate 10 and continuously covers the semiconductor structure 24, the second ohmic contact structure 22, the first boss 23, the first ohmic contact structure 21, and the buffer layer 11.

[0072] At the first protrusion 23, a portion of the gate insulating layer 13 is laid flat on the buffer layer 11 and the horizontally arranged semiconductor structure 24. A portion of the gate insulating layer 13 extends along the semiconductor structure 24 on the sidewall 230 and is also inclined. Another portion of the gate insulating layer 13 extends to the side surface of the second ohmic contact structure 22 opposite to the first protrusion 23 and covers the semiconductor structure 24 located above the second surface 232 of the first protrusion 23.

[0073] A portion of the gate 25 is laid flat on the horizontally disposed gate insulating layer 13, and a portion of the gate 25 is disposed on the gate insulating layer 13 in an inclined state, and is also in an inclined state. Another portion of the gate 25 extends to the side surface of the gate insulating layer 13 opposite to the second ohmic contact structure 22.

[0074] The orthographic projection of the gate 25 on the sidewall 230 can cover the orthographic projection of the channel portion 240 on the sidewall 230, thus ensuring the control of the channel portion 240 by the gate 25.

[0075] In one embodiment, the first ohmic contact structure 21 has a first sidewall 210 adjacent to the sidewall 230, and the semiconductor structure 24 is in contact with the first sidewall 210.

[0076] like Figure 2 As shown, the surface of the first ohmic contact structure 21 near the first protrusion 23 completely overlaps with the first surface 231 of the first protrusion 23. The end of the first ohmic contact structure 21 near the semiconductor structure 24 has an inclined first sidewall 210, which is adjacent to the sidewall 230 of the first protrusion 23, and the semiconductor structure 24 is in contact with the first sidewall 210.

[0077] In one embodiment, the first sidewall 210 and the sidewall 230 are both flat surfaces, and the included angle between the first sidewall 210 and the sidewall 230 of the first boss 23 and the plane where the substrate 10 is located can be the same, that is, the first sidewall 210 and the sidewall 230 are on the same inclined plane.

[0078] In one embodiment, the sidewall 230 may also be an arc surface, a non-planar surface with multiple protrusions or depressions, or other irregularly shaped surfaces. The arc surface may be an arc surface that is recessed into the first protrusion 23 or an arc surface that protrudes outwards; there is no limitation here.

[0079] Furthermore, the semiconductor structure 24 is configured to extend along the sidewall 230 to the side surface of the second ohmic contact structure 22 opposite to the first boss 23.

[0080] like Figure 2 As shown, the surface of the second ohmic contact structure 22 near the first protrusion 23 completely overlaps with the second surface 232 of the first protrusion 23. The end of the second ohmic contact structure 22 near the semiconductor structure 24 has an inclined second sidewall 220, which is adjacent to the sidewall 230 of the first protrusion 23. The semiconductor structure 24 can contact the second sidewall 220 and extends along the second sidewall 220 to the surface of the second ohmic contact structure 22 facing away from the first protrusion 23.

[0081] In one embodiment, the semiconductor structure 24 may have a first part 241, a second part 242 and a third part 243. The first part 241 may be disposed on the substrate 10 and / or the first ohmic contact structure 21, the second part 242 may be disposed on the sidewall 230, and the third part 243 may be disposed on the side surface of the second ohmic contact structure 22 opposite to the first boss 23.

[0082] like Figure 2 As shown, the first part 241 can be laid flat on the side surface of the buffer layer 11 facing away from the substrate 10. When the buffer layer 11 is not provided, the first part 241 can be directly laid flat on the substrate 10. The second part 242 is not only provided on the side wall 230, but can also be provided on the first side wall 210 and the second side wall 220, so as to contact the first ohmic contact structure 21 and the second ohmic contact structure 22 respectively. The third part 243 can be laid flat on the side surface of the second ohmic contact structure 22 facing away from the first boss 23.

[0083] It should be noted that by extending the distribution range of the semiconductor structure 24 in the BB direction, extending it to the buffer layer 11 on one side of the first ohmic contact structure 21 and the surface of the second ohmic contact structure 22 facing away from the substrate 10, it is easier to achieve in existing processes and can reduce the precision requirements of the exposure machine.

[0084] In one embodiment, the semiconductor structure 24 may have only the second part 242, that is, the semiconductor structure 24 may be disposed only on the first sidewall 210, the sidewall 230 and the second sidewall 220.

[0085] The first part 241 and the third part 243 can be arranged parallel to each other and form a certain angle with the second part 242.

[0086] When the amorphous silicon in the semiconductor structure 24 is crystallized by excimer laser annealing (ELA), a seed crystal can be formed at the corner between the first part 241 and the second part 242. The seed crystal can grow along the sidewall 230 of the first protrusion 23. By controlling the length of the sidewall 230 to between 0.01 micrometers and 1 micrometer, the channel length L of the thin film transistor can be controlled to between 0.01 micrometers and 1 micrometer, so that only one grain exists in the channel portion 240 of the semiconductor structure 24.

[0087] Compared to existing low-temperature polycrystalline silicon thin-film transistors (LTS-TFTs) where the entire active layer is on a single plane, the channel length is generally greater than 2 micrometers due to limitations in exposure and etching processes, and there are many grain boundaries within the channel, resulting in low mobility for the thin-film transistor. In this embodiment, by forming the channel of the thin-film transistor (i.e., the channel portion 240 of the semiconductor structure 24) on the sidewall 230 of the first protrusion 23, the channel length of the thin-film transistor can be shortened to between 0.01 micrometers and 1 micrometer using existing processes. Furthermore, the channel is composed of a single grain and does not contain grain boundaries, thereby significantly improving the mobility of the thin-film transistor while reducing its size.

[0088] Furthermore, the angle θ between the sidewall 230 and the plane containing the substrate 10 is between 45 degrees and 90 degrees.

[0089] For example, the angle θ between the sidewall 230 and the plane where the substrate 10 is located can be 45 degrees, 60 degrees, 75 degrees, 80 degrees or 90 degrees, etc., so that the sidewall 230 of the first boss 23 can form a corner with the plane where the substrate 10 or the buffer layer 11 is located, and ensure that during the ELA process, a seed crystal growing along the sidewall 230 can be formed at the corner between the first part 241 and the second part 242.

[0090] Furthermore, the thickness H of the first protrusion 23 in the thickness direction of the display panel is between 0.0071 micrometers and 1 micrometer.

[0091] It should be noted that the channel length L of the thin-film transistor 20 is equal to the length of the sidewall 230 of the first protrusion 23. The channel length L of the thin-film transistor 20 depends on the thickness H of the first protrusion 23 along the thickness direction of the display panel and the angle θ between the sidewall 230 and the plane of the substrate 10, i.e., L = H / sinθ. By limiting the thickness H of the first protrusion 23 to between 0.0071 micrometers and 1 micrometer, and limiting the angle θ between the sidewall 230 and the plane of the substrate 10 to between 45 degrees and 90 degrees, the channel length L of the thin-film transistor can be between 0.01 micrometers and 1 micrometer, thereby ensuring that only one die exists in the channel of the thin-film transistor.

[0092] Furthermore, the display panel also includes an interlayer dielectric layer 14, a source electrode 26, and a drain electrode 27. The interlayer dielectric layer 14 is disposed on the side of the gate insulating layer 13 facing away from the substrate 10 and covers the gate electrode 25.

[0093] The source electrode 26 and the drain electrode 27 are both disposed on the side of the interlayer dielectric layer 14 away from the substrate 10. One of the source electrode 26 and the drain electrode 27 is electrically connected to the first ohmic contact structure 21, and the other of the source electrode 26 and the drain electrode 27 is electrically connected to the second ohmic contact structure 22. The thin film transistor 20 may be composed of, but is not limited to, the source electrode 26, the drain electrode 27, the first ohmic contact structure 21, the second ohmic contact structure 22, the semiconductor structure 24, and the gate electrode 25.

[0094] like Figure 3 As shown, the first ohmic contact structure 21 includes a body portion 211 and an overlapping portion 213. The body portion 211 is disposed between the first boss 23 and the substrate 10. The overlapping portion 213 is connected to the body portion 211. The orthographic projection of the overlapping portion 213 on the substrate 10 does not overlap with the orthographic projection of the first boss 23 on the substrate 10.

[0095] The overlapping portion 213 and the body portion 211 are part of the first ohmic contact structure 21. The overlapping portion 213 can be regarded as part of the first ohmic contact structure 21 that extends from the body portion 211 along the AA direction and exceeds one side edge of the first boss 23. The drain 27 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 and contacts the side surface of the overlapping portion 213 opposite to the substrate 10. The source 26 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 and contacts the side surface of the second ohmic contact structure 22 opposite to the substrate 10.

[0096] Combination Figures 4 to 6 As shown, Figure 4 This is a planar schematic diagram of a second type of thin-film transistor provided in an embodiment of this application. Figure 5 This is a schematic cross-sectional view of the second type of thin-film transistor provided in an embodiment of this application along the BB direction. Figure 6 This is a schematic cross-sectional view of the second type of thin-film transistor provided in an embodiment of this application along the AA direction. Figures 4 to 6 The structure of the second type of display panel shown is similar to... Figures 1 to 3 The structure of the first type of display panel shown is roughly the same, except that: the first ohmic contact structure 21 includes a body portion 211 and a protrusion portion 212. The body portion 211 is disposed between the first boss 23 and the substrate 10. The protrusion portion 212 is connected to the body portion 211. The orthographic projection of the protrusion portion 212 on the substrate 10 does not overlap with the orthographic projection of the first boss 23 on the substrate 10.

[0097] It should be noted that the protrusion 212 and the body portion 211 are part of the first ohmic contact structure 21. The protrusion 212 can be regarded as a part of the first ohmic contact structure 21 that extends from one end of the body portion 211 and exceeds the edge of the first boss 23. The semiconductor structure 24 is in contact with the side surface of the protrusion 212 that is away from the substrate 10.

[0098] exist Figure 2 In the illustrated embodiment, the semiconductor structure 24 contacts the first sidewall 210 of the first ohmic contact structure 21, and the contact area is relatively small. Figure 4 In the embodiment shown, the semiconductor structure 24 contacts the surface of the first ohmic contact structure 21 on the side away from the substrate 10, which is the protrusion 212 of the first boss 23. The contact area is relatively large. In this way, by increasing the contact area between the semiconductor structure 24 and the first ohmic contact structure 21, the risk of poor contact between the semiconductor structure 24 and the first ohmic contact structure 21 is reduced.

[0099] In one embodiment, the first portion 241 of the semiconductor structure 24 may be disposed on the substrate 10 and the first ohmic contact structure 21.

[0100] It should be noted that "deposited on the substrate 10" can refer to being in direct contact with the substrate 10 or to being in indirect contact with the substrate 10.

[0101] like Figure 2 As shown, the first part 241 of the semiconductor structure 24 is disposed on the side surface of the buffer layer 11 facing away from the substrate 10 and on the side surface of the protrusion 212 facing away from the substrate 10. The semiconductor structure 24 can simultaneously contact the side surface of the protrusion 212 facing away from the substrate 10 and the first sidewall 210 of the protrusion 212, thereby further increasing the contact area between the semiconductor structure 24 and the first ohmic contact structure 21.

[0102] In one embodiment, the first part 241 of the semiconductor structure 24 may also be disposed only on the side surface of the protrusion 212 of the first ohmic contact structure 21 facing away from the substrate 10, which can also increase the contact area with the first ohmic contact structure 21.

[0103] Furthermore, the length L1 of the protrusion 212 is between 0.5 micrometers and 3 micrometers. For example, the length L1 of the protrusion 212 can be 0.5 micrometers, 0.8 micrometers, 1 micrometer, 1.5 micrometers, 2 micrometers, 2.5 micrometers, or 3 micrometers, etc. This ensures that a corner can be formed between the protrusion 212 and the sidewall 230 of the first protrusion 23, and that the semiconductor structure 24 can form a seed crystal growing along the sidewall 230 at the corner between the protrusion 212 and the sidewall 230, thereby ensuring that only one grain exists in the channel of the thin-film transistor.

[0104] Combination Figures 7 to 9 As shown, Figure 7 This is a planar schematic diagram of the third type of thin-film transistor provided in the embodiments of this application. Figure 8 This is a schematic cross-sectional view of the third type of thin-film transistor provided in an embodiment of this application along the BB direction. Figure 9 This is a schematic cross-sectional view of the third type of thin-film transistor provided in the embodiments of this application along the AA direction. Figures 7 to 9 The structure of the third type of display panel shown is similar to Figures 4 to 6 The structure of the second type of display panel shown is roughly the same, except that: the first protrusion 23 has two sidewalls 230 arranged opposite to each other, and the semiconductor structure 24 and the gate 25 located on the side of the semiconductor structure 24 facing away from the substrate 10 are provided on both sidewalls 230.

[0105] like Figure 8 The first boss 23 includes two sidewalls 230a and 230b arranged opposite to each other. The semiconductor structure 24 is provided on both sidewalls 230a and 230b. The semiconductor structure 24 on both sidewalls 230a and 230b is in contact with the first ohmic contact structure 21 and the second ohmic contact structure 22.

[0106] The semiconductor structure 24 on sidewall 230a has a gate 25 on the side facing away from the substrate 10, and the semiconductor structure 24 on sidewall 230b also has a gate 25 on the side facing away from the substrate 10. The two gates on either side of the first protrusion 23 can control the semiconductor structures 24 on sidewalls 230a and 230b respectively. This is equivalent to connecting the channels of the semiconductor structures 24 on both sides of the first protrusion 23 in parallel, thereby increasing the equivalent channel width of the thin-film transistor and thus increasing the on-state current of the thin-film transistor. For the pixel driving circuit of the liquid crystal display panel, this can reduce the charging time of the pixel capacitor, which is beneficial to improving the refresh rate of the display panel.

[0107] In one embodiment, the semiconductor structure 24 is continuously disposed on the two sidewalls 230 of the first boss 23 and the second ohmic contact structure 22.

[0108] Combination Figures 7 to 8 As shown, the semiconductor structure 24 is configured to extend from one side of the first protrusion 23, through the sidewall 230a, and the side surface of the second ohmic contact structure 22 opposite to the first protrusion 23, to the sidewall 230b on the other side of the first protrusion 23.

[0109] Furthermore, the gate 25 is continuously disposed on the semiconductor structure 24 on the two sidewalls 230 of the first boss 23 and on the semiconductor structure 24 on the side of the second ohmic contact structure 22 facing away from the substrate 10.

[0110] Combination Figures 7 to 8 As shown, the gate 25 is configured to extend from one side of the first protrusion 23, sequentially passing through the sidewall 230a and the surface of the second ohmic contact structure 22 facing away from the first protrusion 23, to the sidewall 230b on the other side of the first protrusion 23. The orthogonal projection of the gate 25 on the substrate 10 can cover the orthogonal projection of the semiconductor structure 24 on the substrate 10. From the perspective of the thin-film transistor array, by connecting the gates 25 on opposite sides of the first protrusion 23 together, the gates located on opposite sides of each first protrusion 23 can be controlled simultaneously using a single, uninterrupted scan line, thereby simplifying the patterning complexity of the gate metal layer.

[0111] In one embodiment, the semiconductor structures 24 located on both sides of the first protrusion 23 may also be disconnected from each other and spaced apart on the surface of the second ohmic contact structure 22 opposite to the first protrusion 23. Similarly, the gates 25 located on both sides of the first protrusion 23 may also be disconnected from each other and spaced apart on the surface of the second ohmic contact structure 22 opposite to the first protrusion 23.

[0112] In one embodiment, combined with Figures 10 to 12 As shown, Figure 10 This is a planar schematic diagram of the fourth type of thin-film transistor provided in the embodiments of this application. Figure 11 This is a schematic cross-sectional view of the fourth type of thin-film transistor provided in the embodiments of this application along the BB direction. Figure 12 This is a cross-sectional schematic diagram along the AA direction of the fourth type of thin-film transistor provided in the embodiments of this application. Figures 10 to 12 The structure of the fourth type of display panel shown is similar to... Figures 7 to 9The structure of the third type of display panel shown is roughly the same, except that the display panel further includes a second protrusion 28, a third ohmic contact structure 29, and two fourth ohmic contact structures 30. The third ohmic contact structure 29 is disposed on the substrate 10, the second protrusion 28 is disposed on the side of the third ohmic contact structure 29 opposite to the substrate 10, and the fourth ohmic contact structures 30 are disposed on the side of the second protrusion 28 opposite to the third ohmic contact structure 29.

[0113] like Figure 11 As shown, the third ohmic contact structure 29 is disposed in the same layer as the first ohmic contact structure 21, and both are disposed on the side surface of the buffer layer 11 facing away from the substrate 10. The second protrusion 28 is disposed on the side of the third ohmic contact structure 29 facing away from the substrate 10, and the fourth ohmic contact structure 30 is disposed on the side of the second protrusion 28 facing away from the third ohmic contact structure 29.

[0114] The structure of the second protrusion 28 can refer to the structure of the first protrusion 23 in the above embodiment. The structure of the semiconductor structure on the protrusion 28 can also refer to the structure of the semiconductor structure 24 corresponding to the first protrusion 23 in the above embodiment, which will not be described in detail here.

[0115] In one embodiment, the structure of the second protrusion 28 may be the same as that of the first protrusion 23, having two opposing inclined sidewalls. The semiconductor structure 24 may be disposed at least on the sidewall of the second protrusion 28 and contact the third ohmic contact structure 29 and the fourth ohmic contact structure 30, respectively. At the second protrusion 28, the gate 25 is also disposed on the side of the semiconductor structure 24 facing away from the substrate 10.

[0116] One of the source electrode 26 and the drain electrode 27 is electrically connected to the first ohmic contact structure 21 and the third ohmic contact structure 29, and the other of the source electrode 26 and the drain electrode 27 is electrically connected to the second ohmic contact structure 22 and the fourth ohmic contact structure 30.

[0117] For example, within the same thin-film transistor, the thin-film transistor can simultaneously have a first protrusion 23 and a second protrusion 28. The source 26 is connected to the first ohmic contact structure 21 and the third ohmic contact structure 29, and the drain 27 is connected to the second ohmic contact structure 22 and the fourth ohmic contact structure 30. The first ohmic contact structure 21 and the third ohmic contact structure 29 are connected in parallel through the source 26, and the second ohmic contact structure 22 and the fourth ohmic contact structure 30 are connected in parallel through the drain 27. Figures 7 to 9Based on the embodiment shown, the equivalent channel width of the thin-film transistor is further increased.

[0118] In other embodiments, the thin-film transistor may also include three or more protrusions and corresponding ohmic contact structures on the upper and lower sides of the protrusions. By connecting the channels corresponding to multiple protrusions in parallel, the equivalent channel width of the thin-film transistor 20 can be further increased. The number of protrusions and corresponding ohmic contact structures on the upper and lower sides of the protrusions in the thin-film transistor can be selected according to actual needs and is not limited here.

[0119] In one embodiment, the semiconductor structure 24 is continuously disposed on the first protrusion 23 and the second protrusion 28, and in the region between the first protrusion 23 and the second protrusion 28.

[0120] Combination Figures 10 to 11 As shown, the semiconductor structure 24 extends from the side of the first protrusion 23 away from the second protrusion 28, through the first protrusion 23, and the area between the first protrusion 23 and the second protrusion 28 to the side of the second protrusion 28 away from the first protrusion 23.

[0121] Furthermore, the gate 25 is continuously disposed on the semiconductor structure 24 corresponding to the first protrusion 23 and the second protrusion 28, and on the semiconductor structure 24 between the first protrusion 23 and the second protrusion 28.

[0122] Combination Figures 10 to 11 As shown, the gate 25 extends from the side of the first protrusion 23 opposite to the second protrusion 28, through the first protrusion 23, and the area between the first protrusion 23 and the second protrusion 28, to the side of the second protrusion 28 opposite to the first protrusion 23. The orthogonal projection of the gate 25 on the substrate 10 can cover the orthogonal projection of the semiconductor structure 24 on the substrate 10. From the perspective of the thin-film transistor array, by connecting the gates 25 on the first protrusion 23 and the second protrusion 28 together, the gates 25 located on the first protrusion 23 and the second protrusion 28 can be controlled simultaneously using a single, uninterrupted scan line, thereby simplifying the patterning complexity of the gate metal layer.

[0123] In one embodiment, the semiconductor structure 24 may also be disconnected and spaced apart in the region between the first protrusion 23 and the second protrusion 28. The gate 25 may also be disconnected and spaced apart in the region between the first protrusion 23 and the second protrusion 28.

[0124] Furthermore, the display panel also includes a gate insulating layer 13 and an interlayer dielectric layer 14. The gate insulating layer 13 is disposed on the side of the semiconductor structure 24 away from the substrate 10 and covers the semiconductor structure 24, the second ohmic contact structure 22, the first boss 23 and the first ohmic contact structure 21. The gate 25 is disposed on the side of the gate insulating layer 13 away from the substrate 10.

[0125] The interlayer dielectric layer 14 is disposed on the side of the gate insulating layer 13 facing away from the substrate 10 and covers the gate 25.

[0126] The source electrode 26 and the drain electrode 27 are both disposed on the side of the interlayer dielectric layer 14 away from the substrate 10. One of the source electrode 26 and the drain electrode 27 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 to contact the first ohmic contact structure 21, and the other of the source electrode 26 and the drain electrode 27 passes through the interlayer dielectric layer 14 and the gate insulating layer 13 to contact the second ohmic contact structure 22.

[0127] In one embodiment, such as Figure 2 As shown, the display panel also includes a light-shielding structure 12, which is disposed on the side of the first ohmic contact structure 21 near the substrate 10. The semiconductor structure 24 includes a channel portion 240 disposed opposite to the sidewall 230.

[0128] The orthographic projection of the light-shielding structure 12 on the substrate 10 covers the orthographic projection of the channel portion 240 on the substrate 10. By using the light-shielding structure 12 to block the channel portion 240, light can be prevented from shining through one side of the substrate 10 onto the channel portion 240, thereby preventing light from affecting the electrical performance of the thin-film transistor 20.

[0129] In one embodiment, combined with Figure 8 and 11 As shown, when the thin-film transistor has two or more channel portions 240, a corresponding light-shielding structure 12 is provided below each channel portion 240.

[0130] Based on the display panel provided in the above embodiments of this application, this application also provides a method for manufacturing a display panel, combined with... Figures 13a to 13g As shown, Figures 13a to 13g This is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of this application. The method for manufacturing the display panel includes:

[0131] Step S1: Form a light-shielding structure 12 on the substrate 10;

[0132] Step S2: A buffer layer 11 is formed on the substrate 10. A first ohmic contact layer, an insulating layer, and a second ohmic contact layer are sequentially formed on the buffer layer 11. The first ohmic contact layer, the insulating layer, and the second ohmic contact layer are etched to form a first ohmic contact structure 21, a first boss 23, and a second ohmic contact structure 22.

[0133] In step S20, the material of the buffer layer 11 may be, but is not limited to, any one or a combination of silicon nitride, silicon oxide, or silicon oxynitride.

[0134] In step S20, such as Figure 13b As shown, the first ohmic contact structure 21 is disposed on the buffer layer 11, the first boss 23 is disposed on the side of the first ohmic contact structure 21 opposite to the buffer layer 11, and the second ohmic contact structure 22 is disposed on the side of the first boss 23 opposite to the first ohmic contact structure 21.

[0135] The first boss 23 has a side wall 230, and the angle θ between the side wall 230 and the plane of the substrate 10 is between 45 degrees and 90 degrees.

[0136] The first ohmic contact structure 21 has a first sidewall 210 adjacent to the sidewall 230. The second ohmic contact structure 22 has a second sidewall 220 adjacent to the sidewall 230. The angle between the first sidewall 210 and the second sidewall 220 and the plane of the substrate can be equal to the angle θ between the sidewall 230 and the plane of the substrate 10, that is, the first sidewall 210, the sidewall 230 and the second sidewall 220 are on the same inclined plane.

[0137] In this embodiment, both the first ohmic contact layer and the second ohmic contact layer are made of N-type heavily doped amorphous silicon, and both the first ohmic contact layer and the second ohmic contact layer may be doped with impurity elements such as phosphorus or arsenic.

[0138] The insulating layer can be made of commonly used inorganic insulating materials such as silicon nitride, silicon oxide, or silicon oxynitride.

[0139] In step S20, the first ohmic contact layer, the insulating layer, and the second ohmic contact layer can be sequentially deposited by chemical vapor deposition (CVD).

[0140] Step S3: Etch the first ohmic contact structure 21, the first boss 23 and the second ohmic contact structure 22, so that the second ohmic contact structure 22 and the first boss 23 are partially etched, while the first ohmic contact structure 21 is not etched.

[0141] like Figure 13c As shown, by partially etching the second ohmic contact structure 22 and the first boss 23, a portion of the first ohmic contact structure 21 is not covered by the first boss 23 and the second ohmic contact structure 22.

[0142] Step S4: An amorphous silicon layer is formed on the buffer layer 11, the amorphous silicon layer covering the first ohmic contact structure 21, the first boss 23 and the second ohmic contact structure 22; the amorphous silicon layer is crystallized and then patterned to form a semiconductor structure 24.

[0143] In step S4, the amorphous silicon layer can be crystallized by excimer laser annealing, so that the amorphous silicon in the amorphous silicon layer can be transformed into a polycrystalline silicon structure, and then the polycrystalline silicon structure is etched to form the semiconductor structure 24.

[0144] Since the energy of the excimer laser annealing process is limited and is entirely absorbed by the amorphous silicon layer, the first ohmic contact structure 21 and the second ohmic contact structure 22 can still maintain the amorphous silicon structure when the amorphous silicon layer is crystallized.

[0145] During the crystallization process of the amorphous silicon layer, a seed crystal can be formed at the corner of the buffer layer 11 and the sidewall 230 of the first protrusion 23. The seed crystal can grow along the direction of the sidewall 230. By controlling the length of the sidewall 230 to between 0.01 micrometers and 1 micrometer, only one grain can exist in the semiconductor structure 24 on the sidewall 230.

[0146] Step S5: A gate insulating layer 13 is formed on the semiconductor structure 24, the gate insulating layer 13 covering the semiconductor structure 24, the first ohmic contact structure 21, the first boss 23 and the second ohmic contact structure 22; a gate 25 is formed on the gate insulating layer 13.

[0147] Step S6: An interlayer dielectric layer 14 is formed on the gate insulating layer 13, the interlayer dielectric layer 14 covering the gate 25; a first via OH1 and a second via OH2 are formed on the interlayer dielectric layer 14, the first via OH1 exposing the first ohmic contact structure 21, and the second via OH2 exposing the second ohmic contact structure 22.

[0148] Step S7: A source 26 and a drain 27 are formed on the interlayer dielectric layer 14. The drain 27 passes through the first via OH1 and contacts the first ohmic contact structure 21. The source 26 passes through the second via OH2 and contacts the second ohmic contact structure 22.

[0149] It should be noted that the method for manufacturing the display panel provided in this application embodiment is only for reference. Figures 1 to 3 Taking the structure of the first type of display panel shown as an example, the manufacturing methods of the display panels in other embodiments can be referred to. Figures 13a to 13b The manufacturing method of the display panel shown is not described in detail here.

[0150] The beneficial effects of the embodiments of this application are as follows: The embodiments of this application provide a display panel, the display panel including a substrate and a first ohmic contact structure, a first boss, a second ohmic contact structure, a semiconductor structure and a gate stacked on the substrate. The first boss has at least one sidewall. By disposing the semiconductor structure on the sidewall of the first boss and contacting the first ohmic contact structure and the second ohmic contact structure respectively, the length of the channel in the semiconductor structure can be shortened using existing processes, and the volume of the thin film transistor can be reduced, thereby improving the integration density of the thin film transistor in the display panel.

[0151] In summary, although the present application discloses the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application is based on the scope defined by the claims.

Claims

1. A display panel, characterized in that, include: substrate; A first ohmic contact structure is disposed on the substrate; A first protrusion is disposed on the side of the first ohmic contact structure opposite to the substrate, and the first protrusion has at least one sidewall. The second ohmic contact structure is disposed on the side of the first boss that is opposite to the first ohmic contact structure. A semiconductor structure is disposed at least on the sidewall and is in contact with the first ohmic contact structure and the second ohmic contact structure, respectively; as well as A gate is disposed on the side of the semiconductor structure opposite to the substrate; The display panel further includes a source and a drain, which are disposed on the side of the gate opposite to the substrate. The semiconductor structure includes a first part, a second part, and a third part. The first part is disposed on the substrate and / or the first ohmic contact structure. The second part is disposed on the sidewall and connected to the first part. The third part is disposed on the side of the second ohmic contact structure opposite to the first boss and connected to the second part.

2. The display panel as described in claim 1, characterized in that, The first ohmic contact structure has a first sidewall adjacent to the sidewall, and the semiconductor structure is in contact with the first sidewall.

3. The display panel as described in claim 1, characterized in that, The first ohmic contact structure includes: The body portion is disposed between the first boss and the substrate; and The protrusion is connected to the body portion. The orthographic projection of the protrusion on the substrate does not overlap with the orthographic projection of the first boss on the substrate. The semiconductor structure is in contact with the side surface of the protrusion facing away from the substrate.

4. The display panel as described in claim 1, characterized in that, The angle between the sidewall and the plane of the substrate is between 45 degrees and 90 degrees.

5. The display panel as described in claim 1, characterized in that, The first protrusion has two opposing sidewalls, and each of the two sidewalls is provided with a semiconductor structure and a gate located on the side of the semiconductor structure opposite to the substrate; The semiconductor structures on both sidewalls are in contact with the first ohmic contact structure and the second ohmic contact structure.

6. The display panel as described in claim 5, characterized in that, The semiconductor structure is continuously disposed on the two sidewalls of the first boss and the second ohmic contact structure.

7. The display panel as described in claim 6, characterized in that, The orthogonal projection of the gate on the substrate covers the orthogonal projection of the semiconductor structure on the substrate.

8. The display panel as described in claim 1, characterized in that, The display panel includes: A third ohmic contact structure is disposed on the substrate; The second protrusion is disposed on the side of the third ohmic contact structure opposite to the substrate; and A fourth ohmic contact structure is disposed on the side of the second protrusion away from the first ohmic contact structure. The semiconductor structure is disposed at least on the sidewall of the second protrusion and is in contact with the third ohmic contact structure and the fourth ohmic contact structure, respectively. One of the source and the drain is electrically connected to the first ohmic contact structure and the third ohmic contact structure, and the other of the source and the drain is electrically connected to the second ohmic contact structure and the fourth ohmic contact structure.

9. The display panel as described in claim 8, characterized in that, The semiconductor structure is continuously disposed on the first boss and the second boss, and in the region between the first boss and the second boss.

10. The display panel as claimed in claim 9, characterized in that, The orthogonal projection of the gate on the substrate covers the orthogonal projection of the semiconductor structure on the substrate.

11. The display panel as claimed in claim 1, characterized in that, The display panel further includes a gate insulating layer and an interlayer dielectric layer. The gate insulating layer is disposed at least between the gate and the semiconductor structure and covers the second ohmic contact structure and the first ohmic contact structure. The interlayer dielectric layer is disposed on the side of the gate insulating layer opposite to the substrate and covers the gate. The source and the drain are both disposed on the side of the interlayer dielectric layer away from the substrate. One of the source and the drain passes through the interlayer dielectric layer and the gate insulating layer to contact the first ohmic contact structure, and the other of the source and the drain passes through the interlayer dielectric layer and the gate insulating layer to contact the second ohmic contact structure.

12. The display panel as claimed in claim 1, characterized in that, The display panel further includes a light-shielding structure disposed on the side of the first ohmic contact structure near the substrate, and the semiconductor structure includes a channel portion connecting the first ohmic contact structure and the second ohmic contact structure. Wherein, the orthogonal projection of the light-shielding structure on the substrate covers the orthogonal projection of the channel portion on the substrate.

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