A gallium nitride power device and its fabrication method

Abstract

This application belongs to the field of power device technology and provides a gallium nitride (GaN) power device and its fabrication method. The GaN power device includes: a substrate layer, a buffer layer, a gallium nitride layer, a barrier layer, a source layer, a gate layer, a first drain, a second drain, a capping layer, and a P-type substrate. A first N-type doped region and a second N-type doped region are formed on both sides of the P-type substrate, respectively. A passivation layer is disposed between the P-type substrate and the second drain, and the second drain is electrically connected to the first drain. By forming a high threshold voltage N-type MOSFET between the gate and the source of the GaN power device, the N-type MOSFET turns on when the source-drain voltage of the device is high, causing a short circuit between the source and the gate. This prevents the gate of the GaN power device from being turned on even when the source-drain voltage is high, allowing the device to withstand greater inductive energy conversion and improving the reliability of the GaN power device when applied to high-load inductive scenarios.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a gallium nitride power device and its fabrication method. Background Technology

[0002] In gallium nitride high-speed electron mobility field-effect transistors (GaN HEMTs), there is no parasitic body diode between the drain and source, whereas in silicon or silicon carbide-based field-effect transistors (MOSFETs), a parasitic body diode exists between the drain and source. In applications with highly inductive loads, when a switch transitions from the open to the closed state, the energy stored in the inductor charges the closed-state switch by releasing a current.

[0003] When a MOSFET based on a silicon substrate or silicon carbide substrate is used as a switching device and is turned off, the source-drain voltage Vds between its drain and source rises all the way to the avalanche voltage of its parasitic body diode. At this time, the body diode turns on, current flows, and the source-drain voltage Vds is equal to the avalanche voltage of the diode. When a GaN HEMT is used as a switching device and is turned off, the energy stored in the inductor is released. Since there is no parasitic body diode, it can only charge the output capacitor of the device. The source-drain voltage Vds will rise all the way until it reaches the maximum voltage Vm. That is, the inductor energy can no longer charge the capacitor. The energy in the capacitor is consumed in the process of exchanging energy with the energy in the inductor.

[0004] However, if GaN HEMT is used as a switching device, excessive energy stored in its inductor will cause the parasitic capacitance between the drain and source terminals to be fully charged when the output capacitor is charged. This will cause the source-drain voltage Vds to continue to rise, leading to an increase in the gate-source voltage Vgs, which in turn turns on the switching device that should be turned off, resulting in malfunction of the switching device. Summary of the Invention

[0005] The purpose of this application is to provide a gallium nitride power device and its fabrication method, aiming to provide a novel gallium nitride power device to improve the reliability of switching devices when applied to high-load inductor scenarios.

[0006] A first aspect of this application provides a gallium nitride power device, the gallium nitride power device comprising:

[0007] The substrate layer, buffer layer, gallium nitride layer, and barrier layer are stacked sequentially from bottom to top.

[0008] A source layer and a first drain are disposed on both sides of the barrier layer, wherein the source layer and the first drain are located on the gallium nitride layer;

[0009] A capping layer disposed on the barrier layer;

[0010] A gate layer disposed on the cap layer;

[0011] A P-type substrate is disposed between the capping layer and the source layer, wherein both sides of the P-type substrate are doped with N-type dopant ions to form a first N-type doped region and a second N-type doped region on both sides of the P-type substrate, respectively.

[0012] A passivation layer disposed on the P-type substrate;

[0013] A second drain is disposed on the passivation layer, wherein the second drain is electrically connected to the first drain.

[0014] In one embodiment, the distance between the capping layer and the first drain is less than the distance between the capping layer and the source layer.

[0015] In one embodiment, the thickness of the P-type substrate is equal to the thickness of the capping layer, and the passivation layer is disposed between the gate layer and the source layer.

[0016] In one embodiment, both the source layer and the first drain layer extend into the gallium nitride layer.

[0017] In one embodiment, the capping layer is P-type gallium nitride.

[0018] In one embodiment, the first N-type doped region and the second N-type doped region are N-type gallium nitride.

[0019] In one embodiment, the thickness of the passivation layer is less than the thickness of the P-type substrate.

[0020] In one embodiment, the barrier layer is AlGaN.

[0021] A second aspect of this application also provides a method for fabricating a gallium nitride power device, the method comprising:

[0022] The substrate layer, buffer layer, gallium nitride layer, and barrier layer are fabricated sequentially from bottom to top.

[0023] A P-type substrate and a capping layer are formed on the barrier layer, wherein the P-type substrate and the capping layer are disposed adjacent to each other.

[0024] N-type dopant ions are doped into both sides of the P-type substrate to form a first N-type doped region and a second N-type doped region inside the P-type substrate;

[0025] A passivation layer is formed on the P-type substrate;

[0026] A source layer and a first drain are formed on both sides of the barrier layer, a second drain is formed on the passivation layer, and a gate layer is formed on the capping layer.

[0027] In one embodiment, the step of doping N-type dopant ions in both regions of the P-type substrate includes:

[0028] A mask is used to define the source doped region and the drain doped region on the P-type substrate;

[0029] N-type doped ions are implanted into the source doped region and the drain doped region under the cover of the mask to form a first N-type doped region and a second N-type doped region inside the P-type substrate.

[0030] This application provides a gallium nitride (GaN) power device and its fabrication method. The GaN switching device includes: a substrate layer, a buffer layer, a GaN layer, a barrier layer, a source layer, a gate layer, a first drain, a second drain, a capping layer, and a P-type substrate. The substrate layer, buffer layer, GaN layer, and barrier layer are stacked sequentially from bottom to top. The source layer and the first drain are disposed on both sides of the barrier layer. The capping layer is disposed between the barrier layer and the gate layer. The P-type substrate is disposed between the capping layer and the source layer, and a first N-type doped region and a second N-type doped region are formed on both sides of the P-type substrate, respectively. In the region, a passivation layer is disposed between the P-type substrate and the second drain, and the second drain is electrically connected to the first drain. By forming an N-type MOSFET with a high threshold voltage between the gate and the source of the gallium nitride power device, the N-type MOSFET turns on when the source-drain voltage of the device is high, which makes the source and gate short-circuited. This prevents the gate of the gallium nitride power device from being turned on even when the source-drain voltage is high, allowing the device to withstand greater inductive energy conversion and improving the reliability of gallium nitride power devices when applied to high-load inductive scenarios. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of the test structure for the unclamped inductive switching (UIS) process of the gallium nitride switching device provided in the embodiments of this application;

[0032] Figure 2 This is a schematic diagram of the current and voltage waveforms of the gallium nitride switching device provided in the embodiments of this application;

[0033] Figure 3 This is a schematic diagram of the structure of the gallium nitride switching device provided in the embodiments of this application;

[0034] Figure 4 This is a schematic flowchart of a method for fabricating a gallium nitride switching device provided in an embodiment of this application;

[0035] Figure 5This is an example diagram provided in this application embodiment showing that a buffer layer 200, a gallium nitride layer 300, and a barrier layer 400 are sequentially formed on a substrate layer 100;

[0036] Figure 6 This is an example diagram of the formation of a P-type substrate 510 and a capping layer 720 provided in the embodiments of this application;

[0037] Figure 7 This is an example diagram of the formation of the passivation layer 710 provided in the embodiments of this application. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] In applications with highly inductive loads, when a switching device switches from the open to the closed state, the energy stored in the inductor charges the closed switch by releasing current. Specifically, Figure 1 This is a circuit diagram of the switching device Uh applied to a highly inductive load, combined with... Figure 1As shown, the pulse generator 700 is connected to the gate G of the switching device Uh through the first diode D1. A first resistor R1 is connected between the gate G and the source S of the switching device Uh, and the drain D of the switching device Uh is connected to the load inductor L0. VDD is an external power supply. When the voltage of the gate G of the switching device Uh flips to a high level, the external power supply VDD charges the load inductor L0. After the inductor L0 is fully charged, current begins to flow through the switching device Uh. When the voltage of the gate G of the switching device Uh flips to a low level, the switching device Uh is turned off. The load inductor L0 maintains the slow change of current between the drain D and the source S of the switching device Uh, and the voltage between the drain D and the source S of the switching device Uh increases rapidly.

[0043] Combination Figure 2 As shown in (a), when the MOSFET on a silicon substrate or a silicon carbide substrate is turned off as a switching device Uh, the gate-source voltage Vgs of the switching device Uh rises to a high level. Since the switching device Uh has a body diode, the diode enters the avalanche region. Figure 2 As shown in (b), the voltage Vds between the drain and source rises all the way to the avalanche voltage of the parasitic body diode inside the switching device. The body diode inside the switching device Uh turns on, and the current Ids flows through. When the switching device Uh turns off, the maximum current IL is reached. The voltage Vds is equal to the avalanche voltage BVava of the diode.

[0044] When a gallium nitride (GaN) HEMT is used as a switching device Uh and is turned off, since Uh does not have a body diode, energy conversion is required between the output capacitance of Uh and the load inductor L0. When the load inductor L0 is normal, the conversion process consumes the energy stored in the load inductor L0. If the load inductor L0 is too large, the energy conversion causes an excessively high voltage at its gate terminal G, leading to damage to the switching device. Specifically, in conjunction with... Figure 2 As shown in (c), the energy stored in inductor L0 is released. Since there is no parasitic diode, it can only charge the output capacitor of switching device Uh. Current Ids flows through it and reaches its maximum current IL when switching device Uh is turned off. The voltage Vds between its drain and source will rise all the way up. After Vds reaches its maximum voltage Vm, the inductor energy can no longer charge the capacitor. Then, the energy in the capacitor is consumed in the process of exchanging energy with the energy in the inductor. However, if the load inductance L0 connected to the drain D of switching device Uh is too large, it will store too much energy. When charging the output capacitor, after the parasitic capacitance at its drain and gate ends is saturated, the voltage Vds between the drain and source will continue to rise, causing the voltage Vgs between the gate and source of switching device Uh to rise. This will turn on the switching device Uh, which should be turned off, leading to the problem of malfunction of switching device Uh.

[0045] To address the aforementioned technical problems, this application provides a gallium nitride power device, see [link to relevant documentation]. Figure 3 As shown, the gallium nitride power device includes: a substrate layer 100, a buffer layer 200, a gallium nitride layer 300, a barrier layer 400, a source layer 610, a gate layer 620, a first drain 631, a gate layer 620, a second drain 632, a P-type substrate 510, a first N-type doped region 511, a second N-type doped region 512, and a passivation layer 710.

[0046] Specifically, the substrate layer 100, buffer layer 200, gallium nitride layer 300, and barrier layer 400 are stacked sequentially from bottom to top. The source layer 610 and the second drain 632 are disposed on the gallium nitride layer 300 and located on both sides of the barrier layer 400. The barrier layer 400 is provided with a P-type substrate 510 and a capping layer 720. Both sides of the P-type substrate 510 are doped with N-type doped ions to form a first N-type doped region 511 and a second N-type doped region 512 on both sides of the P-type substrate 510, respectively. The passivation layer 710 is disposed on the P-type substrate 510, the gate layer 620 is disposed on the capping layer 720, and the second drain 632 is disposed on the passivation layer 710 and is electrically connected to the first drain 631.

[0047] In this embodiment, combined with Figure 3 As shown, an N-type MOSFET is formed by a P-type substrate 510, a first N-type doped region 511, a second N-type doped region 512, a passivation layer 710, and a second drain 632. The first N-type doped region 511 is in contact with the source layer 610, and the second N-type doped region 512 is in contact with the capping layer 720 and indirectly connected to the gate layer 620. This forms a high threshold voltage N-type MOSFET between the gate and source of the gallium nitride power device. The N-type MOSFET turns on when the source-drain voltage of the device is high, causing a short circuit between the source and the gate. This prevents the gate of the gallium nitride power device from being turned on even when the source-drain voltage is high, allowing the device to withstand greater inductive energy conversion and improving the reliability of the gallium nitride power device when applied to high-load inductive scenarios.

[0048] In specific application embodiments, the threshold voltage of the N-type MOSFET can be adjusted by adjusting the doping concentration of the P-type substrate 510, the first N-type doped region 511, the second N-type doped region 512, and the material or thickness of the passivation layer 710.

[0049] In one embodiment, combined Figure 3 As shown, the thickness of the source layer 610 is greater than the sum of the thicknesses of the barrier layer 400, the P-type substrate 510, and the passivation layer 710.

[0050] In one embodiment, combined Figure 3As shown, the thickness of the first drain 631 is greater than the thickness of the barrier layer 400.

[0051] Combination Figure 3 As shown, the substrate layer 100, buffer layer 200, gallium nitride layer 300, and barrier layer 400 are stacked sequentially from bottom to top. The source layer 610 is located on the first side of the barrier layer 400 and is in contact with the first N-type doped region 511 and the passivation layer 710. The second drain 632 is located on the second side of the barrier layer 400 and is located on the gallium nitride layer 300.

[0052] When the device is turned on, the energy conversion on its load inductance causes the voltage between the drain and source of the device to reach the threshold voltage of the N-type MOSFET. When the N-type MOSFET is turned on, it shorts the gate layer 620 and the source layer 610 of the device. This prevents the gate of the device from turning on even when the source-drain voltage Vds is extremely high. At this time, when the gallium nitride power device is connected to a highly inductive load, it can withstand a greater inductive energy conversion, which improves the reliability of gallium nitride power devices when applied to high-load inductive scenarios.

[0053] In one embodiment, the distance between the capping layer 720 and the first drain 631 is less than the distance between the capping layer 720 and the source layer 610.

[0054] In one embodiment, the capping layer 720 can be P-type gallium nitride, the gate layer 620 can be a gate metal layer, and the area between the capping layer 720 and the gate layer 620 can be a Schottky contact.

[0055] In this embodiment, the capping layer can be a P-type gallium nitride gate metal layer, which can be at least one of copper, gold, and silver, and the gate metal layer can be integrally formed with the gate electrode.

[0056] In one embodiment, the thickness of the P-type substrate 510 is equal to the thickness of the capping layer 720, and the passivation layer 710 is disposed between the gate layer 620 and the source layer 610.

[0057] In one embodiment, both the source layer 610 and the first drain layer 631 extend into the gallium nitride layer 300.

[0058] In one embodiment, the capping layer 720 is P-type gallium nitride.

[0059] In one embodiment, the first N-type doped region 511 and the second N-type doped region 512 are N-type gallium nitride.

[0060] In one embodiment, the thickness of the passivation layer 710 is less than the thickness of the P-type substrate 510.

[0061] In one embodiment, the first N-type doped region 511 and the second N-type doped region 512 have the same area.

[0062] In one embodiment, the first N-type doped region 511 and the second N-type doped region 512 have the same shape.

[0063] In one embodiment, the substrate 100 may be a silicon-based substrate or a silicon carbide substrate.

[0064] In one embodiment, the distance between the gate layer 620 and the source layer 610 is equal to the distance between the gate layer 620 and the first drain 631.

[0065] In one embodiment, the thickness of the gate layer 620, the source layer 610, and the first drain 631 is greater than the thickness of the gallium nitride layer 300.

[0066] In one embodiment, the barrier layer 400 is AlGaN.

[0067] In one embodiment, the buffer layer 200 may be gallium nitride.

[0068] This application also provides a method for fabricating a gallium nitride power device, see [link to relevant documentation]. Figure 4 As shown, the preparation method includes steps S100 to S600.

[0069] In step S100, a substrate layer, a buffer layer, a gallium nitride layer, and a barrier layer are prepared sequentially from bottom to top.

[0070] See Figure 5 As shown, a buffer layer 200, a gallium nitride layer 300, and a barrier layer 400 are sequentially formed on the substrate layer 100.

[0071] Specifically, a buffer layer 200 and a gallium nitride layer 300 can be formed on the substrate layer 100 by first depositing gallium nitride material, and then a barrier layer 400 can be formed by depositing AlGaN material.

[0072] In one embodiment, the substrate 100 may be a silicon-based substrate or a silicon carbide substrate.

[0073] In step S200, a P-type substrate and a capping layer are formed on the barrier layer, wherein the P-type substrate and the capping layer are disposed adjacent to each other.

[0074] In this embodiment, combined with Figure 6 As shown, a P-type substrate 510 and a capping layer 720 are formed by depositing P-type gallium nitride material on the barrier layer 400, with the P-type substrate and the capping layer being disposed adjacent to each other.

[0075] In one specific application embodiment, a P-type gallium nitride layer can be formed by depositing P-type gallium nitride material on the barrier layer 400, and then P-type doped ions can be implanted into the P-type gallium nitride layer under the cover of the base region mask to form the substrate base region of the N-type MOSFET. Finally, the excess substrate base region is etched away, thereby dividing the P-type gallium nitride layer into a P-type substrate 510 and a capping layer 720. The P-type substrate 510 is the region where ion implantation is performed again after depositing P-type gallium nitride material, and the capping layer 720 is the part formed by depositing P-type gallium nitride material.

[0076] In step S300, N-type dopant ions are doped into both sides of the P-type substrate to form a first N-type doped region and a second N-type doped region inside the P-type substrate.

[0077] In this embodiment, see Figure 7 As shown, by injecting N-type doped ions into the regions at the two opposite edges of the P-type substrate 510, a first N-type doped region 511 and a second N-type doped region 512 are formed inside the P-type substrate 510.

[0078] Specifically, the first N-type doped region 511 can be used as the source region of the N-type MOSFET, and the second N-type doped region 512 can be used as the drain region of the N-type MOSFET.

[0079] In specific applications, the doping concentration of the first N-type doped region 511 and the second N-type doped region 512 is greater than the doping concentration of the P-type substrate 510. For example, the doping concentration of the first N-type doped region 511 and the second N-type doped region 512 is at least 10 times the doping concentration of the P-type substrate 510.

[0080] In step S400, a passivation layer is formed on the P-type substrate;

[0081] In this embodiment, combined with Figure 7 As shown, an insulating dielectric material, such as silicon dioxide or silicon nitride, is deposited in the gate region of an N-type MOSFET to form a passivation layer 710.

[0082] In step S500, a source layer and a first drain are formed on both sides of the barrier layer, a second drain is formed on the passivation layer, and a gate layer is formed on the capping layer.

[0083] In this embodiment, combined with Figure 3 As shown, a source layer and a first drain can be formed on both sides of the barrier layer 400 by etching source and drain regions on both sides of the barrier layer, and then depositing source and drain materials in the etched source and drain regions.

[0084] In one specific application embodiment, the source and drain regions etched on both sides of the barrier layer can extend into the gallium nitride layer 300, but not exceeding half the thickness of the gallium nitride layer 300.

[0085] In one embodiment, step S300, which involves doping N-type dopant ions in the regions on both sides of the P-type substrate, includes: defining a source doping region and a drain doping region on the P-type substrate using a mask; and implanting N-type dopant ions into the source doping region and the drain doping region under the cover of the mask to form a first N-type doped region and a second N-type doped region inside the P-type substrate.

[0086] In this embodiment, a source doped region and a drain doped region are defined on a P-type substrate 510 using a mask. The source doped region and the drain doped region are located at two opposite edges of the P-type substrate 510 and are positioned opposite each other. Then, N-type dopant ions are implanted into the source doped region and the drain doped region, thereby forming a first N-type doped region 511 and a second N-type doped region 512 inside the P-type substrate 510.

[0087] Specifically, the first N-type doped region 511 can serve as the source region of the N-type MOSFET, and the second N-type doped region 512 can serve as the drain region of the N-type MOSFET. In this case, the P-type substrate 510, the first N-type doped region 511, the second N-type doped region 512, the passivation layer 710, and the second drain 632 form an N-type MOSFET. The first N-type doped region 511 is in contact with the source layer 610, and the second N-type doped region 512 is in contact with the capping layer 720 and indirectly connected to the gate layer 620. This forms a high threshold voltage N-type MOSFET between the gate and the source of the gallium nitride power device. The N-type MOSFET turns on when the source-drain voltage of the device is high, causing a short circuit between the source and the gate. This prevents the gate of the gallium nitride power device from being turned on even when the source-drain voltage is high, allowing the device to withstand greater inductive energy conversion and improving the reliability of the gallium nitride power device when applied to high-load inductive scenarios.

[0088] In one embodiment, a diode can be disposed on the back side of the substrate 100, for example, by forming a PN junction through P-type ion doping and N-type ion doping on the back side of the substrate 100, thereby disposing a diode on its back side.

[0089] Specifically, a P-type doped region is formed by P-type ion doping on the back side of the substrate 100, and an N-type doped region is formed by N-type ion doping on the back side of the substrate 100. The diode is composed of adjacent N-type doped regions and P-type doped regions.

[0090] In one embodiment, a substrate layer 100 is formed by adjacent N-type doped regions and P-type doped regions, with the P-type doped region in contact with the source electrode and the N-type doped region in contact with the drain electrode. The P-type doped region and the N-type doped region form a PN junction, thereby forming a diode between the drain and source terminals of the device. When the device is turned on, the energy conversion on its load inductance causes the voltage between the drain and source terminals to reach the avalanche voltage of the diode, at which point the diode turns on, fixing the voltage between the drain and source terminals and preventing the gate from being turned on. This allows the device to withstand greater inductance energy conversion and improves the reliability of the device when applied to high-load inductance scenarios.

[0091] In one embodiment, the boundary between the N-type doped region and the P-type doped region in the diode is opposite to the gate layer 620.

[0092] In this embodiment, the gate layer 620 is located on the barrier layer 400 and in the region between the source layer 610 and the drain layer 630, and its position is opposite to the boundary line between the N-type doped region and the P-type doped region.

[0093] Specifically, the length of the N-type doped region in the diode is the distance between the gate layer 620 and the drain layer 630, and the length of the P-type doped region is the distance between the gate layer 620 and the source layer 610.

[0094] In one embodiment, the N-type doped region in the diode has the same area as the P-type doped region.

[0095] In one embodiment, the N-type doped region in the diode has the same shape as the P-type doped region.

[0096] In one embodiment, the substrate 100 can be a silicon-based substrate or a silicon carbide substrate. The N-type doped and P-type doped regions can be formed by implanting different types of dopant ions into the substrate 100. For example, P-type dopant ions can be implanted into the region of the substrate 100 near the source electrode to form a P-type doped region, and N-type dopant ions can be implanted into the region of the substrate 100 near the drain electrode to form an N-type doped region.

[0097] This application provides a gallium nitride (GaN) power device and its fabrication method. The GaN power device includes: a substrate layer, a buffer layer, a gallium nitride layer, a barrier layer, a source layer, a gate layer, a first drain, a second drain, a capping layer, and a P-type substrate. A first N-type doped region and a second N-type doped region are formed on both sides of the P-type substrate, respectively. A passivation layer is disposed between the P-type substrate and the second drain, and the second drain is electrically connected to the first drain. By forming a high threshold voltage N-type MOSFET between the gate and the source of the GaN power device, the N-type MOSFET turns on when the source-drain voltage of the device is high, causing a short circuit between the source and the gate. This prevents the gate of the GaN power device from being turned on even when the source-drain voltage is high, allowing the device to withstand greater inductive energy conversion and improving the reliability of the GaN power device when applied to high-load inductive scenarios.

[0098] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0099] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0100] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A gallium nitride power device, characterized in that, The gallium nitride power device includes: The substrate layer, buffer layer, gallium nitride layer, and barrier layer are stacked sequentially from bottom to top. A source layer and a first drain are disposed on both sides of the barrier layer, wherein the source layer and the first drain are located on the gallium nitride layer; A capping layer disposed on the barrier layer; A gate layer disposed on the cap layer; A P-type substrate is disposed between the capping layer and the source layer, wherein both sides of the P-type substrate are doped with N-type dopant ions to form a first N-type doped region and a second N-type doped region on both sides of the P-type substrate, respectively. A passivation layer disposed on the P-type substrate; A second drain is disposed on the passivation layer, wherein the second drain is electrically connected to the first drain.

2. The gallium nitride power device as described in claim 1, characterized in that, The distance between the capping layer and the first drain is less than the distance between the capping layer and the source layer.

3. The gallium nitride power device as described in claim 1, characterized in that, The thickness of the P-type substrate is equal to the thickness of the capping layer, and the passivation layer is disposed between the gate layer and the source layer.

4. The gallium nitride power device as described in claim 1, characterized in that, Both the source layer and the first drain layer extend into the gallium nitride layer.

5. The gallium nitride power device as described in claim 1, characterized in that, The capping layer is P-type gallium nitride.

6. The gallium nitride power device as described in claim 1, characterized in that, The first N-type doped region and the second N-type doped region are N-type gallium nitride.

7. The gallium nitride power device as described in claim 1, characterized in that, The thickness of the passivation layer is less than the thickness of the P-type substrate.

8. The gallium nitride power device according to any one of claims 1-7, characterized in that, The barrier layer is AlGaN.

9. A method for fabricating a gallium nitride power device, characterized in that, The preparation method includes: The substrate layer, buffer layer, gallium nitride layer, and barrier layer are fabricated sequentially from bottom to top. A P-type substrate and a capping layer are formed on the barrier layer, wherein the P-type substrate and the capping layer are disposed adjacent to each other. N-type dopant ions are doped in both sides of the P-type substrate to form a first N-type doped region and a second N-type doped region inside the P-type substrate; the first N-type doped region serves as the source region of the N-type MOSFET, and the second N-type doped region serves as the drain region of the N-type MOSFET. A passivation layer is formed on the P-type substrate; A source layer and a second drain are formed on both sides of the barrier layer, and a first drain is formed on the passivation layer. A gate layer is formed on the capping layer. The source layer is located on the first side of the barrier layer and is in contact with the first N-type doped region and the passivation layer. The second drain is located on the second side of the barrier layer and is located on the gallium nitride layer.

10. The preparation method according to claim 9, characterized in that, The step of doping N-type dopant ions in both regions of the P-type substrate includes: A mask is used to define the source doped region and the drain doped region on the P-type substrate; N-type doped ions are implanted into the source doped region and the drain doped region under the cover of the mask to form a first N-type doped region and a second N-type doped region inside the P-type substrate.

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