Audio power amplifier circuit, its duty cycle modulation circuit and noise suppression circuit

Abstract

The application discloses an audio power amplifier circuit, a duty cycle modulation circuit and a noise suppression circuit thereof. The audio power amplifier circuit comprises an integral amplification module and a high-frequency switch arranged between the input resistance of the second-stage integral amplifier in the integral amplification module. The duty cycle modulation circuit is used for adjusting the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch. The duty cycle modulation circuit comprises a first counting module, a second counting module and a logic output module. The first counting module is used for counting the pulses of a duty cycle modulation signal to obtain a first counting value. The second counting module is used for counting the pulses of a clock signal to obtain a second counting value. The logic output module is used for performing logic operation according to the first counting value, the second counting value and the clock signal to obtain a switch modulation signal for controlling the high-frequency switch. The "POP" noise in the process of starting up or shutting down the chip is weakened by controlling the gain of the audio power amplifier circuit, and the cost is reduced while the high linearity of the circuit is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of audio power amplifier, more particularly, to an audio power amplifier circuit, a duty cycle modulation circuit and a noise suppression circuit thereof. BACKGROUND

[0002] Class-D amplifier circuit is a kind of switch-mode power amplifier circuit, which has the characteristics of high efficiency and less heat compared with linear power amplifier circuit, so it is widely used as an audio power amplifier circuit in the field of consumer electronics such as smart TVs and mobile phones.

[0003] Figure 1 The circuit schematic diagram of an existing two-stage audio power amplifier circuit is shown. As shown in the figure, Figure 1 The audio power amplifier circuit 100 includes an integral amplification module 110, a signal modulation module 120 and a drive output module 130.

[0004] The integral amplification module 110 includes a first-stage integral amplifier AMP1 and a second-stage integral amplifier AMP2. A pair of differential signals INA and INB are coupled to the input of the first-stage integral amplifier AMP1 through a capacitor Cin and a resistor Rin, respectively, and the output signals OPA and OPB are output after full differential amplification by the first-stage integral amplifier AMP1 and the second-stage integral amplifier AMP2 in sequence. The output signals OPA and OPB are modulated by a modulating signal RAMP through a comparator CMP1 and a comparator CMP2 in the signal modulation module 120, respectively, to generate pulse width modulation signals PWMA and PWMB. The drive output module 130 performs power amplification on the pulse width modulation signals PWMA and PWMB through the alternate operation of a transistor half-bridge to generate drive signals OUTA and OUTB. Feedback resistors Rfb1 and Rfb2 are used to feedback the drive signals OUTA and OUTB to the input end. In actual application, the drive signals output by the drive output module 130 can be directly transmitted to a loudspeaker to restore an audio signal (the loudspeaker itself has a certain low-pass filtering capability) or transmitted to a loudspeaker to play after being restored into an audio signal by a low-pass filtering circuit.

[0005] The existing audio power amplifier circuit will generate a "POP" noise at the output end when the device is powered on or off, which will cause the loudspeaker to produce a burst sound when the power amplifier is powered on or off. Small "POP" noise may make the user feel unpleasant, while large "POP" noise is more likely to damage the loudspeaker. Therefore, it is very important to suppress the "POP" noise of the audio power amplifier circuit. SUMMARY

[0006] In view of the above problems, the present application aims to provide an audio power amplifier circuit, a duty cycle modulation circuit and a noise suppression circuit thereof, which weakens the "POP" noise in the process of starting up or shutting down the chip by controlling the gain of the audio power amplifier circuit, and reduces the cost while meeting the high linearity of the circuit.

[0007] According to a first aspect of the embodiments of the present application, a duty cycle modulation circuit of an audio power amplifier circuit is provided, the audio power amplifier circuit comprising an integral amplification module and a high-frequency switch arranged between the input resistance of a second-stage integral amplifier in the integral amplification module, the duty cycle modulation circuit being configured to adjust the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch, wherein the duty cycle modulation circuit comprises: a first counting module configured to count the pulses of a duty cycle modulation signal to obtain a first count value; a second counting module configured to count the pulses of a clock signal to obtain a second count value; and a logic output module configured to perform a logic operation on the first count value, the second count value and the clock signal to obtain a switch modulation signal for controlling the high-frequency switch.

[0008] Optionally, the logic output module is configured to determine the pulse width of the switch modulation signal based on the first count value, and determine the switching period of the switch modulation signal based on the second count value.

[0009] Optionally, the duty cycle modulation circuit further comprises a first detection module configured to provide a first detection signal to the logic output module when the first count value is 0, and the logic output module is configured to set the switch modulation signal to an initial level state based on the first detection signal.

[0010] Optionally, the duty cycle modulation circuit further comprises a second detection module configured to provide a second detection signal to the first counting module and the logic output module when the first count value reaches a first preset value, the first counting module is configured to stop counting the pulses of the duty cycle modulation signal in response to the second detection signal, and the logic output module is configured to set the switch modulation signal to a final level state in response to the second detection signal.

[0011] Optionally, the duty cycle modulation circuit further comprises a third detection module configured to output a third detection signal when the second count value reaches a second preset value, and a first NOR gate configured to perform a NOR logic operation on the third detection signal and the first detection signal to provide a first logic signal to the second counting module, wherein the first NOR gate is configured to reset the second counting module when one of the first detection signal and the third detection signal is valid.

[0012] Optionally, the first counting module comprises: a first D flip-flop having a first data signal input end, a first clock control end, a first reset end and a first signal output end, the first data signal input end being configured to receive the duty cycle modulation signal, the first clock control end being configured to receive the clock signal, the first reset end being configured to receive a reset signal, and the first signal output end being configured to output a second logic signal; a second NOR gate configured to perform NOR logic operation on the second detection signal, the second logic signal and an inverted reset signal to output a third logic signal; and a first counter having a second clock control end, a second reset end and a second signal output end, the second clock control end being configured to receive the third logic signal, the second reset end being configured to receive the reset signal, and the second signal output end being configured to output the first count value.

[0013] Optionally, the second counting module comprises: a second counter having a third clock control end, a third reset end and a third signal output end, the third clock control end being configured to receive the clock signal, the third reset end being configured to receive the first logic signal, and the third signal output end being configured to output the second count value.

[0014] Optionally, the logic output module comprises: a logic unit having a first and a second count input end, a fourth clock control end, a fourth reset end and a fourth signal output end, the first count input end being configured to receive the first count value, the second count input end being configured to receive the second count value, the fourth clock control end being configured to receive the clock signal, the fourth reset end being configured to receive a reset signal, and the fourth signal output end being configured to output a fourth logic signal; a second D flip-flop having a second data signal input end, a fifth clock control end, a fifth reset end and a fifth signal output end, the second data signal input end being configured to receive a power supply voltage, the fifth clock control end being configured to receive the fourth logic signal, the fifth reset end being configured to receive the first logic signal, and the fifth signal output end being configured to output a fifth logic signal; a third D flip-flop having a third data signal input end, a sixth clock control end, a sixth reset end and a sixth signal output end, the third data signal input end being configured to receive the fifth logic signal, the sixth clock control end being configured to receive the clock signal, the sixth reset end being configured to receive an inverted first detection signal, and the sixth signal output end being configured to output a sixth logic signal; a third NOR gate configured to perform NOR logic operation on the second detection signal and the sixth logic signal to output a seventh logic signal; and a fourth NOR gate configured to perform NOR logic operation on the first detection signal and the seventh logic signal to output the switch modulation signal.

[0015] Optionally, the logic unit is configured to determine whether the first count value is equal to the second count value before each falling edge of the clock signal arrives, and if so, set the fourth logic signal to a logic high level.

[0016] Optionally, the first count value and the second count value are constituted by a multi-bit binary number, and the first counter and the second counter are implemented by a synchronous counter.

[0017] Optionally, the synchronous counter comprises a plurality of D flip-flops with the same number of bits as the multi-bit binary number, a clock control end of a first D flip-flop in the plurality of D flip-flops is configured to receive a count signal, and a plurality of signal transfer units are located before the second to last D flip-flop in the plurality of D flip-flops, wherein each signal transfer unit is configured to obtain a signal of a clock control end of a corresponding D flip-flop according to an output logic state of a D flip-flop before the corresponding D flip-flop and an inverted signal of the count signal.

[0018] Optionally, each signal transfer unit is configured to determine whether the output logic states of all D flip-flops before the corresponding D flip-flop are logic high levels, if so, control the signal of the clock control end of the corresponding D flip-flop to be the same as the count signal, and if not, control the signal of the clock control end of the corresponding D flip-flop to be a logic high level constantly.

[0019] Optionally, the signal transfer unit comprises at least one NAND gate or a combination of at least one NAND gate and an inverter.

[0020] Optionally, the frequency of the clock signal is set by the frequency of the switch modulation signal and the required linearity of the duty cycle variation of the system.

[0021] Optionally, the frequency of the duty cycle modulation signal is set by the time of chip switching or shutdown.

[0022] According to a second aspect of the embodiments of the present application, there is provided a noise suppression circuit for an audio power amplifier circuit, the audio power amplifier circuit comprising at least an integral amplification module, a signal modulation module and a driving output module, wherein the noise suppression circuit comprises: a high-frequency switch arranged between input resistors of a second-stage integral amplifier in the integral amplification module; and the above-mentioned duty cycle modulation circuit, which is configured to adjust the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch.

[0023] According to a third aspect of the embodiments of the present application, an audio power amplifier circuit is provided, comprising: an integral amplification module comprising at least a first-stage operational amplifier and a second-stage integral amplifier, configured to obtain a differential output signal by integral operational amplification of a differential input signal; a signal modulation module configured to generate a first pulse width modulation signal and a second pulse width modulation signal according to the differential output signal; a driving output module configured to amplify the first pulse width modulation signal and the second pulse width modulation signal respectively to obtain a driving signal for driving a loudspeaker; a high-frequency switch arranged between input resistors of the second-stage integral amplifier in the integral amplification module; and the above-mentioned duty cycle modulation circuit, configured to adjust the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch.

[0024] The audio power amplifier circuit of the embodiments of the present application comprises the high-frequency switch arranged between the input resistors of the second-stage integral amplifier in the integral amplification module and the duty cycle modulation circuit, which generates the switch modulation signal of the high-frequency switch by counting the duty cycle modulation signal and the clock signal during the process of turning on or off the chip, so that the duty cycle of the high-frequency switch can be gradually reduced or increased according to the set linearity to adjust the gain of the audio power amplifier circuit, which not only can weaken the "POP" noise, but also can improve the linearity of the circuit while reducing the cost of the circuit.

[0025] In further embodiments, the present application further provides a synchronous counter for counting, which can determine whether the outputs of all the D flip-flops before a D flip-flop in the counter are logic high levels before the clock control signal input of the D flip-flop by setting a signal transmission unit, and if the outputs of all the D flip-flops before the D flip-flop are logic high levels, the clock control signal of the D flip-flop is set to be the same as the counting signal, otherwise, the clock control signal of the D flip-flop is set to be logic high, so that the output delay of the counter can be only the delay of one D flip-flop, greatly reducing the delay of the counter. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 a circuit schematic diagram of an existing two-stage audio power amplifier circuit is shown;

[0028] Figure 2 a circuit schematic diagram of an audio power amplifier circuit with noise suppression capability according to embodiments of the present application is shown;

[0029] Figure 3A circuit schematic diagram of the duty cycle modulation circuit according to an embodiment of the present application is shown;

[0030] Figure 4 A working timing diagram of the duty cycle modulation circuit according to an embodiment of the present application is shown;

[0031] Figure 5 A working timing diagram of the first counting module according to an embodiment of the present application is shown;

[0032] Figure 6 A circuit schematic diagram of a synchronous counter according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] The present application is described in detail based on the embodiments. However, the present application is not limited to these embodiments. In the following detailed description of the present application, some specific details are described in detail. The present application can be fully understood without the description of these specific details. In order to avoid confusion of the essence of the present application, the well-known methods, processes, procedures, elements and circuits are not described in detail.

[0034] In addition, those skilled in the art should understand that the drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0035] Meanwhile, it should be understood that in the following description, "circuit" refers to a conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is said to be "connected to" another element or said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be intermediate elements, and the connection between elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0036] The present application is further described below in conjunction with the drawings and embodiments.

[0037] Figure 2 A circuit schematic diagram of an audio power amplifier circuit with noise suppression capability according to an embodiment of the present application is shown. As shown in Figure 2 The audio power amplifier circuit 200 includes an integral amplification module 210, a signal modulation module 220, a drive output module 230, a high-frequency switch K1, and a duty cycle modulation circuit 300.

[0038] The integral amplification module 210 includes a first-stage operational amplifier AMP1 and a second-stage integral amplifier AMP2. A pair of differential input signals INA and INB are coupled to the input of the first-stage operational amplifier AMP1 through input capacitors Cin and input resistors Rin, respectively, and are amplified in full differential mode by the first-stage operational amplifier AMP1 and the second-stage integral amplifier AMP2 in sequence to obtain differential output signals OPA and OPB. The differential input signals INA and INB are converted into current signals by resistors and input to the first-stage operational amplifier AMP1. The voltage signal output by the first-stage operational amplifier AMP1 is converted into a current signal by resistors R5-R8 and input to the second-stage integral amplifier AMP2. The differential output signals OPA and OPB output by the second-stage integral amplifier AMP2 are voltage signals. Further, feedback resistors R3 and R4 are arranged between the input and output of the first-stage operational amplifier AMP1. Integral capacitors C1 and C2 are arranged between the differential input and differential output of the second-stage integral amplifier AMP2. The signal modulation module 220 is configured to input the corrected differential output signals OPA and OPB, respectively, and generate first and second pulse width modulation signals PWMA and PWMB according to the differential output signals OPA and OPB. The first pulse width modulation signal PWMA is modulated by the differential output signal OPA, and the second pulse width modulation signal PWMB is modulated by the differential output signal OPB. Specifically, the signal modulation module 220 can include two parallel comparators CMP1 and CMP2. The comparator CMP1 is configured to compare the differential output signal OPA with a modulation signal RAMP and output the first pulse width modulation signal PWMA. The comparator CMP2 is configured to compare the differential output signal OPB with the modulation signal RAMP and output the second pulse width modulation signal PWMB. The modulation signal RAMP is usually a triangular wave or a sawtooth wave, which has periodic inclined rising and inclined falling edges. Thus, the two differential signals can be easily modulated into PWM signals. Of course, the signal modulation module 220 can also use other circuit structures to realize PWM modulation.

[0039] The drive output module 230 is configured to amplify the first pulse width modulation signal PWMA and the second pulse width modulation signal PWMB respectively to obtain the drive signals OUTA and OUTB. The drive output module 230 can be implemented by a half-bridge circuit including two transistors connected in series between a power supply and the ground. When the input pulse width modulation signal is at a high level, the transistor connected to the power supply is turned on and the transistor connected to the ground is turned off, so that a voltage and current defined by the power supply are output. When the input pulse width modulation signal is at a low level, the transistor connected to the ground is turned on and the transistor connected to the power supply is turned off, so that the PWM signal can be amplified. It should be noted that the integral amplification module 210 and the signal modulation module 220 of the present embodiment are usually powered by a low voltage domain power supply VDD generated by a low dropout linear regulator (LDO) (not shown in the figure) inside the chip, and VDD is usually about 4V-6V. The power supply of the drive output module 230 is usually a high voltage domain power supply PVDD (not shown in the figure) input from outside the chip, which can be as low as 4V and as high as 30V, and is usually about 20V-30V.

[0040] Further, the audio power amplifier circuit 200 of the present embodiment further includes a feedback circuit connected between the differential output end of the drive output module 230 and the differential input end of the second stage integral amplifier AMP2. Specifically, the feedback circuit is composed of two feedback resistors Rfb1 and Rfb2. The feedback resistor Rfb1 is connected between the first output end of the drive output module 230 and the first input end of the second stage integral amplifier AMP2, and the feedback resistor Rfb2 is connected between the second output end of the drive output module 230 and the second input end of the second stage integral amplifier AMP2.

[0041] In the present embodiment, the high-frequency switch K1 is arranged between the input resistors R5-R8 of the second stage integral amplifier AMP2 in the integral amplification module 210, and the duty cycle modulation circuit 300 is configured to generate a switching signal for controlling the on and off of the high-frequency switch K1, and control the duty cycle of the high-frequency switch K1 by controlling the duty cycle of the switching signal, so as to adjust the gain of the audio power amplifier circuit 200, and then weaken the "POP" noise.

[0042] In the present embodiment, before the chip is powered on, the duty cycle of the control signal of the high-frequency switch K1 generated by the duty cycle modulation circuit 300 is 100%, i.e. the high-frequency switch K1 is kept in the on state, at this time the gain of the circuit is 0, then the duty cycle modulation circuit 300 gradually reduces the duty cycle of the high-frequency switch K1 according to the set linearity, until the duty cycle of the switching signal is 0, at this time the gain of the circuit reaches the normal gain, when the chip is powered off, the duty cycle modulation circuit 300 gradually increases the duty cycle of the high-frequency switch according to the set linearity, until the duty cycle of the high-frequency switch K1 reaches 100%.

[0043] Figure 3 A circuit schematic diagram of a duty cycle modulation circuit 300 according to an embodiment of the present application is shown. As shown in the figure, the duty cycle modulation circuit 300 provided in this embodiment includes a first counting module 310, a second counting module 320, a logic output module 330, a NOR gate NOR1, and a first to third detection module 340-360. Figure 3

[0044] The first counting module 310 is configured to receive a duty cycle modulation signal CTRL_in and count the pulses of the duty cycle modulation signal CTRL_in to obtain a first count value CONT1. The second counting module 320 is configured to count the pulses of a clock signal CLK and obtain a second count value CONT2. The first count value CONT1 and the second count value CONT2 are, for example, multi-bit binary numbers. The logic output module 330 is configured to perform logic operations based on the first count value CONT1, the second count value CONT2, and the clock signal CLK, and finally output a switch modulation signal Fade_in and a switch modulation signal Fade_out. The switch modulation signal Fade_in is configured to control the change of the duty cycle of the high-frequency switch K1 during the chip startup process, and the switch modulation signal Fade_out is configured to control the change of the duty cycle of the high-frequency switch K1 during the chip shutdown process. In this embodiment, the switch modulation signal Fade_in and the switch modulation signal Fade_out are mutually inverse signals.

[0045] The duty cycle of the switch modulation signal refers to the ratio of the high level time to the switching period, and the logic output module 330 is configured to determine the pulse width (i.e., the high level time) of the switch modulation signal Fade_in and the switch modulation signal Fade_out based on the first count value CONT1, and determine the switching period of the switch modulation signal Fade_in and the switch modulation signal Fade_out based on the second count value CONT2, so as to finally control the duty cycle of the switch modulation signal.

[0046] ​The first detection module 340 is configured to detect the first count value CONT1, and output a first detection signal T1 to the logic output module 330 when the first count value CONT1 is 0. The second detection module 350 is configured to detect the first count value CONT1, and output a second detection signal T2 to the logic output module 330 when the first count value CONT1 reaches a first preset value. The third detection module 360 is configured to detect the second count value CONT2, and output a third detection signal T3 when the second count value CONT2 reaches a second preset value. One input terminal of the NOR gate NOR1 is configured to receive the third detection signal T3, another input terminal is configured to receive the first detection signal T1, and an output terminal is configured to provide a logic signal B1 to the logic output module. The first preset value is used to limit the total time period of the chip startup process or shutdown process, and the second preset value is used to limit the switching period of the switch modulation signal.

[0047] Specifically, the first counting module 310 includes a D flip-flop 301, a NOR gate NOR2, an inverter INV1, and a first counter 302.

[0048] The D flip-flop 301 has a data signal input terminal D, a clock control terminal Clk, a reset terminal NCLR (also referred to as a clear terminal), and signal output terminals Q and QN. The data signal input terminal D of the D flip-flop 301 is configured to receive the duty cycle modulation signal CTRL_in, the clock control terminal Clk is connected with the clock signal CLK, the reset terminal NCLR is connected with the reset signal Reset, and the signal output terminal QN is configured to output a logic signal B2. One input terminal of the NOR gate NOR2 is configured to receive the second detection signal T2, a second input terminal is connected with the signal output terminal QN of the D flip-flop 301 to receive the logic signal B2, and a third input terminal is connected with the output of the inverter INV1 to receive the inverted signal of the reset signal Reset. The first counter 302 has a clock control terminal Clk, a reset terminal NCLR, and an output terminal Out. The clock control terminal of the first counter 302 is connected with the output terminal of the NOR gate NOR2 to receive a logic signal B3, the reset terminal NCLR is connected with the reset signal Reset, and the output terminal Out is configured to output the first count value CONT1.

[0049] The second counting module 320 includes a second counter 303, which has a clock control terminal Clk, a reset terminal NCLR, and an output terminal Out. The clock control terminal Clk of the second counter 303 is connected with the clock signal CLK, the reset terminal NCLR is connected with the output terminal of the NOR gate NOR1, and the output terminal Out is configured to output the second count value CONT2.

[0050] The logic output module 330 comprises a logic unit 304, D flip-flops 305 and 306, NOR gates NOR3 and NOR4, and inverters INV2 and INV3. The logic unit 304 has count input terminals A and B, a clock control terminal Clk, a reset terminal NCLR, and an output terminal Out, wherein the count input terminal A is configured to receive the first count value CONT1, the count input terminal B is configured to receive the second count value CONT2, the clock control terminal Clk is configured to receive the clock signal CLK, the reset terminal NCLR is configured to receive the reset signal Reset, and the output terminal Out is configured to output a logic signal B4. The data signal input terminal D of the D flip-flop 305 is configured to receive a power supply voltage Vdd, the clock control terminal Clk is connected to the output terminal of the logic unit 304 to receive the logic signal B4, the reset terminal NCLR is connected to the output terminal of the NOR gate NOR1, and the signal output terminal QN is configured to output a logic signal B5. The data signal input terminal D of the D flip-flop 306 is connected to the signal output terminal QN of the D flip-flop 305 to receive the logic signal B5, the clock control terminal Clk is configured to receive the clock signal CLK, the reset terminal NCLR is connected to the output of the inverter INV2 to receive an inverted signal of the first detection signal T1, and the signal output terminal Q is configured to output a logic signal B6. One input terminal of the NOR gate NOR3 is connected to the output terminal of the second detection module 350 to receive the second detection signal T2, and the other input terminal is connected to the signal output terminal Q of the D flip-flop 306 to receive the logic signal B6 output therefrom. One input terminal of the NOR gate NOR4 is connected to the output terminal of the first detection module 340 to receive the first detection signal T1, the other input terminal is connected to the output terminal of the NOR gate NOR3 to receive the logic signal B7 output therefrom, and the output terminal is configured to output a switch modulation signal Fade_out. The input terminal of the inverter INV3 is connected to the output terminal of the NOR gate NOR4, and the output terminal is configured to output the switch modulation signal Fade_in.

[0051] Figure 4 The working timing diagrams of the duty cycle modulation circuit according to the embodiment of the present application are shown, wherein the timing diagrams of the reset signal Reset, the duty cycle modulation signal CTRL_in, the clock signal CLK, the output signal B4 of the logic unit 304, and the switch modulation signals Fade_in and Fade_out are shown respectively. The working principle of the duty cycle modulation circuit of the embodiment of the present application is described in detail below in combination with the working timing diagrams. Figure 3 and Figure 4 The working principle of the duty cycle modulation circuit of the embodiment of the present application is described in detail taking the chip shutdown process as an example.

[0052] First, the frequency of the input clock signal CLK is designed according to the frequency of the switch modulation signal Fade_out and the linearity of the required duty cycle variation. Assuming that the output frequency of the switch modulation signal Fade_out is 1M and the linearity of the required duty cycle variation is 1%, the frequency of the input clock signal CLK is 1M / 1% = 100M. Then, the frequency of the duty cycle modulation signal CTRL_in is designed according to the time requirement of the switch modulation signal Fade_out. Assuming that the time of the chip shutdown process is 10ms, the period of the duty cycle modulation signal CTRL_in is 10ms / 100 = 0.1ms.

[0053] In the embodiment, the reset end NCLR of the D flip-flop, the counter and the logic unit in the circuit is low active. Before time t0, the reset signal Reset is set to logic low, each module in the circuit is reset, the output of the first counter 302 is reset to zero, the first detection signal T1 output by the first detection module 340 is flipped to logic high, the switch modulation signal Fade_out is set to the initial level state, i.e. logic low (at this time, the duty cycle of the switch modulation signal Fade_out is 0), and the second counter 303, the D flip-flop 305 and the D flip-flop 306 are reset. After time t0, the reset signal Reset is set to logic high, each module in the circuit exits the reset state. At time t1, the pulse signal CTRL_in is input through the duty cycle modulation pin, and the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At this time, the first count value CONT1 is <000···001>.

[0054] Figure 5 The working timing diagram of the first counting module according to the embodiment of the application is shown. As shown in FIG. 4, the first counting module 310 is reset at time t0, and the first count value CONT1 is <000···001> at this time. At time t1, the first count value CONT1 is <000···010> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At time t2, the first count value CONT1 is <000···011> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At time t3, the first count value CONT1 is <000···100> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At time t4, the first count value CONT1 is <000···101> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At time t5, the first count value CONT1 is <000···110> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. At time t6, the first count value CONT1 is <000···111> after the first counting module 310 counts the pulses of the duty cycle modulation signal CTRL_in. Figure 5As shown, when the reset signal Reset is at a logic high level, the D flip-flop 301 determines the logic state of the output signal B2 according to the logic state of the duty cycle modulation signal CTRL_in at the duty cycle of the data signal input end D before each rising edge of the clock signal CLK, and finally obtains the waveform of the logic signal B2. Since the second detection signal T2 and the output of the inverter INV1 are both at a low level at this time, the logic signal B3 output by the NOR gate NOR2 is completely opposite to the waveform of the logic signal B2. The first counter 302 is effective before each rising edge of the logic signal B3, and counts the pulses of the signal B3, and outputs the first count value CONT1. Since the signal B3 is the same as the phase of the duty cycle modulation signal CTRL_in, the first counter 302 is equivalent to counting the pulses of the duty cycle modulation signal CTRL_in. When the value of the first count value CONT1 reaches a first preset value m (for example, m = 100, and 100 pulses of the duty cycle modulation signal CTRL_in correspond to a linearity requirement of 1% for the duty cycle change of the switch modulation signal), the second detection signal T2 output by the second detection module 350 flips to a logic high level, at this time the output signal B3 of the NOR gate NOR2 flips to a logic low level, and the first counter 302 stops pulse counting.

[0055] With reference to the foregoing description, the first detection module 300 can be used to detect the pulse number of the duty cycle modulation signal CTRL_in, and the second detection module 350 can be used to detect the pulse number of the switch modulation signal. The first detection module 300 and the second detection module 350 can be used to detect the pulse number of the switch modulation signal and the pulse number of the duty cycle modulation signal CTRL_in respectively, and the first detection module 300 and the second detection module 350 can be used to detect the pulse number of the switch modulation signal and the pulse number of the duty cycle modulation signal CTRL_in respectively. Figure 4When the second detection signal T2 is at a logic high level, or the output signal B7 of the NOR gate NOR3 flips to a logic low level, since the first count value CONT1 is not 0 after the first count module 310 starts counting, the first detection signal T1 is also at a logic low level at this time, and the output of the NOR gate NOR4 is set to a logic high level, corresponding to the switch modulation signal Fade_out being set to a logic high level (at this time, the duty cycle of the switch modulation signal Fade_out is 100%). When the first count value CONT1 is greater than 0 and less than the first preset value, the second counter 303 starts working, counting the pulses of the clock signal CLK, and outputting the second count value CONT2. At time t2, the D flip-flop 306 outputs the logic high level of the signal output end QN of the D flip-flop 305 in the reset stage to the signal output end Q of the D flip-flop 306 at the rising edge of the clock signal CLK every cycle, the NOR gate NOR3 sets the signal B7 to a logic low level according to the logic high level of the signal B6, and the NOR gate NOR4 sets the switch modulation signal Fade_out to a high level according to the logic low level of the detection signal T1 and the signal B7. At time t3, the second count value CONT2 and the first count value CONT1 are equal, and the logic unit 304 jumps the output signal B4 from a logic low level to a logic high level at the falling edge of the clock signal CLK, and the D flip-flop 306 sets the switch modulation signal Fade_out to a logic low level when the next rising edge of the clock signal CLK arrives. The second counter 303 continues to count the pulses of the clock signal CLK, and when the second count value CONT2 reaches the second preset value (for example, equal to 100), the third detection module 360 outputs the third detection signal T3 flipping to a high level, and the NOR gate NOR1 sets the signal B1 to a logic low level according to the high level of the third detection signal T3, resets the D flip-flop 305 and the second counter 303, and a switch cycle of the switch modulation signal Fade_out ends, and the process is repeated in the subsequent switch cycles.

[0056] Figure 6 A circuit schematic diagram of a synchronous counter according to an embodiment of the present application is shown. In this embodiment, the key factor of limiting the frequency of the clock signal CLK is the counting delay of the counter. In a conventional design, the counter is a binary counter composed of a plurality of D flip-flops connected in series. If the number of bits output by the counter is large, the delay will become the key factor of limiting the frequency of the clock signal CLK. In order to minimize the delay, a new synchronous counter is designed for the first counter 302 and the second counter 303 in this embodiment, which greatly reduces the delay of the counter.

[0057] As Figure 6As shown, the synchronization counter 400 of the embodiment includes a plurality of D flip-flops DFF1-DFF4 (four D flip-flops are taken as an example in the embodiment, and the present application is not limited thereto) and a plurality of signal transfer units (such as the signal transfer units 401-403 shown in the middle) located before the second D flip-flop DFF2 and the last D flip-flop DFF4 in the plurality of D flip-flops. Each signal transfer unit is configured to obtain the clock control signal of the D flip-flop connected thereto according to the logic state of the signal output end Q of the previous D flip-flop and the inverted signal of the count signal IN. Figure 6

[0058] Specifically, the data signal input ends D of the plurality of D flip-flops DFF1-DFF4 are connected with the signal output ends QN, the clock control ends Clk are configured to receive the clock control signal, and the signal output ends Q are respectively configured to output each bit of the multi-bit binary count value <q0q1q2q3>.

[0059] The D flip-flop DFF1 further comprises inverters INV4 and INV5 connected in sequence, an input terminal of the inverter INV4 is configured to receive the counting signal IN, an output terminal of the inverter INV4 is connected with an input terminal of the inverter INV5, and an output terminal of the inverter INV5 is connected with the clock control terminal Clk of the D flip-flop DFF1, so that the clock control signal of the D flip-flop DFF1 is the same as the waveform of the counting signal IN.

[0060] The signal transmission unit 401 comprises, for example, a NAND gate NAND1, one input terminal of the NAND gate NAND1 is configured to receive the logic level of the signal output terminal Q of the D flip-flop DFF1, the other input terminal of the NAND gate NAND1 is configured to receive the inverted signal of the counting signal IN, and an output terminal of the NAND gate NAND1 is connected with the clock control terminal Clk of the D flip-flop DFF2 to provide the clock control signal thereof.

[0061] The signal transmission unit 402 comprises, for example, a NAND gate NANB5, an inverter INV6 and a NAND gate NANB6. One input terminal of the NAND gate NANB5 is connected with the signal output terminal Q of the D flip-flop DFF2, the other input terminal of the NAND gate NANB5 is connected with the signal output terminal of the D flip-flop DFF1, an output terminal of the NAND gate NAND is connected with an input terminal of the inverter INV6, an output terminal of the inverter INV6 and one input terminal of the NAND gate NANB6 are connected, the other input terminal of the NAND gate NANB6 is connected with the inverted signal of the counting signal IN, and an output terminal of the NAND gate NANB6 is connected with the clock control terminal of the D flip-flop DFF3. Wherein, the signal transmission unit 402 is configured to perform NAND logic operation on the output results of the D flip-flops DFF1 and DFF2, the operation result is inverted by the inverter INV6 and then performs NAND logic operation with the inverted signal of the counting signal IN, and finally obtains the clock control signal of the D flip-flop DFF3.

[0062] The signal transmission unit 403 comprises, for example, a NAND gate NAND4, an inverter INV7 and a NAND gate NAND5. One input terminal of the NAND gate NAND4 is used for receiving the AND logic operation result of the outputs of the D flip-flops DFF1 and DFF2, the other input terminal receives the output result of the D flip-flop DFF3, and the output terminal is connected with the input terminal of the inverter INV7. One input terminal of the NAND gate NAND5 is connected with the output terminal of the inverter INV7, the other input terminal is connected with the inverted signal of the count signal IN, and the output terminal is connected with the clock control terminal of the D flip-flop DFF4. The NAND gate NAND4 is used for performing NAND logic operation on the AND logic operation result of the outputs of the D flip-flops DFF1 and DFF2 and the output logic of the D flip-flop DFF3, the result is inverted by the inverter INV7 to obtain the AND logic operation result of the output results of the D flip-flops DFF1 to DFF3, and the result is subjected to NAND logic operation with the inverted signal of the count signal IN, and finally the clock control signal of the D flip-flop DFF4 is obtained.

[0063] In summary, the synchronization counter provided by the embodiment can, through the signal transmission unit, judge whether the signal output terminals Q of all the D flip-flops before a D flip-flop in the counter are at a logic high level before the clock control signal of the D flip-flop is input, if the signal output terminals Q of all the D flip-flops before the D flip-flop are at a logic high level, the clock control signal of the D flip-flop is the same as the count signal IN, otherwise, the clock control signal of the D flip-flop is always at a logic high level, so the output delay of the synchronization counter of the embodiment is only the delay of one D flip-flop, and the delay of the counter is greatly reduced.

[0064] In summary, the audio power amplifier circuit of the embodiment comprises a high-frequency switch and a duty cycle modulation circuit arranged between the input resistors of the second-stage integral amplifier of the integral amplification module. The duty cycle modulation circuit generates a switch modulation signal of the high-frequency switch by counting a duty cycle modulation signal and a clock signal during the process of turning on or turning off the chip, so as to gradually reduce or increase the duty cycle of the high-frequency switch according to the set linearity, thereby adjusting the gain of the audio power amplifier circuit. The audio power amplifier circuit not only can weaken the "POP" noise, but also can improve the linearity of the circuit and reduce the cost of the circuit.

[0065] In further embodiments, the application also provides a synchronous counter for counting, which can judge in advance whether the outputs of all the D flip-flops before a D flip-flop in the counter are logic high level before the clock control signal input of the D flip-flop by setting the signal transmission unit, if the outputs of all the D flip-flops before the D flip-flop are logic high level, the clock control signal of the D flip-flop is the same as the counting signal, otherwise, the clock control signal of the D flip-flop is set to logic high level, so that the output delay of the counter can be only one D flip-flop delay, greatly reducing the delay of the counter.

[0066] Those of ordinary skill in the art will appreciate that the words "during," "while," and "when" as used herein in relation to circuit operation are not strict temporal terms; there can be one or more delays of small but reasonable amounts between the initiation of an action and the reaction that it initiates, e.g., various transmission delays, etc. The use of the word "about" or "substantially" herein means that an element has a parameter that is intended to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that make it difficult to be strictly the stated value. It has been properly determined in the art that a deviation of at least ten percent (10%) (at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the described accurate ideal target. When used in connection with signal states, the actual voltage value or logic state of a signal (e.g., "1" or "0") depends on whether positive logic or negative logic is used.

[0067] Furthermore, it is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting; it is also possible in the present application that units operations are presented in a form that is different than described herein. For example, the use of "a" or "an" to describe a singular entity also encompasses the meaning of "one or more" in reference to that entity. Furthermore, the use of terms like first and second are not intended to imply a chronological order but are used to distinguish one from another unless otherwise indicated. Moreover, the use of terminology like "including" or "comprising" is not intended to rule out other elements or steps not specifically mentioned. Furthermore, the use of the term "about" in relation to a value or position is intended to encompass a value or position that is intended to be close to the stated value or position. However, as is well known in the art, there are always slight deviations that make it difficult to be strictly the stated value. It has been properly determined in the art that a deviation of at least ten percent (10%) (at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the described accurate ideal target. When used in connection with signal states, the actual voltage value or logic state of a signal (e.g., "1" or "0") depends on whether positive logic or negative logic is used.

[0068] In accordance with the present application, the embodiments as described above do not represent all the possible implementations of the present application. It will be apparent to those skilled in the art that many modifications and variations can be made. The embodiments selected and described are for the purposes of best explaining the principles of the present application and its practical application. The present application is therefore to be considered as limited by the scope of the claims, which appear below. ​

Claims

1. A duty cycle modulation circuit of an audio power amplifier circuit, the audio power amplifier circuit comprising an integral amplification module and a high frequency switch arranged between input resistances of a second stage integral amplifier in the integral amplification module, the duty cycle modulation circuit being configured to adjust a gain of the audio power amplifier circuit by controlling a duty cycle of the high frequency switch, wherein the duty cycle modulation circuit comprising: a first counting module configured to count pulses of a duty cycle modulation signal to obtain a first count value; a second counting module configured to count pulses of a clock signal to obtain a second count value; and a logic output module configured to perform a logic operation on the first count value, the second count value and the clock signal to obtain a switch modulation signal for controlling the high frequency switch.

2. The duty cycle modulation circuit of claim 1, wherein, the logic output module is configured to determine a pulse width of the switch modulation signal based on the first count value and to determine a switching period of the switch modulation signal based on the second count value.

3. The duty cycle modulation circuit of claim 1, further comprising: a first detection module configured to provide a first detection signal to the logic output module when the first count value is 0, the logic output module is configured to set the switch modulation signal to an initial level state based on the first detection signal.

4. The duty cycle modulation circuit of claim 3, further comprising: a second detection module configured to provide a second detection signal to the first counting module and the logic output module when the first count value reaches a first preset value, the first counting module is configured to stop counting the pulses of the duty cycle modulation signal in response to the second detection signal, and the logic output module is configured to set the switch modulation signal to a final level state in response to the second detection signal.

5. The duty cycle modulation circuit of claim 4, further comprising: a third detection module configured to output a third detection signal when the second count value reaches a second preset value; and a first NAND gate configured to perform a NAND logic operation on the third detection signal and the first detection signal to provide a first logic signal to the second counting module, wherein the first NAND gate is configured to reset the second counting module when one of the first detection signal and the third detection signal is valid. the first counting module comprises:

6. The duty cycle modulation circuit of claim 5, wherein, a first D flip-flop having a first data signal input configured to receive the duty cycle modulation signal, a first clock control input configured to receive the clock signal, a first reset input configured to receive a reset signal, and a first signal output configured to output a second logic signal; a second NAND gate configured to perform a NAND logic operation on the second detection signal, the second logic signal and an inverse of the reset signal to output a third logic signal; and a first NOR gate configured to perform a NOR logic operation on the third logic signal, the second logic signal and the inverse of the reset signal to output the switch modulation signal. a first counter having a second clock control terminal, a second reset terminal and a second signal output terminal, the second clock control terminal being configured to receive the third logic signal, the second reset terminal being configured to receive the reset signal, and the second signal output terminal being configured to output the first count value.

7. The duty cycle modulation circuit of claim 6, wherein, The second counting module comprises: a second counter having a third clock control terminal, a third reset terminal and a third signal output terminal, the third clock control terminal being configured to receive the clock signal, the third reset terminal being configured to receive the first logic signal, and the third signal output terminal being configured to output the second count value.

8. The duty cycle modulation circuit of claim 5, wherein, The logic output module comprises: a logic unit having a first and a second count input terminal, a fourth clock control terminal, a fourth reset terminal and a fourth signal output terminal, the first count input terminal being configured to receive the first count value, the second count input terminal being configured to receive the second count value, the fourth clock control terminal being configured to receive the clock signal, the fourth reset terminal being configured to receive the reset signal, and the fourth signal output terminal being configured to output a fourth logic signal; a second D flip-flop having a second data signal input terminal, a fifth clock control terminal, a fifth reset terminal and a fifth signal output terminal, the second data signal input terminal being configured to receive a power voltage, the fifth clock control terminal being configured to receive the fourth logic signal, the fifth reset terminal being configured to receive the first logic signal, and the fifth signal output terminal being configured to output a fifth logic signal; a third D flip-flop having a third data signal input terminal, a sixth clock control terminal, a sixth reset terminal and a sixth signal output terminal, the third data signal input terminal being configured to receive the fifth logic signal, the sixth clock control terminal being configured to receive the clock signal, the sixth reset terminal being configured to receive an inverted signal of the first detection signal, and the sixth signal output terminal being configured to output a sixth logic signal; a third NOR gate configured to perform a NOR logic operation on the second detection signal and the sixth logic signal, and output a seventh logic signal; and a fourth NOR gate configured to perform a NOR logic operation on the first detection signal and the seventh logic signal, and output the switch modulation signal.

9. The duty cycle modulation circuit of claim 8, wherein, The logic unit is configured to determine whether the first count value is equal to the second count value before each falling edge of the clock signal arrives, and set the fourth logic signal to a logic high level if the first count value is equal to the second count value.

10. The duty cycle modulation circuit of claim 7, wherein, The first count value and the second count value are constituted by a multi-bit binary number, and the first counter and the second counter are implemented by a synchronous counter.

11. The duty cycle modulation circuit of claim 10, wherein, The synchronous counter comprises: a plurality of D flip-flops, the number of the plurality of D flip-flops being equal to the number of bits of the multi-bit binary number, a first D flip-flop of the plurality of D flip-flops having a clock control terminal configured to receive a count signal; and a plurality of signal transfer units located before the second to last D flip-flop of the plurality of D flip-flops, wherein each signal transfer unit is configured to obtain a signal of a clock control terminal of a corresponding D flip-flop according to an output logic state of a previous D flip-flop of the corresponding D flip-flop and an inverted signal of the count signal.

12. The duty cycle modulation circuit of claim 11, wherein, Each signal transfer unit is configured to: The output logic state of all D flip-flops before the D flip-flop corresponding to the D flip-flop is determined, and if the output logic state is a logic high level, the signal of the clock control end of the D flip-flop corresponding to the D flip-flop is controlled to be the same as the counting signal; otherwise, the signal of the clock control end of the D flip-flop corresponding to the D flip-flop is controlled to be a logic high level.

13. The duty cycle modulation circuit of claim 12, wherein, The signal transmission unit comprises at least one NAND gate or a combination of at least one NAND gate and an inverter.

14. The duty cycle modulation circuit of claim 1, wherein, The frequency of the clock signal is set by the frequency of the switching modulation signal and the variation linearity of the required duty cycle of the system.

15. The duty cycle modulation circuit of claim 1, wherein, The frequency of the duty cycle modulation signal is set by the time of chip switching or shutdown.

16. A noise suppression circuit for an audio power amplifier circuit, the audio power amplifier circuit comprising at least an integration amplification module, a signal modulation module and a drive output module, wherein, The noise suppression circuit comprises: A high-frequency switch arranged between the input resistors of the second-stage integration amplifier in the integration amplification module; and The duty cycle modulation circuit according to any one of claims 1-15, wherein the gain of the audio power amplifier circuit is adjusted by controlling the duty cycle of the high-frequency switch.

17. An audio power amplifier circuit, comprising: The audio power amplifier circuit comprises: An integration amplification module comprising at least a first-stage operational amplifier and a second-stage integration amplifier, for obtaining a differential output signal by integrating and amplifying a differential input signal; A signal modulation module, for generating a first pulse width modulation signal and a second pulse width modulation signal according to the differential output signal; A driving output module, for respectively amplifying the first pulse width modulation signal and the second pulse width modulation signal to obtain a driving signal for driving a loudspeaker; A high-frequency switch arranged between the input resistors of the second-stage integration amplifier in the integration amplification module; and The duty cycle modulation circuit according to any one of claims 1-15, for adjusting the gain of the audio power amplifier circuit by controlling the duty cycle of the high-frequency switch. ​

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