A Jitter Adjustment Circuit and Method for a Phase Interpolator
By introducing a rate converter and frequency divider into the phase interpolator, adjusting the offset step and substep increments, the big problem of clock signal jitter caused by the complex operation logic of the phase interpolator is solved, and smaller jitter and faster update speed are achieved.
Patent Information
- Application Number
- CN202211151789.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-09-21
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2042-09-21
AI Technical Summary
The operation logic of the existing phase interpolator is complicated, resulting in too large update step setting, resulting in a large clock signal jitter.
By introducing phase interpolation controllers, rate converters, phase accumulators, and frequency dividers, adjust the offset step increments and substep increments to reduce the update step.
The jitter output clock signal by the phase interpolator is effectively reduced, the control word update speed is improved, the clock signal waveform changes are reduced, and the jitter is reduced by 68%.
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Figure CN115459761B_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present disclosure relate to the field of circuit design technology, and in particular, to a jitter adjustment circuit and method for a phase interpolator. Background Art
[0002] In the prior art, in order to effectively reduce electromagnetic interference (EMI), a frequency spreading technology is usually adopted at the signal sending end. The frequency spreading function makes the data frequency at the sending end change slightly around a center frequency. At the same time, in order to accurately sample the received data, a phase interpolator is usually used at the receiving end to obtain the optimal sampling phase. Therefore, the phase interpolator is often applied in clock recovery circuits and frequency adjustment circuits.
[0003] However, the arithmetic logic of the phase interpolation controller is relatively complex, which greatly limits its operating speed, and then causes a phenomenon that the update step of the phase interpolator needs to be set very large to track the frequency change. However, if the update step is too large, the jitter of the clock signal output by the phase interpolator will be large. Summary of the Invention
[0004] Embodiments of the present disclosure provide a jitter adjustment circuit for a phase interpolator, which can reduce the update step, thereby reducing the jitter of the clock signal output by the phase interpolator.
[0005] On the one hand, embodiments of the present disclosure provide a jitter adjustment circuit for a phase interpolator, including: a phase interpolation controller, a rate converter, a phase accumulator, a phase interpolator, a first frequency divider, and a second frequency divider, wherein:
[0006] The phase interpolation controller is configured to determine an offset step increment P of the current offset step update period according to the clock signal and send it to the rate converter whenever receiving the clock signal divided by the first frequency divider;
[0007] The rate converter is configured to determine an offset sub-step increment p of each offset step update sub-period according to the offset step increment P received from the phase interpolation controller, the number of periods of offset step update, and the number of sub-periods of offset step update specified in advance; and is further configured to send the offset sub-step increment of the current offset step update sub-period to the phase accumulator whenever receiving the clock signal divided by the second frequency divider;
[0008] The phase accumulator is configured to accumulate the offset sub-step increment of the current offset step update sub-cycle sent by the rate converter and the offset sub-step of the historical offset step update sub-cycle to obtain the offset sub-step of the new current offset step update sub-cycle. It is further configured to send the offset sub-step of the current offset step update sub-cycle to the phase interpolator whenever a clock signal divided by the second frequency divider is received.
[0009] The phase interpolator is configured to receive the phase-locked loop clock signal and perform step offset on the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-cycle sent by the phase accumulator, and output the clock signal.
[0010] On the other hand, an embodiment of the present disclosure further provides a jitter adjustment method for a phase interpolator, which is applied to a jitter adjustment circuit of the phase interpolator. The method includes:
[0011] Whenever the phase interpolation controller receives a clock signal divided by the first frequency divider, it determines the offset step increment P of the current offset step update cycle according to the clock signal and sends it to the rate converter.
[0012] The rate converter determines the offset sub-step increment p of each offset step update sub-cycle according to the offset step increment P received from the phase interpolation controller, the number of cycles of the offset step update, and the number of pre-specified offset step update sub-cycles. It is further configured to send the offset sub-step increment of the current offset step update sub-cycle to the phase accumulator whenever a clock signal divided by the second frequency divider is received.
[0013] The phase accumulator accumulates the offset sub-step increment of the current offset step update sub-cycle sent by the rate converter and the offset sub-step of the historical offset step update sub-cycle to obtain the offset sub-step of the new current offset step update sub-cycle. It is further configured to send the offset sub-step of the current offset step update sub-cycle to the phase interpolator whenever a clock signal divided by the second frequency divider is received.
[0014] The phase interpolator receives the phase-locked loop clock signal and performs step offset on the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-cycle sent by the phase accumulator, and outputs the clock signal.
[0015] Compared with the related art, the jitter adjustment circuit of the phase interpolator provided by the embodiments of the present disclosure reduces the update step by a rate converter that can determine the offset sub-step increment for each offset step update sub-cycle according to the offset step increment P received from the phase interpolation controller, the number of cycles of offset step update, and the pre-specified number of sub-cycles of offset step update, thereby reducing the jitter of the clock signal output by the phase interpolator.
[0016] Other features and advantages of the present disclosure will be described in the following specification, and in part will be obvious from the specification, or will be understood by implementing the present disclosure. Other advantages of the present disclosure can be realized and obtained by the solutions described in the specification and the accompanying drawings. Description of the Drawings
[0017] The drawings are used to provide an understanding of the technical solutions of the present disclosure, and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation to the technical solutions of the present disclosure.
[0018] Figure 1 Schematic diagram of an existing phase interpolator circuit according to an embodiment of the present disclosure;
[0019] Figure 2 Schematic diagram of a jitter adjustment circuit of a phase interpolator according to an embodiment of the present disclosure;
[0020] Figure 3 Schematic diagram of another jitter adjustment circuit of a phase interpolator according to an embodiment of the present disclosure;
[0021] Figure 4 Schematic diagram of the circuit signal waveform of an existing phase interpolator circuit according to an embodiment of the present disclosure;
[0022] Figure 5 Schematic diagram of the circuit signal waveform of a jitter adjustment circuit of a phase interpolator according to an embodiment of the present disclosure;
[0023] Figure 6 Schematic diagram of the eye diagram of an existing phase interpolator circuit according to an embodiment of the present disclosure;
[0024] Figure 7 Schematic diagram of the eye diagram of a jitter adjustment circuit of a phase interpolator according to an embodiment of the present disclosure;
[0025] Figure 8 Schematic diagram of the flow of a jitter adjustment method of a phase interpolator according to an embodiment of the present disclosure. Detailed Embodiments
[0026] The present disclosure describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be apparent to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope of the embodiments described in the present disclosure. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.
[0027] The present disclosure includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in the present disclosure can also be combined with any conventional features or elements to form unique solutions defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other solutions to form another unique solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in the present disclosure can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made in accordance with the appended claims and their equivalents. In addition, various modifications and changes can be made within the scope of the appended claims.
[0028] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific order of the steps described herein, the method or process should not be limited to the specific order of steps described. As will be understood by those of ordinary skill in the art, other step orders are possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of the present disclosure.
[0029] The output clock jitter of the prior art phase interpolator is relatively large. The commonly used design circuits in the prior art are as Figure 1 shown, including:
[0030] A phase interpolation controller 11, a phase accumulator 12, a phase interpolator 13, and a frequency divider 14 (assumed to be an n-frequency divider), where:
[0031] The phase interpolation controller 11 is configured to, whenever receiving the clock signal divided by the frequency divider 14, determine the offset step increment of the current offset step update period according to the clock signal, and send it to the phase accumulator 12;
[0032] The phase accumulator 12 is configured to accumulate the offset step increment of the current offset step update period sent by the phase interpolation controller 11 with the offset step of the historical offset step update period to obtain the offset step of the new current offset step update period; and is further configured to, whenever receiving the clock signal divided by the frequency divider 14, send the offset step of the current offset step update period to the phase interpolator 13;
[0033] The phase interpolator 13 is configured to receive the phase-locked loop clock signal, perform step offset on the phase-locked loop clock signal according to the offset step of the current offset step update period sent by the phase accumulator 12, and output the clock signal.
[0034] The phase interpolator is usually a common module in the clock recovery circuit and the frequency adjustment circuit. If the input clock signal period is T, the phase interpolator can output a clock signal with a phase of T*SEL / N, where SEL is the phase control signal and N is the number of adjustable phases of the phase interpolator. SEL = phase_sel[7:0], N = 256. The phase interpolator is based on the phase-locked loop clock (CLK_SRC) sent by the phase-locked loop, and selects the clock (CLK_PI) corresponding to the phase according to the value of phase_sel[7:0] for output. Generally speaking, the operation logic of the phase interpolation controller is relatively complex, which will greatly limit its operating speed. On the other hand, in order to be able to follow the phase-locked loop clock (CLK_SRC) in a timely manner, the update step phase_add_tmp1 of the phase interpolator is set to be very large, and a very large update step will cause a large jitter of the phase interpolator clock (CLK_PI).
[0035] The embodiment of the present disclosure provides a jitter adjustment circuit for a phase interpolator, as Figure 2 shown, including: a phase interpolation controller 21, a rate converter 22, a phase accumulator 23, a phase interpolator 24, a first frequency divider 25, and a second frequency divider 26, where:
[0036] The phase interpolation controller 21 is configured to, whenever receiving the clock signal divided by the first frequency divider 25, determine the offset step increment P of the current offset step update period according to the clock signal, and send it to the rate converter 22;
[0037] The rate converter 22 is configured to determine an offset sub-step increment p for each offset step update sub-period according to the offset step increment P received from the phase interpolation controller 21, the number of periods for offset step update, and the number of pre-specified sub-periods for offset step update; and is further configured to send the offset sub-step increment of the current offset step update sub-period to the phase accumulator 23 whenever receiving the clock signal divided by the second frequency divider 26.
[0038] The phase accumulator 23 is configured to perform an accumulation calculation on the offset sub-step increment of the current offset step update sub-period sent by the rate converter 22 and the offset sub-step of the historical offset step update sub-period to obtain a new offset sub-step of the current offset step update sub-period; and is further configured to send the offset sub-step of the current offset step update sub-period to the phase interpolator 24 whenever receiving the clock signal divided by the second frequency divider 26.
[0039] The phase interpolator 24 is configured to receive the phase-locked loop clock signal, perform a step offset on the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-period sent by the phase accumulator 23, and output the clock signal.
[0040] The offset sub-step of the historical offset step update sub-period refers to the offset sub-step of the previous offset step update sub-period.
[0041] The jitter adjustment circuit of the phase interpolator provided by the embodiment of the present application reduces the update step through the rate converter that can determine the offset sub-step increment for each offset step update sub-period according to the offset step increment P received from the phase interpolation controller, the number of periods for offset step update, and the number of pre-specified sub-periods for offset step update, thereby reducing the jitter of the clock signal output by the phase interpolator.
[0042] Exemplarily, the first frequency divider is an n-frequency divider, where n = the number of periods for offset step update.
[0043] The second frequency divider is an m-frequency divider, where m = the number of sub-periods for offset step update.
[0044] Wherein, the number of periods for offset step update refers to: the number of clock periods between offset step updates, that is, how many clock periods to update the offset step; the number of periods for offset sub-step update refers to: the number of clock periods between offset sub-step updates, that is, how many clock periods to update the offset sub-step.
[0045] Exemplarily, n is an integer multiple of m.
[0046] The jitter adjustment circuit of the phase interpolator provided by the embodiment of the present application, compared with the existing technology circuit structure, increases a rate converter to improve the control word update speed, thereby reducing the update step size, so as to achieve the purpose of reducing the jitter of the clock signal (CLK_PI) of the phase interpolator.
[0047] Exemplarily, when P*m is divisible by n, the offset sub-step increment p of each offset step update sub-period is P*m / n.
[0048] Exemplarily, when P*m is not divisible by n, the offset sub-step increment p of each offset step update sub-period is Or Wherein, the sum of the offset sub-step increments of all offset step update sub-periods in an offset step update period is P.
[0049] The embodiment of the present disclosure also provides a jitter adjustment circuit of a phase interpolator. As Figure 3 shown, it is assumed that the phase interpolation controller of this circuit updates the offset step size every 8 clock cycles. It is assumed that the desired phase offset step size each time is P (corresponding to Figure 3 Phase_add_x4[7:0] in), and it is assumed that the rate converter needs to update the offset sub-step (Step) every 2 clock cycles. The phase offset step (Step0, Step1, Step2, Step3) each time is P / 4 (corresponding to Figure 3 Phase_add_x1[7:0] in) = M + N / 4, where M is the quotient and N is the remainder, N = 0 to 3. By selecting the phase offset step each time through Table 1, the accuracy before and after the rate conversion can be kept unchanged.
[0050]
[0051] Compared with Figure 4 the circuit signal waveform schematic diagram of the existing phase interpolator circuit shown (assuming that the phase interpolation controller of this circuit updates the offset step size every 8 clock cycles), Figure 3 the circuit signal waveform schematic diagram of the corresponding jitter adjustment circuit of the phase interpolator is as Figure 5 shown, wherein, Figure 4 phase_add_x4 in is the offset step increment of each current offset step update period, and phase_add_sel is the offset step of each offset step update period; Figure 5Among them, phase_add_x4 is the offset step increment for each current offset step update period, phase_add_x1 is the offset sub-step increment for each current offset sub-step update period, and phase_add_sel is the offset sub-step for each offset sub-step update period. CLK_PI is based on the received CLK_SRC, and its phase is changed and output according to phase_add_sel.
[0052] From Figure 4 and Figure 5 By comparison, it can be seen that at the update of the offset step update period of the existing phase interpolator circuit, that is, at the circled position, the waveform of the clock signal CLK_PI output by the phase interpolator changes greatly, so its jitter is large; while for the jitter adjustment circuit of the phase interpolator provided by the embodiments of the present disclosure at the update of the offset step update period, the waveform of the clock signal CLK_PI output by the phase interpolator changes very little, and almost no change can be seen, so its jitter is very small.
[0053] The eye diagram of the clock signal CLK_PI of the existing phase interpolator circuit is as Figure 6 shown. The eye diagram of the clock signal CLK_PI of the jitter adjustment circuit of the phase interpolator provided by the embodiments of the present disclosure is as Figure 7 shown. By comparing Figure 6 , 7 it can be seen that the jitter of the eye diagram of the clock signal of the jitter adjustment circuit (whose circuit structure is as Figure 2 shown) is 68% lower than that of the clock signal of the existing phase interpolator circuit (whose circuit structure is as Figure 1 shown). (The jitter is reduced from 17.3 ps to 5.6 ps)
[0054] The embodiments of the present disclosure also provide a method for adjusting the jitter of a phase interpolator, as Figure 8 shown, including:
[0055] Step 301: Whenever the phase interpolation controller receives the clock signal divided by the first frequency divider, it determines the offset step increment P of the current offset step update period according to the clock signal and sends it to the rate converter;
[0056] Step 302: The rate converter determines the offset sub-step increment p of each offset step update sub-period according to the offset step increment P received from the phase interpolation controller, the number of periods of offset step update, and the number of pre-specified offset step update sub-periods; it is also used to send the offset sub-step increment of the current offset step update sub-period to the phase accumulator whenever it receives the clock signal divided by the second frequency divider;
[0057] Step 303: The phase accumulator adds the offset sub-step increment of the current offset step update sub-cycle sent by the rate converter to the offset sub-step of the historical offset step update sub-cycle to obtain a new offset sub-step of the current offset step update sub-cycle. It is also used to send the offset sub-step of the current offset step update sub-cycle to the phase interpolator whenever it receives the clock signal divided by the second frequency divider.
[0058] Step 304: The phase interpolator receives the phase-locked loop clock signal and performs a step offset on the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-cycle sent by the phase accumulator, and outputs the clock signal.
[0059] Exemplarily, the first frequency divider is an n-frequency divider, where n = the number of cycles of offset step update;
[0060] The second frequency divider is an m-frequency divider, where m = the number of sub-cycles of offset step update.
[0061] Exemplarily, n is an integer multiple of m.
[0062] Exemplarily, when P*m is divisible by n, the offset sub-step increment p of each offset step update sub-cycle is P*m / n.
[0063] Exemplarily, when P*m is not divisible by n, the offset sub-step increment p of each offset step update sub-cycle is or where the sum of the offset sub-step increments of all offset step update sub-cycles in an offset step update cycle is P.
[0064] It should be understood that the processor can be a central processing unit (Central Processing Unit, abbreviated as "CPU"), and the processor can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.
[0065] The memory can include a read-only memory and a random access memory, and provide instructions and data to the processor. A part of the memory can also include a non-volatile random access memory. For example, the memory can also store information about the device type.
[0066] In the implementation process, the processing performed by the terminal device can be completed by the integrated logic circuit of the hardware in the processor or the instructions in the form of software. That is, the steps of the method disclosed in the embodiments of the present disclosure can be embodied as being executed and completed by the hardware processor, or executed and completed by the combination of the hardware and software modules in the processor. The software module can be located in a storage medium such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory, or an electrically erasable programmable memory, a register, etc. This storage medium is located in the memory, and the processor reads the information in the memory and combines its hardware to complete the steps of the above method. To avoid repetition, it will not be described in detail here.
[0067] This application describes multiple embodiments, but the description is exemplary rather than restrictive, and it will be obvious to those of ordinary skill in the art that there can be more embodiments and implementation solutions within the scope covered by the embodiments described in this application. Although many possible feature combinations are shown in the drawings and discussed in the detailed description, many other combination ways of the disclosed features are also possible. Unless specifically restricted, any feature or element of any embodiment can be combined with any other feature or element in any other embodiment, or can replace any other feature or element in any other embodiment.
[0068] This application includes and contemplates combinations with features and elements known to those of ordinary skill in the art. The embodiments, features, and elements already disclosed in this application can also be combined with any conventional features or elements to form a unique inventive solution defined by the claims. Any feature or element of any embodiment can also be combined with features or elements from other inventive solutions to form another unique inventive solution defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application can be implemented alone or in any suitable combination. Therefore, the embodiments are not subject to other limitations except those made according to the appended claims and their equivalent replacements. In addition, various modifications and changes can be made within the scope of the protection of the appended claims.
[0069] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not depend on the specific sequence of the steps described herein, the method or process should not be limited to the specific sequence of steps described. As will be understood by those of ordinary skill in the art, other step sequences are also possible. Therefore, the specific sequence of steps set forth in the specification should not be construed as a limitation on the claims. In addition, the claims directed to the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can easily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.
Claims
1. A jitter adjustment circuit for a phase interpolator, characterized in that, Comprising: A phase interpolation controller, a rate converter, a phase accumulator, a phase interpolator, a first frequency divider, and a second frequency divider, wherein: The phase interpolation controller is configured to, whenever receiving a clock signal divided by the first frequency divider, determine an offset step increment P of the current offset step update period according to the clock signal and send it to the rate converter; The rate converter is configured to determine an offset sub-step increment p of each offset step update sub-period according to the offset step increment P received from the phase interpolation controller, the number of periods of offset step update, and the number of pre-specified offset step update sub-periods; and is further configured to, whenever receiving a clock signal divided by the second frequency divider, send the offset sub-step increment of the current offset step update sub-period to the phase accumulator; The phase accumulator is configured to perform an accumulation calculation on the offset sub-step increment of the current offset step update sub-period sent by the rate converter and the offset sub-step of the historical offset step update sub-period to obtain a new offset sub-step of the current offset step update sub-period; and is further configured to, whenever receiving a clock signal divided by the second frequency divider, send the offset sub-step of the current offset step update sub-period to the phase interpolator; The phase interpolator is configured to receive a phase-locked loop clock signal, perform a step offset on the phase-locked loop clock signal according to the offset sub-step of the current offset step update sub-period sent by the phase accumulator, and output the clock signal.
2. The jitter adjustment circuit of the phase interpolator according to claim 1, wherein The first frequency divider is an n-frequency divider, where n = the number of periods of offset step update; The second frequency divider is an m-frequency divider, where m = the number of offset step update sub-periods.
3. The jitter adjustment circuit of the phase interpolator according to claim 2, characterized in that, n is an integer multiple of m.
4. The jitter adjustment circuit of the phase interpolator according to claim 3, characterized in that, When P*m is divisible by n, the offset sub-step increment p of each offset step update sub-period is P*m / n.
5. The jitter adjustment circuit of the phase interpolator according to claim 3, wherein When P*m cannot be divided evenly by n, the offset sub-step increment p for each offset step update sub-period is or where the sum of the offset sub-step increments for all offset step update sub-periods in an offset step update period is P.
6. A jitter adjustment method for a phase interpolator, characterized in that, A jitter adjustment circuit applied to a phase interpolator, the method comprising: Whenever receiving a clock signal divided by the first frequency divider, the phase interpolation controller determines an offset step increment P of the current offset step update period according to the clock signal and sends it to the rate converter; The rate converter determines an offset sub-step increment p of each offset step update sub-period according to the offset step increment P received from the phase interpolation controller, the number of periods of offset step update, and the number of pre-specified offset step update sub-periods; and is further configured to, whenever receiving a clock signal divided by the second frequency divider, send the offset sub-step increment of the current offset step update sub-period to the phase accumulator; The phase accumulator performs an accumulation calculation on the offset sub-step increment of the current offset step update sub-period sent by the rate converter and the offset sub-step of the historical offset step update sub-period to obtain a new offset sub-step of the current offset step update sub-period; and is further configured to, whenever receiving a clock signal divided by the second frequency divider, send the offset sub-step of the current offset step update sub-period to the phase interpolator; The phase interpolator receives the phase-locked loop clock signal, updates the offset sub-step of the sub-cycle according to the current offset step sent by the phase accumulator, performs step offset on the phase-locked loop clock signal, and outputs the clock signal.
7. The dithering adjustment method according to claim 6, wherein The first frequency divider is an n-frequency divider, where n = the number of cycles for offset step update; The second frequency divider is an m-frequency divider, where m = the number of sub-cycles for offset step update.
8. The jitter adjustment method according to claim 7, characterized in that, n is an integer multiple of m.
9. The jitter adjustment method according to claim 8, wherein When P*m can be divided evenly by n, the offset sub-step increment p for each offset step update sub-cycle is P*m / n.
10. The dithering adjustment method according to claim 8, wherein When P*m cannot be divided evenly by n, the offset sub-step increment p for each offset step update sub-period is or where the sum of the offset sub-step increments for all offset step update sub-periods in an offset step update period is P.
Citation Information
Patent Citations
Fractional frequency division ratio phase-locked loop
CN113783568A
Fractional frequency clock divider with direct division
US20180097523A1