Semiconductor growth-anneal cycle

Abstract

A method of manufacturing a semiconductor device includes providing a substrate, performing a growth process to form a semiconductor layer supported by the substrate, performing an anneal of the semiconductor layer, wherein the anneal is performed at a higher temperature than the growth process, and repeating the growth process and the anneal. The anneal is performed at or greater than a decomposition temperature of the semiconductor layer.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit of U.S. Provisional Application entitled “Semiconductor Growth-Anneal Cycling” assigned serial number 62 / 992,246, filed March 20, 2020, the entire disclosure of which is expressly incorporated herein by reference.

[0003] Statement Regarding Federally Sponsored Research or Development

[0004] This invention was made with government support under Contract No. W911NF-17-1-0109 awarded by the U.S. Army Research Office (ARO). The government has certain rights in the invention.

[0005] BACKGROUND TECHNICAL FIELD

[0006] The present disclosure relates generally to semiconductor devices. BACKGROUND

[0007] High-quality aluminum nitride (AlN) epitaxially grown on sapphire substrates can be used for a wide range of applications, including, for example, mid-ultraviolet (UV) optoelectronics and deep-UV optoelectronics and high-power / frequency electronics. Also, AlN on sapphire has a wide bandgap and transparency down to wavelengths of about 0.2 pm, which has emerged as a useful material for integrating UV, visible, and quantum photonics, enabling a wide range of classical / non-classical applications in photonics. Moreover, for high-power photonics applications, ultra-wide bandgap materials such as AlN can be used to avoid nonlinear absorption.

[0008] The quality of AlN on sapphire is severely limited by a large density of defects and dislocations and undesirable impurity incorporation (e.g., carbon and oxygen). In the past, methods for growing AlN on sapphire, primarily by metal-organic chemical vapor deposition (MOCVD), involved the use of relatively thick buffer layers and techniques such as lateral epitaxial overgrowth and patterned substrates to reduce the formation of dislocations and obtain usable AlN epitaxial templates. Unfortunately, however, many applications, such as AlN waveguides and micro-ring resonators that operate in the UV spectrum, use very thin AlN epitaxial layers.

[0009] AlN has been deposited on sapphire using a sputtering method. The use of ultra-high temperature annealing significantly improved the quality of the sputtered AlN layers. However, such high-temperature annealing can deteriorate the surface morphology and negatively affect dopant distribution in optoelectronic and electronic devices. SUMMARY

[0010] According to one aspect of the disclosure, a method of manufacturing a semiconductor device includes providing a substrate, performing a growth process to form a semiconductor layer supported by the substrate, conducting an anneal of the semiconductor layer, where the anneal is performed at a higher temperature than the growth process, and repeating the growth process and the anneal. The anneal is performed at or greater than a decomposition temperature of the semiconductor layer.

[0011] According to another aspect of the disclosure, a method of manufacturing a semiconductor device includes providing a substrate, performing a growth process to form a semiconductor layer on the substrate, conducting an anneal of the semiconductor layer, where the anneal is performed at a higher temperature than the growth process, and repeating the growth process and the anneal. The anneal is performed at a temperature at which the semiconductor layer decomposes.

[0012] According to yet another aspect of the disclosure, a method of manufacturing a semiconductor device includes providing a substrate, performing an epitaxial growth process to form a semiconductor layer on the substrate, conducting an anneal of the semiconductor layer, where the anneal is performed at a higher temperature than the epitaxial growth process, and repeating the epitaxial growth process and the anneal for a plurality of cycles. The anneal is performed at a temperature at which the semiconductor layer decomposes.

[0013] In conjunction with any of the preceding aspects, the methods described herein can alternatively or additionally include or involve any combination of one or more of the following aspects or features. Repeating the growth process and the anneal includes repeating the growth process and the anneal for a plurality of cycles. The growth process and the anneal are performed without exposing the semiconductor layer to ambient conditions between the growth process and the anneal. The anneal is conducted in a growth chamber in which the growth process is performed. The growth process and the anneal are performed in different chambers. The method further includes performing an additional growth process to further form the semiconductor layer after repeating the growth process and the anneal. The additional growth process is performed under metal-rich conditions. The anneal is conducted in a plasma environment of the growth process. The growth process is performed and the anneal is conducted in a growth chamber under nitrogen-rich conditions. The growth process includes an epitaxial growth process. Performing the growth process includes growing the semiconductor layer directly on the substrate. The substrate has a uniform composition that is different than the semiconductor layer. The semiconductor layer includes aluminum nitride. The substrate includes sapphire. The semiconductor layer includes a III-V semiconductor material. Conducting the anneal includes gradually increasing a temperature of the growth chamber. The anneal is conducted at a temperature that is greater than 50% higher than the epitaxial growth process. The semiconductor layer and the substrate have a lattice mismatch. The method further includes depositing a cap layer on the semiconductor layer after performing the growth process and before conducting the anneal. The cap layer includes aluminum oxide. BRIEF DESCRIPTION OF DRAWINGS

[0014] For a more complete understanding of the present disclosure, reference is made to the following detailed description and accompanying drawings that are deemed to be a part of this application, and in which like numerals designate like elements in the several figures as follows.

[0015] Figure 1The diagram and image depict a cross-sectional view of a semiconductor device having a semiconductor layer grown using a growth-annealing cycle, based on an example.

[0016] Figure 2 A more detailed description Figure 1 Images of the semiconductor layer, as well as graphical representations of the strain distribution and strain profile of the semiconductor layer.

[0017] Figure 3 describe Figure 1 The graph shows the intensity curve and linewidth of the reflection from the semiconductor layer.

[0018] Figure 4 Description as Figure 1 A graph showing the integral intensity of the semiconductor layer as a function of temperature and wavelength, and Figure 1 Graphical charts of the emission spectra of the semiconductor layer at various temperatures.

[0019] Figure 5 A more detailed description Figure 1 Other images of the semiconductor layer, and Figure 1 The semiconductor layer exhibits spectral and [other properties] at room temperature and low temperature. Figure 1 A graphical representation of the strength of the semiconductor layer compared to a commercially available template.

[0020] Figure 6 This is a flowchart illustrating a method for manufacturing a semiconductor device using a growth-annealing cycle to grow a semiconductor layer, based on an example.

[0021] Implementations of the disclosed method can take various forms. Specific embodiments are shown in the accompanying drawings and described below; it should be understood that this disclosure is illustrative. This disclosure is not intended to limit the invention to the specific embodiments described and shown herein. Detailed Implementation

[0022] Methods of fabricating devices are described in which a semiconductor layer is formed by a combination (e.g., repetition) of growth and annealing processes. Repetition of the growth and annealing processes provides a method for eliminating, minimizing, or otherwise reducing defect and dislocation formation in the semiconductor layer. As described herein, a growth process (e.g., an epitaxial growth process) and annealing (e.g., multiple cycles) are repeated. The annealing can or can not be performed in a growth chamber in which the epitaxial growth process or other growth process is performed or otherwise without exposing the semiconductor layer to ambient conditions between the growth process and the annealing. Thus, in some cases, the disclosed methods can cycle between growth and annealing without exposure to the surrounding environment. Accordingly, ultra-thin semiconductor layers (e.g., films) can be grown by molecular beam epitaxy using an in-situ high-temperature annealing method. In some cases, the semiconductor layer can be or include an aluminum nitride (AIN) layer (e.g., an epitaxial layer) grown (e.g., directly grown) on a sapphire substrate.

[0023] The annealing is performed at a temperature higher than the epitaxial growth process or other growth process. For example, the annealing is performed at or above a decomposition temperature of the semiconductor layer. Thus, in some cases, the annealing is performed at a temperature at which decomposition of the semiconductor layer occurs. In other cases, the annealing can not result in decomposition of the semiconductor layer despite being performed at or above the decomposition temperature due to, for example, the presence of a cap layer or other layer. The decomposition temperature can vary, for example, depending on the composition of the semiconductor layer and the annealing conditions (e.g., overpressure).

[0024] Decomposition of the semiconductor material (e.g., AIN) of the growing semiconductor layer involves breaking chemical bonds of the semiconductor to produce constituent elements (e.g., Al and N). The constituent elements can then desorb from the surface, causing the film or layer to thin during the growing process. The decomposition temperature and decomposition rate can vary in common with the strength of the bonds of the growing semiconductor. The annealing temperature of the disclosed methods can vary accordingly. In some cases, the annealing temperature is selected to be high enough to promote crystallization or recrystallization of the semiconductor material (which involves breaking and reforming bonds) but not so high that there is excessive bond breaking such that the entire film or layer being grown is completely decomposed. Thus, the annealing temperature can be optimized for a given semiconductor material and desired growth rate.

[0025] Using the disclosed methods, high quality (e.g., strain-free) ultrathin semiconductor layers have been grown despite lattice mismatch between the substrate and the semiconductor layer. As described herein, transmission electron microscopy analysis shows that AlN epitaxial layers formed via the disclosed methods are strain relaxed within the first nanometer (nm), thus growing close to strain-free. The number of dislocations generated at the AlN / sapphire interface is reduced within the first 50 nm of growth. An example of an approximately 100 nm thick epitaxial film grown directly on sapphire shows X-ray diffraction (XRD) (002) and (102) rocking curve peaks with full width at half maximum (FWHM) of less than 150 and 1400 arcsec, respectively, which are the narrowest linewidths reported for AlN of this thickness. Photoluminescence analysis further shows that such AlN epitaxial layers exhibit relatively high luminescence efficiency and strong near-band-edge emission without defect-related transitions.

[0026] While described in connection with formation of AlN buffer layers on sapphire substrates, the disclosed methods can be used to form a wide variety of semiconductor layers. For example, the disclosed methods can be used to form active and other layers in a wide variety of types of devices. The positioning, function, and other characteristics of the layers can vary accordingly from the examples described herein. The disclosed methods can be used to form other compound semiconductors such as III-nitride semiconductors (e.g., AlGaN), other III-V semiconductors, II-VI semiconductors, and oxide semiconductors. The annealing of the disclosed methods can vary accordingly. For example, the annealing of non-nitride III-V semiconductors can be performed at a corresponding Group V flux rather than in a nitrogen environment formed via a nitrogen plasma and / or ammonia gas. The semiconductor layers can be formed on other substrates. For example, substrates having a composition of or otherwise including Si, SiC, Ga2O3, diamond, highly oriented pyrolytic graphite (HOPG), GaAs, InP, and GaSb can also be used.

[0027] The properties of semiconductor devices fabricated via the disclosed methods can vary. The semiconductor devices can be or otherwise include high efficiency and high power deep UV light emitting diodes (LEDs) and laser diodes. Other types of optoelectronic devices and / or high power / frequency electronic devices can be fabricated. Alternatively or additionally, the semiconductor devices can be configured for applications involving a wide range of wavelengths, including but not limited to the UV and visible light bands. The semiconductor devices can be configured for various applications implementing quantum photonics, including a wide range of classical and non-classical applications in photonics such as high power photonics applications. Thus, the properties of the semiconductor devices can vary significantly.

[0028] Molecular beam epitaxy (MBE) can be used for the epitaxy of III-V and other semiconductors such as AlN and Al-rich AlGaN. For example, MBE provides more controlled nucleation and Al incorporation, efficient Mg dopant activation, and reduced impurity incorporation. However, high-quality AlN epitaxial layers by MBE have been lacking in the past, primarily due to the limited growth temperatures of conventional systems. Recent advances in MBE substrate heater technology and reports of growth of high-temperature materials such as boron nitride (BN) can be used to overcome these challenges.

[0029] As described herein, molecular beam epitaxy can be used to directly form high-quality ultrathin AlN epitaxial layers on sapphire. For this purpose, the disclosed methods can use multiple cycles in an in-situ high-temperature anneal. By using in-situ high-temperature annealing, dislocation density is significantly reduced. In one example of AlN directly grown on sapphire with a thickness of about 0.1 μιη, the (002) line width measured with X-ray diffraction (XRD) is less than 150 arcsec, which is comparable or better than epitaxial layers grown directly on AlN substrates. Using in-situ high-temperature annealing, the (102) line width is significantly reduced from more than 4000 arcsec to less than 1400 arcsec. Detailed temperature-dependent photoluminescence (PL) measurements show a luminescence efficiency of about 30% measured at room temperature. Detailed scanning transmission electron microscopy (STEM) indicates that propagation of dislocations is substantially suppressed in the thin AlN epitaxial layers grown directly on sapphire, and that the AlN layers are grown completely strain relaxed. Substantially improved results are also measured for AlN epitaxial layers with increased thickness.

[0030] Figure 1 A method 100 of fabricating a semiconductor device according to an example of growing an AlN layer on a c-plane sapphire substrate is schematically described. Alternative or additional semiconductor layers can be grown. Other substrates can be used. In some cases, the method can use a plasma-assisted MBE system such as a Veeco GENxplor radio frequency (RF) nitrogen plasma-assisted MBE system. The MBE system can be equipped with an Al effusion source such as an Al SUMO effusion source and a substrate heater such as a NOVA ultra-high temperature substrate heater (e.g., heated to 1850 °C). In this case, the sapphire wafer backside is metallized with molybdenum to allow efficient heat conduction in vacuum.

[0031] Figure 1 A schematic diagram depicting a sequence of growth of AlN on a sapphire substrate is included in part (a). In this example, the sequence of growth includes a stage I of initial AlN buffer growth using a modified migration enhanced epitaxy (MEE) method, a stage II of high-temperature annealing of the grown ultrathin film, a stage III of repeating the growth and annealing steps to improve the buffer layer quality, and a stage IV of epitaxy of a high-quality AlN epitaxial layer using an interrupt-assisted method.Figure 1 It also includes section (b), which describes a photograph of the RHEED pattern observed during growth. In this example, the RHEED pattern includes (I) dotted and segmented patterns during the initial stage of growth, (II) striped patterns during the buffer stage, (III) broadened and brighter patterns during the annealing stage, and (IV) narrow striped patterns during the epitaxial layer growth stage.

[0032] As in Figure 1 As illustrated in part (a), stage I of method 100 includes growing a buffer (or other) layer using, for example, a modified migration-enhanced epitaxy (MEE) method to promote AlN nucleation and smooth the interface directly over lattice-mismatched sapphire. In this example, the layer has a thickness of approximately 80 nm, but other thicknesses can be used. The growth temperature can be approximately 950 °C. An 8 × 10⁸ nm beam equivalent pressure (BEP) can be used. -8 The Al flux and the low nitrogen flux of 0.3 sccm at a constant RF plasma forward power of 350 W are parameters that correspond to slightly nitrogen-rich conditions at this growth temperature.

[0033] In one instance, stage I could have the following shutter sequence: 1 minute of Al (i.e., forced metal-rich surface coverage), followed by four minutes of Al and N (e.g., approximately stoichiometric AlN growth on a thin liquid-metal surface). This can be achieved by monitoring... Figure 1 The reflective high-energy electron diffraction (RHEED) pattern 102 shown in part (b) can be used to determine the opening and closing sequence.

[0034] like Figure 1 As shown in section (b), in the first minute of growth, the RHEED pattern 102 becomes segmented and dotted (pattern I) due to lattice mismatch nucleation, but quickly begins to revert to a striped pattern, representing two-dimensional epitaxial growth within the third modulation loop. The RHEED pattern 102 is striped (pattern II) at the end of this first or initial buffer stage.

[0035] After the initial growth phase, stage II of the method 100 includes gradually ramping up the substrate temperature. In one example, the temperature of the chamber (and thus the substrate) is ramped up to about 1550 °C. Thus, this example is annealed in situ for 30 minutes, for example, under the same nitrogen plasma environment. This annealing step can be used to promote recrystallization of the buffer layer and to obtain significantly higher quality AlN epitaxial layers at later stages of growth. During this high temperature annealing process, there can be decomposition of the AlN buffer even in the presence of the nitrogen plasma and RHEED patterns are seen to broaden (pattern III). Higher annealing temperatures promote recrystallization, contributing to superior material properties, but can increase decomposition and coarsening of the grown film.

[0036] Other annealing temperatures and durations can be used. For example, the annealing temperature can fall within the following ranges: about 650 degrees Celsius to about 850 degrees Celsius for GaAs grown on Si, about 850 degrees Celsius to about 1000 degrees Celsius for GaN grown on AlN or sapphire, and about 1000 degrees Celsius to about 1400 degrees Celsius for AlGaN grown on sapphire (depending on the Al composition). The duration of the annealing can vary accordingly.

[0037] The rate of decomposition can increase as the annealing temperature is increased. Thus, the growth and decomposition rates can be adjusted. For example, the annealing temperature and / or other annealing conditions (e.g., overpressure) can be adjusted to ensure that the annealing step does not completely decompose the grown film. Alternatively or additionally, the decomposition can be controlled by a nitrogen overpressure and / or other overpressure. Such a nitrogen overpressure or other overpressure can bombard the surface of the semiconductor layer with nitrogen, which can lead to reformation of broken semiconductor (e.g., AlN) bonds due to the annealing temperature. Thus, the rate of decomposition can be reduced or otherwise controlled.

[0038] The annealing temperature can be selected to achieve a desired rate of decomposition. In an example involving growth of AlN in vacuum (i.e., without a nitrogen overpressure), decomposition begins at approximately 1200 °C. In one test, at annealing temperatures less than 1400 °C, the decomposition was negligible. The rate of decomposition increases superlinearly with increasing temperature. For example, at annealing temperatures of 1450 °C, 1550 °C, and 1600 °C, decomposition rates of about 30 nanometers per hour (nm / h), about 120 nm / h, about 180-200 nm / h, respectively, were achieved. At temperatures greater than about 1600 °C, the rate of decomposition was difficult to measure due to significant coarsening of the surface of the semiconductor layer.

[0039] In some cases, each growth / annealing cycle results in at least about 10 nm of AlN buffer layer thickness remaining. This effect is shown in a STEM image of an AlN film cross-section of Figure 2 When growth is resumed after the annealing phase, the RHEED pattern 102 (Fig. 1) is restored. The RHEED pattern 102 is shown in Fig. 1 as a series of lines, but can include other patterns, such as a series of dots. The RHEED pattern 102 can be used to monitor the quality of the grown film. For example, the RHEED pattern 102 can be used to determine whether the film is coarsened or decomposed. The RHEED pattern 102 can be used to determine whether the film is coarsened or decomposed. For example, if the RHEED pattern 102 is a series of lines, the film can be coarsened. If the RHEED pattern 102 is a series of dots, the film can be decomposed. Figure 1It shows an inverted V-shaped sawtooth feature consistent with the facets already formed on the surface.

[0040] Repeated stages I (growth) and II (annealing) are used to improve the quality of the AlN template or layer. For example, after three such cycles, the thickness of the AlN buffer layer is approximately 30 nm. Additional or fewer cycles can be used. For instance, a test involving additional cycles yielded similar results to those using three cycles of growth / annealing.

[0041] The cycle can end with the growth of the final buffer layer (Stage III). The final buffer layer can be grown in a manner similar to Stage I and / or in different ways, such as under different growth conditions. Therefore, the growth conditions can be varied depending on, for example, the layer composition and / or other aspects. This stage can be configured to help restore and smooth faceted surfaces.

[0042] exist Figure 1 In one example, method 100 includes an additional growth step to form the remainder of the AlN layer (stage IV). In some cases, the remainder can be grown with parameters unchanged from the previous growth step. In other cases, the growth conditions can be directed to near-stoichiometric growth conditions. Alternatively or additionally, the metal (e.g., Al) flux is increased (e.g., to 1.1 × 10⁻⁶). -7 (e.g., slightly metal-rich conditions) can be used to transition the growth to metal-rich conditions. Periodic interruptions of the source-metal flux can aid this process, maintaining the striped RHEED pattern (pattern IV) without excessive Al accumulation. Under these conditions, a growth rate of approximately 180 nm / hour is achieved. Using this growth process, instances with AlN thicknesses varying between 0.1 and 1 μm can be achieved by adjusting the duration of this final stage of growth.

[0043] The final stage of growth can be optional. For example, method 100 can be implemented without a final stage of growth to form a thinner semiconductor layer. Obtaining high crystallinity quality for such thin semiconductor layers using existing methods has always been the most challenging aspect.

[0044] The bulk structural properties of several example semiconductor layers grown according to the disclosed methods were characterized by electron microscopy and XRD. For example, an example of a thin AlN grown directly on sapphire was investigated using a FEI Titan Cubed 80-300 STEM equipped with CEOS correctors on both the probe and imaging lens systems and operating at an acceleration voltage of 200 kV. The local lattice parameter distribution in the structure was investigated using point-probe analysis (PPA) software. A transparent electron specimen of AlN / sapphire was prepared by focused ion beam (FIB) for STEM analysis using a Zeiss NVis ion 40 dual beam instrument operating at 30 keV.

[0045] Figure 2 Part (a) is included, where a STEM cross-sectional image is shown. Yellow arrows are drawn to indicate the growth direction. Figure 2 Part (b) is also included, where a high magnification STEM image of the AlN and sapphire interface is depicted. The atomic step height mismatch at the interface is highlighted by the arrows. Figure 2 Part (c) is also included, a plot of the εxx strain distribution obtained during analysis (in a direction contained within the growth plane), where the strain values (taking sapphire as the zero reference) are in the included color scale bar. Figure 2 Part (d) is also included, where a strain profile along the strain distribution plot in part (c) indicated by the arrows is depicted.

[0046] Figure 2 Part (a) of FIG. 6 shows a STEM image in cross-section taken under moderate angle conditions to more prominently reveal defects in the example. The two layers of the structure are marked with white arrows. The AlN layer thickness was measured to be about 100 nm. Thread dislocations (TDs) that pass through the AlN layer appear to be present in the image. This type of defect can release strain at interfaces with high lattice mismatch, as in the case of AlN / sapphire. From this STEM image, then, a large number of initially formed TDs are terminated and stop propagating within the first 50 nm of growth, consistent with the initial buffer layers before and after multiple in-situ annealing cycles. In contrast to this, in previous reports, buffer layers of several hundred nanometers were used to obtain the desired top layer, and the majority of dislocations generated in these layers propagated all the way to the surface. Another notable finding of these examples is the presence of orientation errors in the AlN film, which are directly due to small misalignments (less than 1 degree) caused by steps on the sapphire surface. These observations reveal the impact of the substrate surface on the epitaxial layer, and that precise control of the initial interface can be used to grow high quality AlN.

[0047] Figure 2Part (b) of Figure 1 shows a high magnification STEM image of the interface between the AlN layer and the sapphire substrate. The brighter spots seen in the example are due to contamination / redeposition from the FIB example preparation process. The interface between the two materials is very smooth, but atomic steps can be observed, for example the step marked with an arrow. To obtain quantitative information about the local atomic dislocations in the AlN layer compared to the sapphire substrate (area of reference), the PPA is applied to part (b) of Figure 1. Figure 2 The PPA is applied to part (b) of Figure 1. Figure 2 Part (c) of Figure 1 presents the map of the (defined with respect to the reference plane) exx strain obtained during the analysis (in the direction contained in the growth plane). Given the values close to zero (as the sapphire substrate is taken as reference), no significant strain variation is observed in the sapphire substrate. However, a clear variation of the lattice parameter can be observed in the AlN layer. Based on the strain map along the Figure 3 The profile plotted in part (d) of Figure 1, the apparent "strain" value, i.e. the difference compared to the reference sapphire, is measured to be 13.1 ± 0.2%. This value is consistent with the expected lattice mismatch between AlN and sapphire (13.3%), indicating that the AlN layer is grown almost completely relaxed, as it is extremely close to maintaining its bulk lattice parameter.

[0048] Figure 3 Parts (a) and (b) are included to respectively describe the XRD rocking curves (shown in solid line) of the symmetric reflection (002) and asymmetric reflection (102) of the AlN layer grown on a sapphire substrate. The dashed curves are Lorentzian fits of each curve, used to obtain the FWHM of 126 arcsec and 1387 arcsec for parts (a) and (b) respectively. Figure 3 Part (c) is also included, where a comparison of the AlN XRD (002) rocking curve linewidth is presented, previously reported in the literature and the present disclosure (red).

[0049] XRD analysis was performed using a Rigaku SmartLab X-ray diffractometer, with a Ge (220) two-fold reflection monochromator aligned for thin film rocking curve analysis. For the example with a thickness of about 100 nm, the XRD (002) rocking curve was measured at a constant angle of incidence of 0.5°. Figure 3 Part (a) of Figure 1 shows the measured XRD (002) rocking curve. Based on the Lorentzian fit, its full width at half maximum (FWHM) is 126 arcsec. Figure 3 The Lorentzian fit of the curve of part (b) of Figure 1, the (102) linewidth (FWHM) is 1387 arcsec. As Figure 4highlighted in part (c) of the disclosure, these are the narrowest linewidths reported for fairly thick AlN epitaxial layers grown by any technique. In contrast, for instances grown at similar thickness but without multiple cycles in the in-situ annealing step, the (102) linewidth is greater than 4000 arcsec. Higher annealing temperatures can help to achieve narrower linewidths, up to a limit beyond which (002) linewidth degradation and surface becoming increasingly difficult to recover are observed. These observations are consistent with the fact that (102) FWHM will become narrower with overall reduced threading dislocation density, especially edge dislocations, while (002) linewidth is sensitive to screw dislocations, which will remain regardless of subsequent epitaxial or other growth processes.

[0050] Figure 4 Part (a) of the disclosure includes, where the normalized temperature dependence of the integrated PL intensity of an AlN instance is described. The inset shows the emission spectrum at constant excitation power at various temperatures. Figure 4 Part (b) of the disclosure is also included, where a comparison of the PL intensity of the same instance (402) and a commercial AlN epitaxial template (404) that is about 10 times thicker is presented. The inset shows an estimated internal quantum efficiency (IQE) of about 30% for the instance.

[0051] The optical properties of thin AlN epitaxial layers (e.g., about 100 nm thickness) grown directly on sapphire were characterized by variable excitation power and temperature dependent photoluminescence (PL) spectroscopy using a 193 nm ArF excimer laser as the excitation source. The instance emission was spectrally resolved by a Horiba iHR550 spectrometer and a UV-sensitive Symphony II CCD detector. At low temperature, the excitonic emission of AlN at about 205 nm is accompanied by a lower energy shoulder emission, which can be attributed to its longitudinal optical (LO) phonon sideband, as shown in the inset of part (a) of the disclosure. As the temperature is increased, the emission intensity decreases and the emission peak redshifts to about 208 nm. Figure 4 Part (a) of the disclosure shows the temperature dependence of the integrated PL intensity. As seen in the inset of part (a) of the disclosure, the excitonic emission is accompanied by a lower energy shoulder emission, which can be attributed to its longitudinal optical (LO) phonon sideband. Figure 4 Part (a) of the disclosure shows the temperature dependence of the integrated PL intensity. As seen in the inset of part (a) of the disclosure, the excitonic emission is accompanied by a lower energy shoulder emission, which can be attributed to its longitudinal optical (LO) phonon sideband. Figure 4 As seen in the inset of part (b) of the disclosure, assuming near unit quantum efficiency at low temperature, an estimated internal quantum efficiency (IQE) of about 30% is obtained by taking the ratio of the integrated PL intensity at room temperature and at low temperature. The droop can be due to heating and other non-ideal effects under high laser excitation conditions. For comparison, as shown in part (b) of the disclosure, the near-band-edge PL emission of this instance (402) is almost twice as strong as that of a commercial AlN epitaxial template (404; DOWA Electronics Materials Co., Ltd.) that is about 10 times thicker. Figure 1 Part (b) of the disclosure shows the near-band-edge PL emission of this instance (402) is almost twice as strong as that of a commercial AlN epitaxial template (404; DOWA Electronics Materials Co., Ltd.) that is about 10 times thicker.

[0052] The optical properties of thin AlN epitaxial layers (e.g., about 100 nm thickness) grown directly on sapphire were characterized by variable excitation power and temperature dependent photoluminescence (PL) spectroscopy using a 193 nm ArF excimer laser as the excitation source. The instance emission was spectrally resolved by a Horiba iHR550 spectrometer and a UV-sensitive Symphony II CCD detector. At low temperature, the excitonic emission of AlN at about 205 nm is accompanied by a lower energy shoulder emission, which can be attributed to its longitudinal optical (LO) phonon sideband, as shown in the inset of part (a) of the disclosure. As the temperature is increased, the emission intensity decreases and the emission peak redshifts to about 208 nm.Figure 5 In stage IV, AlN epitaxial layers and other semiconductor layers of various thicknesses can be formed.

[0053] Figure 5 The description section (a) shows a 1 μm thick example, with a low-magnification SEM image of the example surface. Intentional scratch marks are provided in the upper left corner to properly focus on the example surface. Optical images are included as insets. Figure 5 Part (b) presents a high-magnification AFM image of the surface topology of the example. Figure 5 It also includes section (c), which describes the PL spectra of examples at room temperature (300K) and low temperature (20K). Figure 4 It also includes part (d), which presents the same instance 402 ( Figure 4 ) and commercial AlN epitaxial template 404 ( Figure 5 Comparison of PL strength.

[0054] For an example with a thickness of 1 μm, the (002) and (102) X-ray rocking curve peaks have FWHM values ​​of approximately 60 arcseconds and 1050 arcseconds, respectively. Using a Hitachi SU8000 scanning electron microscope (SEM), the surface of this example was... Figure 5 In part (a), a uniform and smooth surface is visible, without the bumps or cracks typically seen after the growth of lattice mismatch layers due to strain. This also applies across the entire wafer scale, as verified by optical microscopy, including images as insets. A 1×1 μm wafer was obtained using a Bruker Dimens ion Icon atomic force microscope (AFM) in tapping mode in air. 2 Surface topology ( Figure 5 Part (b)). The observed mesa has atomic steps corresponding to the top epitaxial monolayer that was not fully formed at the end of growth. The 60 root mean square (RMS) roughness is approximately 0.3 nm.

[0055] exist Figure 5 Part (c) shows the PL spectra at room temperature and low temperature. The PL intensity is approximately 20 times stronger than that of a similar 1 μm thick commercial AlN epitaxial template. Figure 6 (b)). Further improvements in material quality are expected with finer surface treatment methods on sapphire substrates.

[0056] ​A method 600 of fabricating a semiconductor device is described according to one example. The method 600 can be used to fabricate any type of semiconductor device described herein or another type of semiconductor device. The method 600 can include additional, fewer, or alternative acts. For example, the method 600 can or can not include one or more acts directed to preparing a substrate for further processing.

[0057] The method 600 can begin with an act 602 of providing a substrate. The substrate can be or be formed from a sapphire wafer. Other substrates can be used. Providing the substrate can include preparing the substrate in act 604. For example, the preparation can include one or more cleaning processes. Alternatively or additionally, the act 604 can include one or more doping processes. Providing the substrate can include processing a surface of the substrate in act 606. For example, the substrate surface can be smoothed or otherwise processed to facilitate epitaxial growth thereon.

[0058] In some cases, the preparation of the substrate can include deposition or other formation of one or more layers (e.g., metal layers) on either side (e.g., the backside) of the substrate. The function(s) of the layer(s) can vary. As described above, in some cases, a metal layer can be deposited to allow for efficient heat conduction in a vacuum. For example, molybdenum and / or other efficient heat conductors can be deposited. The manner of forming the layers can vary.

[0059] In act 610, a growth process is implemented to form a semiconductor layer on the substrate (e.g., directly on the substrate) or to otherwise form a semiconductor layer supported by the substrate. In some cases, the growth process is or otherwise includes an epitaxial growth process. Alternatively or additionally, the growth process is or includes a non-epitaxial growth process such as a pulsed laser deposition process. In non-epitaxial cases, the growth can not include or involve crystal or lattice formation. In such cases, crystallization or other lattice formation occurs subsequently during annealing.

[0060] In some cases, an epitaxial or other growth process is implemented and annealing is performed in act 612 in which growth occurs under nitrogen-rich conditions. In epitaxial cases, the act 610 can include implementing a migration enhanced epitaxy (MEE) process (act 614). The semiconductor layer can include aluminum nitride, although other semiconductors can be grown.

[0061] The semiconductor layer can be configured as a buffer layer or other layer. The buffer layer can be grown directly on the substrate. In such cases, there is no intervening layer or other intermediary between the semiconductor layer and the substrate despite a lattice mismatch between the semiconductor layer and the substrate. For example, the buffer layer can be composed of or otherwise include AlN grown on a sapphire substrate or other substrate of a uniform composition different from the semiconductor layer. The semiconductor layer and the substrate can or can not have a lattice mismatch as described herein.

[0062] In some cases, operation 610 includes depositing or otherwise forming a cap layer (or capping layer) and / or other layers in operation 616. The cap layer can be deposited, grown, or otherwise formed on the semiconductor layer being grown in operation 610 to provide a barrier layer and / or to act as a sacrificial layer in subsequent processing, such as the annealing process described below. For example, the cap layer can protect the semiconductor layer during annealing. The protection can include or involve preventing evaporation. Accordingly, the semiconductor layer can reach the temperature at which deformation occurs (e.g., greater than the decomposition temperature) without significant material loss.

[0063] The cap layer can have a composition or be otherwise configured to withstand the high temperature environment of the anneal. However, the composition and other characteristics of the cap layer can vary. For example, the cap layer can or can not have the same or similar composition as the semiconductor layer being grown in operation 610. In some cases, the cap layer is composed of or otherwise includes aluminum oxide, other oxides, or materials can be used.

[0064] The cap layer can be a thin layer. For example, the cap layer can be thin enough to avoid thermal insulation effects. The cap layer can have a thickness that allows the semiconductor layer to reach the anneal (or other desired) temperature during annealing. In some cases, the cap layer has a thickness falling within a range of about 10 nm to about 20 nm. However, other thicknesses can be used, including thicknesses of up to 100 nm, for example.

[0065] In operation 618, an anneal of the semiconductor layer is performed. In some cases, the anneal is performed in a different chamber than the growth chamber. In operation 619, the device can be moved accordingly to the new chamber. In other cases, the anneal is performed in situ or without exposure to environmental conditions between the growth in operation 610 and the anneal of operation 618. For example, the anneal can be performed in the growth chamber in which the epitaxial growth process is implemented (operation 620). Thus, operations 616 and 618 can be performed in the same chamber. In some cases, the anneal is performed under nitrogen-rich conditions and / or in the plasma environment of the epitaxial growth process (operation 622). In other cases, operations 616 and 618 are performed in multiple chambers that are connected, configured, or otherwise integrated to avoid exposure to environmental conditions.

[0066] The anneal is performed at a higher temperature than the epitaxial growth process. For example, the anneal can include gradually increasing the temperature of the growth chamber (operation 624). In some cases, the temperature can reach greater than 50% higher than the epitaxial growth process.

[0067] The anneal is performed at or above a decomposition temperature of the semiconductor layer. Thus, in some cases, the anneal is performed at a temperature at which decomposition of the semiconductor layer occurs. In other cases, the anneal can not result in decomposition of the semiconductor layer, despite the anneal temperature being at or above the decomposition temperature, due to, for example, the presence of the cap layer and / or other layers.

[0068] The decomposition temperature can vary significantly. For example, the decomposition temperature can vary based on the composition of the semiconductor layer. The decomposition temperature can also vary based on the pressure and / or other conditions of the anneal. For example, for GaAs, decomposition can occur at 600 degrees Celsius in a vacuum. However, GaAs can be stable (i.e., not decompose) at 700 degrees Celsius due to an arsenic overpressure. GaN and AlN can exhibit similar behavior. In a vacuum, GaN can begin to decompose at 900 degrees Celsius, and AlN at greater than 1200 degrees Celsius. However, the decomposition temperature can increase with a nitrogen overpressure.

[0069] In cases where a cap layer is formed to protect the semiconductor layer, the cap layer is removed after the anneal in operation 625. The cap layer can be removed by an etching process, such as a wet etch. The properties of the process can vary depending on the composition of the cap layer.

[0070] In operation 626, the epitaxial growth process and anneal are repeated or cycled. In some cases, the epitaxial growth process and anneal are repeated for a plurality of cycles (operation 628), such as at least three cycles. The repeating or cycling can end with the implementation of a final growth process (operation 630).

[0071] In some cases, the method 100 includes an operation 632 of implementing an additional epitaxial growth process to further form the semiconductor layer after repeating the epitaxial growth process and anneal. The additional epitaxial growth process can be implemented under different conditions than the growth phases of operations 610, 626. For example, the growth can be implemented under metal-rich conditions (operation 634).

[0072] The method 100 can then include an operation 636 of fabricating one or more additional layers or other elements of the semiconductor device. For example, one or more additional semiconductor layers can be grown or otherwise formed to establish, for example, a heterostructure. Alternatively or additionally, one or more metal layers can be deposited or otherwise formed to define contacts, interconnects, or other circuit elements.

[0073] The order in which the operations of the method 600 are implemented can vary in other instances. For example, one or more layers or other elements of the semiconductor device can be formed prior to forming the semiconductor layer described herein.

[0074] The above describes a method of fabrication of AlN (or other semiconductor layer) epitaxial layers grown (e.g., directly grown) on sapphire using a high temperature assisted MBE process. Strain-free ultra-thin AlN epitaxial layers were directly obtained on sapphire by using in-situ high temperature annealing. The optical properties are better than commercial AlN templates, which is consistent with the excellent structural properties of the semiconductor layers grown via the disclosed method.

[0075] The present disclosure has been described with reference to specific examples which are intended to be illustrative, not limiting. Changes, additions and / or deletions can be made to the examples without departing from the spirit and scope of the present disclosure.

[0076] The above description is given for clarity of understanding only and no unnecessary limitations should be understood therefrom as to the scope of the disclosure.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: Provide substrate; Perform a growth process to form a semiconductor layer on the substrate; Annealing of the semiconductor layer is performed, wherein the annealing is carried out at a higher temperature than that of the growth process; and Repeat the growth process and the annealing process; The annealing is performed at the temperature at which the semiconductor layer decomposes. The growth process includes depositing a capping layer on the semiconductor layer after the growth process is completed and before the annealing is performed. The capping layer is configured to prevent decomposition of the semiconductor layer during annealing. The annealing process includes removing the capping layer after the annealing is performed.

2. The method of claim 1, wherein the growth process and the annealing are performed without exposing the semiconductor layer to environmental conditions between the growth process and the annealing.

3. The method of claim 1, wherein repeating the growth process and the annealing includes repeating the growth process and the annealing multiple cycles.

4. The method of claim 1, further comprising performing an additional growth process after repeating the growth process and the annealing to further form the semiconductor layer, wherein the additional growth process is performed under metal-rich conditions.

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