A chip package, an electronic device, and a method for manufacturing a chip package

Abstract

This application provides a chip package, an electronic device, and a method for preparing the chip package, relating to the field of heat dissipation technology for electronic products. The chip package includes: a chip, a composite heat dissipation substrate, and a connection layer. The composite heat dissipation substrate is connected to the passive surface of the chip through the connection layer. The composite heat dissipation substrate includes: multiple diamond sheets and a substrate layer. The multiple diamond sheets are arranged along a surface parallel to the chip and disposed within the substrate layer.

Description

Technical Field

[0001] This application relates to the field of heat dissipation technology for electronic products, and in particular to a chip packaging, electronic device, and a method for preparing the chip packaging. Background Technology

[0002] With the rapid development of semiconductor technology, the number of transistors on semiconductor chips is constantly increasing. High-density transistor integration and increased circuit speed mean that the power per unit of semiconductor chips is also constantly increasing. This increase in power per unit inevitably leads to the generation of more heat in semiconductor chips, which can easily cause electronic devices to overheat. When the temperature of electronic devices is too high, their performance and lifespan will decrease rapidly.

[0003] In the prior art, there is a chip package with heat dissipation function, such as Figure 1 As shown, a metal layer 02 is used to connect chip 01 to a diamond sheet 03. That is, the heat dissipated by chip 01 is conducted to diamond sheet 03 through metal layer 02, and heat is dissipated through diamond with high thermal conductivity (thermal conductivity can reach 2000W / mK at room temperature).

[0004] With the development of System-On-Chip (SOC), the area of ​​multifunctional integrated chips is constantly increasing, which exacerbates the overheating problem of chips. More efficient heat dissipation technology is crucial to ensuring the performance and reliability of multifunctional integrated chips.

[0005] When using Figure 1 When heat dissipation is performed using the diamond wafer shown, a single, integral diamond wafer is typically fabricated using chemical vapor deposition (CVD). This means that for larger chip areas, a larger diamond wafer needs to be fabricated. With current CVD processes, the yield rate of diamond wafer manufacturing decreases as the wafer area increases, leading to a significant increase in cost. Currently, some chip areas already exceed 800 mm². 2 If a single diamond sheet is used to dissipate heat from the chip, the manufacturing cost is quite high, making it difficult to achieve commercial mass production. Summary of the Invention

[0006] The embodiments of this application provide a chip package, an electronic device, and a method for preparing the chip package, the main purpose of which is to reduce manufacturing costs while ensuring the heat dissipation effect of the chip.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In a first aspect, this application provides a chip package, including: a chip, a connection layer and a composite heat dissipation substrate, wherein the passive surface of the chip is connected to the composite heat dissipation substrate through the connection layer, and the composite heat dissipation substrate includes: a plurality of diamond sheets and a substrate layer, wherein the plurality of diamond sheets are arranged along a surface parallel to the chip, and the plurality of diamond sheets are disposed within the substrate layer.

[0009] The chip package provided in this application embodiment includes multiple diamond sheets for heat dissipation, arranged parallel to the chip surface. This allows for the dissipation of heat generated by the chip through multiple diamond sheets. Compared to the prior art using a single, integrated diamond sheet, the chip package provided in this application embodiment uses multiple diamond sheets for heat dissipation. For example, if a 20mm × 20mm square diamond sheet is required for heat dissipation, the prior art would require a single 20mm × 20mm square diamond sheet. However, the solution in this application can use an array of four 10mm × 10mm square diamond sheets, which is expected to reduce costs by more than 50% while still ensuring good heat dissipation. Therefore, the chip package provided in this application embodiment effectively reduces manufacturing costs while ensuring effective heat dissipation.

[0010] In one possible implementation of the first aspect, the composite heat dissipation substrate further includes a thermally conductive layer disposed on the surface of the diamond wafer, with the thermally conductive layers on adjacent diamond wafers connected together. In practical implementation, the temperature of the heat-generating area of ​​the chip is uneven, resulting in different amounts of heat being conducted to the diamond wafers at corresponding locations. This leads to some diamond wafers having higher temperatures and others lower temperatures. By providing a thermally conductive layer, heat can be conducted from the higher-temperature diamond wafers to the lower-temperature diamond wafers, ultimately improving the chip's heat dissipation efficiency.

[0011] In one possible implementation of the first aspect, a thermally conductive layer is disposed on the surface of the diamond wafer that is away from the chip. Disposing of the thermally conductive layer on the surface of the diamond wafer that is away from the chip enables heat conduction between the diamonds.

[0012] In one possible implementation of the first aspect, the surface of the diamond wafer furthest from the chip is flush with the surface of the substrate layer furthest from the chip, and the thermally conductive layer extends to the surface of the substrate layer furthest from the chip. That is, extending the thermally conductive layer to the surface of the substrate layer furthest from the chip simplifies the manufacturing process and enhances the overall strength of the composite heat dissipation substrate. In a practical implementation, this exposed thermally conductive layer dissipates heat to a heat sink located outside the chip package through a thermal interface material layer. In other words, the exposed thermally conductive layer reduces the thermal resistance between the chip package and the thermal interface material layer and heat sink, thereby improving heat dissipation.

[0013] In one possible implementation of the first aspect, the heat-conducting layer is disposed on all surfaces of the diamond sheet except the surface adjacent to the chip. By disposing the heat-conducting layer on all surfaces of the diamond sheet except the surface adjacent to the chip, the contact area between the heat-conducting layer and the diamond sheet is increased, thereby improving the heat transfer efficiency between the two diamond sheets.

[0014] In one possible implementation of the first aspect, the surface of the thermally conductive layer located on the surface of the diamond wafer away from the chip is flush with the surface of the substrate layer away from the chip. In a specific implementation, this exposed thermally conductive layer will contact the heat sink outside the chip package through a thermal interface material layer, reducing the thermal resistance between the chip package and the thermal interface material and heat sink, thereby improving the heat dissipation effect.

[0015] In one possible implementation of the first aspect, the heat-conducting layer is a metal layer. Using a metal layer as the heat-conducting layer is advantageous because metals have high thermal conductivity and are relatively inexpensive to manufacture.

[0016] In one possible implementation of the first aspect, the distance between the opposite sides of two adjacent diamond sheets gradually decreases from the direction away from the chip to the direction closer to the chip. The closer to the chip, the closer the distance between two adjacent diamond sheets, thus enabling rapid heat conduction on the adjacent diamond sheets and improving heat dissipation.

[0017] In one possible implementation of the first aspect, the connecting layer is a silicon-based inorganic material connecting layer, a metal connecting layer, or an organic adhesive connecting layer.

[0018] In one possible implementation of the first aspect, the vertical projection of the chip onto multiple diamond wafers covers portions of the diamond wafers. This allows the heat dissipated by the chip to be diffused to the outside of the entire chip, thereby improving heat dissipation.

[0019] In one possible implementation of the first aspect, a redistribution layer is provided on the active surface of the chip. The redistribution layer is electrically connected to the chip. The vertical projection of the chip onto the redistribution layer covers a portion of the redistribution layer, and the vertical projection of the chip onto the connection layer covers a portion of the connection layer. The uncovered portion of the redistribution layer is connected to the uncovered portion of the connection layer through a fixing layer. Metal bumps are distributed on the surface of the redistribution layer away from the chip, and the metal bumps are electrically connected to the redistribution layer. That is, the redistribution layer extends to the outside of the chip. Compared with the prior art where the outer edge of the redistribution layer is flush with the outer edge of the chip, the distribution area of ​​the metal bumps can be increased, thereby increasing the spacing between each pair of adjacent metal bumps, so that the chip package can be electrically connected to pins with a larger spacing on the circuit board.

[0020] In one possible implementation of the first aspect, a high electron mobility transistor (HEMT) is disposed on the active surface of the chip. A conductive via is formed at the source position of the HEMT, connecting the active and passive surfaces of the chip. Both the interconnect layer and the substrate layer are metal layers, and at least some adjacent diamond sheets have a gap near the interconnect layer. When the source of the HEMT needs to be grounded, a conductive via is formed on the chip, and the interconnect layer and substrate layer are metal layers, with a gap at least some adjacent diamond sheets near the interconnect layer. This gap forms a metal grounding trench, thereby grounding the source of the HEMT to the power supply grounding terminal. However, the existing technology uses a single-piece diamond sheet, which requires the fabrication of conductive vias on the diamond sheet. Moreover, fabricating conductive vias on a diamond sheet has very high process requirements. Therefore, this application effectively reduces the process difficulty.

[0021] In one possible implementation of the first aspect, there is a gap between two adjacent diamond sheets opposite to the conductive via to form a metal grounding groove. That is, the positions of the conductive via and the metal grounding groove correspond, which has the advantage of reducing the resistance and parasitic inductance between the source of the high electron mobility transistor and the power supply ground terminal.

[0022] Secondly, embodiments of this application also provide a method for fabricating a chip package, the method comprising:

[0023] A temporary interconnect layer is provided on a support substrate, and multiple diamond sheets are disposed on the surface of the support substrate through the temporary interconnect layer, wherein the multiple diamond sheets are arranged along a plane parallel to the chip; a substrate layer is provided so that the multiple diamond sheets are disposed within the substrate layer; the support substrate and the temporary interconnect layer are removed to obtain a composite heat dissipation substrate containing a substrate layer and multiple diamond sheets; an interconnect layer is fabricated on the surface of the composite heat dissipation substrate, and the passive surface of the chip is connected to the composite heat dissipation substrate through the interconnect layer.

[0024] The chip packaging fabrication method provided in this application involves firstly placing multiple phase-separated diamond sheets onto a support substrate via a temporary connecting layer, then setting a substrate layer, and finally removing the support substrate and the temporary connecting layer to form a composite heat dissipation substrate. Finally, the composite heat dissipation substrate is connected to the passive surface of the chip via a connecting layer to obtain the chip package. The chip package prepared in this application, while ensuring effective heat dissipation for the chip, effectively reduces manufacturing costs compared to existing monolithic diamond sheets by combining multiple diamond sheets, while maintaining effective heat dissipation for the chip.

[0025] In a possible implementation of the second aspect, after connecting the passive surface of the chip to the composite heat dissipation substrate via a bonding layer, the method further includes: removing a portion of the substrate layer from the surfaces of multiple diamond wafers away from the chip, thereby exposing the surfaces of the diamond wafers away from the chip; and depositing a thermally conductive layer on the surfaces of the diamond wafers away from the chip, with the thermally conductive layers on adjacent diamond wafers connected together. By depositing a thermally conductive layer on the surfaces of the diamond wafers away from the chip, the heat dissipation efficiency of the chip is improved.

[0026] In a possible implementation of the second aspect, after the multiple diamond sheets are disposed on the surface of the support substrate via a temporary connection layer, a heat-conducting layer is further disposed on all surfaces of the multiple diamond sheets except the surface close to the chip, and the heat-conducting layers on adjacent diamond sheets are connected. By disposing heat-conducting layers on all surfaces of the diamond sheets except the surface close to the chip, heat dissipation efficiency is further improved.

[0027] In a possible implementation of the second aspect, after fabricating the interconnect layer on the surface of the composite heat dissipation substrate, the method further includes: fabricating an interconnect layer on the passive surface of the chip, so that the interconnect layer of the composite heat dissipation substrate is connected to the interconnect layer of the passive surface of the chip; wherein, the interconnect layer of the composite heat dissipation substrate and the interconnect layer of the passive surface of the chip are both metal interconnect layers, or, the interconnect layer of the composite heat dissipation substrate and the interconnect layer of the passive surface of the chip are both silicon-based inorganic material interconnect layers.

[0028] Thirdly, this application also provides an electronic device, including a printed circuit board and a chip package as described in the first aspect or any implementation thereof, wherein the printed circuit board is electrically connected to the chip package.

[0029] The electronic device provided in this application includes the chip package provided in the first aspect embodiment. Therefore, the electronic device provided in this application and the chip package of the above technical solution can solve the same technical problem and achieve the same expected effect. Attached Figure Description

[0030] Figure 1 This is a cross-sectional view of chip packaging in the prior art;

[0031] Figure 2 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0032] Figure 3 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0033] Figure 4 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0034] Figure 5 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0035] Figure 6 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0036] Figure 7 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0037] Figure 8 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0038] Figure 9 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0039] Figure 10 This is a cross-sectional view of the chip package according to an embodiment of this application;

[0040] Figure 11 This is a schematic diagram showing the positional relationship between a chip containing high electron mobility transistors and a composite heat dissipation substrate, according to an embodiment of this application.

[0041] Figure 12 for Figure 11 AA cross-section view;

[0042] Figure 13 Figure 11 A schematic diagram showing the positional relationship between multiple diamond sheets and the matrix layer;

[0043] Figure 14a This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0044] Figure 14b This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0045] Figure 14c This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0046] Figure 14d This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0047] Figure 14e This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0048] Figure 14f This is a schematic diagram showing the positional relationship between multiple diamond sheets and the chip in an embodiment of this application;

[0049] Figure 15 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0050] Figure 16 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0051] Figure 17 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0052] Figure 18 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0053] Figure 19 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0054] Figure 20 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0055] Figure 21 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0056] Figure 22 These are cross-sectional views showing the completion of each step in the chip packaging fabrication method according to the embodiments of this application;

[0057] Figure 23 These are cross-sectional views corresponding to the completion of each step in the chip packaging fabrication method of this application embodiment.

[0058] Figure label:

[0059] 01-Chip; 02-Metal layer; 03-Diamond sheet; 1-Chip; 101-Conductive via; 2-Connection layer; 21-First connection layer; 22-Second connection layer; 3-Composite heat dissipation substrate; 31-Diamond sheet; 32-Substrate layer; 33A, 33B-Thermal conduction layer; 311-Metal grounding trench; 4-Rewiring layer; 41-First redistribution layer; 42-Second redistribution layer; 5-Metal bump; 6-High electron mobility transistor; 61-Source; 7-Fixing layer; 8-Support substrate; 9-Temporary connection layer; F-Active surface of the chip; B-Passive surface of the chip. Detailed Implementation

[0060] This application relates to chip packaging, electronic devices, and methods for preparing chip packaging. The following describes the chip packaging, electronic devices, and methods for preparing chip packaging in detail with reference to the accompanying drawings.

[0061] On the one hand, embodiments of this application provide a chip package, referring to... Figure 2 This is a cross-sectional view of a chip package, which includes a chip 1, a connection layer 2, and a composite heat dissipation substrate 3. The composite heat dissipation substrate 3 is connected to the passive surface of the chip 1 (e.g., through the connection layer 2) via the connection layer 2. Figure 2The composite heat dissipation substrate 3 includes multiple diamond sheets 31 and a substrate layer 32. The multiple diamond sheets 31 are arranged along a surface parallel to the chip 1 and are disposed within the substrate layer 32.

[0062] Compared to the chip packaging structure formed by a single diamond sheet in the prior art, the chip packaging provided in this application uses multiple diamond sheets 31 for heat dissipation of chip 1. The specific technical effects are as follows: First, a thermal simulation tool was used to simulate the chip packaging of a certain model. The results show that using multiple diamond sheets provided in this application can achieve a maximum chip temperature reduction of 10%-20%, which is less than 1% different from the temperature reduction achieved by using a single diamond sheet in the prior art. Therefore, the heat dissipation effect of using multiple diamond sheets in this application is comparable to that of existing heat dissipation methods. Furthermore, when dissipating heat from this model of chip, this application uses four 10mm×10mm square diamond sheets, which reduces costs by more than 50% compared to the 20mm×20mm square diamond sheets used in the prior art. Therefore, the use of multiple diamond sheets provided in this application significantly reduces manufacturing costs while ensuring good heat dissipation for the chip.

[0063] It should be noted that: the arrangement of multiple diamond sheets 31 along a surface parallel to the chip 1 means that the surface where the multiple diamond sheets 31 are located is parallel to or nearly parallel to the surface where the chip 1 is located.

[0064] It should be noted that the passive surface of chip 1 (e.g.) Figure 2 The B-side of a chip refers to the side of the chip opposite to the side containing active devices and metal interconnect layers. The side containing active devices and metal interconnect layers is the active side of the chip (e.g., the side with active devices and metal interconnect layers). Figure 2 (F side).

[0065] The material of the substrate layer 32 can be of various types. For example, it can be metal, glass, silicon, polymer (e.g., epoxy resin, benzocyclobutene or polyimide), sintered metal particles, composite sintered diamond particles and metal, or other materials.

[0066] Chip 1 in the chip package can be a chip with high power, such as an integrated circuit, an RF power amplifier, or a high-power light-emitting diode. Of course, chip 1 can also be other types of chips.

[0067] When chip 1 is in operation, the temperature of the heat-generating area is uneven, with some areas having low temperatures and others high temperatures. This results in varying amounts of heat being conducted to the diamond sheet at the corresponding location. Areas with higher temperatures in the heat-generating area receive more heat, leading to a higher temperature for the diamond sheet, while areas with lower temperatures receive less heat, resulting in a lower temperature for the diamond sheet. This leads to a situation where some diamond sheets are hot and cannot dissipate heat in time, while others are cold and not effectively utilized, thus reducing the chip's heat dissipation efficiency.

[0068] To improve heat dissipation efficiency, refer to Figure 3 and Figure 4 The chip package also includes a thermally conductive layer 33A (such as...). Figure 3 As shown), heat conduction layer 33B (as shown) Figure 4 As shown, heat-conducting layers 33A and 33B are disposed on the surface of the diamond wafer 31, and the heat-conducting layers on two adjacent diamond wafers 31 are connected. These heat-conducting layers 33A and 33B are used to conduct heat between the two adjacent diamond wafers 31. In other words, heat on two adjacent diamond wafers 31 can be conducted to each other. This allows heat from one diamond wafer with a higher temperature to be conducted to the other diamond wafer with a lower temperature through the heat-conducting layers, ultimately improving the heat dissipation efficiency of the chip.

[0069] The locations where the heat conduction layer 33A and the heat conduction layer 33B are formed can vary, and will be explained below through various embodiments.

[0070] Example 1

[0071] Reference Figure 3 This is a cross-sectional view of a chip package with a thermally conductive layer, wherein the thermally conductive layer 33A is disposed on the surface of the diamond sheet 31 away from the chip 1.

[0072] In this first embodiment, there are two scenarios. The first scenario is that the surface of the diamond sheet 31 furthest from the chip 1 is flush with the surface of the substrate layer 32 furthest from the chip 1, and the heat-conducting layer 33A extends to the surface of the substrate layer 32 furthest from the chip 1. The second scenario is that the surface of the heat-conducting layer 33A furthest from the chip 1 is flush with the surface of the substrate layer 32 furthest from the chip 1; that is, the surface of the substrate layer 32 furthest from the chip 1 is not provided with the heat-conducting layer 33A. Compared to the second scenario, the heat conduction effect between adjacent diamond sheets is comparable in the first scenario. However, from a manufacturing process perspective, the first scenario is simpler to manufacture, as it does not require avoiding the surface of the substrate layer.

[0073] Figure 3The structure shown also has the following technical effects: since the heat conduction layer 33A is exposed on the entire chip package, and the outside of the chip package is usually provided with a thermal interface material layer and a heat sink, by exposing the heat conduction layer 33A, the thermal resistance between the heat conduction layer 33A and the heat sink can be reduced, so that the heat on the heat conduction layer 33A can be conducted to the heat sink in a timely manner through the thermal interface material layer, and then diffused away by the heat sink, thereby improving the heat dissipation effect.

[0074] Example 2

[0075] Reference Figure 4 This is a cross-sectional view of another chip package with a thermally conductive layer 33B, which is disposed on the remaining surfaces of the diamond sheet 31 except for the surface close to the chip 1.

[0076] Since a heat-conducting layer 33B is provided on all surfaces of the diamond sheet 31 except for the surface that is close to the chip 1, the heat-conducting layer 33B and the diamond sheet 31 have a large contact area, that is, a large heat-conducting area, which can also improve the heat conduction efficiency.

[0077] Example 3

[0078] Reference Figure 5 This is a cross-sectional view of another chip package with a thermally conductive layer. The diamond sheet 31 has a thermally conductive layer 33B on all surfaces except the surface close to the chip 1. The surface of the thermally conductive layer 33B on the surface of the diamond sheet 31 away from the chip 1 is flush with the surface of the substrate layer 32 away from the chip 1.

[0079] Figure 5 The heat conduction layer 33B shown is exposed outside the entire chip package. Typically, a heat sink is also provided on the outside of the chip package. By exposing the heat conduction layer 33B, the thermal resistance between the heat conduction layer 33B and the heat sink can be reduced, so that the heat on the heat conduction layer 33B can be dissipated through the heat sink, thereby improving the heat dissipation effect.

[0080] Example 4

[0081] Reference Figure 6 This is a cross-sectional view of another chip package with a thermally conductive layer. A thermally conductive layer 33B is provided on all surfaces of the diamond sheet 31 except the surface close to the chip 1. The surface of the thermally conductive layer 33B on the surface of the diamond sheet 31 away from the chip 1 is flush with the surface of the substrate layer 32 away from the chip 1. A thermally conductive layer 33A is also provided on the surface of the thermally conductive layer 33B and the surface of the substrate layer 32.

[0082] The materials of the heat-conducting layers 33A and 33B can be the same or different.

[0083] The materials used for the heat-conducting layer provided in this application's embodiments are varied. For example, the materials for the heat-conducting layer include metal, silicon carbide, and aluminum nitride. This application preferentially uses heat-conducting layers made of metal materials because metals have high thermal conductivity and low manufacturing costs, and manufacturing a heat-conducting layer will not increase the overall chip packaging manufacturing cost.

[0084] Reference Figures 2 to 6 The distance between the opposite sides of two adjacent diamond sheets 31 gradually decreases from the direction away from the chip to the direction closer to the chip. That is, the closer to the chip 1, the smaller the distance between two adjacent diamond sheets. The technical effect achieved by this is that the closer to the chip, the smaller the distance between the two diamond sheets, which facilitates the conduction of heat between the two adjacent diamond sheets; in addition, since the diamond sheets are prepared by chemical vapor deposition, it is also easier to manufacture than to set the side of the diamond sheet to be perpendicular to the top surface of the diamond.

[0085] To further improve heat dissipation, refer to Figures 2 to 6 The vertical projection of chip 1 onto multiple diamond sheets 31 covers a portion of each diamond sheet 31. In other words, the diamond sheets extend to the outside of the chip, thus allowing heat to be transferred from chip 1 to the outside of the chip, resulting in better heat dissipation.

[0086] Reference Figure 9 and Figure 10 A redistribution layer 4 is provided on the active surface of chip 1. The redistribution layer 4 is electrically connected to chip 1. The vertical projection of chip 1 onto the redistribution layer 4 covers a portion of the redistribution layer 4, and the vertical projection of chip 1 onto the connection layer 2 covers a portion of the connection layer 2. The uncovered portion of the redistribution layer 4 is connected to the uncovered portion of the connection layer 2 through a fixing layer 7. Metal bumps 5 are provided on the surface of the redistribution layer 4 away from chip 1, and the metal bumps 5 are electrically connected to the redistribution layer 4. In the fan-out package (redistribution layer and metal bumps) used in this embodiment, since the edge of the redistribution layer 4 is outside the edge of chip 1, the number of metal bumps 5 can be increased in some scenarios that require more metal bumps, and the spacing between two adjacent metal bumps 5 can be increased in some scenarios that require a larger spacing between two adjacent metal bumps, thereby improving the applicability.

[0087] Figure 9 and Figure 10 The material of the fixing layer 7 can be a polymer (e.g., epoxy resin, benzocyclobutene, or polyimide), or other materials that can fix and support the redistribution layer.

[0088] Reference Figure 11 and Figure 12 as well as Figure 13 , Figure 11 This is a schematic diagram showing the positional relationship between a chip containing a high electron mobility transistor 6 and a composite heat dissipation substrate (excluding the interconnect layer). Figure 12 for Figure 11 AA cross-section (including the connecting layer). Figure 13 for Figure 11 A schematic diagram showing the positional relationship between multiple diamond sheets 31 and the substrate layer 32 in the structure. A high electron mobility transistor 6 is disposed on the active surface of the chip 1. A conductive via 101 is provided at the position of the source 61 of the high electron mobility transistor 6 of the chip 1, which connects the active surface and the passive surface of the chip 1. Both the connecting layer 2 and the substrate layer 32 are metal layers. At least some of the adjacent diamond sheets 31 have a gap near the position of the connecting layer 2, and this gap forms a metal grounding groove 311.

[0089] In other words, when the transistor on chip 1 is a high electron mobility transistor 6 (with a drain, gate, and source 61), this high electron mobility transistor 6 is a transistor whose source 61 needs to be grounded. Since the high electron mobility transistor 6 is located on the active surface of chip 1, in order to ground the source 61 to the power supply grounding terminal, a conductive via 101 is formed on the chip, and the connection layer 2 and the substrate layer 32 are set as metal layers. At least some of the adjacent diamond sheets 31 have a gap near the connection layer 2, thus achieving grounding of the source to the power supply grounding terminal. Compared with the prior art, it is not necessary to form conductive vias on the diamond sheets. The source 61 of the high electron mobility transistor 6 can be grounded through the connection layer and substrate layer made of metal material and the metal grounding trench, thereby simplifying the manufacturing process. Forming conductive vias on diamond sheets is difficult to process, and this application correspondingly reduces the processing difficulty.

[0090] For example, a conductive via can be a metal via or a silicon via. Of course, it can also be a via made of other materials.

[0091] The connecting layer 2 provided in this application embodiment is a silicon-based inorganic material connecting layer (for example, the material is one or more of Si, SiC, SiO2, and SiN), a metal connecting layer (one of Ti, Cr, Mo, W, Pt, Pb, Ni, Cu, Au, and Ag, or a stack of multiple materials therein), or an organic binder connecting layer.

[0092] Reference Figure 14a , Figure 14b , Figure 14c , Figure 14d , Figure 14e and Figure 14f The number and arrangement of the multiple diamond sheets 31 provided in this application embodiment can have various forms, such as... Figure 14aand Figure 14b As shown, the diamond sheet has two... Figure 14a The arrangement direction of the two diamond plates in the middle and Figure 14b The two diamond plates in the middle are arranged perpendicularly; for example... Figure 14c As shown in Figure 14d, there are three diamond sheets; as shown in Figure 14d, there are four diamond sheets; as... Figure 14e As shown, the diamond sheet has six; as Figure 14f As shown, there are eight diamond sheets. In specific implementations, the number and arrangement of diamond sheets can be designed according to the specific size of chip 1. There are no limitations on the number and arrangement of diamond sheets here, and any number and arrangement are within the protection scope of this application.

[0093] On the other hand, this application also provides an electronic device, which includes a printed circuit board and a chip package provided in the first aspect embodiment above, wherein the printed circuit board and the chip package are electrically connected.

[0094] Since the electronic device includes the chip package, the chip package can effectively reduce manufacturing costs while ensuring heat dissipation for the chip. This effect is even more pronounced for larger chips, which in turn greatly reduces the manufacturing cost of the electronic device.

[0095] For example, the electronic device could be a mobile phone, tablet, etc.

[0096] Furthermore, embodiments of this application also provide a method for manufacturing chip packaging, referring to... Figure 15 The manufacturing method of this chip package includes:

[0097] A temporary connection layer 9 is provided on the support substrate 8, and multiple diamond sheets 31 are disposed on the surface of the support substrate 8 through the temporary connection layer 9. The multiple diamond sheets are arranged along a surface parallel to the chip.

[0098] A substrate layer 32 is provided so that multiple diamond sheets 31 are disposed within the substrate layer 32.

[0099] Remove the support substrate 8 and the temporary connection layer 9 to obtain a composite heat dissipation substrate 3 containing a substrate layer 32 and multiple diamond sheets 31.

[0100] A connection layer 2 is fabricated on the surface of a composite heat dissipation substrate. The passive surface of chip 1 is connected to the composite heat dissipation substrate 3 through the connection layer 2 to obtain a chip package.

[0101] The support substrate 8 is for forming the composite heat dissipation substrate 3. The material of the support substrate 8 can be silicon or glass. The temporary connection layer 9 is provided on the support substrate 8 to fix the subsequent diamond sheet 31 and substrate layer 32 to the support substrate 8. The temporary connection layer 9 can be an organic adhesive connection layer, a silicon-based inorganic material connection layer, or a metal connection layer. In this application, an organic adhesive connection layer is preferred because the organic adhesive connection layer also facilitates the removal of the finally formed composite heat dissipation substrate 3 from the support substrate 8.

[0102] Since the chip is a silicon chip, the bonding layer 2 can be a silicon-based inorganic material bonding layer or an organic adhesive bonding layer, which can achieve bonding with the silicon chip.

[0103] To ensure the connection strength between chip 1 and composite heat dissipation substrate 3, the surface of the composite heat dissipation substrate is polished. After depositing connection layer 2 on the surface of composite heat dissipation substrate 3 near the diamond sheet, the surface of connection layer 2 is polished. This ensures the final connection strength between the chip and the composite heat dissipation substrate and a low interface thermal resistance.

[0104] In practice, the substrate layer 32 is generally formed by compression molding, molding, liquid sealing, vacuum lamination or spin coating. The substrate layer 32 formed in this way will generally firmly encapsulate multiple diamond sheets.

[0105] Reference Figure 16 and Figure 18 In order to form the heat conduction layer 33A, after connecting the passive surface of chip 1 to the composite heat dissipation substrate 3 through the connection layer 1, the following is also included:

[0106] Removing a portion of the substrate layer 32 on the surface of multiple diamond sheets 31 away from the chip 1 (generally by polishing) can be done by removing the substrate layer on the surface of the diamond sheet opposite to the chip to expose the surface of the diamond sheet 31 opposite to the chip 1, or by removing the substrate layer on the surface of the diamond sheet opposite to the chip, as well as the substrate layer on other surfaces of the diamond sheet.

[0107] A heat-conducting layer 33A is disposed on the surface of the diamond sheet 31 away from the chip 1, and the heat-conducting layers 33A on two adjacent diamond sheets 31 are connected.

[0108] It should be noted that the preparation of such Figure 16 and Figure 18 When packaging the chip containing the thermal conductive layer 33A as shown, after setting the substrate layer 32, the surface of the substrate layer 32 away from the chip 1 can be polished to expose the surface of the diamond sheet 31; the thermal conductive layer 33A is set on the surface of the diamond sheet 31 away from the chip 1 and the surface of the substrate layer 32 away from the chip 1.

[0109] To further enhance the connection strength between chip 1 and composite heat dissipation substrate 3, the connection layer 2 can be a metal connection layer. When a metal connection layer is used as the connection layer, in the chip packaging fabrication method, refer to... Figure 17 After obtaining the composite heat dissipation substrate 3, the process includes:

[0110] A first interconnect layer 21 (a metal interconnect layer) is fabricated on the surface of the composite heat dissipation substrate 3, and a second interconnect layer 22 (a metal interconnect layer) is fabricated on the passive surface of the chip 1. Finally, the composite heat dissipation substrate 3 with the first interconnect layer 21 is bonded to the chip 1 with the second interconnect layer 22 deposited thereon.

[0111] The purpose of setting the first interconnect layer 21 (a metal interconnect layer) and the second interconnect layer 22 (a metal interconnect layer) is as follows: When depositing the metal interconnect layer on the composite heat dissipation substrate, since the chip is a silicon chip, the silicon chip cannot be bonded to the metal interconnect layer. Therefore, it is also necessary to deposit a metal interconnect layer on the passive surface of the chip to ultimately obtain the desired result. Figure 7 and Figure 8 The chip package shown.

[0112] Reference Figure 19 The fabrication method for this type of chip package includes:

[0113] A temporary connection layer 9 is provided on the support substrate 8.

[0114] Multiple diamond sheets 31 are disposed on the surface of the temporary connection layer 9 away from the support substrate 8.

[0115] A heat-conducting layer 33B is provided on the remaining surfaces of the diamond sheet except for the surface close to the chip, and the heat-conducting layers 33B of two adjacent diamond sheets are connected together.

[0116] Then a substrate layer 32 is set so that multiple diamond sheets 31 are disposed within the substrate layer 32.

[0117] Remove the support substrate 8 and the temporary connection layer 9 to obtain a composite heat dissipation substrate 3 containing a substrate layer 32, multiple diamond sheets 31, and a heat conduction layer 33B.

[0118] A first interconnect layer 21 (a silicon-based inorganic material interconnect layer) is fabricated on the surface of the composite heat dissipation substrate 3, and a second interconnect layer 22 (a silicon-based inorganic material interconnect layer) is fabricated on the passive surface of the chip 1. Finally, the composite heat dissipation substrate 3 with the first interconnect layer 21 is bonded to the chip 1 with the second interconnect layer 22 deposited thereon.

[0119] It should be noted that when a silicon-based inorganic material bonding layer is placed on the passive side of the composite heat dissipation substrate facing the chip, the silicon-based inorganic material bonding layer can be placed on the passive side of the chip, so that the two silicon-based inorganic material bonding layers can be bonded. Alternatively, it is not necessary to place a silicon-based inorganic material bonding layer on the passive side of the chip, and the bonding can be achieved through silicon to silicon-based inorganic material bonding layers.

[0120] Reference Figure 20 In order to Figure 19 The heat-conducting layer 33B formed in the process is exposed. After the chip package is fabricated, the following steps are performed:

[0121] The surface of the substrate layer 32 away from the chip 1 is polished to expose the surface of the thermal conductive layer 33B.

[0122] To further improve heat dissipation, refer to Figure 21 , can Figure 21 A thermally conductive layer 33A is disposed on the surface of the thermally conductive layer 33B of the chip package and on the surface of the substrate layer 32.

[0123] Reference Figure 22 and Figure 23 Before connecting the passive surface of chip 1 to the interconnect layer 2, the following steps are also included:

[0124] A first redistribution layer 41 is deployed on the active surface of chip 1;

[0125] The passive surface of the chip 1, on which the first redistribution layer 41 is disposed, is connected to the interconnect layer.

[0126] A fixing layer 7 is provided on the connection layer and at the outer edge of chip 1;

[0127] A second redistribution layer 42 is disposed on the surface of the first redistribution layer 41 away from the chip 1, and the second redistribution layer 42 extends onto the fixing layer 7.

[0128] Metal bumps 5 are provided on the surface of the second redistribution layer 42 away from the first redistribution layer 41 to obtain a chip package. The materials of the first redistribution layer 41 and the second redistribution layer 42 may be the same or different.

[0129] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0130] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A chip package, characterized by The chip is connected to the composite heat dissipation substrate through the connecting layer, and the composite heat dissipation substrate comprises: a plurality of diamond pieces arranged along a plane parallel to the chip, the distance between the opposite sides of adjacent two diamond pieces gradually decreases from the direction away from the chip to the direction close to the chip; a base layer, the plurality of diamond pieces are arranged in the base layer; a heat conduction layer arranged on the surfaces of the diamond pieces except the surfaces close to the chip, and the heat conduction layers on adjacent two diamond pieces are connected. The heat conduction layer is arranged on the surface of the diamond piece away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip, and the heat conduction layer extends to the surface of the base layer away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip.

2. The chip package of claim 1, wherein, The connecting layer is a silicon-based inorganic material connecting layer, a metal connecting layer or an organic adhesive connecting layer.

3. The chip package of claim 2, wherein, The vertical projection of the chip on the plurality of diamond pieces covers part of the plurality of diamond pieces.

4. The chip package of claim 1, wherein, The active surface of the chip is provided with a rewiring layer, the rewiring layer is electrically connected to the chip, the vertical projection of the chip on the rewiring layer covers part of the rewiring layer, the vertical projection of the chip on the connecting layer covers part of the connecting layer, the uncovered part of the rewiring layer is connected to the uncovered part of the connecting layer through a fixing layer, and the surface of the rewiring layer away from the chip is provided with a metal bump, and the metal bump is electrically connected to the rewiring layer.

5. The chip package of any one of claims 1-4, wherein, The active surface of the chip is provided with a high electron mobility transistor, a conductive via hole penetrating the active surface and the passive surface of the chip is arranged at the position corresponding to the source of the high electron mobility transistor, the connecting layer and the base layer are metal layers, and at least part of the positions close to the connecting layer of adjacent two diamond pieces have a spacing.

6. The chip package of any one of claims 1-4, wherein, The chip is connected to the composite heat dissipation substrate through the connecting layer, and the composite heat dissipation substrate comprises:

7. The chip package of claim 6, wherein, a plurality of diamond pieces arranged along a plane parallel to the chip, the distance between the opposite sides of adjacent two diamond pieces gradually decreases from the direction away from the chip to the direction close to the chip; 8. The chip package of any one of claims 1-4, wherein, a base layer, the plurality of diamond pieces are arranged in the base layer; 9. A method of fabricating a chip package, characterized by, a heat conduction layer arranged on the surfaces of the diamond pieces except the surfaces close to the chip, and the heat conduction layers on adjacent two diamond pieces are connected. The heat conduction layer is arranged on the surface of the diamond piece away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip, and the heat conduction layer extends to the surface of the base layer away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip. The connecting layer is a silicon-based inorganic material connecting layer, a metal connecting layer or an organic adhesive connecting layer. The vertical projection of the chip on the plurality of diamond pieces covers part of the plurality of diamond pieces. The active surface of the chip is provided with a rewiring layer, the rewiring layer is electrically connected to the chip, the vertical projection of the chip on the rewiring layer covers part of the rewiring layer, the vertical projection of the chip on the connecting layer covers part of the connecting layer, the uncovered part of the rewiring layer is connected to the uncovered part of the connecting layer through a fixing layer, and the surface of the rewiring layer away from the chip is provided with a metal bump, and the metal bump is electrically connected to the rewiring layer. The active surface of the chip is provided with a high electron mobility transistor, a conductive via hole penetrating the active surface and the passive surface of the chip is arranged at the position corresponding to the source of the high electron mobility transistor, the connecting layer and the base layer are metal layers, and at least part of the positions close to the connecting layer of adjacent two diamond pieces have a spacing. The chip is connected to the composite heat dissipation substrate through the connecting layer, and the composite heat dissipation substrate comprises: a plurality of diamond pieces arranged along a plane parallel to the chip, the distance between the opposite sides of adjacent two diamond pieces gradually decreases from the direction away from the chip to the direction close to the chip; a base layer, the plurality of diamond pieces are arranged in the base layer; a heat conduction layer arranged on the surfaces of the diamond pieces except the surfaces close to the chip, and the heat conduction layers on adjacent two diamond pieces are connected. The heat conduction layer is arranged on the surface of the diamond piece away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip, and the heat conduction layer extends to the surface of the base layer away from the chip. The surface of the heat conduction layer on the surface of the diamond piece away from the chip is flush with the surface of the base layer away from the chip. The connecting layer is a silicon-based inorganic material connecting layer, a metal connecting layer or an organic adhesive connecting layer. The vertical projection of the chip on the plurality of diamond pieces covers part of the plurality of diamond pieces. The active surface of the chip is provided with a rewiring layer, the rewiring layer is electrically connected to the chip, the vertical projection of the chip on the rewiring layer covers part of the rewiring layer, the vertical projection of the chip on the connecting layer covers part of the connecting layer, the uncovered part of the rewiring layer is connected to the uncovered part of the connecting layer through a fixing layer, and the surface of the rewiring layer away from the chip is provided with a metal bump, and the metal bump is electrically connected to the rewiring layer. The active surface of the chip is provided with a high electron mobility transistor, a conductive via hole penetrating the active surface and the passive surface of the chip is arranged at the position corresponding to the source of the high electron mobility transistor, the connecting layer and the base layer are metal layers, and at least part of the positions close to the connecting layer of adjacent two diamond pieces have a spacing.

10. The method of claim 9, wherein the method further comprises: After connecting the passive surface of the chip with the composite heat-dissipating substrate through the connecting layer, the method further comprises: removing part of the base layer on the surface of the diamond pieces away from the chip to expose the surface of the diamond pieces away from the chip; setting a heat-conducting layer on the surface of the diamond pieces away from the chip, and connecting the heat-conducting layers on two adjacent diamond pieces.

11. The method of claim 9 or 10, wherein the method further comprises: After making the connecting layer on the surface of the composite heat-dissipating substrate, the method further comprises: making a connecting layer on the passive surface of the chip, so that the connecting layer of the composite heat-dissipating substrate is connected with the connecting layer of the passive surface of the chip; wherein the connecting layer of the composite heat-dissipating substrate and the connecting layer of the passive surface of the chip are both metal connecting layers, or the connecting layer of the composite heat-dissipating substrate and the connecting layer of the passive surface of the chip are both silicon-based inorganic material connecting layers.

12. An electronic device, comprising: The method further comprises: connecting the chip package with a printed circuit board through an electrical connection.

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