Zero point offset correction circuit, zero point offset correction method and oscilloscope

Abstract

The invention discloses a zero offset correction circuit, a zero offset correction method and an oscilloscope, which are applied to the oscilloscope. The oscilloscope includes a signal conditioning circuit, and the zero offset correction circuit includes a signal acquisition circuit and a data processing unit. The signal acquisition circuit is used to collect the output analog signal of the output end of the signal conditioning circuit, and output the corresponding output digital signal through the first output end. The output end of the data processing unit is connected to the controlled end of the signal conditioning circuit; the data processing unit is used to calculate a plurality of output digital signals to obtain a result level; the data processing unit is also used to calculate the difference between the result level and the reference level to obtain a zero offset value. The data processing unit is also used to generate a correction control signal according to the zero offset value, and output it to the signal conditioning circuit. The zero offset correction of the invention is not limited by time, and can be corrected at any time, and there is no need to manually correct the zero offset separately when stopping the acquisition of normal waveforms.

Description

Technical Field

[0001] The present invention relates to the field of oscilloscopes, and in particular to a zero offset correction circuit, a zero offset correction method and an oscilloscope. Background Art

[0002] A digital oscilloscope is a general-purpose measuring instrument that displays the curve of voltage or current changing over time. Its measurement accuracy can generally reach 2%, which can help users view, analyze problems or verify results. A digital oscilloscope generally adjusts the voltage to a suitable size through a signal attenuation circuit and a signal conditioning circuit and outputs it to an analog-to-digital converter, and then sends the converted digital signal to the FPGA. After being processed by the FPGA, the waveform signal is displayed on the screen.

[0003] However, due to differences in device performance and the inconsistency of temperature sensitivity of each device at different ambient temperatures, the signal waveform displayed on the screen will have a zero-point deviation, causing the waveform signal that should have been displayed at zero to deviate from the zero point. It will take a long time for the oscilloscope to start from room temperature and stabilize during operation. During this time, the operating temperature of the device is constantly changing, which will further affect the zero point of the waveform signal. When the gear is changed or other parameters are changed, the zero point of the waveform signal will also change. When the signal deviates from the zero point, an erroneous reference will be generated, which will affect the user's judgment of the signal size and accuracy, resulting in erroneous results. Summary of the invention

[0004] The main purpose of the present invention is to provide a zero offset correction circuit, a zero offset correction method and an oscilloscope, aiming to realize automatic correction of zero offset.

[0005] To achieve the above object, the present invention proposes a zero offset correction circuit, which is applied to an oscilloscope. The oscilloscope includes a signal conditioning circuit. The zero offset correction circuit includes:

[0006] A signal acquisition circuit, comprising an output acquisition terminal and a first output terminal, wherein the output acquisition terminal of the signal acquisition circuit is connected to the output terminal of the signal conditioning circuit; the signal acquisition circuit is used to acquire the output analog signal of the output terminal of the signal conditioning circuit, and output the corresponding output digital signal through the first output terminal;

[0007] A data processing unit, wherein a first input end of the data processing unit is connected to a first output end of the signal acquisition circuit, and an output end of the data processing unit is connected to a controlled end of the signal conditioning circuit; the data processing unit is used to calculate a plurality of the output digital signals to obtain a result level; the data processing unit is also used to compare the result level with a reference level, and when the result level is inconsistent with the reference level, calculate the difference between the result level and the reference level to obtain a zero offset value;

[0008] The data processing unit is also used to generate a correction control signal according to the zero point offset value and output it to the signal conditioning circuit.

[0009] In one embodiment, the signal acquisition circuit includes:

[0010] An output branch, wherein the input end of the output branch is the output acquisition end of the signal acquisition circuit, and the output end of the output branch is the first output end of the signal acquisition circuit; the output branch is used to collect the output analog signal of the output end of the signal conditioning circuit and output the corresponding output digital signal.

[0011] In one embodiment, the output branch includes:

[0012] A high-speed analog-to-digital converter, wherein the input end of the high-speed analog-to-digital converter is the input end of the output branch, and the output end of the high-speed analog-to-digital converter is the output end of the output branch;

[0013] The high-speed analog-to-digital converter is used to convert the output analog signal into a high-speed output digital signal.

[0014] In one embodiment, the output branch includes:

[0015] A first low-pass filter, wherein the input end of the first low-pass filter is the input end of the output branch; the first low-pass filter is used to filter out the output analog signal within a preset frequency range and output it;

[0016] A first low-speed analog-to-digital converter, wherein the input end of the first low-speed analog-to-digital converter is connected to the output end of the first low-pass filter, the output end of the first low-speed analog-to-digital converter is the output end of the output branch, and the first low-speed analog-to-digital converter is used to convert the received output analog signal into a low-speed output digital signal.

[0017] In one embodiment, the signal acquisition circuit has an input acquisition terminal and a second output terminal;

[0018] The input acquisition end of the signal acquisition circuit is connected to the input end of the signal conditioning circuit; the signal acquisition circuit is also used to collect the input analog signal of the input end of the signal conditioning circuit, and output the corresponding input digital signal through the second output end;

[0019] The second input end of the data processing unit is connected to the second output end of the signal acquisition circuit; the data processing unit is used to generate a reference level according to the input digital signal.

[0020] The signal acquisition circuit also includes:

[0021] An input branch, the input end of the input branch is the input acquisition end of the signal acquisition circuit, and the output end of the input branch is the second output end of the signal acquisition circuit; the input branch is used to collect the input analog signal of the input end of the signal conditioning circuit and output the corresponding input digital signal.

[0022] In one embodiment, the input branch includes:

[0023] A second low-pass filter, wherein the input end of the second low-pass filter is the input end of the input branch; the second low-pass filter is used to filter out the input analog signal within a preset frequency range and output it;

[0024] A second low-speed analog-to-digital converter, the input end of the second low-speed analog-to-digital converter is connected to the output end of the second low-pass filter, the output end of the second low-speed analog-to-digital converter is the output end of the input branch, and the second low-speed analog-to-digital converter is used to convert the received input analog signal into an input digital signal.

[0025] The data processing unit is used to calculate the difference between the reference level and the result level to obtain a zero-point offset value; and to generate a correction control signal according to the zero-point offset value and output it to the signal conditioning circuit.

[0026] In one embodiment, the zero offset correction circuit further includes:

[0027] A switch circuit, wherein the switch circuit has a controlled end, a first input end, a second input end and an output end, the controlled end of the switch circuit is connected to the data processing unit, the first input end of the switch circuit is used to receive an input analog signal, the second input end of the switch circuit is connected to a reference level, and the output end of the switch circuit is connected to the input end of the signal conditioning circuit; the data processing unit is also used to control the output end of the switch circuit to be connected to the second input end to obtain a reference level.

[0028] In one embodiment, the zero offset correction circuit further includes a digital-to-analog conversion circuit;

[0029] The input end of the digital-to-analog conversion circuit is connected to the data processing unit, and the output end of the digital-to-analog conversion circuit is connected to the signal conditioning circuit;

[0030] The digital-to-analog conversion circuit is used to convert the correction control signal into a corresponding analog signal and output it to the signal conditioning circuit.

[0031] The present invention also provides a zero offset correction method, which is applied to the above-mentioned zero offset correction circuit. The zero offset correction method comprises the following steps:

[0032] collecting an output analog signal from an output terminal of the signal conditioning circuit, and generating a result level according to the output analog signal;

[0033] Calculating the difference between the reference level and the result level to obtain a zero point offset value;

[0034] A correction control signal is generated according to the zero offset value and output to the signal conditioning circuit.

[0035] The present invention also provides an oscilloscope, which comprises a signal attenuation circuit, a signal conditioning circuit and the above-mentioned zero offset correction circuit.

[0036] The input end of the signal attenuation circuit is used to receive an input analog signal, and the output end of the signal attenuation circuit is connected to the input end of the signal conditioning circuit; the signal attenuation circuit is used to attenuate and output the received input analog signal; the signal conditioning circuit is used to attenuate or amplify the input analog signal.

[0037] The present invention obtains the output analog signal of the output end of the signal conditioning circuit through a signal acquisition circuit and converts it into a corresponding output digital signal. The data processing unit calculates multiple output digital signals to obtain a result level, and compares the result level with a reference level to determine whether a zero offset occurs. When the result level is inconsistent with the reference level, the difference between the result level and the reference level is calculated to obtain a zero offset value, and a correction control signal is generated according to the zero offset value and output to the signal conditioning circuit to adjust the output analog signal of the output end of the signal conditioning circuit so that the zero baseline reading displayed on the display screen is the same as the zero level represented by the standard zero signal, thereby realizing timely correction of the zero offset. The zero offset correction of the present invention is not limited by time and can be corrected at any time, without the need for manual correction of the zero offset when the normal waveform is stopped. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying creative work.

[0039] Figure 1 This is a waveform diagram with no zero point offset;

[0040] Figure 2 This is a schematic diagram of the waveform after adjusting the waveform position;

[0041] Figure 3 This is a waveform diagram after the zero point is offset;

[0042] Figure 4 It is a structural schematic diagram of an embodiment of a zero offset correction circuit of the present invention;

[0043] Figure 5 It is a structural schematic diagram of an embodiment of a zero offset correction circuit of the present invention;

[0044] Figure 6 It is a structural schematic diagram of another embodiment of the zero offset correction circuit of the present invention;

[0045] Figure 7 It is a structural schematic diagram of another embodiment of the zero offset correction circuit of the present invention;

[0046] Figure 8 It is a structural schematic diagram of another embodiment of the zero offset correction circuit of the present invention;

[0047] Fig. 9 It is a structural schematic diagram of another embodiment of the zero offset correction circuit of the present invention;

[0048] Fig.10 It is a structural schematic diagram of another embodiment of the zero offset correction circuit of the present invention;

[0049] Fig.11 It is a flow chart of the zero offset correction method of the present invention.

[0050] Description of Figure Numbers:

[0051]

[0052] The realization of the purpose, functional features and advantages of the present invention will be further explained in conjunction with embodiments and with reference to the accompanying drawings. DETAILED DESCRIPTION

[0053] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0054] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0055] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0056] The signal is input from the outside, processed by the signal attenuation circuit, signal conditioning circuit and analog-to-digital converter, and then sent to the data processing unit. The data processing unit further processes the input signal and displays the waveform on the display screen. Figure 1 The schematic diagram shows the signal waveform in the middle. If the vertical position of the signal waveform needs to be changed, the data processing unit adjusts the output of the signal conditioning circuit, then amplifies and attenuates the signal conditioning circuit’s gain, and then converts it through the analog-to-digital converter and outputs it to the data processing unit, thereby achieving shift and zero-bias adjustment. Figure 2 Adjust the position of the output signal waveform for the data processing unit.

[0057] Electronic devices in the signal conditioning circuit are easily affected by changes in ambient temperature or their own temperature, which changes the efficiency of transmitting electrical signals, resulting in an offset in the output voltage value when receiving low-frequency components in analog signals. The zero-point level input from the signal conditioning circuit becomes larger or smaller after being processed and output by the signal conditioning circuit. The data processing circuit controls the display waveform according to the changed zero-point level, resulting in the displayed zero-point waveform being inconsistent with the original zero-point waveform. Figure 3 As shown. For receiving devices such as oscilloscopes, the offset of the output voltage value greatly affects the display accuracy of the analog signal waveform. Oscilloscopes may be used in different places with different temperatures, which may have different impacts on the signal conditioning circuit. It is impossible to perform zero point calibration on all oscilloscopes before leaving the factory.

[0058] To solve the above problems, refer to Figure 4 The present invention provides a zero offset correction circuit, which is applied to an oscilloscope. The oscilloscope includes a signal conditioning circuit. The zero offset correction circuit includes:

[0059] The signal acquisition circuit 100 has an output acquisition terminal and a first output terminal, and the output acquisition terminal of the signal acquisition circuit 100 is connected to the output terminal of the signal conditioning circuit; the signal acquisition circuit 100 is used to collect the output analog signal of the output terminal of the signal conditioning circuit, and output the corresponding output digital signal through the first output terminal;

[0060] A data processing unit 200, wherein a first input terminal of the data processing unit 200 is connected to a first output terminal of the signal acquisition circuit 100, and an output terminal of the data processing unit 200 is connected to a controlled terminal of the signal conditioning circuit; the data processing unit 200 is used to calculate a plurality of the output digital signals to obtain a result level; the data processing unit 200 is also used to compare the result level with a reference level, and when the result level is inconsistent with the reference level, calculate the difference between the result level and the reference level to obtain a zero offset value;

[0061] The data processing unit 200 is further configured to generate a correction control signal according to the zero offset value, and output the correction control signal to a signal conditioning circuit.

[0062] In this embodiment, when the signal conditioning circuit has a zero-point offset, the zero-point baseline displayed on the display screen after the input zero-point signal is processed by the signal conditioning circuit will be offset upward or downward. The signal acquisition circuit 100 collects the output analog signal of the output end of the signal conditioning circuit through the output acquisition end, and can separate the zero-point signal of the low-frequency component therein, convert it into a corresponding digital output signal and output it to the data processing unit 200. The data processing unit 200 calculates the average value of multiple digital output signals to obtain the result level; or, the data processing unit 200 can also calculate the variance of multiple digital output signals to obtain the result level. The data processing unit 200 compares the result level with the reference level. When the result level is inconsistent with the reference level, it indicates that a zero-point offset has occurred. At this time, the data processing unit 200 calculates the difference between the result level and the reference level, determines the zero-point offset value, and generates a correction control signal according to the zero-point offset value and outputs it to the signal conditioning circuit to adjust the low-frequency component of the output analog signal of the output end of the signal conditioning circuit so that the zero-point baseline reading on the display screen is the reference level. The standard zero-point signal may be a preset standard zero-point signal, or may be a standard zero-point signal obtained from the input end of a signal conditioning circuit.

[0063] For example, the reference level is 0V, and the data processing unit 200 calculates the average value of multiple digital output signals to obtain a result level of 300mV, which indicates that the signal conditioning circuit has a zero offset, and the data processing circuit calculates the difference between the result level and the reference level to obtain a zero offset value of 300mV.

[0064] It is understandable that the data processing unit 200 is also used to control the signal conditioning circuit to adjust the position of the signal waveform, so the data processing unit 200 itself will output a control signal to the signal conditioning circuit. The data processing unit 200 calculates the sum of the zero offset value and the voltage value of the control signal originally output, and converts it into a correction control signal and outputs it to the signal conditioning circuit, so that it is superimposed on the input analog signal of the signal conditioning circuit, and then through the gain amplification and attenuation in the signal conditioning circuit and the processing of the data processing unit 200, the zero baseline reading finally displayed on the display screen is 0V, thereby realizing the zero offset correction.

[0065] The present invention obtains the output analog signal of the output end of the signal conditioning circuit through a signal acquisition circuit and converts it into a corresponding output digital signal. The data processing unit calculates multiple output digital signals to obtain a result level, and compares the result level with a reference level to determine whether a zero offset occurs. When the result level is inconsistent with the reference level, the difference between the result level and the reference level is calculated to obtain a zero offset value, and a correction control signal is generated according to the zero offset value and output to the signal conditioning circuit to adjust the output analog signal of the output end of the signal conditioning circuit so that the zero baseline reading displayed on the display screen is the same as the zero level represented by the standard zero signal, thereby realizing timely correction of the zero offset. The zero offset correction of the present invention is not limited by time and can be corrected at any time, without the need for manual correction of the zero offset when the normal waveform is stopped.

[0066] Reference Figure 5 In one embodiment, the signal acquisition circuit 100 includes:

[0067] The output branch 110 has an input end that is the output acquisition end of the signal acquisition circuit 100, and an output end that is the first output end of the signal acquisition circuit 100; the output branch 110 is used to collect the output analog signal of the output end of the signal conditioning circuit and output a corresponding output digital signal.

[0068] In this embodiment, the output branch 110 is arranged between the signal conditioning circuit and the data processing unit 200. The output branch 110 collects the output analog signal of the output end of the signal conditioning circuit, separates the zero-point signal of the low-frequency component therein, converts it into a corresponding digital output signal and outputs it to the data processing unit 200 for calculation by the data processing unit 200. In this embodiment, by collecting the output analog signal of the output end of the signal conditioning circuit in real time, a correction control signal can be output in time to correct the zero-point offset when a zero-point offset occurs, and there is no need to manually correct the zero-point offset separately when stopping the acquisition of normal waveforms.

[0069] Reference Figure 6 In one embodiment, the output branch 110 includes:

[0070] A high-speed analog-to-digital converter 111, wherein the input end of the high-speed analog-to-digital converter 111 is the input end of the output branch 110, and the output end of the high-speed analog-to-digital converter 111 is the output end of the output branch 110;

[0071] The high-speed analog-to-digital converter 111 is used to convert the output analog signal into a high-speed output digital signal.

[0072] In this embodiment, the high-speed analog-to-digital converter 111 can provide a higher sampling rate, so that the sampled data is more accurate, and thus the calculation result is more accurate. The high-speed analog-to-digital converter 111 collects the output analog signal of the output end of the signal conditioning circuit at a certain sampling rate, and converts the collected output analog signal into a corresponding output digital signal and outputs it to the data processing unit 200. The data processing unit 200 performs low-pass filtering on the received output digital signal to separate the zero-point signal of the low-frequency component.

[0073] Furthermore, the output branch 110 further includes a low-pass filter. The low-pass filter can separate the zero-point signal of the low-frequency component in the collected output analog signal and output it to the high-speed analog-to-digital converter 111 for analog-to-digital conversion.

[0074] Reference Figure 7 In one embodiment, the output branch 110 includes:

[0075] A first low-pass filter 112, wherein the input end of the first low-pass filter 112 is the input end of the output branch 110; the first low-pass filter 112 is used to filter out the output analog signal within a preset frequency range and output it;

[0076] A first low-speed analog-to-digital converter 113, wherein the input end of the first low-speed analog-to-digital converter 113 is connected to the output end of the first low-pass filter 112, the output end of the first low-speed analog-to-digital converter 113 is the output end of the output branch 110, and the first low-speed analog-to-digital converter 113 is used to convert the received output analog signal into a low-speed output digital signal.

[0077] In this embodiment, the first low-pass filter 112 separates the zero-point signal of the low-frequency component in the output analog signal, and outputs it to the first low-speed analog-to-digital converter 113 to convert it into a corresponding output digital signal for processing by the data processing unit 200. Compared with the high-speed analog-to-digital converter 111, the sampling rate of the low-speed analog-to-digital converter is lower, and the data collected in the same time is less, but the cost is also lower. In this embodiment, the use of a low-speed analog-to-digital converter can meet the sampling requirements of the low-frequency component in the output analog signal and reduce costs.

[0078] Reference Figure 6 , in one embodiment, the signal acquisition circuit 100 has an input acquisition terminal and a second output terminal;

[0079] The input acquisition terminal of the signal acquisition circuit 100 is connected to the input terminal of the signal conditioning circuit; the signal acquisition circuit 100 is also used to collect the input analog signal of the input terminal of the signal conditioning circuit, and output the corresponding input digital signal through the second output terminal;

[0080] The second input terminal of the data processing unit 200 is connected to the second output terminal of the signal acquisition circuit 100 ; the data processing unit 200 is used to generate a reference level according to the input digital signal.

[0081] The signal acquisition circuit 100 further includes:

[0082] An input branch 120, wherein the input end of the input branch 120 is the input acquisition end of the signal acquisition circuit 100, and the output end of the input branch 120 is the second output end of the signal acquisition circuit 100; the input branch 120 is used to collect the input analog signal of the input end of the signal conditioning circuit and output the corresponding input digital signal.

[0083] In this embodiment, the signal acquisition circuit 100 acquires the input analog signal of the input end of the signal conditioning circuit through the input acquisition end, and can separate the zero-point signal of the low-frequency component therein through the input branch 120, and convert it into a corresponding digital input signal and output it to the data processing unit 200. The input analog signal at the input end of the signal conditioning circuit does not have a zero-point offset, and the corresponding digital input signal does not have a zero-point offset. The data processing unit 200 can calculate multiple digital input signals and use the calculation results as standard level signals. For example, the data processing unit 200 calculates the average value of multiple digital input signals to obtain a reference level; or the data processing unit 200 can also calculate the variance of multiple digital output signals to obtain a reference level.

[0084] This embodiment collects the input analog signal of the input end of the signal conditioning circuit and converts it into a corresponding output digital signal. The data processing unit 200 calculates the reference level of multiple digital output signals, and calculates the difference between the result level and the marked zero point level to obtain the zero point offset value. That is, the difference between the input analog signal at the input end of the signal conditioning circuit and the output analog signal at the output end is calculated to obtain the zero point offset generated by the signal conditioning circuit, and the corresponding correction control signal is output according to the zero point offset value.

[0085] Reference Figure 8 In one embodiment, the input branch 120 includes:

[0086] A second low-pass filter 121, wherein the input end of the second low-pass filter 121 is the input end of the input branch 120; the second low-pass filter 121 is used to filter out the input analog signal within a preset frequency range and output it;

[0087] A second low-speed analog-to-digital converter 122, wherein the input end of the second low-speed analog-to-digital converter 122 is connected to the output end of the second low-pass filter 121, the output end of the second low-speed analog-to-digital converter 122 is the output end of the input branch 120, and the second low-speed analog-to-digital converter 122 is used to convert the received input analog signal into an input digital signal.

[0088] The data processing unit 200 is used to calculate the difference between the reference level and the result level to obtain a zero-point offset value; and to generate a correction control signal according to the zero-point offset value and output it to the signal conditioning circuit.

[0089] In this embodiment, the second low-pass filter 121 separates the zero-point signal of the low-frequency component in the input analog signal, and outputs it to the second low-speed analog-to-digital converter 122 to convert it into a corresponding input digital signal for processing by the data processing unit 200. Compared with the high-speed analog-to-digital converter 111, the sampling rate of the low-speed analog-to-digital converter is lower, and the data collected in the same time is less, but the cost is also lower. In this embodiment, the low-speed analog-to-digital converter can meet the sampling requirements of the low-frequency component in the input analog signal and reduce the cost.

[0090] Reference Fig. 9 In one embodiment, the zero offset correction circuit further includes:

[0091] The switch circuit 300 has a controlled end, a first input end, a second input end and an output end. The controlled end of the switch circuit 300 is connected to the data processing unit 200. The first input end of the switch circuit 300 is used to receive an input analog signal. The second input end of the switch circuit 300 is connected to a reference level. The output end of the switch circuit 300 is connected to the input end of the signal conditioning circuit. The data processing unit 200 is also used to control the output end of the switch circuit 300 to be connected to the second input end to obtain a reference level.

[0092] In this embodiment, the data processing unit 200 collects the gap of the output analog circuit in the output branch 110, controls the second input terminal of the switch circuit 300 to be connected to the output terminal, so as to disconnect the input of the signal conditioning circuit and connect the reference level. Among them, the input terminal of the switch circuit 300 can be grounded, and the voltage of the ground is 0V, so the ground level can be used as the reference level. The data processing circuit samples the ground for a short time to obtain multiple sampling data, calculates the multiple sampling data, and uses the calculation result as the reference level value. After the sampling is completed, the data processing unit 200 controls the first input terminal of the switch circuit 300 to be connected to the output terminal, and reconnects the external input signal.

[0093] Reference Fig.10 In one embodiment, the switch circuit 300 includes a relay 310 and a first resistor R1, the input end of the first resistor R1 is grounded, and the output end of the first resistor R1 is connected to the second input end of the relay 310. The data processing unit 200 controls the relay 310 to be closed / released to switch sampling / accessing external input signals.

[0094] In one embodiment, the zero offset correction circuit further includes a digital-to-analog conversion circuit;

[0095] The input end of the digital-to-analog conversion circuit is connected to the data processing unit 200, and the output end of the digital-to-analog conversion circuit is connected to the signal conditioning circuit;

[0096] The digital-to-analog conversion circuit is used to convert the correction control signal into a corresponding analog signal and output it to the signal conditioning circuit.

[0097] In this embodiment, the data processing unit 200 calculates the difference between the result level and the reference level to obtain a zero-point offset value, and adds the zero-point offset value to the original output of the digital-to-analog conversion circuit to obtain a correction control signal. The correction control signal output by the data processing unit 200 is a digital signal, which cannot be directly received by the signal conditioning circuit. The digital-to-analog conversion circuit converts the correction control signal into a corresponding analog signal and outputs it to the signal conditioning circuit, which is superimposed on the input analog signal of the signal conditioning circuit to adjust the output analog signal output by the signal conditioning circuit, and then adjusts the position of the zero-point baseline displayed on the display screen so that its reading is the reference level. Among them, the digital-to-analog conversion circuit can be integrated in the data processing unit 200, or it can be set separately.

[0098] Reference Fig.11 The present invention also provides a zero offset correction method, which is applied to the above-mentioned zero offset correction circuit, and the zero offset correction method comprises the following steps:

[0099] Collecting an input analog signal from an input end of the signal conditioning circuit, and generating a reference level according to the input analog signal;

[0100] collecting an output analog signal from an output terminal of the signal conditioning circuit, and generating a result level according to the output analog signal;

[0101] Calculating the difference between the reference level and the result level to obtain a zero point offset value;

[0102] A correction control signal is generated according to the zero offset value and output to the signal conditioning circuit.

[0103] In this embodiment, when the signal conditioning circuit has a zero-point offset, the zero-point baseline displayed on the display screen after the input zero-point signal is processed by the signal conditioning circuit will be offset upward or downward. The output analog signal of the output end of the signal conditioning circuit is collected, and the zero-point signal of the low-frequency component is separated and converted into a corresponding digital output signal. The result level is obtained by calculating the average value of multiple digital output signals; or, the result level is obtained by calculating the variance of multiple digital output signals. The result level is compared with the reference level. When the result level is inconsistent with the reference level, it indicates that a zero-point offset has occurred. At this time, the difference between the result level and the reference level is calculated to determine the zero-point offset value, and a correction control signal is generated according to the zero-point offset value and output to the signal conditioning circuit to adjust the low-frequency component of the output analog signal at the output end of the signal conditioning circuit so that the zero-point baseline reading on the display screen is the reference level. Among them, the standard zero-point signal can be a pre-set standard zero-point signal, or it can be a standard zero-point signal obtained by collecting the input end of the signal conditioning circuit.

[0104] For example, the reference level is 0V, and by calculating the average value of multiple digital output signals, the resulting level is 300mV, which indicates that the signal conditioning circuit has a zero offset, and the data processing circuit calculates the difference between the resulting level and the reference level, and obtains a zero offset value of 300mV.

[0105] It is understandable that the data processing unit is also used to control the signal conditioning circuit to adjust the position of the signal waveform, so the data processing unit itself will output a control signal to the signal conditioning circuit. The data processing unit calculates the sum of the zero offset value and the voltage value of the control signal originally output, and converts it into a correction control signal and outputs it to the signal conditioning circuit, so that it is superimposed on the input analog signal of the signal conditioning circuit, and then through the gain amplification and attenuation in the signal conditioning circuit and the processing of the data processing unit, the zero baseline reading finally displayed on the display screen is 0V, thereby realizing the zero offset correction.

[0106] The present invention collects the output analog signal of the output end of the signal conditioning circuit and converts it into a corresponding output digital signal. The result level is obtained by calculating multiple output digital signals, and the result level is compared with the reference level to determine whether a zero offset occurs. When the result level is inconsistent with the reference level, the difference between the result level and the reference level is calculated to obtain a zero offset value, and a correction control signal is generated according to the zero offset value and output to the signal conditioning circuit to adjust the output analog signal of the output end of the signal conditioning circuit so that the zero baseline reading displayed on the display screen is the same as the zero level represented by the standard zero signal, thereby realizing timely correction of the zero offset. The zero offset correction of the present invention is not limited by time and can be corrected at any time, without the need for manual correction of the zero offset when the normal waveform is stopped.

[0107] The present invention also provides an oscilloscope, which comprises a signal attenuation circuit, a signal conditioning circuit and the above-mentioned zero offset correction circuit.

[0108] The input end of the signal attenuation circuit is used to receive an input analog signal, and the output end of the signal attenuation circuit is connected to the input end of the signal conditioning circuit; the signal attenuation circuit is used to attenuate and output the received input analog signal; the signal conditioning circuit is used to attenuate or amplify the input analog signal.

[0109] The detailed structure of the zero offset correction circuit can be referred to the above-mentioned embodiment, which will not be described in detail here; it can be understood that since the above-mentioned zero offset correction circuit is used in the oscilloscope of the present invention, the embodiment of the oscilloscope of the present invention includes all technical solutions of all embodiments of the above-mentioned zero offset correction circuit, and the technical effects achieved are also exactly the same, which will not be described in detail here.

[0110] The above are only optional embodiments of the present invention, and are not intended to limit the patent scope of the present invention. All equivalent structural changes made using the contents of the present invention's specification and drawings, or directly / indirectly applied in other related technical fields, are included in the patent protection scope of the present invention.

Claims

1. A zero offset correction circuit is applied to an oscilloscope, wherein the oscilloscope includes a signal conditioning circuit, characterized in that: The zero offset correction circuit comprises: A signal acquisition circuit, comprising an output acquisition terminal and a first output terminal, wherein the output acquisition terminal of the signal acquisition circuit is connected to the output terminal of the signal conditioning circuit; the signal acquisition circuit is used to acquire the output analog signal of the output terminal of the signal conditioning circuit, and output the corresponding output digital signal through the first output terminal; A data processing unit, wherein a first input end of the data processing unit is connected to a first output end of the signal acquisition circuit, and an output end of the data processing unit is connected to a controlled end of the signal conditioning circuit; the data processing unit is used to calculate a plurality of the output digital signals to obtain a result level; the data processing unit is also used to compare the result level with a reference level, and when the result level is inconsistent with the reference level, calculate the difference between the result level and the reference level to obtain a zero offset value; The data processing unit is also used to generate a correction control signal according to the zero point offset value, and output it to the signal conditioning circuit; Wherein, the signal acquisition circuit also has an input acquisition terminal and a second output terminal; The input acquisition end of the signal acquisition circuit is connected to the input end of the signal conditioning circuit; the signal acquisition circuit is also used to collect the input analog signal of the input end of the signal conditioning circuit, and output the corresponding input digital signal through the second output end; The second input terminal of the data processing unit is connected to the second output terminal of the signal acquisition circuit; the data processing unit is used to generate a reference level according to the input digital signal; The signal acquisition circuit also includes: An input branch, the input end of the input branch is the input acquisition end of the signal acquisition circuit, and the output end of the input branch is the second output end of the signal acquisition circuit; the input branch is used to collect the input analog signal of the input end of the signal conditioning circuit and output the corresponding input digital signal.

2. The zero offset correction circuit according to claim 1, characterized in that: The signal acquisition circuit comprises: An output branch, wherein the input end of the output branch is the output acquisition end of the signal acquisition circuit, and the output end of the output branch is the first output end of the signal acquisition circuit; the output branch is used to collect the output analog signal of the output end of the signal conditioning circuit and output the corresponding output digital signal.

3. The zero offset correction circuit according to claim 2, characterized in that: The output branches include: A high-speed analog-to-digital converter, wherein the input end of the high-speed analog-to-digital converter is the input end of the output branch, and the output end of the high-speed analog-to-digital converter is the output end of the output branch; The high-speed analog-to-digital converter is used to convert the output analog signal into a high-speed output digital signal.

4. The zero offset correction circuit according to claim 2, characterized in that: The output branches include: A first low-pass filter, wherein the input end of the first low-pass filter is the input end of the output branch; the first low-pass filter is used to filter out the output analog signal within a preset frequency range and output it; A first low-speed analog-to-digital converter, wherein the input end of the first low-speed analog-to-digital converter is connected to the output end of the first low-pass filter, the output end of the first low-speed analog-to-digital converter is the output end of the output branch, and the first low-speed analog-to-digital converter is used to convert the received output analog signal into a low-speed output digital signal.

5. The zero offset correction circuit according to claim 1, characterized in that: The input branch comprises: A second low-pass filter, wherein the input end of the second low-pass filter is the input end of the input branch; the second low-pass filter is used to filter out the input analog signal within a preset frequency range and output it; a second low-speed analog-to-digital converter, wherein an input end of the second low-speed analog-to-digital converter is connected to an output end of the second low-pass filter, an output end of the second low-speed analog-to-digital converter is an output end of the input branch, and the second low-speed analog-to-digital converter is used to convert the received input analog signal into an input digital signal; The data processing unit is used to calculate the difference between the reference level and the result level to obtain a zero-point offset value; and to generate a correction control signal according to the zero-point offset value and output it to the signal conditioning circuit.

6. The zero offset correction circuit according to claim 1, characterized in that: The zero offset correction circuit also includes: A switch circuit, wherein the switch circuit has a controlled end, a first input end, a second input end and an output end, the controlled end of the switch circuit is connected to the data processing unit, the first input end of the switch circuit is used to receive an input analog signal, the second input end of the switch circuit is connected to a reference level, and the output end of the switch circuit is connected to the input end of the signal conditioning circuit; the data processing unit is also used to control the output end of the switch circuit to be connected to the second input end to obtain a reference level.

7. The zero offset correction circuit according to claim 1, characterized in that: The zero offset correction circuit also includes a digital-to-analog conversion circuit; The input end of the digital-to-analog conversion circuit is connected to the data processing unit, and the output end of the digital-to-analog conversion circuit is connected to the signal conditioning circuit; The digital-to-analog conversion circuit is used to convert the correction control signal into a corresponding analog signal and output it to the signal conditioning circuit.

8. A zero offset correction method, applied to the zero offset correction circuit as claimed in any one of claims 1 to 7, characterized in that: The zero offset correction method comprises the following steps: collecting an output analog signal from an output terminal of the signal conditioning circuit, and generating a result level according to the output analog signal; Calculating the difference between the reference level and the result level to obtain a zero point offset value; A correction control signal is generated according to the zero offset value and output to the signal conditioning circuit.

9. An oscilloscope, characterized in that: The oscilloscope comprises a signal attenuation circuit, a signal conditioning circuit and a zero offset correction circuit as claimed in any one of claims 1 to 7; The input end of the signal attenuation circuit is used to receive an input analog signal, and the output end of the signal attenuation circuit is connected to the input end of the signal conditioning circuit; the signal attenuation circuit is used to attenuate and output the received input analog signal; the signal conditioning circuit is used to attenuate or amplify the input analog signal.

Images