Power supply circuit, corresponding device and method

Abstract

Various embodiments of the present disclosure relate to power supply circuits, corresponding devices and methods. A voltage regulator coupled between a first node and a second node includes a first (full power) regulator circuit and a second (low power) regulator circuit. In a first mode: when the voltage at the first node is a battery voltage, the first regulator circuit is activated (wherein the second regulator circuit is not activated), and when the voltage at the first node is a ground voltage, the voltage regulator remains deactivated. In a second mode: when the voltage at the first node is a battery voltage, the first regulator circuit is activated (wherein the second regulator circuit is not activated), and when the voltage at the first node is a ground voltage, the voltage regulator is not activated. In a third mode: regardless of whether the voltage at the first node is at a battery voltage or a ground voltage, the second regulator circuit is activated (wherein the first regulator circuit is not activated).

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102021000015176 filed on June 10, 2021, the contents of which are incorporated herein by reference in their entirety to the maximum extent permitted by law. Technical Field

[0003] The present description relates to power supply circuits.

[0004] One or more embodiments may be adapted for use in a variety of products, such as, for example, industrial electronics applications, mass market applications (eg, in an Internet of Things or IoT environment), various embedded applications, and the like. Background Art

[0005] In operation, a voltage regulator configured to support "high voltage" capability (eg, at 4.5V), such as a low dropout (LDO) regulator, may cause a significant junction temperature increase, which in some cases makes the use of such a regulator nearly infeasible.

[0006] Note also that under certain circumstances, such high voltage capability of the regulator may not be necessary and may therefore be redundant.

[0007] Therefore, increased flexibility in configuring a device power scheme according to specific application requirements represents a desirable feature.

[0008] Therefore, a solution for solving the above problems is needed in the art. Summary of the invention

[0009] One or more embodiments are directed to a circuit.

[0010] One or more embodiments are directed to corresponding systems.A microcontroller unit (MCU) with associated (external) memory (eg, flash memory) may be an example of such a device.

[0011] One or more embodiments may be directed to a corresponding method.

[0012] One or more embodiments provide the possibility to select whether a voltage regulator (eg an embedded LDO regulator) needs to be activated at power-up and becomes available to be controllably switched off together with an associated control circuit in order to save power.

[0013] One or more embodiments provide the possibility to select a desired power scheme based on application requirements in terms of, for example, power consumption, battery power range and thermal performance, and reduce power consumption and semiconductor area costs.

[0014] One or more embodiments may provide flexible supply schemes that allow various operating conditions, such as: a single power supply at 4.5V with an external load (such as an external memory) supplied by a power supply voltage in the range of 1.8V-3.3V; a dual power supply at 4.5V / 3.6V with an external load supplied by a power supply voltage in the range of 1.8V-3.6V; and a single power supply at 3.6V with an external load supplied by a power supply voltage of 2.5V-3.6V.

[0015] The quantitative diagrams given above are purely exemplary and do not limit the exemplary embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0017] Figure 1 It is the overall block diagram of the circuit;

[0018] Figure 2 and Figure 3 It is a combination Figure 1 An exemplary block diagram of a conventional arrangement of circuits employed is shown;

[0019] Figure 4 is a block diagram illustrating certain heat dissipation issues that may occur in a power supply circuit including an embedded voltage regulator;

[0020] Figure 5 , Figure 6 and Figure 7 are examples of different operating conditions supported by embodiments of this specification;

[0021] Figure 8 is an exemplary block diagram of an embodiment of the present specification; and

[0022] Fig. 9 is an example diagram of possible operating modes of an embodiment. DETAILED DESCRIPTION

[0023] Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated.

[0024] The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

[0025] The edges of a feature drawn in a drawing do not necessarily indicate the end of the extent of the feature.

[0026] In the following description, various specific details are shown to provide a deeper understanding of various examples of embodiments according to the description. Embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure aspects of the embodiments.

[0027] References to "an embodiment" or "one embodiment" in the framework of this description are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment," "in one embodiment," etc., which may appear in various points of this description, do not necessarily refer exactly to one embodiment and the same embodiment. Furthermore, particular configurations, structures, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0028] The headings / references used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0029] For the sake of brevity and simplicity, the same name (eg, VBAT, VDDIO, etc.) may be used below to designate both a certain circuit node or a certain line and a signal (eg, a voltage signal) appearing at the node or line.

[0030] Figure 1 is a simplified representation of a circuit 10, such as, for example, a microcontroller unit or MCU powered by a power source such as a battery LB.

[0031] A (rechargeable) lithium-ion battery may be an example of a battery LB. Those skilled in the art will appreciate that the embodiments are not limited to the presence of such a battery, which is a distinct element from the embodiments. For example, the battery LB may be a battery that is intended to be coupled to the circuit 10 ("plugged in") only by an end user and / or for a limited period of time.

[0032] A battery such as LB is representative of a power source that is configured to apply a supply voltage between a “hot” node VDD and ground GND to circuit 10 .

[0033] As mentioned above, although batteries such as modern rechargeable lithium-ion batteries have operating voltages up to 4.5V and (slightly) higher charging voltages, most commercial technology does not include devices capable of / required to operate above 3.6V.

[0034] Going to higher voltages involves using "high voltage" circuits, which can be quite complex and increase semiconductor area usage, cost, and power consumption.

[0035] Figure 2is an example of such a conventional approach, wherein an (external) embedded voltage regulator (REG) 12 is provided between a battery LB and a node VDD in a circuit 10, wherein a decoupling capacitor 14 is provided between the node VDD and ground GND.

[0036] like Figure 2 The arrangement shown suffers from the problem of extra components which negatively impacts the bill of materials (BoM) with increased size, complexity and cost.

[0037] A further disadvantage relates to the increased power consumption in active mode as well as in low-power (quiescent) mode.

[0038] All of the above makes Figure 2 The solution exemplified in is hardly attractive for applications such as Internet of Things (IoT) applications, where it is desirable to reduce consumption in low power modes.

[0039] like Figure 3 Another conventional approach shown is based on a system-on-chip (SoC) architecture, in which an embedded voltage regulator 12 is "embedded" in a circuit 10, with an input / output (I / O) analog circuit device 16 provided similarly embedded in the circuit 10. A decoupling capacitor 14 may be arranged between ground GND and a node intermediate the embedded voltage regulator 12 and the circuit device 16.

[0040] Although it provides slightly better performance, Figure 3 The arrangement shown has essentially the same Figure 2 Same drawbacks as discussed.

[0041] One or more embodiments described below are directed to Figure 3 The embedded layout in the example solves the above combination Figure 2 The shortcomings discussed.

[0042] For this reason, unless the context indicates otherwise, the above Figures 1 to 3 The general disclosure provided also applies to the other drawings and will not be incorporated in conjunction with the drawings for the sake of brevity. Figure 4 The previous figures are repeated.

[0043] The regulator (REG) 100 may be a low dropout (LDO) regulator.

[0044] As described below (for example, in conjunction with Figure 8 ), the regulator 100 may include a high drive (HD) LDO circuit device designated as 102, and a low power (LP) LDO circuit device designated as 104.

[0045] LDO is an acronym for "Low Dropout" and designates a DC linear voltage regulator architecture that is configured to regulate its output voltage even when the voltage supplied to it is very close to the output voltage.

[0046] Using an embedded voltage regulator (such as an LDO regulator) may result in an increase in the (junction) temperature during operation, which in some extreme cases may outweigh the use of such a regulator.

[0047] In this regard, please refer to Figure 4 Figures of the drawings in which parts of elements corresponding to parts or elements already discussed in connection with previous figures are designated with corresponding reference numerals, unless the context indicates otherwise.

[0048] like Figure 4 As shown, the regulator 100 is configured to operate between: a first node VBAT is configured to have a voltage from a power source (eg, 4.5V from a battery) applied thereto, and a second node IOVDD is configured to supply power to an external device designated as an ED via line 180 .

[0049] Decoupling capacitor 14 may be arranged between node IOVDD (line 180) and ground.

[0050] Another node designated as VDDIO is coupled to line 180 , with nodes IOVDD and VDDIO being arranged “upstream” and “downstream” of decoupling capacitor 14 .

[0051] Node VDDIO may be intended to provide a voltage supply for circuit devices such as 16 included in circuit 10 .

[0052] For example, VDDIO may be the main power supply node for the entire circuit 10 (eg, a microcontroller), except for subsystems directly connected to VBAT.

[0053] The device ED designated as "external" emphasizes that this may represent an element different from the circuit 10. A memory such as a flash memory coupled to an MCU such as 10 may be an example of such an external device ED.

[0054] For the sake of illustration, it may be assumed that the circuit 10 is configured to cooperate with an external device ED via a set of I / O nodes (pins) 18 .

[0055] Therefore, the regulator 100 receives a voltage at the node VBAT, for example a voltage of 4.5 V. This is a voltage that may be provided from a battery coupled between the node VBAT and the ground GND.

[0056] The (regulated) supply voltage applied to the external device ED (via line 180) and to the node VDDIO would be expected to be low, in the range of 1.8V - 3.3V.

[0057] exist Figure 4 In the drawings, reference numeral 16 is designated to a circuit arrangement of an analog type, such as, for example, an RF (Radio Frequency) circuit arrangement.

[0058] It should also be understood that the specific characteristics and mode of operation of the circuit arrangement 16 and the specific characteristics and mode of operation of the external device ED coupled to the circuit 10 are not relevant to the embodiment.

[0059] Thus, embodiments may be considered to be substantially “transparent” with respect to the specific characteristics and mode operation of the circuit arrangement 16 and / or the specific characteristics and mode operation of the external device ED.

[0060] As discussed, using Figure 4 The embedded voltage regulator of the regulator 100 shown may result in an increase in (junction) temperature during operation, which in some extreme cases may be a trade-off against the use of such a regulator.

[0061] For example, if the battery voltage VBAT input to the regulator 100 reaches 4.5 V and the regulated voltage at the node IOVDD at the output of the regulator (when supplied to the circuit ED) is set to 1.8 V, the dissipated power H1 can be about 540 mW: this is of course a pure example, since the actual dissipated power depends on the current, i.e. on the load.

[0062] Assuming a conventional value of about 35°C / W for package thermal resistance (such as for current semiconductor device packages), this dissipated power may result in a corresponding temperature increase of about 19°C.

[0063] Potential heat dissipation H2 from circuit 16 (and other portions of circuit 10 ) may increase heat dissipation H1 from regulator 100 .

[0064] For example, for the highest consumption operating mode of a circuit such as circuit 16 , the heat dissipation H2 from circuit 16 may be from a few mW up to 800 mW.

[0065] The actual situation may depend on factors such as the voltage drop across the regulator 100 , the characteristics of the load (device ED), the heat generated by the circuit arrangement 16 , and the like.

[0066] As discussed, these factors utilize voltage regulators such as embedded LDO regulators in applications such as Figure 4 is hardly feasible in the context illustrated in .

[0067] On the other hand, in certain applications, the 4.5V supply may not be a concern, so in the end, a voltage regulator such as regulator 100 may end up being redundant.

[0068] One or more embodiments contemplate the possibility of (virtually) “removing” (ie, deactivating) an embedded voltage regulator such as regulator 100 .

[0069] Figures 5 to 7 Various desired operating configurations for a circuit such as circuit 10 are illustrated.

[0070] Figure 5 A first “single supply” operating condition is involved, wherein a supply voltage VBAT (eg, 4.5 V from a battery LB) is applied to the regulator 100 .

[0071] In this first operating condition, the regulator 100 operates at an output node designated as IOVDD and provides a regulated supply voltage for an external device (e.g., a memory) ED coupled via line 180, wherein the supply voltage provided by the regulator 100 is regulated within a range, for example, between 1.8 V and 3.3 V. The same voltage may be applied to the node VDDIO.

[0072] Figure 6 and Figure 7 Concerning possible situations in which the regulator 100 may be "removed" (ie, deactivated).

[0073] exist Figure 6 and Figure 7 Under the “dual supply” operating condition, the external load ED (and node VDDIO) can be supplied: Figure 6 In the case shown, the voltage regulator 12 (see also Figure 2 ) provides a voltage of 1.8V to 3.6V, or Figure 7 In the case shown, the voltage is, for example, 2.5 V to 3.6 V derived from the battery LB.

[0074] Figure 6 Concerns the situation where a battery such as a Li-ion battery (eg, up to 4.5 V) is used and an embedded LDO such as regulator 100 cannot be used for "thermal" reasons (junction temperature too high).

[0075] In this case, the external LDO 12 is used to generate a voltage compatible with VDDIO (eg, from 1.8V to 3.3V / 3.6V) and a voltage compatible with an external device (eg, ED).

[0076] Figure 7This concerns the (application dependent) case where a Li-Ion battery is not used and the voltage VBAT is in the range of 2.5V - 3.3V / 3.6V (these are only examples and are not hard limits by the specifications of the circuits involved).

[0077] In this case, the same VBAT supply may be used to power all circuits involved, ie all circuits powered via node VDDIO (eg a microcontroller) plus the external device (ED) and the (RF) circuitry 16 .

[0078] Of course, this assumes that the power supply of the external circuit ED is compatible with the VBAT voltage range.

[0079] In short, Figure 7 In the case of a MCU, the 2.5-3.6V voltage comes directly from the main power source (such as a battery).

[0080] Again, it is recalled that the quantitative diagrams given above are purely exemplary and not limiting of the embodiments.

[0081] The general idea is to offer the user the possibility to adapt the configuration according to specific application needs, thus allowing to obtain a desired cost / performance trade-off.

[0082] One or more embodiments address the problem of supporting different usage conditions, such as Figure 5 , Figure 6 and Figure 7 As illustrated, desired low power operation and performance are simultaneously facilitated.

[0083] To this end, the connection states of the circuit 10 corresponding to, for example, the RF circuit device 16 being “disconnected” (OFF state, i.e., all internal circuits in the circuit 10 are deactivated) and “connected” (RUN state, i.e., all internal circuits in the circuit 10 are activated and running) are supplemented by two new states, namely:

[0084] The first “disconnect LDO” state, in which, in order to support Figure 5 The operating conditions shown, regulator 100 remains active ("ON"), which may support high drive mode and low power mode (see Figure 8 to obtain an optimized low power mode for the entire circuit, for example, under the condition that the circuit device 16 is deactivated, and

[0085] A second “operate LDO” state, in which circuit arrangement 16 is operated with regulator 100 activated, means that the entire circuit 10 (including regulator 100 ) is active.

[0086] In this way, even if, for example, the RF circuit arrangement 16 is in a switched-off state, there is the possibility of activating the regulator 100 so that the rest of the system can be powered.

[0087] therefore, Figures 5 to 7 The circuit configuration shown in can be represented by the following table.

[0088] Table I - Single power supply (e.g., VBAT @ 4.5V and line 180 / node VDDIO @ 1.8-3.3V- Figure 5 )

[0089]

[0090]

[0091] Table II - Dual Supply (eg, Regulator 100 "removed", Line 180 / Node VDDIO @ 1.8 - 3.6V - Figure 6 or @2.5-3.6V- Figure 7 )

[0092]

[0093] That is, in Figure 5 In the single power mode of Table I above, the regulator 100 is activated in a startup state, for example, in response to the battery LB being inserted.

[0094] In this state / condition, the voltage at the node IOVDD is gradually increased from zero to avoid damaging the circuit ED. More details in this respect can be gathered from the Italian patent application filed on the same date and partly assigned to the assignee of the present application.

[0095] exist Figure 6 and Figure 7 As well as in the dual power mode of Table II above, the regulator 100 may be (remained) disconnected or deactivated in response to a control signal ctrl from an (always on) control feature in the circuit arrangement 16, which may also enable a low power mode to reduce consumption.

[0096] In dual supply mode, regulator 100 can be kept permanently disconnected. This can be achieved by connecting pin VBATLDO to ground (see Figure 8 ).

[0097] In one or more embodiments, when the regulator 100 is switched from a low power mode (circuit device 104 is activated and circuit device 102 is not activated) to a high drive mode (circuit device 104 is not activated and circuit device 102 is activated), when the signal ldo_rdy from the control feature 16 is asserted, the corresponding information is available in the voltage domain.

[0098] like Figure 8 As shown in , one or more embodiments provide the possibility of whether to select the embedded regulator 100 will be:

[0099] Starts up at power on (START UP, as described above) and becomes available for possible shutdown, where the signal Ido_rdy is asserted, indicating that the embedded regulator 100 is ready for high drive operation (high drive circuit device 102 is activated and low power circuit device 104 is deactivated), or

[0100] “removed” from circuit 10 (ie, left inactive—both high drive circuitry 102 and low power circuitry 104 ), in which case power supply for circuit 10 and power supply for external devices ED may be provided by external power source ES, as previously discussed.

[0101] like Figure 8 As shown, the switch 22 (e.g., an electronic switch such as a MOSFET transistor) is provided and controlled by a signal LDO_enable generated in a manner known per se to those skilled in the art, so as to selectively disconnect the circuit controlling the embedded regulator 100 (supplied via the low voltage regulator 24). In this way, further power savings can be obtained when the circuit is operated in a low power mode.

[0102] exist Figure 8 AOVDD represents an internally generated power supply that facilitates control of the regulator 100 and other circuits. If the LDO is not needed, the power supply node / line AOVDD can be disconnected in low power mode to further reduce power consumption.

[0103] Figure 8 Also shown is coupling node VBATLDO of regulator 100 to the (normal) supply voltage VBAT (battery voltage at 4.5V, e.g. see Figure 8 The possibility of connecting the regulator 100 to the line designated as IOVBAT in the circuit 10 or to ground GND allows the regulator 100 to be activated or “removed” from the circuit 10.

[0104] These options may be software controlled by the controller unit 10 itself, or take the form of wired logic.

[0105] The arrangement discussed herein may involve a regulator 100 comprising a high drive circuit device 102 capable of producing 200 mA at a voltage of 1.84 V + / - 6%, and a current energy of approximately 2 mA for a low power circuit device 104, wherein the regulated output voltage at the output node IOVDD is programmable (e.g., via software) in a range of, for example, 1.8 V - 3.3 V in steps of 300 mV.

[0106] Therefore, the following operating conditions can be Fig. 9 This occurs as illustrated in boxes 1000, boxes 1002, boxes 1003, and boxes 1004 in the graph of FIG.

[0107] Block 1000 (behavior at power-up, e.g. a battery LB providing voltage VBAT is inserted into the circuit):

[0108] VBATLDO=VBAT The regulator 100 starts up in a high drive mode (respectively, the circuit arrangement 102 is activated and the circuit 104 is deactivated).

[0109] VBATLDO = GND The regulator 100 remains switched off (both the circuit arrangement 102 and the circuit arrangement 104 are deactivated).

[0110] Block 1002 (behavior when circuit arrangement 16 is in the "Run" state):

[0111] VBATLDO=VBAT The regulator 100 remains in the high drive mode or switches to the high drive mode (the circuit device 102 is activated and the circuit device 104 is deactivated).

[0112] VBATLDO = GND The regulator 100 remains switched off (both the circuit arrangement 102 and the circuit arrangement 104 are deactivated).

[0113] Block 1003 (behavior when the circuit arrangement 16 is in the off (deactivated) state):

[0114] VBATLDO=VBAT Where the signal LDO_enable is asserted (eg, transition 1 0); the switch 22 is closed and the regulator 100 switches to the low power mode (the circuit device 102 is deactivated and the circuit device 104 is activated).

[0115] VBATLDO = GND Where the LDO_enable signal is deasserted (e.g., transition 1 0); switch 22 is open, wherein the regulator 100 is deactivated at both 102 and 104.

[0116] Box 1004 (Behavior when exiting from disconnected state):

[0117] VBATLDO=VBAT The regulator 100 switches back to operating in the high drive mode (circuit device 102 is activated and circuit device 104 is deactivated), wherein the circuit 16 asserts the corresponding signal Ido_rdy, for example with transition 0 1.

[0118] VBATLDO = GND The regulator 100 remains in the off state (both the circuit arrangement 102 and the circuit arrangement 104 are deactivated).

[0119] Solutions such as those discussed previously provide flexibility in configuring device power schemes based on specific application requirements and usage conditions.

[0120] For example, by noting that a “high voltage” supply at 4.5V may be undesirable, one or more solutions discussed herein may take an “aggressive” approach to promoting low power operation, configuring the circuit for single supply operation at, for example, 3.6V.

[0121] In situations where a "high voltage" supply at 4.5V is desired, by considering possible thermal issues, one may selectively employ either of two options, such as a single supply at 4.5V (where thermal issues are not expected) or a dual supply at 4.5 / 3.6V (where thermal issues are expected).

[0122] One or more embodiments facilitate control of an embedded voltage regulator, such as an LDO voltage regulator, thereby facilitating power settings when the regulator is disabled by resorting to an isolation approach when high voltage operation is not desired.

[0123] One or more embodiments facilitate selecting an appropriate power scheme based on specific application requirements in terms of power consumption, battery power range, and thermal performance.

[0124] The solutions discussed here help achieve the goals of having reduced power consumption and reduced semiconductor area occupancy.

[0125] Without prejudice to the essential principles, the details and embodiments may vary, even significantly, with respect to what is described merely by way of example, without departing from the scope of protection.

[0126] The scope of protection is determined by the appended claims.

Claims

1. A circuit comprising: First node; a second node configured to provide a power supply to an electrically powered device; a voltage regulator coupled to the first node and configured to provide a regulated voltage to the second node, the voltage regulator comprising a first regulator circuit configured to provide full power operation of the voltage regulator and a second regulator circuit configured to provide low power operation of the voltage regulator; wherein the circuit is configured to: i) operating in a first operating mode, wherein: the first regulator circuit in the voltage regulator is activated when the voltage at the first node is at a first voltage level, wherein the second regulator circuit is inactivated, and the voltage regulator is kept deactivated when the voltage at the first node is at a second voltage level; ii) operating in a second operating mode, wherein: when the voltage at the first node is at the first voltage level, the first regulator circuit in the voltage regulator is activated, wherein the second regulator circuit is inactivated, and when the voltage at the first node is at the second voltage level, the voltage regulator is inactivated, wherein both the first regulator circuit and the second regulator circuit are inactivated; and iii) operating in a third operation mode, the second regulator circuit in the voltage regulator is activated and the first regulator circuit is inactivated, regardless of whether the voltage at the first node is at the first voltage level or at the second voltage level. 2 . The circuit of claim 1 , wherein the circuit is configured to switch from the third operation mode to the second operation mode in response to the voltage at the first node changing from the second voltage level to the first voltage level. 3 . The circuit of claim 1 , further comprising a control circuit for the voltage regulator, the control circuit being configured to be shut down in response to the voltage regulator being inactive. 4 . The circuit of claim 1 , wherein the circuit is configured to issue a ready signal indicating that switching from the second operating mode to the third operating mode is possible in response to receiving a signal indicating a request for low power operation.

5. The circuit of claim 1 , further comprising a power node configured to be coupled to the powered device, wherein the power node is configured to be coupled to a power source selected from the group consisting of: another voltage regulator external to the circuit and a voltage source at the first voltage level, the another voltage regulator coupled to the voltage source at the first voltage level in response to the voltage regulator being inactivated.

6. The circuit of claim 1, wherein the first regulator circuit in the voltage regulator is activated to the first operating mode in response to a power supply coupled to the first node applying the first voltage level to the first node.

7. The circuit of claim 1, wherein: The voltage regulator comprises a low dropout (LDO) regulator; and The circuit comprises a microcontroller unit.

8. The circuit of claim 1, wherein the first voltage level is a battery voltage and the second voltage level is a ground voltage.

9. An electric power system comprising: The circuit according to claim 1, and An electrically powered device is coupled to the second node.

10. The system of claim 9, wherein the electrically powered device coupled to the second node comprises a memory.

11. A method of operating the circuit according to claim 1, comprising: coupling an electrically powered device to the second node; as well as A power source is coupled to the first node.

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