A voltage-to-current circuit
By integrating the voltage-to-current conversion function with the bandgap reference circuit, the separate bandgap reference module and operational amplifier are eliminated, solving the problems of large area and high power consumption of existing voltage-to-current circuits, and realizing a high-precision and low-power circuit design.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- IMPERSON SEMICON (ZHUHAI) CO LTD
- Filing Date
- 2026-03-17
- Publication Date
- 2026-05-26
AI Technical Summary
Existing voltage-to-current circuits suffer from problems such as large area, high power consumption, and complex design. In particular, the need for independent bandgap reference modules and operational amplifiers increases chip area and circuit power consumption.
The voltage-to-current conversion function is deeply integrated with the bandgap reference circuit, sharing its core components. The bandgap reference voltage is directly applied to the voltage divider resistor through a matched transistor to generate a precise current, eliminating the need for a separate bandgap reference module and operational amplifier.
It achieves a reduction in chip area and power consumption, maintains high precision and good power supply rejection capability, and simplifies circuit design.
Smart Images
Figure CN121857893B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of analog integrated circuit design, and more specifically to a voltage-to-current circuit. Background Technology
[0002] In analog integrated circuits, voltage-to-current (V-to-I) circuits are a fundamental and critical module, widely used in bias circuits, data converters, sensor interfaces, and more. High-precision, low-temperature-drift, and insensitive-to-power-fluid-ripple V-to-I circuits are essential for improving the performance of the entire system.
[0003] Figure 3 A voltage-to-current converter circuit in the prior art is described. This circuit typically includes a separate bandgap reference module, an operational amplifier OP, a feedback resistor R1, an NMOS transistor MN1, and a current mirror consisting of PMOS transistors MP1 and MP2. The bandgap reference module generates a stable reference voltage VBG. The operational amplifier OP, MN1, and resistor R1 form a negative feedback loop, forcing the voltage at node FB1 to equal the voltage at node VBG, thereby generating a precise current I across resistor R1. R1 =V VBG / R1. The current is conducted by MN1 and MP1, and output from the output port IO through a current mirror composed of replicas of MP1 and MP2.
[0004] However, this traditional structure has the following drawbacks:
[0005] High area and cost: It requires a separate, often complex bandgap reference module and operational amplifier, which occupy a large chip area.
[0006] High power consumption: The operational amplifier itself consumes quiescent current, which increases the overall power consumption of the circuit.
[0007] Complex design: The frequency compensation and stability design of the operational amplifier increases the complexity of the circuit design.
[0008] Therefore, how to design a voltage-to-current circuit with a simpler structure that saves area and power consumption while maintaining high accuracy and good power supply suppression capability is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0009] In view of the above problems, the present invention is proposed to provide a voltage-to-current circuit that overcomes or at least partially solves the above problems.
[0010] To achieve the above objectives, the present invention adopts the following technical solution:
[0011] A voltage-to-current circuit is based on the core concept of deeply integrating the voltage-to-current function with a bandgap reference circuit, sharing its core components and bias, and using a matched transistor to directly apply the bandgap reference voltage to a voltage divider resistor on an external structure to generate a precise current.
[0012] The specific structure of this circuit includes a bandgap reference circuit and a voltage-to-current output circuit:
[0013] A bandgap reference circuit is used to output a bandgap reference voltage V. VBG The bandgap reference circuit includes a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, and a third resistor.
[0014] In this configuration, the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD; the gates of the first PMOS transistor and the second PMOS transistor are connected to form a current mirror; and the drain of the first PMOS transistor is shorted to its gate and connected to the drain of the first NMOS transistor.
[0015] The drain of the second PMOS transistor is connected to the source of the fifth and sixth PMOS transistors; the gates of the fifth and sixth PMOS transistors are connected to form a current mirror; the drain of the fifth PMOS transistor is shorted to the gate and connected to the collector of the second bipolar transistor; the drain of the sixth PMOS transistor is connected to the collector of the first bipolar transistor.
[0016] The bases of the first bipolar transistor and the second bipolar transistor are both connected to the gate of the first NMOS transistor; the emitter of the first bipolar transistor is grounded through the second resistor; the second bipolar transistor is grounded through the first resistor and the second resistor; the gate of the first NMOS transistor is connected to the drain of the sixth PMOS transistor.
[0017] The drain of the first NMOS transistor and the base of the second bipolar transistor are connected to the output node VBG of the bandgap reference voltage.
[0018] One end of the third resistor is connected to the source of the first NMOS transistor, and the other end is grounded.
[0019] The voltage-to-current output circuit is used to convert the bandgap reference voltage into current and output it; the voltage-to-current output circuit includes a second NMOS transistor, a sixth resistor, a ninth PMOS transistor, and a tenth PMOS transistor.
[0020] In this configuration, the sources of the ninth and tenth PMOS transistors are connected to the power supply VDD, and the drain of the ninth PMOS transistor is shorted to the gate and connected to the drain of the second NMOS transistor.
[0021] The gate of the second NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the first NMOS transistor. The source of the second NMOS transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded.
[0022] The drain output current of the tenth PMOS transistor.
[0023] Preferably, the ratio of the emitter area of the first bipolar transistor to the emitter area of the second bipolar transistor in the bandgap reference circuit is 1:N, where N>1.
[0024] Preferably, the bandgap reference circuit further includes a cascaded structure consisting of a third PMOS transistor, a fourth PMOS transistor, and a fourth resistor, and a cascaded structure consisting of a seventh PMOS transistor, an eighth PMOS transistor, and a fifth resistor.
[0025] The cascaded structure consisting of a third PMOS transistor, a fourth PMOS transistor, and a fourth resistor connects the drain of the first PMOS transistor to the source of the third PMOS transistor. The drain of the third PMOS transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the first NMOS transistor. The drain of the third PMOS transistor is shorted to the gates of the first and second PMOS transistors. The source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor. The drain of the fourth PMOS transistor is connected to the sources of the fifth and sixth PMOS transistors. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The other end of the fourth resistor is shorted to the gates of the third and fourth PMOS transistors.
[0026] The cascaded structure consisting of the seventh PMOS transistor, the eighth PMOS transistor, and the fifth resistor connects the drain of the fifth PMOS transistor to the source of the seventh PMOS transistor. The drain of the seventh PMOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the collector of the second bipolar transistor. The drain of the seventh PMOS transistor is shorted to the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the drain of the eighth PMOS transistor is connected to the collector of the first bipolar transistor. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the other end of the fifth resistor is shorted to the gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor.
[0027] Preferably, the voltage-to-current output circuit further includes a cascaded structure consisting of an eleventh PMOS transistor, a twelfth PMOS transistor, and a seventh resistor:
[0028] The cascaded structure consisting of the eleventh PMOS transistor, the twelfth PMOS transistor, and the seventh resistor connects the drain of the ninth PMOS transistor to the source of the eleventh PMOS transistor. The drain of the eleventh PMOS transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the drain of the ninth PMOS transistor. The drain of the eleventh PMOS transistor is shorted to the gates of the ninth and tenth PMOS transistors. The source of the twelfth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the twelfth PMOS transistor outputs current. The gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor, and the other end of the seventh resistor is shorted to the gates of the eleventh and twelfth PMOS transistors.
[0029] Preferably, the bandgap reference circuit outputs a reference voltage V with near-zero temperature coefficient at the VBG node. VBG .
[0030] VBG node voltage V in bandgap reference circuit VBG The specific expression is:
[0031] V VBG =V be1 +V R2 =V be1 +2(I R1 ) R2=V be1 +2( V be / R1) R2;
[0032] V R1 = V be =V be1 -V be2 ;
[0033] V R2 =2(I R1 ) R2=2( V be / R1) R2;
[0034] Among them, V VBG V is the VBG node voltage, which is the source voltage of the first NMOS transistor. R1 The voltage across the first resistor is V. be1 V is the base-emitter negative temperature coefficient voltage of the first bipolar transistor. be2 This is the base-emitter voltage of the second bipolar transistor. V beV is the positive temperature coefficient voltage representing the difference between the base-emitter voltage of the first bipolar transistor and the base-emitter voltage of the second bipolar transistor. R2 I is the voltage value of the second resistor. R1 R1 is the current value of the first resistor, R2 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.
[0035] V VBG =V GN1 -V thn ;
[0036] Among them, V GN1 V is the GN1 node voltage, i.e., the gate voltage of the first NMOS transistor. thn The threshold voltage of the first NMOS transistor is the difference between the gate voltage and the source voltage of the first NMOS transistor.
[0037] Preferably, the current I at the IO node in the voltage-to-current output circuit is... IO The specific expression is:
[0038] I IO =V VBG / R6;
[0039] Among them, I IO R6 represents the current at the IO node, and R6 is the resistance value of the sixth resistor.
[0040] As can be seen from the above technical solution, compared with the prior art, the present invention discloses a voltage-to-current circuit, which has the following beneficial effects:
[0041] High integration and simplification: No separate bandgap reference module and operational amplifier are required. The V-to-I function is directly embedded in the bandgap reference structure, which significantly reduces chip area and manufacturing cost.
[0042] Low power consumption: Saves power consumption of operational amplifiers, reducing the overall quiescent current consumption of the circuit.
[0043] High precision: Through device matching technology, the first NMOS transistor and the second NMOS transistor are matched, effectively canceling the threshold voltage V of the NMOS transistor. thn The process deviations and temperature variations have been mitigated to ensure the accuracy of current generation.
[0044] Good power supply rejection capability: The stacked current mirror structure used in the bandgap reference circuit inherently possesses a certain degree of power supply rejection capability. As a preferred option, the suppression performance against power supply voltage fluctuations can be further improved by adding cascaded structures along the critical current mirror paths. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.
[0046] Figure 1 This is a schematic diagram of a voltage-to-current conversion circuit provided in an embodiment of the present invention;
[0047] Figure 2 This is an improved schematic diagram of the voltage-to-current conversion circuit provided in an embodiment of the present invention;
[0048] Figure 3 This is a schematic diagram of a prior art voltage-to-current circuit provided in an embodiment of the present invention. Detailed Implementation
[0049] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0050] This invention discloses a voltage-to-current conversion circuit.
[0051] Example 1: The basic structure includes a bandgap reference circuit and a voltage-to-current output circuit.
[0052] A bandgap reference circuit is used to output a bandgap reference voltage V. VBG The bandgap reference circuit includes a first PMOS transistor MP1, a second PMOS transistor MP2, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6, a first NMOS transistor MN1, a first bipolar transistor Q1, a second bipolar transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3.
[0053] The voltage-to-current output circuit is used to convert the bandgap reference voltage into current and output it. The voltage-to-current output circuit includes the second NMOS transistor MNi2, the sixth resistor R6, the ninth PMOS transistor MPi1, and the tenth PMOS transistor MPi2.
[0054] The bandgap reference circuit is connected as follows: the sources of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to the power supply VDD; the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2 are connected to form a current mirror; the drain of the first PMOS transistor MP1 is shorted to the gate and connected to the drain of the first NMOS transistor MN1.
[0055] The drain of the second PMOS transistor MP2 is connected to the source of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6; the gate of the fifth PMOS transistor MP5 and the gate of the sixth PMOS transistor MP6 are connected to form a current mirror; the drain of the fifth PMOS transistor MP5 is shorted to the gate and connected to the collector of the second bipolar transistor Q2; the drain of the sixth PMOS transistor MP6 is connected to the collector of the first bipolar transistor Q1.
[0056] The bases of the first bipolar transistor Q1 and the second bipolar transistor Q2 are both connected to the gate of the first NMOS transistor MN1; the emitter of the first bipolar transistor Q1 is grounded through the second resistor R2; the second bipolar transistor Q2 is grounded through the first resistor R1 and the second resistor R2; the gate of the first NMOS transistor MN1 is connected to the drain of the sixth PMOS transistor MP6.
[0057] The drain of the first NMOS transistor MN1 and the base of the second bipolar transistor Q2 are connected to the output node VBG of the bandgap reference voltage.
[0058] One end of the third resistor R3 is connected to the source of the first NMOS transistor MN1, and the other end is grounded.
[0059] The bandgap reference circuit, through a system consisting of a first bipolar transistor Q1, a second bipolar transistor Q2, a first resistor R1, a second resistor R2, a current mirror composed of a first PMOS transistor MP1 and a second PMOS transistor MP2, and a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6, outputs a reference voltage V with near-zero temperature coefficient at the VBG node. VBG .
[0060] VBG node voltage V in bandgap reference circuit VBG The specific expression is:
[0061] V VBG =V be1 +V R2 =V be1 +2(I R1 ) R2=V be1 +2( V be / R1) R2;
[0062] V R1 = V be =V be1 -V be2 ;
[0063] V R2 =2(I R1 ) R2=2( V be / R1) R2;
[0064] Among them, V VBG V is the VBG node voltage, which is the source voltage of the first NMOS transistor. R1 The voltage across the first resistor is V. be1 V is the base-emitter negative temperature coefficient voltage of the first bipolar transistor. be2 This is the base-emitter voltage of the second bipolar transistor. V be V is the positive temperature coefficient voltage representing the difference between the base-emitter voltage of the first bipolar transistor and the base-emitter voltage of the second bipolar transistor. R2 I is the voltage value of the second resistor. R1 R1 is the current value of the first resistor, R2 is the resistance value of the first resistor, and R2 is the resistance value of the second resistor.
[0065] V VBG =V GN1 -V thn ;
[0066] Among them, V GN1 V is the GN1 node voltage, i.e., the gate voltage of the first NMOS transistor. thn The threshold voltage of the first NMOS transistor is the difference between the gate voltage and the source voltage of the first NMOS transistor.
[0067] Its core principle is to cancel out the positive and negative temperature coefficients of the base-emitter voltage difference of the bipolar transistor, and finally output a stable voltage with a near-zero temperature coefficient at the VBG node.
[0068] The voltage-to-current output circuit is used to convert the bandgap reference voltage into current and output it. The voltage-to-current output circuit includes the second NMOS transistor MNi2, the sixth resistor R6, the ninth PMOS transistor MPi1, and the tenth PMOS transistor MPi2.
[0069] The voltage-to-current output circuit is connected as follows: the sources of the ninth PMOS transistor MPi1 and the tenth PMOS transistor MPi2 are connected to the power supply VDD, and the drain of the ninth PMOS transistor is shorted to the gate and connected to the drain of the second NMOS transistor.
[0070] The gate of the second NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the first NMOS transistor. The source of the second NMOS transistor is connected to one end of the sixth resistor, and the other end of the sixth resistor is grounded.
[0071] The drain output current of the tenth PMOS transistor.
[0072] The voltage-to-current output circuit, through a system composed of the ninth PMOS transistor, the tenth PMOS transistor, the second NMOS transistor, and the sixth resistor, outputs the voltage V at the IO node. VBG The converted current I IO .
[0073] Current I at the IO node in the voltage-to-current output circuit IO The specific expression is:
[0074] I IO =V VBG / R6;
[0075] Among them, I IO R6 represents the current at the IO node, and R6 is the resistance value of the sixth resistor.
[0076] Example 2: Enhanced structure for Example 1
[0077] refer to Figure 2 This embodiment adds a cascaded structure to improve performance, based on the bandgap reference circuit and voltage-to-current output circuit of Embodiment 1.
[0078] Based on the bandgap reference circuit, a cascaded structure consisting of a third PMOS transistor MP3, a fourth PMOS transistor MP4, and a fourth resistor R4 was added to the current mirror composed of the first PMOS transistor MP1 and the second PMOS transistor MP2. Similarly, a cascaded structure consisting of a seventh PMOS transistor MP7, an eighth PMOS transistor MP8, and a fifth resistor R5 was added to the current mirror composed of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6. This significantly improves the power supply rejection ratio of the bandgap reference circuit itself, resulting in a more stable voltage output at the VBG voltage node.
[0079] The cascaded structure consisting of the third PMOS transistor MP3, the fourth PMOS transistor MP4, and the fourth resistor R4 is such that the drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3, the drain of the third PMOS transistor MP3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to the drain of the first NMOS transistor MN1, the drain of the third PMOS transistor MP3 is shorted to the gate of the first PMOS transistor MP1 and the gate of the second PMOS transistor MP2, the source of the fourth PMOS transistor MP4 is connected to the drain of the second PMOS transistor MP2, the drain of the fourth PMOS transistor MP4 is connected to the source of the fifth PMOS transistor MP5 and the sixth PMOS transistor MP6, the gate of the third PMOS transistor MP3 is connected to the gate of the fourth PMOS transistor MP4, and the other end of the fourth resistor R4 is shorted to the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4.
[0080] The cascaded structure consisting of the seventh PMOS transistor MP7, the eighth PMOS transistor MP8, and the fifth resistor R5 is as follows: the drain of the fifth PMOS transistor MP5 is connected to the source of the seventh PMOS transistor MP7; the drain of the seventh PMOS transistor MP7 is connected to one end of the fifth resistor R5; the other end of the fifth resistor R5 is connected to the collector of the second bipolar transistor Q2; the drain of the seventh PMOS transistor MP7 is shorted to the gate of the fifth PMOS transistor MP5 and the gate of the sixth PMOS transistor MP6; the source of the eighth PMOS transistor MP8 is connected to the drain of the sixth PMOS transistor MP6; the drain of the eighth PMOS transistor MP8 is connected to the collector of the first bipolar transistor Q1; the gate of the seventh PMOS transistor MP7 is connected to the gate of the eighth PMOS transistor MP8; and the other end of the fifth resistor R5 is shorted to the gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8.
[0081] Based on the voltage-to-current output circuit, a cascaded structure consisting of the eleventh PMOS transistor MPi3, the twelfth PMOS transistor MPi4, and the seventh resistor Ria was added to the current mirror composed of the ninth PMOS transistor MPi1 and the tenth PMOS transistor MPi2.
[0082] The cascaded structure consisting of the eleventh PMOS transistor MPi3, the twelfth PMOS transistor MPi4, and the seventh resistor Ria connects the drain of the ninth PMOS transistor MPi1 to the source of the eleventh PMOS transistor MPi3. The drain of the eleventh PMOS transistor MPi3 is connected to one end of the seventh resistor Ria, and the other end of the seventh resistor Ria is connected to the drain of the ninth PMOS transistor MPi1. The drain of the eleventh PMOS transistor MPi3 is shorted to the gate of the ninth PMOS transistor MPi1 and the gate of the tenth PMOS transistor MPi2. The source of the twelfth PMOS transistor MPi4 is connected to the drain of the tenth PMOS transistor MPi2. The drain of the twelfth PMOS transistor MPi4 outputs current. The gate of the eleventh PMOS transistor MPi3 is connected to the gate of the twelfth PMOS transistor MPi4. The other end of the seventh resistor Ria is shorted to the gate of the eleventh PMOS transistor MPi3 and the gate of the twelfth PMOS transistor MPi4.
[0083] This further enhances the ability to suppress power supply voltage fluctuations, meaning the output current is less affected by fluctuations in the VDD node voltage, further improving the immunity of the output current IO to changes in the power supply voltage VDD, making IO more stable and accurate.
[0084] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0085] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A voltage-to-current circuit, comprising: The voltage-to-current conversion circuit includes: A bandgap reference circuit is used to output a bandgap reference voltage VVBG; the bandgap reference circuit includes a first PMOS transistor, a second PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a first NMOS transistor, a first bipolar transistor, a second bipolar transistor, a first resistor, a second resistor, and a third resistor; A voltage-to-current output circuit is used to convert the bandgap reference voltage into current and output it; the voltage-to-current output circuit includes a second NMOS transistor, a sixth resistor, a ninth PMOS transistor, and a tenth PMOS transistor; The connection relationship of the bandgap reference circuit is as follows: The sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD; the gates of the first PMOS transistor and the second PMOS transistor are connected to form a current mirror; the drain of the first PMOS transistor is shorted to the gate and connected to the drain of the first NMOS transistor. The drain of the second PMOS transistor is connected to the source of the fifth and sixth PMOS transistors; the gates of the fifth and sixth PMOS transistors are connected to form a current mirror; the drain of the fifth PMOS transistor is shorted to its gate and connected to the collector of the second bipolar transistor; the drain of the sixth PMOS transistor is connected to the collector of the first bipolar transistor. The base of the first bipolar transistor and the base of the second bipolar transistor are both connected to the gate of the first NMOS transistor; the emitter of the first bipolar transistor is grounded through the second resistor; the second bipolar transistor is grounded through the first resistor and the second resistor; the gate of the first NMOS transistor is connected to the drain of the sixth PMOS transistor. The drain of the first NMOS transistor and the base of the second bipolar transistor are connected to the output node VBG of the bandgap reference voltage; One end of the third resistor is connected to the source of the first NMOS transistor, and the other end is grounded; The connection relationship of the voltage-to-current output circuit is as follows: The sources of the ninth PMOS transistor and the tenth PMOS transistor are connected to the power supply VDD. The drain of the ninth PMOS transistor is shorted to the gate and connected to the drain of the second NMOS transistor. The gate of the second NMOS transistor is connected to the drain of the sixth PMOS transistor and the gate of the first NMOS transistor, and the source of the second NMOS transistor is connected to one end of the sixth resistor, the other end of the sixth resistor is grounded; The drain output current of the tenth PMOS transistor; The bandgap reference circuit also includes a cascaded structure consisting of a third PMOS transistor, a fourth PMOS transistor, and a fourth resistor, and a cascaded structure consisting of a seventh PMOS transistor, an eighth PMOS transistor, and a fifth resistor. The cascaded structure consisting of the third PMOS transistor, the fourth PMOS transistor, and the fourth resistor connects the drain of the first PMOS transistor to the source of the third PMOS transistor. The drain of the third PMOS transistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is connected to the drain of the first NMOS transistor. The drain of the third PMOS transistor is short-circuited to the gate of the first PMOS transistor and the gate of the second PMOS transistor. The source of the fourth PMOS transistor is connected to the drain of the second PMOS transistor. The drain of the fourth PMOS transistor is connected to the sources of the fifth and sixth PMOS transistors. The gate of the third PMOS transistor is connected to the gate of the fourth PMOS transistor. The other end of the fourth resistor is short-circuited to the gates of the third and fourth PMOS transistors. The cascaded structure consisting of the seventh PMOS transistor, the eighth PMOS transistor, and the fifth resistor connects the drain of the fifth PMOS transistor to the source of the seventh PMOS transistor. The drain of the seventh PMOS transistor is connected to one end of the fifth resistor, and the other end of the fifth resistor is connected to the collector of the second bipolar transistor. The drain of the seventh PMOS transistor is short-circuited to the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor. The source of the eighth PMOS transistor is connected to the drain of the sixth PMOS transistor, and the drain of the eighth PMOS transistor is connected to the collector of the first bipolar transistor. The gate of the seventh PMOS transistor is connected to the gate of the eighth PMOS transistor, and the other end of the fifth resistor is short-circuited to the gate of the seventh PMOS transistor and the gate of the eighth PMOS transistor. The voltage-to-current output circuit also includes a cascaded structure consisting of an eleventh PMOS transistor, a twelfth PMOS transistor, and a seventh resistor: The cascaded structure consisting of the eleventh PMOS transistor, the twelfth PMOS transistor, and the seventh resistor connects the source of the eleventh PMOS transistor to the drain of the ninth PMOS transistor. The drain of the eleventh PMOS transistor is connected to one end of the seventh resistor, and the other end of the seventh resistor is connected to the drain of the ninth PMOS transistor. The drain of the eleventh PMOS transistor is shorted to the gates of the ninth and tenth PMOS transistors. The source of the twelfth PMOS transistor is connected to the drain of the tenth PMOS transistor, and the drain of the twelfth PMOS transistor outputs current. The gate of the eleventh PMOS transistor is connected to the gate of the twelfth PMOS transistor, and the other end of the seventh resistor is shorted to the gates of the eleventh and twelfth PMOS transistors.
2. The voltage-to-current circuit of claim 1, wherein, The ratio of the emitter area of the first bipolar transistor to the emitter area of the second bipolar transistor is 1:N, where N>1.
3. The voltage-to-current circuit of claim 1, wherein, The bandgap reference circuit outputs a reference voltage VVBG with near-zero temperature coefficient at the VBG node; The specific expression for the VBG node voltage VVBG in the bandgap reference circuit is as follows: VVBG=Vbe1+VR2=Vbe1+2(IR1) R2=Vbe1+2( Vbe / R1) R2; VR1= Vbe=Vbe1-Vbe2; VR2=2(IR1) R2=2( Vbe / R1) R2; Where VVBG is the VBG node voltage, i.e., the source voltage of the first NMOS transistor; VR1 is the voltage value of the first resistor; Vbe1 is the negative temperature coefficient voltage between the base and emitter of the first bipolar transistor; and Vbe2 is the base-emitter voltage of the second bipolar transistor. Vbe is the positive temperature coefficient voltage of the difference between the base-emitter voltage of the first bipolar transistor and the base-emitter voltage of the second bipolar transistor; VR2 is the voltage value of the second resistor; IR1 is the current value of the first resistor; R1 is the resistance value of the first resistor; and R2 is the resistance value of the second resistor. VVBG = VGN1 - Vthn; Where VGN1 is the GN1 node voltage, which is the gate voltage of the first NMOS transistor, and Vthn is the threshold voltage of the first NMOS transistor, which is the difference between the gate voltage and the source voltage of the first NMOS transistor.
4. The voltage-to-current conversion circuit according to claim 1, characterized in that, The voltage-to-current output circuit, through a system composed of the ninth PMOS transistor, the tenth PMOS transistor, the second NMOS transistor, and the sixth resistor, outputs the current IIO converted from the voltage VVBG at the IO node. The specific expression for the IO node current IIO in the voltage-to-current output circuit is as follows: IIO = VVBG / R6; Where IIO is the IO node current and R6 is the resistance value of the sixth resistor.