Address encoding method and apparatus for multi-submodule system

Abstract

The application provides an address coding method and device for a multi-submodule system, comprising the following steps: all submodules iteratively send address coding signals to the next submodule; all submodules judge whether the time of iteratively sending address coding signals reaches a preset time threshold; if yes, all submodules obtain corresponding conversion address coding values according to the received address coding signals; and all submodules determine the final address coding value according to the conversion address coding values. The application realizes the address coding process by transmitting information among multiple submodules, and does not need to control the high and low of the output level by pulling the coding switch to realize the address coding, thereby canceling the design of the coding switch and the participation of the upper system in the address coding of the submodule, so that the hardware circuit can be simplified to reduce the cost, the problem of manual misoperation can be avoided, and the accuracy of coding is ensured.

Description

Technical Field

[0001] This invention relates to the field of address encoding technology, and specifically to an address encoding method and an address encoding device for a multi-submodule system. Background Technology

[0002] With the promotion of new energy applications, battery safety management has become increasingly important. In order to better manage battery safety, it is usually necessary to encode the battery management system. Currently, the following methods are commonly used for address encoding: (1) Hardware DIP switch method: A toggle switch is set in the battery management unit (BMU) circuit. Each BMU corresponds to a different DIP switch sequence. The output level is controlled by manually toggling the switch. The CPU detects the level signal of each switch position to determine the address of the BMU; (2) Static configuration method: A unique address is assigned to the BMU through different software codes, and then the BMU is installed at fixed points according to the address sequence assigned by the software code; (3) Main module assignment method: The main module sends an address encoding message to the BMU, and then the BMU starts encoding one by one.

[0003] However, the circuit design of the above address encoding method is complex and prone to human error. Loose or faulty DIP switches can also cause address allocation errors. In addition, each BMU requires different software code, and manual installation of the BMU in the designated location according to the address sequence assigned by the code is prone to errors and makes later maintenance and upgrades difficult. Summary of the Invention

[0004] To address the aforementioned technical problems, this invention provides an address encoding method for multi-submodule systems. This method achieves address encoding by transmitting information between multiple submodules, eliminating the need to toggle an encoding switch to control the output level. This eliminates the need for an encoding switch and a main module design for address encoding, simplifying the hardware circuitry, reducing costs, avoiding human error, ensuring encoding accuracy, and providing features such as simple maintenance, high reliability, and automatic encoding.

[0005] The technical solution adopted in this invention is as follows:

[0006] An address encoding method for a multi-submodule system includes the following steps: all submodules iteratively send address encoding signals to the next submodule; all submodules determine whether the time for iteratively sending the address encoding signals has reached a preset time threshold; if so, all submodules obtain corresponding converted address encoding values ​​based on the received address encoding signals; and all submodules determine the final address encoding value based on the converted address encoding values.

[0007] According to one embodiment of the present invention, before all the submodules iteratively send the address encoding signal to the next submodule, the method further includes the step of initializing all the submodules.

[0008] According to one embodiment of the present invention, the plurality of sub-modules are peer units, and the plurality of sub-modules are connected sequentially.

[0009] According to one embodiment of the present invention, the initial signal count value after the initialization of all said submodules is a fixed constant.

[0010] According to an embodiment of the present invention, all the sub-modules iteratively send address encoding signals to the next sub-module, specifically including the following steps: after initialization, all the sub-modules send address encoding signals to the next sub-module; after receiving the address encoding signal sent by the previous sub-module, all the sub-modules send the received address encoding signal to the next sub-module, and the signal count values ​​of the sub-modules are synchronously accumulated.

[0011] According to one embodiment of the present invention, all the sub-modules obtain the corresponding converted address code value based on the received address code signal, specifically including the following steps: all the sub-modules stop sending and receiving address code signals; after all the sub-modules stop sending and receiving address code signals, each sub-module converts the signal count value of the received address code signal into the corresponding converted address code value.

[0012] According to one embodiment of the present invention, all the sub-modules determine the final address encoding value based on the converted address encoding value, specifically including the following steps: determining whether the converted address encoding value is consistent with the address encoding value stored in the sub-module; if not, replacing the address encoding value stored in the sub-module with the converted address encoding value.

[0013] According to one embodiment of the present invention, the first submodule among the plurality of submodules is not used to receive the address encoding signal, and the converted address encoding value of the first submodule is the address encoding value corresponding to the initial signal count value 1.

[0014] According to one embodiment of the present invention, all the sub-modules use the same set of software code.

[0015] An address encoding device for a multi-submodule system includes: a transmitting module, wherein each submodule iteratively transmits an address encoding signal to the next submodule via the transmitting module; a judging module, wherein each submodule judges whether the time for iteratively transmitting the address encoding signal has reached a preset time threshold; a conversion module, wherein if the time for iteratively transmitting the address encoding signal reaches the preset time threshold, the submodule obtains a corresponding converted address encoding value based on the received address encoding signal via the conversion module; and a determining module, wherein each submodule determines a final address encoding value based on the converted address encoding value via the determining module.

[0016] The beneficial effects of this invention are as follows:

[0017] 1) This invention achieves the address encoding process by sequentially connecting multiple sub-modules and transmitting information between them. It eliminates the need to toggle an encoding switch to control the output level and thus eliminates the encoding switch. This simplifies the hardware circuit, reduces costs, and avoids human error. In addition, it also avoids address allocation errors caused by loose or faulty toggle switches.

[0018] 2) By using the same set of code in all sub-modules, this invention can reduce the workload of code embedding and avoid the problem of manually installing sub-modules in non-specified locations. In addition, it also facilitates later program upgrades and maintenance.

[0019] 3) This invention automatically enters address encoding after power-on restart and initialization, without needing to communicate with the upper level or main system to receive encoding instructions sent by the upper level or main system. This eliminates the need for the design of the address encoding main module, thereby further simplifying the hardware circuit to reduce costs and reducing system complexity. Attached Figure Description

[0020] Figure 1 This is a connection diagram of multiple BMU modules in a battery management system according to an embodiment of the present invention;

[0021] Figure 2 This is a flowchart of an address encoding method for a multi-submodule system according to the present invention;

[0022] Figure 3 This is a block diagram of an address encoding device for a multi-submodule system according to an embodiment of the present invention;

[0023] Figure 4 This is a block diagram of an address encoding device for a multi-submodule system according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] It should be noted that the present invention applies to systems comprising multiple sub-modules, such as the battery management system shown in Figure 1, which includes multiple BMU modules. Furthermore, the multiple BMU modules in the battery management system are all at the same level. In addition, the multiple BMU modules can be connected sequentially, for example, through single-wire, multi-wire, visible light, or invisible light communication methods. The following will use... Figure 1 Taking a battery management system comprising multiple BMU modules as an example, the implementation process of the address encoding method and apparatus for multi-submodule systems of the present invention is specifically illustrated. Of course, it is understood that... Figure 1 The battery management system shown, which includes multiple BMU modules, is only one applicable scenario of the present invention. The present invention can also be used in other systems that include multiple sub-modules.

[0026] like Figure 2 As shown, the address encoding method for a multi-submodule system of the present invention includes the following steps:

[0027] S1, initialize all submodules.

[0028] Specifically, all sub-modules in the corresponding system can be restarted upon power-up, for example... Figure 1 The battery management system shown initializes all BMU modules, where the initial signal count value of all BMU modules after initialization is a fixed constant, for example, it can be set to 1.

[0029] S2, all submodules iteratively send address encoding signals to the next submodule.

[0030] Specifically, refer to Figure 1 In the battery management system shown, all BMU modules can send address encoding signals to the next BMU module after initialization. After receiving the address encoding signal from the previous BMU module, each BMU module can send the received address encoding signal to the next BMU module, and the signal count values ​​of the BMU modules are synchronously incremented. The address encoding signal can be a communication signal between BMU modules, such as message data, voltage, current, visible light, or invisible light communication signals.

[0031] More specifically, refer to Figure 1After startup, all BMU modules can send address-encoded signals: BMU module 1 can send address-encoded signals to BMU module 2, BMU module 2 can send address-encoded signals to BMU module 3, and so on, up to BMU module N-1 can send address-encoded signals to BMU module N. Furthermore, after receiving an address-encoded signal from a previous BMU module, each of the following modules can transmit the received address-encoded signal to the next BMU module. It should be noted that each time a BMU module receives an address-encoded signal, its signal count value is synchronously incremented by 1.

[0032] S3, all submodules determine whether the time for iteratively sending the address encoding signal has reached the preset time threshold.

[0033] Specifically, refer to Figure 1 In the battery management system shown, all BMU modules have a preset time threshold, which is the time required for all BMU modules to iteratively send all address encoding signals. Specifically, after the first BMU module (BMU module 1) completes its address encoding signal iterative sending, its signal count is 1; after the second BMU module (BMU module 2), its signal count is 2; after the third BMU module (BMU module 3), its signal count is 3; and so on, until the Nth BMU module (BMU module N) completes its address encoding signal iterative sending, its signal count is N.

[0034] S4, if so, all submodules obtain the corresponding converted address code value based on the received address code signal.

[0035] Specifically, refer to Figure 1 In the battery management system shown, all BMU modules stop sending and receiving address encoding signals. After stopping sending and receiving address encoding signals, each BMU module converts the signal count value of the received address encoding signal into the corresponding converted address encoding value.

[0036] More specifically, the first BMU module, namely BMU module 1, is not used to receive address-encoded signals, and the converted address-encoded value of the first BMU module, namely BMU module 1, is the address-encoded value corresponding to the initial signal count value 1; the converted address-encoded value of the second BMU module, namely BMU module 2, is the address-encoded value corresponding to the signal count value 2; the converted address-encoded value of the third BMU module, namely BMU module 3, is the address-encoded value corresponding to the signal count value 3; ...; the converted address-encoded value of the Nth BMU module, namely BMU module N, is the address-encoded value corresponding to the signal count value N.

[0037] S5, all submodules determine the final address encoding value based on the converted address encoding value.

[0038] Specifically, refer to Figure 1 All BMU modules in the battery management system shown can determine whether the converted address code value matches the address code value stored in the corresponding BMU module. If not, the converted address code value can replace the address code value stored in the corresponding BMU module. Conversely, if the converted address code value matches the address code value stored in the corresponding BMU module, no replacement operation is performed to retain the address code value stored in the BMU module.

[0039] It should be noted that the above steps S2-S5 do not require the participation of the upper level or the main system and can be completed in the corresponding BMU module. Furthermore, all BMU modules can store the same set of code. Thus, after all BMU modules are powered on and restarted to complete the initialization, an address encoding signal can be sent to the next BMU module. If an address encoding signal sent by the previous BMU module is received, the received address encoding signal can be sent to the next BMU module. The corresponding converted address encoding value can be obtained based on all received address encoding signals to determine the final address encoding value.

[0040] The beneficial effects of this invention are as follows:

[0041] 1) This invention achieves the address encoding process by sequentially connecting multiple sub-modules and transmitting information between them. It eliminates the need to toggle an encoding switch to control the output level and thus eliminates the encoding switch. This simplifies the hardware circuit, reduces costs, and avoids human error. In addition, it also avoids address allocation errors caused by loose or faulty toggle switches.

[0042] 2) By using the same set of code in all sub-modules, this invention can reduce the workload of code embedding and avoid the problem of manually installing sub-modules in non-specified locations. In addition, it also facilitates later program upgrades and maintenance.

[0043] 3) This invention automatically enters address encoding after power-on restart and initialization, without needing to communicate with the upper level or main system to receive encoding instructions sent by the upper level or main system. This eliminates the need for the design of the address encoding main module, thereby further simplifying the hardware circuit to reduce costs and reducing system complexity.

[0044] Corresponding to the address encoding method for multi-submodule systems in the above embodiments, the present invention also proposes an address encoding device for multi-submodule systems.

[0045] like Figure 3 As shown, the address encoding device for a multi-submodule system according to an embodiment of the present invention includes a sending module 10, a judging module 20, a conversion module 30, and a determining module 40. The submodule iteratively sends address encoding signals to the next submodule via the sending module 10; the submodule judges whether the time for iteratively sending the address encoding signals has reached a preset time threshold via the judging module 20; if the time for iteratively sending the address encoding signals has reached the preset time threshold, the submodule obtains the corresponding converted address encoding value based on the received address encoding signals via the conversion module 30; the submodule determines the final address encoding value based on the converted address encoding value via the determining module 40.

[0046] It should be noted that the sending module 10, the judging module 20, the conversion module 30, and the determining module 40 can be set in all sub-modules of the corresponding system, for example... Figure 1 In the battery management system shown, each BMU module can complete the address encoding process without the need for control from the upper level or the main system. All BMU modules can store the same set of code. Therefore, after all BMU modules are powered on and restarted to complete the initialization, an address encoding signal can be sent to the next BMU module. If an address encoding signal is received from the previous BMU module, the received address encoding signal can be sent to the next BMU module. The corresponding converted address encoding value can be obtained based on all received address encoding signals to determine the final address encoding value.

[0047] In one embodiment of the present invention, such as Figure 4 As shown, the address encoding device for a multi-submodule system may further include an initialization module 50, which can be used for initialization. Figure 1 Each BMU module in the battery management system is shown.

[0048] Specifically, the initialization module 50 can be used to power on and restart all BMU modules to initialize all BMU modules. The initial signal count value after the initialization of all BMU modules is a fixed constant, for example, it can be set to 1.

[0049] In one embodiment of the present invention, after startup, all BMU modules can send an address encoding signal to the next BMU module via the sending module 10. After receiving the address encoding signal sent by the previous BMU module, all BMU modules can send the received address encoding signal to the next BMU module, and the signal count values ​​of the BMU modules are synchronously accumulated. The address encoding signal can be a communication signal between BMU modules, such as message data, voltage, current, visible light, or invisible light communication signals.

[0050] More specifically, refer to Figure 1 After startup, all BMU modules can send address-encoded signals: BMU module 1 can send address-encoded signals to BMU module 2, BMU module 2 can send address-encoded signals to BMU module 3, and so on, up to BMU module N-1 can send address-encoded signals to BMU module N. Furthermore, after receiving an address-encoded signal from a previous BMU module, each of the following modules can transmit the received address-encoded signal to the next BMU module. It should be noted that each time a BMU module receives an address-encoded signal, its signal count value is synchronously incremented by 1.

[0051] In one embodiment of the present invention, the preset time threshold is the time corresponding to when all BMU modules have iteratively sent all address encoding signals, that is, the time corresponding to when each BMU module has completed the iterative sending of address encoding signals. It should be noted that after the first BMU module, i.e., BMU module 1, completes the iterative sending of address encoding signals, its corresponding signal count value is 1; after the second BMU module, i.e., BMU module 2, completes the iterative sending of address encoding signals, its corresponding signal count value is 2; after the third BMU module, i.e., BMU module 3, completes the iterative sending of address encoding signals, its corresponding signal count value is 3, ..., and after the Nth BMU module, i.e., BMU module N, completes the iterative sending of address encoding signals, its corresponding signal count value is N.

[0052] In one embodiment of the present invention, if the time for iteratively sending the address encoding signal reaches a preset time threshold, all BMU modules can stop sending and receiving the address encoding signal. After all BMU modules stop sending and receiving the address encoding signal, each BMU module can convert the signal count value of the received address encoding signal into the corresponding converted address encoding value through the conversion module 30.

[0053] More specifically, the first BMU module, namely BMU module 1, may not be used to receive address-encoded signals, and the converted address-encoded value of the first BMU module, namely BMU module 1, is the address-encoded value corresponding to the initial signal count value 1; the converted address-encoded value of the second BMU module, namely BMU module 2, is the address-encoded value corresponding to the signal count value 2; the converted address-encoded value of the third BMU module, namely BMU module 3, is the address-encoded value corresponding to the signal count value 3; ...; the converted address-encoded value of the Nth BMU module, namely BMU module N, is the address-encoded value corresponding to the signal count value N.

[0054] In one embodiment of the present invention, the BMU module can determine, through the determining module 40, whether the converted address code value is consistent with the address code value stored in the corresponding BMU module. If not, the converted address code value can replace the address code value stored in the corresponding BMU module. Furthermore, if the converted address code value is consistent with the address code value stored in the corresponding BMU module, no replacement operation is performed to retain the address code value stored in the BMU module.

[0055] The beneficial effects of this invention are as follows:

[0056] 1) This invention achieves the address encoding process by sequentially connecting multiple sub-modules and transmitting information between them. It eliminates the need to toggle an encoding switch to control the output level and thus eliminates the encoding switch. This simplifies the hardware circuit, reduces costs, and avoids human error. In addition, it also avoids address allocation errors caused by loose or faulty toggle switches.

[0057] 2) By using the same set of code in all sub-modules, this invention can reduce the workload of code embedding and avoid the problem of manually installing sub-modules in non-specified locations. In addition, it also facilitates later program upgrades and maintenance.

[0058] 3) This invention automatically enters address encoding after power-on restart and initialization, without needing to communicate with the upper level or main system to receive encoding instructions sent by the upper level or main system. This eliminates the need for the design of the address encoding main module, thereby further simplifying the hardware circuit to reduce costs and reducing system complexity.

[0059] In the description of this invention, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. "A plurality of" means two or more, unless otherwise explicitly specified.

[0060] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0061] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "beneath" of the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0062] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. An address encoding method for a multi-submodule system, characterized in that, Includes the following steps: All of the aforementioned submodules iteratively send address encoding signals to the next submodule; All the aforementioned sub-modules determine whether the time for iteratively sending the address encoding signal has reached a preset time threshold; If so, all the aforementioned submodules obtain the corresponding converted address code value based on the received address code signal; All the aforementioned submodules determine the final address encoding value based on the converted address encoding value. All submodules iteratively send address-encoded signals to the next submodule, specifically including the following steps: After initialization, all submodules send address-encoded signals to the next submodule; after receiving the address-encoded signal sent by the previous submodule, all submodules send the received address-encoded signal to the next submodule, and the signal count values ​​of the submodules are synchronously incremented. All the aforementioned submodules then obtain the corresponding converted address code value based on the received address code signal, specifically including the following steps: all the aforementioned submodules stop sending and receiving address code signals; after all the aforementioned submodules stop sending and receiving address code signals, each of the aforementioned submodules converts the signal count value of the received address code signal into the corresponding converted address code value. All the sub-modules determine the final address encoding value based on the converted address encoding value, specifically including the following steps: determining whether the converted address encoding value is consistent with the address encoding value stored in the sub-module; if not, replacing the address encoding value stored in the sub-module with the converted address encoding value.

2. The address encoding method for a multi-submodule system according to claim 1, characterized in that, Before all the aforementioned submodules iteratively send address-encoded signals to the next submodule, the following steps are also included: Initialize all the aforementioned submodules.

3. The address encoding method for a multi-submodule system according to claim 2, characterized in that, The multiple sub-modules are at the same level and are connected sequentially among themselves.

4. The address encoding method for a multi-submodule system according to claim 3, characterized in that, The initial signal count value after all the submodules are initialized is a fixed constant.

5. The address encoding method for a multi-submodule system according to claim 3, characterized in that, The first of the plurality of submodules is not used to receive the address encoding signal, and the converted address encoding value of the first submodule is the address encoding value corresponding to the initial signal count value 1.

6. The address encoding method for a multi-submodule system according to claim 1, characterized in that, All the submodules use the same set of software code.

7. An address encoding apparatus for a multi-submodule system that implements the address encoding method for a multi-submodule system according to any one of claims 1-6, characterized in that, include: The sending module, through which the submodule iteratively sends the address-encoded signal to the next submodule; The judgment module determines whether the time for iteratively sending the address encoding signal has reached a preset time threshold. If the time for iteratively sending the address encoding signal reaches a preset time threshold, the submodule obtains the corresponding converted address encoding value based on the received address encoding signal through the conversion module. The determination module, in which the submodule determines the final address encoding value based on the converted address encoding value, is used by the determination module.

Images