UVM-based verification system for cache coherency

Abstract

The application relates to a UVM-based memory bank replacement consistency verification system. The system comprises an excitation module, a sequence module, an RFM reference model, a data acquisition module and a verification module; the excitation module is used for acquiring input signals through an interface; the sequence module is used for giving corresponding numerical values and constraint conditions to the input signals to form data packets; the RFM reference model is used for receiving the data packets and performing standard calculation on the data packets to obtain standard results; the standard results are sent to the verification module; the data acquisition module is used for acquiring data of a replaced memory bank; and the verification module is used for comparing the standard results and the data of the replaced memory bank to obtain verification results. The method can improve the memory bank replacement consistency verification efficiency.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit verification, in particular to a memory bank replacement consistency verification system based on UVM, a computer device and a storage medium. BACKGROUND

[0002] With the development of integrated circuit verification technology, when developing and designing small integrated circuits, the memory bank involved is relatively small. When the process and performance are improved, the memory bank needs to be replaced. Errors may occur during the replacement process. These errors are difficult to find and can only be found by full function and full system verification. Therefore, it takes a lot of manpower and time to complete all functions and traverse every possible situation.

[0003] However, with the continuous increase of IC design scale, the number of memory banks is also increasing, and the verification of memory bank replacement consistency will also take more and more time. It will spend too much project time and delay the progress of the project. SUMMARY

[0004] Therefore, it is necessary to provide a memory bank replacement consistency verification system and method based on UVM, a computer device and a storage medium, which can improve the efficiency of memory bank replacement consistency verification.

[0005] A memory bank replacement consistency verification system based on UVM, the system comprises: an excitation module, a sequence module, an RFM reference model, a data acquisition module and a verification module;

[0006] The excitation module is used to obtain an input signal through an interface;

[0007] The sequence module is used to give the input signal corresponding numerical values and constraint conditions to form a data packet;

[0008] The RFM reference model is used to receive the data packet and perform standard calculation on the data packet to obtain a standard result; and send the standard result to the verification module;

[0009] The data acquisition module is used to acquire data of a replaced memory bank;

[0010] The verification module is used to compare the standard result with the data of the replaced memory bank to obtain a verification result.

[0011] In one embodiment, the excitation module is further used to register the input signal after randomization processing in the UVM.

[0012] In one of the embodiments, the verification module is further configured to define a data collection channel to collect channel data, and place the RFM reference model and the data of the replaced memory bank into different arrays according to the channel data; and when the array storing the replaced memory bank is determined to be not empty, call a check function to compare the data and obtain a verification result.

[0013] In one of the embodiments, the sequence module is further configured to give the input signal a corresponding read-write address, read-write data, read-write data interval time, and read-write sequence, and set the read-write address, read-write data, read-write data interval time, and read-write sequence according to the constraint conditions of the type of the memory bank.

[0014] In one of the embodiments, the system further comprises a packaging module and a driving module; the packaging module is configured to package the sequence module and the driving module.

[0015] In one of the embodiments, the driving module is configured to drive the input signal and the data packet to the replaced memory bank and the RFM reference model, respectively.

[0016] In one of the embodiments, the system is further configured to package the packaging module, the data collection module, the RFM reference model, and the verification module into a system environment module.

[0017] In one of the embodiments, the driving module of the verification system is connected to the input of the replaced memory bank; and the output of the replaced memory bank is connected to the read data of the data collection module.

[0018] A verification method for memory bank replacement consistency based on UVM, the method comprising:

[0019] acquiring an input signal;

[0020] giving the input signal corresponding numerical values and constraint conditions to form a data packet;

[0021] performing standard calculation on the data packet to obtain a standard result; and collecting data of a replaced memory bank;

[0022] comparing the standard result and the data of the replaced memory bank to obtain a verification result.

[0023] A computer device comprising a memory and a processor, the memory storing a computer program, and the processor implementing the following steps when executing the computer program:

[0024] acquiring an input signal;

[0025] giving the input signal corresponding numerical values and constraint conditions to form a data packet;

[0026] performing standard calculation on the data packet to obtain a standard result; and

[0027] collecting data of the replaced memory bank;

[0028] comparing the standard result and the data of the replaced memory bank to obtain a verification result.

[0029] A computer readable storage medium having stored thereon a computer program, the computer program being executed by a processor to implement the following steps:

[0030] obtaining an input signal;

[0031] composing a data packet by giving the input signal corresponding numerical values and constraint conditions;

[0032] performing standard calculation on the data packet to obtain a standard result;

[0033] collecting data of the replaced memory bank;

[0034] comparing the standard result and the data of the replaced memory bank to obtain a verification result.

[0035] The above-mentioned UVM-based memory bank replacement consistency verification system, method, computer device and storage medium, the application sets an excitation module for obtaining an input signal through an interface, a sequence module for composing a data packet by giving the input signal corresponding numerical values and constraint conditions, and an RFM reference model for receiving the data packet and performing standard calculation thereon to obtain a standard result. The standard result is sent to a verification module, a data collection module is used to collect data of a replaced memory bank, and the verification module is used to compare the standard result and the data of the replaced memory bank to obtain a verification result. A packaging module, the data collection module, the RFM reference model and the verification module are packaged as a system environment module. In the system environment module, key parameters and data in the UVM environment are parameterized, forming a parameterized configuration file. In subsequent projects or later design processes, if the design of a component is changed or modified, only the input signal needs to be modified, without modifying the entire environment platform. At the same time, according to the constraint conditions, more types of data can be input in the shortest possible time, the entire verification platform is standardized, and the verification period and workload can be greatly reduced. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 A structural block diagram of a UVM-based memory bank replacement consistency verification system in one embodiment;

[0037] Figure 2 A flowchart of a UVM-based memory bank replacement consistency verification method in one embodiment;

[0038] Figure 3Fig. 1 is a diagram of an internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0039] For the purpose of the present application, technical solutions and advantages, the following will be further described in detail in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and are not used to limit the present application.

[0040] In one embodiment, as shown in Fig. 1, a UVM-based memory bank replacement consistency verification system is provided, including an excitation module, a sequence module, an RFM reference model, a data acquisition module and a verification module. Figure 1

[0041] The excitation module is used to obtain input signals through an interface.

[0042] The sequence module is used to give corresponding numerical values and constraint conditions to the input signals to form a data packet.

[0043] The RFM reference model is used to receive the data packet and perform standard calculation on the data packet to obtain a standard result; the standard result is sent to the verification module.

[0044] The data acquisition module is used to acquire data of a replaced memory bank.

[0045] The verification module is used to compare the standard result and the data of the replaced memory bank to obtain a verification result.

[0046] In the above UVM-based memory bank replacement consistency verification system, the present application sets the excitation module to obtain input signals through an interface, the sequence module to give corresponding numerical values and constraint conditions to the input signals to form a data packet, the RFM reference model to receive the data packet and perform standard calculation on the data packet to obtain a standard result; the standard result is sent to the verification module, the data acquisition module is used to acquire data of a replaced memory bank, and the verification module is used to compare the standard result and the data of the replaced memory bank to obtain a verification result. The packaging module, the data acquisition module, the RFM reference model and the verification module are packaged as a system environment module, the key parameters and data in the UVM environment are parameterized in the system environment module, a parameterized configuration file is formed, and if the design of a component is changed or modified in a subsequent project or a later design process, only the input signal needs to be modified, the entire environment platform does not need to be modified, at the same time, according to the constraint condition, the sending of data can input more types of data in the shortest possible time, the entire verification platform is standardized, the verification period can be greatly shortened, and the verification workload can be reduced.

[0047] ​In one of the embodiments, the excitation module is further configured to register the input signal into the UVM after randomizing the input signal.

[0048] In a specific embodiment, the input signal is registered into the UVM after randomizing the input signal, so that the driving module can be used to drive the data.

[0049] In one of the embodiments, the verification module is further configured to define a data collection channel to collect channel data, and according to the channel data, put the data of the RFM reference model and the replaced memory bank into different arrays; and when the array storing the replaced memory bank is not empty, call the check function to compare the data and obtain a verification result.

[0050] In one of the embodiments, the sequence module is further configured to give the input signal corresponding read-write addresses, read-write data, read-write data interval time, and read-write sequence, and set the read-write addresses, read-write data, read-write data interval time, and read-write sequence according to the constraint conditions of the type of the memory bank.

[0051] In a specific embodiment, the constraint conditions of the read-write addresses, read-write data, read-write data interval time, and read-write sequence are set according to the type of the memory bank. For example, if the memory bank size is only 1 MB or 2 MB, the range of the read-write addresses should be set to 1 MB or 2 MB. For example, if the memory bank is a single port and can only handle one write or one read at a time, the constraint condition is set to send only one read or one write at a time.

[0052] In one of the embodiments, the system further comprises a packaging module and a driving module; the packaging module is configured to package the sequence module and the driving module.

[0053] In one of the embodiments, the driving module is configured to drive the input signal and the data packet to the replaced memory bank and the RFM reference model, respectively.

[0054] In a specific embodiment, the input signal and the data packet are driven to the replaced memory bank, respectively, to obtain the data of the replaced memory bank, which is used for subsequent comparison with the result of the reference model to obtain a verification result.

[0055] In one of the embodiments, the system is further configured to package the packaging module, the data collection module, the RFM reference model, and the verification module into a system environment module.

[0056] In a specific embodiment, the packaging module, the data collection module, the RFM reference model, and the verification module are packaged into a system environment module, so that when the memory bank is verified later, the verification environment does not need to be reconfigured, and only the input signal of the excitation module needs to be changed to achieve the verification of the memory bank without modifying the entire environment platform.

[0057] In one embodiment, the drive module of the verification system is connected to the input of the replacement memory bank; the output of the replacement memory bank is connected to the read data of the data collection module.

[0058] In one embodiment, the RFM reference model is also used to receive data packets and perform standard calculations on the data packets to obtain standard results.

[0059] In a specific embodiment, the standard calculation on the data packets is an SDRAM read operation and an SDRAM write operation on the data packets, and the addresses read and written are the standard results.

[0060] The SDRAM read operation is specifically that when the EMIFA receives a request from a request source to read the SDRAM, the controller performs one or more read access cycles. The read access cycle first performs an ACTV command to select a target slot and a row in the SDRAM. After opening the row, the EMIFA then performs a read command while specifying a target slot and a column address. During the read command, EMA_A

[10] is pulled low to avoid automatic precharge. The read command informs the SDRAM to output data from the specified address when the EMIFA performs a NOP command. Following the read command, the CL value in the SDCR register defines how many clock cycles after the data starts to be output to the data bus. This delay is the CAS delay. The EMIFA truncates the excess data in a burst of data to complete the current request. The EMIFA truncates a burst of data in the following three ways:

[0061] By performing another read operation, data in the same slot and page is read.

[0062] By performing a PRE command, a different page in the same slot is prepared for access.

[0063] By performing a BT command, a page in a different slot is prepared for access.

[0064] During the read access, several other pins are also activated. EMA_WE_DQM[1:0] is pulled low during the read command and remains low during the NOP command to satisfy the burst request. The EMIFA schedules the command based on the time parameters defined in the SDTIMR register. The time parameters in this register must satisfy the parameters defined in the SDRAM data manual. The EMIFA uses the time parameters to avoid violating the SDRAM limits when performing the command. Usually, a NOP is inserted between various commands to accomplish this.

[0065] A SDRAM write operation is specifically when EMIFA receives a request from a requestor to write to SDRAM, the controller performs one or more write access cycles. A write access cycle first performs an ACTV command to select the target bank and row in SDRAM. After opening the row, EMIFA then performs a write command while specifying the target bank and column address. During the write command, EMA_A

[10] is pulled low to avoid auto precharge. The write command informs SDRAM to write data from the specified address when EMIFA performs a NOP command. The corresponding data is driven on the data bus starting at the beginning of the write command and continuing through the subsequent NOP command. EMIFA will truncate the excess data in a burst to complete the current request. There are three ways EMIFA can truncate a burst:

[0066] By performing another write operation, writing data to the same bank and page.

[0067] By performing a PRE command, preparing for access to the same bank, different page.

[0068] By performing a BT command, preparing for access to a page in a different bank.

[0069] During a write access, several other pins are also activated. EMA_WE_DQM[1:0] are pulled low during the write command and remain low during the NOP command to satisfy the burst request. EMIFA schedules commands based on the timing parameters defined in the SDTIMR register. The timing parameters in this register must satisfy the parameters defined in the SDRAM data sheet. EMIFA uses these timing parameters to avoid violating SDRAM limits when performing commands. This is usually done by inserting NOPs between various commands.

[0070] In one embodiment, as shown in FIG. 1, a UVM-based memory replacement coherency verification method is provided, comprising: Figure 2

[0071] Step 102, obtaining an input signal; giving the input signal a corresponding numerical value and constraint condition to form a data packet.

[0072] ​The corresponding numerical values include read-write address, read-write data, read-write data interval time, read-write sequence, and setting read-write address, read-write data, read-write data interval time, and read-write sequence according to the constraint conditions of the type of the memory bank, such as the memory bank size is only 1MB or 2MB, the range of the read-write address should be set to 1MB or 2MB, for example, the memory bank is a single port, and only one write or one read can be processed at a time, and the constraint condition is set to only one read or one write can be sent at a time. According to the constraint condition, more types of data can be input in the shortest possible time, the entire verification process is standardized, and the verification period and workload can be greatly reduced.

[0073] In step 104, standard calculation is performed on the data packet to obtain a standard result, and data of the replaced memory bank is collected.

[0074] In step 106, the standard result and the data of the replaced memory bank are compared to obtain a verification result.

[0075] In the above-mentioned UVM-based memory bank replacement consistency verification method, the key parameters and data in the UVM environment are parameterized and set to form a parameterized configuration file. If the design of the component is changed or modified in the subsequent project or later design process, only the input signal needs to be modified. At the same time, according to the constraint condition, more types of data can be input in the shortest possible time, the entire verification process is standardized, and the verification period and workload can be greatly reduced.

[0076] It should be understood that, although Figure 2 The steps in the flowchart of the method are displayed in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, the execution of these steps is not strictly limited in sequence, and these steps can be executed in other orders. Moreover, Figure 2 At least part of the steps in the method can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be alternately executed with other steps or sub-steps or stages of other steps.

[0077] The specific definition of the UVM-based memory bank replacement consistency verification system can refer to the definition of the UVM-based memory bank replacement consistency verification method, which will not be repeated here. Each module in the UVM-based memory bank replacement consistency verification system can be implemented by software, hardware, and a combination thereof, in whole or in part. Each module can be embedded in or independent of the processor in the computer device in hardware form, or stored in the memory in the computer device in software form, so that the processor can call and execute the operation corresponding to each module.

[0078] In one embodiment, a computer device, which can be a terminal, has an internal structure as shown in Figure 3 The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is configured to communicate with external terminals through a network connection. The computer program is executed by the processor to implement a UVM-based memory bank replacement consistency verification method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball, or touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0079] Those skilled in the art can understand that Figure 3 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different component arrangement.

[0080] In one embodiment, a computer device is provided, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the steps of the method in the above embodiments.

[0081] In one embodiment, a computer storage medium is provided, which stores a computer program. The computer program is executed by a processor to implement the steps of the method in the above embodiments.

[0082] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in the embodiments provided by the present application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0083] The technical features of the above embodiments can be combined in any way. In order to make the description simple, not all possible combinations of the technical features in the above embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as the scope of the present application.

[0084] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, some modifications and improvements can be made, which are all within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. A memory bank replacement consistency verification system based on UVM, characterized in that, The system comprises an excitation module, a sequence module, an RFM reference model, a data acquisition module and a verification module; The excitation module is configured to obtain an input signal through an interface; The sequence module is configured to give the input signal corresponding numerical values and constraint conditions to form a data packet, and give the input signal corresponding read-write addresses, read-write data, read-write data interval times, read-write sequences, and set constraint conditions of the read-write addresses, read-write data, read-write data interval times and read-write sequences according to the type of the memory bank; The RFM reference model is configured to receive the data packet and perform standard calculation on the data packet to obtain a standard result, and send the standard result to the verification module; The data acquisition module is configured to acquire data of a replacement memory bank; The verification module is configured to compare the standard result and the data of the replacement memory bank to obtain a verification result; The verification module is further configured to define a data acquisition channel to collect channel data, place the RFM reference model and the data of the replacement memory bank into different arrays according to the channel data, and judge the array storing the replacement memory bank, and call a check function to perform data comparison to obtain the verification result when the array storing the replacement memory bank is not empty; The system further comprises a packaging module and a driving module; the packaging module is configured to package the sequence module and the driving module; The driving module is configured to drive the input signal and the data packet to the replacement memory bank and the RFM reference model, respectively.

2. The verification system of claim 1, wherein, The excitation module is further configured to register the input signal to UVM after randomization processing.

3. The verification system of claim 1, wherein, The system is further configured to package the packaging module, the data acquisition module, the RFM reference model and the verification module into a system environment module.

4. The verification system of claim 3, wherein, The driving module of the verification system is connected with the input of the replacement memory bank, and the output of the replacement memory bank is connected with the read data of the data acquisition module. 5.A method for verifying a UVM-based memory bank replacement coherency, characterized in that, The method comprises: obtaining an input signal; giving the input signal corresponding numerical values and constraint conditions to form a data packet, including giving the input signal corresponding read-write addresses, read-write data, read-write data interval times, read-write sequences, and setting constraint conditions of the read-write addresses, read-write data, read-write data interval times and read-write sequences according to the type of the memory bank; performing standard calculation on the data packet to obtain a standard result; acquiring data of a replacement memory bank, and driving the input signal and the data packet to the replacement memory bank and the RFM reference model, respectively; comparing the standard result and the data of the replacement memory bank to obtain a verification result, including: defining a data acquisition channel to collect channel data, placing the RFM reference model and the data of the replacement memory bank into different arrays according to the channel data, and judging the array storing the replacement memory bank, and calling a check function to perform data comparison to obtain the verification result when the array storing the replacement memory bank is not empty. 6.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is configured to perform the method according to any one of claims 1-5 when the computer program is executed by the processor. The processor executes the computer program to realize the steps of the method of claim 5.

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