Sense amplifier for current sensing

Abstract

The present disclosure relates to integrated circuits, and more particularly, to sense amplifier circuits for current sensing in memory structures, and methods of manufacturing and operating the circuits. Specifically, the present disclosure relates to a circuit comprising: a sensing circuit comprising a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bit line capacitor; and a comparator differential circuit that receives a data sense voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.

Description

Technical Field

[0001] The present disclosure relates to integrated circuits and, more particularly, to sense amplifier circuits for current sensing in memory structures and methods of fabrication and operation. Background Art

[0002] In memory, a sense amplifier is one of the components that make up the circuitry on a semiconductor memory chip. The sense amplifier is part of the read circuitry used when reading data from the memory. The sense amplifier senses the low-power signal from the bit line representing the data bit (1 or 0) stored in the memory cell and amplifies the small voltage swing to a recognizable logic level so that the data can be integrated by logic external to the memory.

[0003] In static random access memory (SRAM) operation, to read a bit from a specific memory cell, the word line along the row of specific memory cells is turned on, which activates all cells in the row. The stored value (0 or 1) from the specific memory cell is then sent to the bit line associated with the specific memory cell. The sense amplifier at the end of the two complementary bit lines amplifies the small voltage to normal logic levels. The bit from the desired cell is then latched from the sense amplifier of the specific memory cell into a buffer and placed on the output bus.

[0004] In dynamic random access memory (DRAM) operation, sense amplifiers are similar to SRAM but perform additional functions. Specifically, data in a DRAM chip is stored as charge in capacitors within the memory cells. A read operation depletes the charge in the cell, destroying the data. Therefore, after reading the data, the sense amplifier must immediately write the data back to the cell by applying a voltage to the cell (i.e., a memory refresh). In known circuits such as the one described above, a large amount of area is used and a large amount of power is consumed. Summary of the Invention

[0005] In one aspect of the present disclosure, a structure includes: a sensing circuit comprising a first group of transistors configured to sense a current difference between a reference cell current and a current from a selected one of a first data cell circuit and a second data cell circuit, and output the current difference as a data sensing voltage signal to a differential circuit; and a reference voltage holding circuit comprising a second group of transistors configured to hold a reference voltage level and output the reference voltage level to the differential circuit.

[0006] In another aspect of the present disclosure, a circuit includes: a sensing circuit comprising a first group of transistors, at least one data unit circuit, and a reference unit circuit; a reference voltage holding circuit comprising a second group of transistors and a bit line capacitor; and a comparator differential circuit that receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal.

[0007] In another aspect of the present disclosure, a method includes: selecting one of a first data unit circuit and a second data unit circuit using a sensing circuit; converting a current difference between a reference cell current of a reference unit circuit and a current from the selected one of the first data unit circuit and the second data unit circuit into a data sensing voltage signal using the sensing circuit; maintaining a reference voltage level using a reference voltage holding circuit; and outputting the data sensing voltage signal and the reference voltage level to a differential comparator circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure is described in the following detailed description by way of non-limiting examples of exemplary embodiments thereof and with reference to the several accompanying drawings.

[0009] Figure 1 A sense amplifier circuit for current sensing in a memory structure is shown according to aspects of the present disclosure.

[0010] Figure 2 A reference voltage holding circuit for a sense amplifier circuit in a memory structure according to aspects of the present disclosure is shown.

[0011] Figure 3 A timing diagram of a sense amplifier circuit in a memory structure according to aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0012] The present disclosure relates to integrated circuits and, more particularly, to sense amplifier circuits for current sensing in memory structures and methods of manufacture and operation. More particularly, the present disclosure relates to sense amplifier circuits for current sensing memory systems. In an embodiment, the sense amplifier circuit includes a simplified reference path for reference voltage maintenance and leakage / load matching and a sense path for selecting between a top array and a bottom array. In this way, the bit line switches of unselected banks do not need to be powered up, which saves overall read power. Advantageously, the structure described herein saves approximately 50% of the differential sense amplifier area and saves approximately 25% of the overall read power.

[0013] In a known circuit, a reference voltage is stored on one branch and a data sensing voltage is simultaneously generated on the other branch. Differential sensing is used to compare the two branches. The circuit also uses a symmetrical path to provide input to the comparator. In other known circuits, time interleaving is used to generate a reference voltage, store the reference voltage on a capacitor, and then generate a data sensing voltage. The reference voltage and the data sensing voltage are then compared. However, compared to the present disclosure, the known circuit with a sense amplifier uses a large amount of area (e.g., double the area compared to the present disclosure) and consumes a large amount of power for current-to-voltage amplification in the memory system, and the sense amplifier has a bit line precharge circuit for reading the flash memory cells in the array. In particular, the known circuit with a sense amplifier consumes additional power (e.g., 4 / 3 the power compared to the present disclosure) to turn on the bit line switch in the unselected library, and the sense amplifier has a bit line precharge circuit for reading the flash memory cells in the array. In contrast, the sense amplifier circuit includes an embedded flash memory (eflash) sense amplifier with a single current-to-voltage amplification path, which does not require simultaneous dual branch circuit paths, additional test circuit logic, time interleaving, and additional power consumption when turning on unselected banks.

[0014] Figure 1 A sense amplifier circuit for current sensing in a memory structure according to aspects of the present disclosure is shown. Sense amplifier circuit 10 includes comparators 20, 60, a reference unit circuit 30, data unit circuits 40, 50, a reference voltage holding circuit 70, a capacitor 75, and transistors M0 to M9. Reference voltage holding circuit 70 includes transistors M2, M8, and capacitor 75. Transistors M0, M1, M3, M4, M7, and M8 may be p-type metal oxide semiconductor (PMOS) transistors, while transistors M2, M5, M6, and M9 may be n-type metal oxide semiconductor (NMOS) transistors.

[0015] In operation, the comparator 20 receives a reference voltage VREF and a feedback signal from the drain of the transistor M3 and outputs a signal to the gate of the transistor M0. The feedback signal from the drain of the transistor M3 can be used to convert the current of the reference voltage VREF into a sensing reference unit signal CASREF. In particular, the feedback signal (i.e., a negative feedback loop) forces the drain of the transistor M3 to track the reference voltage VREF and provide a driving capability for the sensing reference unit signal CASREF. Thus, the transistors M0 and M1 can carry the reference unit current generated by the reference unit circuit 30 biased at an appropriate voltage level. The source of the transistor M0 receives the first power supply voltage VDD, and the drain of the transistor M0 is connected to the source of the transistor M3. The gate of the transistor M3 can be connected to the enable signal EN_B, and the drain of the transistor M3 can be connected to the reference unit circuit 30.

[0016] exist Figure 1 In the embodiment of the present invention, the gate of transistor M1 can be connected to the sensing reference cell signal CASREF. The source of transistor M1 can be connected to the first power supply voltage VDD, and the drain of transistor M1 can be connected to the source of transistor M4. Transistor M1 carries the reference cell current of reference cell circuit 30. Further, the reference cell current is transmitted to the first input / output resolving signal IOR during the sensing operation.

[0017] The gate of transistor M4 can be connected to the sensing signal SEN_B, and the drain of transistor M4 can be connected to the first input / output resolution signal IOR (e.g., a data sensing voltage signal). The drains of transistors M5 and M6 can also be connected to the first input / output resolution signal IOR.

[0018] The gate of transistor M5 can be connected to column top signal COL_TOP, and the source of transistor M5 can be connected to data cell circuit 40. The gate of transistor M6 can be connected to column bottom signal COL_BOT, and the source of transistor M6 can be connected to data cell circuit 50. In particular, column top signal COL_TOP enables data cell circuit 40 to be selected, while column bottom signal COL_BOT enables data cell circuit 50 to be selected. Therefore, one of column top signal COL_TOP and column bottom signal COL_BOT can be enabled at a time to select the corresponding one of data cell circuit 40 and data cell circuit 50.

[0019] Still refer to Figure 1 , the gate of transistor M7 can be connected to the control signal ATDb. The source of transistor M7 can be connected to the reference voltage VREF, and the drain of transistor M7 is connected to the first input / output resolution signal IOR. The drain of transistor M9 can be connected to the comparator 60, and the source of transistor M9 can be connected to the ground GND. The gate of transistor M9 can be connected to the comparison enable signal CMP_EN. In operation, after sufficient current accumulates in the first input / output resolution signal IOR, the comparison enable signal CMP_EN can be turned on, and then the comparator 60 can be enabled. The comparator 60 receives the first input / output resolution signal IOR (e.g., the data sensing voltage signal) and the second input / output resolution signal REFIOR (e.g., the reference voltage level), and outputs the output signal OUT when the comparator 60 is enabled (i.e., when the comparison enable signal CMP_EN enables the gate of transistor M9 and thus enables the comparator 60). The reference voltage holding circuit 70 includes transistors M2, M8 and a capacitor 75, and will Figure 2 It is described in further detail in .

[0020] exist Figure 1 In operation, there are two input paths to the comparator 60. In the first path for the first input / output resolution signal IOR, the current difference between the reference cell circuit 30 and the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) is converted into a voltage. Therefore, the first path for the first input / output resolution signal IOR implements current-to-voltage conversion. Compared to known circuits, the first path for the first input / output resolution signal IOR also eliminates the multiplexer for bottom or top bank selection within the sense amplifier.

[0021] In the second path for the second input / output resolution signal REFIOR, the reference voltage level (VREF) is maintained (i.e., held). Furthermore, compared to conventional circuits, the second path for the second input / output resolution signal REFIOR eliminates logic for testing circuits, eliminates a reference current pin, and eliminates a voltage clamp. Therefore, the second path for the second input / output resolution signal REFIOR has fewer components than conventional circuits, saving area and read power. Comparator 60 then compares the first path and the second path and outputs an output signal OUT.

[0022] In further operation, if the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) is equal to the reference cell current in the transistor M1, the first input / output resolution signal IOR is maintained at the same reference voltage level (VREF) as the second input / output resolution signal REFIOR. If the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) is greater than the reference cell current in the transistor M1, the first input / output resolution signal IOR is pulled down to a low level (e.g., pulled down to ground GND). If the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) is less than the reference cell current in the transistor M1, the first input / output resolution signal IOR is pulled up to a high level (e.g., pulled up to the first power supply voltage VDD). In other words, the first input / output resolution signal IOR generates a current that is different from the reference cell current in the transistor M1 and the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50).

[0023] Figure 2A reference voltage hold circuit for a sense amplifier circuit in a memory structure is shown. Reference voltage hold circuit 70 includes transistor M8 having a gate connected to control signal ATDb. The source of transistor M8 can be connected to voltage reference VREF, and the drain of transistor M8 can be connected to the drain of transistor M2. The drain of transistor M2 can be connected to capacitor 75. The gate of transistor M2 can be connected to the source of transistor M2. In addition, the gate and source of transistor M2 can be grounded. Therefore, transistor M2 can be turned off to simulate leakage of a turned-off multiplexer device located on one side of the first input / output resolution signal IOR.

[0024] In operation, transistor M8 can be controlled by control signal ATDb to precharge the second input / output resolve signal REFIOR to voltage reference VREF. Furthermore, the value of capacitor 75 can be equivalent to the total load of the data cell circuits 40 and 50 on the bit lines. Capacitor 75 can be a metal capacitor (e.g., a top layer of metal) and may not be a true bit cell. After the precharging of the second input / output resolve signal REFIOR to voltage reference VREF is turned off, capacitor 75 can maintain the voltage reference VREF level on the second input / output resolve signal REFIOR.

[0025] The capacitor 75 can also match the coupling effect from the control signal ATDb at a high level to the bit line on the first path for the first input / output resolution signal IOR. The transistor M2 can be sized similar to Figure 1 The transistors M5 and M6 in the first path for the first input / output resolution signal IOR are identical so as to match the leakage of one of the transistors M5 and M6 (i.e., the one of the transistors M5 and M6 that is turned off) on the first path for the first input / output resolution signal IOR. For example, when the transistor M5 is turned on by the column top signal COL_TOP at a high level and the transistor M6 is turned off by the column bottom signal COL_BOT at a low level, the transistor M2 has a leakage that matches the leakage of the transistor M6 when the transistor M6 is turned off.

[0026] Furthermore, when transistor M6 is turned on by the column bottom signal COL_BOT at a high level and transistor M5 is turned off by the column top signal COL_TOP at a low level, transistor M2 has a leakage that matches the leakage of transistor M5 when transistor M5 is turned off. Therefore, all leakage and coupling effects are eliminated by capacitor 75. Furthermore, by eliminating leakage and coupling effects using capacitor 75 and transistor M2, the current delta between the first input / output resolution signal IOR and the second input / output resolution signal REFIOR can be a pure current delta between the reference cell circuit 30 and the selected data cell circuit (i.e., the selected data cell circuit among the data cell circuits 40 and 50).

[0027] Figure 3 A timing diagram of a sense amplifier circuit in a memory structure is shown. Timing diagram 100 includes a clock signal CLK, an enable signal EN_B, a control signal ATDb, a sense signal SEN_B, a column top signal COL_TOP / column bottom signal COL_BOT, a comparison enable signal CMP_EN, a first input / output resolution signal IOR, and an output signal OUT. In timing diagram 100, the enable signal EN_B remains low after the chip is powered on to stabilize the closed-loop operational amplifier and obtain a stable column address sensing reference cell signal CASREF. As shown, the control signal ATDb works as a precharge signal at the beginning of each read operation. For example, when the control signal ATDb is low (e.g., "0"), both the first input / output resolution signal IOR and the second input / output resolution signal REFIOR are precharged to the voltage reference VREF level.

[0028] Still referring to the timing diagram 100, the sense signal SEN_B and the column top signal COL_TOP / column bottom signal COL_BOT (i.e., one of the column top signal COL_TOP and the column bottom signal COL_BOT) should be turned on before the end of precharging to ensure that there is a pull-up from the reference cell current and a pull-down from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) on the first path for the first input / output resolution signal IOR. Once precharging is completed, the difference in current will cause the first input / output resolution signal IOR to be pulled up or down and deviate from the precharge voltage reference VREF level.

[0029] For example, in timing diagram 100, if the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) stores zero, the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) is less than the reference cell current in transistor M1, and the first input / output resolution signal IOR is pulled up to a high level (e.g., pulled up to the first power supply voltage VDD). In this case, if the selected data cell circuit stores "0", the output signal OUT is at a low level (e.g., "0" or GND). However, if the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) stores one ("1"), the current from the selected data cell circuit (i.e., the selected data cell circuit of the data cell circuits 40 and 50) will be greater than the reference cell current in transistor M1, and the first input / output reference signal IOR may be pulled down to a low level (e.g., pulled down to ground GND). In this case, if the selected data cell circuit stores "1", the output signal OUT is at a high level (eg, "1" or VDD).

[0030] Furthermore, as shown in timing diagram 100, once sufficient increments have accumulated between the first input / output resolution signal IOR and the second input / output resolution signal REFIOR, comparator 60 begins comparing the first input / output resolution signal IOR and the second input / output resolution signal REFIOR and outputs the output signal OUT. In the present disclosure, the second path for the second input / output resolution signal REFIOR lacks bit cell leakage, so the second input / output resolution signal REFIOR has a higher voltage level than known circuits. Furthermore, the first path for the first input / output resolution signal IOR can have leaky gates on transistors M5 and M6, so the first input / output resolution signal IOR can have a lower voltage level than known circuits. Therefore, when the read value is "1", the circuit described herein has a larger voltage margin than known circuits (i.e., a higher voltage level for the second input / output resolution signal REFIOR and a lower voltage level for the first input / output resolution signal IOR). In particular, statistical analysis shows a 5 sigma margin for reading a 1 and an 8 sigma margin for reading a 0, which allows for very robust applications.

[0031] The sense amplifier circuit can be manufactured in a variety of ways using a variety of different tools. In general, methods and tools are used to form structures with micrometer and nanometer dimensions. Methods, i.e., techniques, for manufacturing sense amplifier circuits have been adopted from integrated circuit (IC) technology. For example, the sense amplifier circuit can be built on a wafer and implemented as a film of material that is patterned by a photolithographic process. In particular, the fabrication of the sense amplifier circuit uses three basic building blocks: (i) depositing a thin film of material on a substrate, (ii) applying a patterned mask on top of the film by photolithographic imaging, and (iii) selectively etching the film to the mask.

[0032] The sense amplifier circuit for current sensing in the memory structure can be used in system-on-chip (SoC) technology. It should be understood by those skilled in the art that SoC is an integrated circuit (also called a "chip") that integrates all components of an electronic system on a single chip or substrate. Because the components are integrated on a single substrate, SoC consumes much less power and occupies much less area than a multi-chip design with equivalent functionality. Therefore, SoC is becoming a dominant force in the mobile computing (e.g., smartphones) and edge computing markets. SoC is also commonly used in embedded systems and the Internet of Things.

[0033] The structures and methods described above are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in raw wafer form as bare chips (i.e., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier whose leads are fixed to a motherboard or other higher-level carrier) or a multi-chip package (such as a ceramic carrier with one or both of surface interconnects and / or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product that includes an integrated circuit chip, from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0034] The description of various embodiments of the present disclosure has been given for the purpose of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein are selected to best explain the principles of the embodiments, practical applications, or technical improvements to technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A circuit for a sense amplifier, comprising: a sensing circuit comprising a first set of transistors, at least one data cell circuit, and a reference cell circuit; a reference voltage holding circuit comprising a second set of transistors and a bit line capacitor; as well as a comparator differential circuit that receives a data sensing voltage signal from the sensing circuit and a reference voltage level from the reference voltage holding circuit and outputs an output signal, wherein the sensing circuit is configured to select one of a first data unit circuit and a second data unit circuit among the at least one data unit circuit, convert a current difference between a reference cell current of the reference unit circuit and a current from the selected one of the first data unit circuit and the second data unit circuit into the data sensing voltage signal, and output the data sensing voltage signal; and The reference voltage holding circuit is configured to hold and output the reference voltage level and match leakage of an unselected one of the first data unit circuit and the second data unit circuit in the at least one data unit circuit.

2. The circuit according to claim 1, wherein The second set of transistors includes NMOS transistors configured to match the leakage of the unselected one of the first and second data cell circuits.

3. The circuit according to claim 1, wherein The second group of transistors includes PMOS transistors configured to be precharged to the reference voltage level.

4. The circuit according to claim 3, wherein The bit line capacitor is configured to maintain the reference voltage level after the pre-charging is turned off.

5. The circuit according to claim 1, wherein The first group of transistors includes a PMOS circuit configured to receive a reference cell current of the reference cell circuit. 6 . The circuit of claim 1 , further comprising a sense amplifier circuit including the sensing circuit and the reference voltage holding circuit.

7. A structure for a sense amplifier, comprising: a sensing circuit comprising a first set of transistors configured to sense a current difference between a reference cell current and a current from a selected one of a first data cell circuit and a second data cell circuit, and output the current difference as a data sense voltage signal to a differential circuit; as well as A reference voltage holding circuit includes a second set of transistors configured to hold a reference voltage level and output the reference voltage level to the differential circuit and match leakage of an unselected one of the first and second data cell circuits.

8. The structure according to claim 7, wherein The reference voltage holding circuit includes a PMOS transistor in the second group of transistors, the PMOS transistor being configured to be precharged to the reference voltage level.

9. The structure according to claim 8, wherein The reference voltage holding circuit includes a capacitor configured to hold the reference voltage level after the pre-charging is turned off.

10. The structure according to claim 7, wherein The reference voltage holding circuit includes an NMOS transistor in the second group of transistors, the NMOS transistor being configured to match the leakage of an unselected one of the first data cell circuit and the second data cell circuit.

11. The structure according to claim 7, wherein The sensing circuit includes a PMOS transistor in the first group of transistors, the PMOS transistor being configured to receive the reference cell current of a reference cell circuit.

12. The structure according to claim 7, wherein The sensing circuit includes a comparator that receives the reference voltage level and a feedback signal connected to a reference cell circuit.

13. The structure according to claim 7, wherein: The sensing circuit includes five PMOS transistors and two NMOS transistors in the first group of transistors.

14. The structure according to claim 7, wherein The differential circuit is a comparator differential circuit that receives the data sensing voltage signal and the reference voltage level and outputs an output signal.

15. The structure according to claim 14, wherein The comparator differential circuit is enabled by a comparator enable signal, which is gated to an NMOS transistor connected to the comparator differential circuit.

16. The structure according to claim 15, wherein In response to a predetermined current increment being accumulated between the data sensing voltage signal and the reference voltage level, the comparator enable signal is at a high level.

17. The structure according to claim 7, wherein The sensing circuit and the reference voltage holding circuit comprise a portion of a sense amplifier circuit.

18. A method for sensing operation of an amplifier, comprising: selecting one of a first data unit circuit and a second data unit circuit using a sensing circuit; converting a current difference between a reference cell current of a reference cell circuit and a current from a selected one of the first data cell circuit and the second data cell circuit into a data sensing voltage signal using the sensing circuit; Using a reference voltage holding circuit to maintain the reference voltage level; as well as outputting the data sensing voltage signal and the reference voltage level to a differential comparator circuit, The reference voltage holding circuit is configured to match leakage of an unselected one of the first data unit circuit and the second data unit circuit.

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