A double-sided heat dissipation flip chip power device packaging clamp and packaging process

Abstract

The application provides a double-sided heat dissipation flip chip power device packaging clamp, which comprises a subunit clamp and a chip module clamp, and is used for packaging of a subunit and packaging of a chip module respectively; the subunit clamp comprises a subunit support base, a subunit support table and a subunit clamping block, the subunit support table and the subunit clamping block are used for controlling the thickness of an interconnection layer between a chip layer and a metal buffer layer and limiting the horizontal freedom degree of the chip layer; the chip module clamp comprises a module support base, a module support table and a module clamping block, the module support table and the module clamping block are used for controlling the thickness of the interconnection layer between the subunit and upper and lower ceramic lining plates and limiting the horizontal freedom degree of the subunit. The application can complete the packaging of the double-sided heat dissipation chip module in a flip mode, the upper and lower ceramic lining plates can be connected through reflowing at one time, the process flow is reduced, the cost is lowered, and the reliability of the double-sided heat dissipation flip chip power device is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, and in particular to a double-sided heat dissipation flip-chip power device packaging fixture and a packaging process. Background Art

[0002] Existing half-bridge circuit power modules are still primarily based on wirebond interconnects and single-sided heat dissipation. These modules have weak heat dissipation capabilities and, due to the wire interconnects, introduce significant parasitic inductance, increasing losses. While the recently introduced double-sided heat dissipation power modules achieve dual-sided heat dissipation, reducing the thermal resistance of the power module to a certain extent, their gate and auxiliary electrodes still utilize wirebonding, which still results in significant parasitic inductance and a complex manufacturing process.

[0003] Specifically, in order to manufacture double-sided cooling power modules, electrical or physical interconnection is required through SnAgCu / SnPb / SnBi / sintered silver, etc. However, during the welding process, due to the gravity of the component itself and the mismatch of thermal expansion coefficients between the materials, the thickness of the solder layer becomes uneven, causing the chip and ceramic liner layers to tilt, thereby reducing the reliability of the power module or reducing the product yield. Summary of the Invention

[0004] The purpose of the present invention is to provide a packaging solution suitable for double-sided heat dissipation flip-chip power devices in order to address the deficiencies in the above-mentioned background technology.

[0005] To achieve the above-mentioned object, the present invention provides a double-sided heat dissipation flip-chip power device packaging fixture, wherein the chip involved includes an upper ceramic liner, an upper solder layer, a metal buffer layer, an intermediate high-temperature solder layer, a chip layer, a lower solder layer, and a lower ceramic liner, which are arranged in sequence from top to bottom. The packaging fixture includes a subunit fixture and a chip module fixture, which are respectively used for packaging the subunit and the chip module;

[0006] The subunit fixture includes a subunit support base, a subunit support platform, and a subunit clamping block. The subunit support base is provided with a chip positioning groove. During packaging, the chip layer is located at the position of the chip positioning groove. The subunit support platform and the subunit clamping block are provided in plurality and are detachably connected to the subunit support base to control the thickness of the intermediate high-temperature solder layer formed between the chip layer and the metal buffer layer, while limiting the horizontal freedom of the chip layer.

[0007] The chip module fixture includes a module support base, a module support platform and a module clamping block. The module support base is provided with a module positioning groove. During packaging, the subunit composed of the chip layer and the metal buffer layer is located in the module positioning groove. The module support platform and the module clamping block are provided in multiple numbers and are detachably connected to the module support base. The module support platform and the module clamping block are used to control the thickness of the upper solder layer between the subunit and the upper ceramic liner and the lower solder layer between the lower ceramic liner, while limiting the horizontal freedom of the subunit.

[0008] Furthermore, the subunit clamping blocks and the module clamping blocks are both arranged horizontally and vertically.

[0009] Furthermore, the subunit clamping block and the module clamping block are rectangular as a whole, and the inner end surfaces are flat, so as to clamp and limit the components.

[0010] Furthermore, the subunit support platforms are respectively arranged diagonally opposite to the chip positioning groove, and the module support platforms are respectively arranged diagonally opposite to the module positioning groove.

[0011] Furthermore, a first limiting surface and a second limiting surface are formed at the inner end of the subunit support platform, the second limiting surface is higher than the first limiting surface, and the second limiting surface and the first limiting surface are transitioned by a horizontal step surface, the first limiting surface is provided with a right-angle groove to limit the diagonal engagement of the chip layer, and the step surface of the subunit support platform is used to support the lower surface of the metal buffer layer so that there is a preset distance between the metal buffer layer and the chip layer.

[0012] Furthermore, a third limiting surface and a fourth limiting surface are formed at the inner end of the module support platform, the fourth limiting surface is higher than the third limiting surface, and the fourth limiting surface and the third limiting surface are transitioned by a horizontal step surface, and the third limiting surface and the fourth limiting surface are both provided with right-angle grooves to respectively engage and limit the diagonal positions of the metal buffer layer and the upper ceramic lining plate, and the step surface of the module support platform is used to support the lower surface of the upper ceramic lining plate so that there is a preset distance between the upper ceramic lining plate and the metal buffer layer.

[0013] Furthermore, the size of the module positioning groove matches the lower ceramic liner, and the lower ceramic liner is placed in the module positioning groove during packaging. The module positioning groove has a preset thickness so that the chip layer and the lower ceramic liner have a preset distance.

[0014] Furthermore, the subunit clamping block is arranged in the mounting groove of the subunit support base; and the module clamping block is arranged in the mounting groove of the module support base.

[0015] Furthermore, a plurality of bolt holes are provided on the subunit support base and the module support base, and bolt grooves are provided on the subunit clamping block, the subunit support platform, the module clamping block, and the module support platform, and the subunit clamping block, the subunit support platform, the module clamping block, and the module support platform are fixed at the corresponding bolt hole positions by bolts.

[0016] The present invention also provides a double-sided heat dissipation flip chip power device packaging process, which uses the double-sided heat dissipation flip chip power device packaging fixture as described above, including the following steps:

[0017] S1, connecting the chip layer and the metal buffer layer through the intermediate high-temperature solder layer to encapsulate them into a submodule;

[0018] S2, the upper layer and the lower layer of the submodule are respectively connected and packaged with the upper ceramic liner through the upper solder layer and the lower ceramic liner through the lower solder layer, and the reflow or sintering is completed in one step.

[0019] The above solution of the present invention has the following beneficial effects:

[0020] The double-sided heat dissipation flip-chip power device packaging solution provided by the present invention enables the packaging of double-sided heat dissipation chip modules using a flip-chip method. The upper and lower ceramic liner plates can be reflow-connected in a single process, simplifying the process flow, reducing costs, and improving the reliability of double-sided heat dissipation flip-chip power devices. Furthermore, the support platform eliminates the problem of interconnect layer tilting after reflow or soldering, and reduces thermal stress caused by mismatched thermal expansion coefficients of various material layers, such as chip warpage and bending of the upper and lower liner plates, further ensuring packaging quality and product reliability.

[0021] Other beneficial effects of the present invention will be described in detail in the subsequent specific implementation section. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Schematic diagram of the subunit fixture structure of the present invention;

[0023] Figure 2 This is a schematic diagram of the modular fixture structure of the present invention;

[0024] Figure 3 This is a schematic diagram of the chip structure involved in the present invention;

[0025] Figure 4 Schematic diagram of the packaging process of the present invention.

[0026] [Description of Reference Numerals]

[0027] 1-upper ceramic liner; 2-upper solder layer; 3-metal buffer layer; 4-middle high-temperature solder layer; 5-chip layer; 6-lower solder layer; 7-lower ceramic liner; 8-first lead frame; 9-second lead frame; 10-third lead frame; 11-gate and auxiliary lead frame; 12-subunit support base; 13-subunit support platform; 14-subunit clamping block; 15-chip positioning groove; 16-first limiting surface; 17-second limiting surface; 18-bolt hole; 19-hexagon socket bolt; 20-module support base; 21-module support platform; 22-module clamping block; 23-module positioning groove; 24-third limiting surface; 25-fourth limiting surface. DETAILED DESCRIPTION

[0028] In order to make the technical problems, technical solutions and advantages to be solved by the present invention clearer, the following will be described in detail with reference to the accompanying drawings and specific embodiments. Obviously, the embodiments described are part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0029] In the description of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they may refer to a locking connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on the specific circumstances.

[0031] Example 1:

[0032] like Figure 1 、 Figure 2 As shown, embodiment 1 of the present invention provides a double-sided heat dissipation flip chip power device packaging fixture, the double-sided heat dissipation flip chip as Figure 3 As shown, the device includes, from top to bottom, an upper ceramic backing plate 1 (DBC copper-clad), an upper solder layer 2 (tin-silver alloy or tin-antimony alloy solder), a metal buffer layer 3 (also known as a spacer layer), an intermediate high-temperature solder layer 4 (tin-lead solder / sintered silver), a chip layer 5 (IGBT chip or SiC chip and FWD chip), a lower solder layer 6 (tin-silver alloy or tin-antimony alloy solder), and a lower ceramic backing plate 7 (DBC copper-clad). It also includes a first lead frame 8 (interconnected to the emitter electrode of the IGBT or SiC chip and the anode of the FWD chip), a second lead frame 9 (interconnected to the collector electrode of the IGBT or SiC chip and the cathode of the FWD chip), a third lead frame 10, and gate and auxiliary electrode lead frames 11. Using a flip-chip packaging method, the chip layer 5 and the metal buffer layer 3 are first connected together through the corresponding interconnect layer (intermediate high-temperature solder layer 4) to form a subunit. Then, the sub-unit and the upper ceramic liner 1 and the lower ceramic liner 7 are respectively reflowed or sintered through the corresponding interconnection layers (upper solder layer 2 and lower solder layer 6) to complete the packaging.

[0033] Based on this, the fixture includes a subunit fixture and a chip module fixture, which are used for packaging the subunit and the chip module respectively.

[0034] The subunit fixture includes a subunit support base 12, a subunit support platform 13, and a subunit clamping block 14. The subunit support base 12 is provided with a chip positioning groove 15, and the chip layer 5 is positioned at the chip positioning groove 15 during packaging. In order to control the thickness of the interconnect layer between the chip layer 5 and the metal buffer layer 3, and further limit the horizontal freedom of the chip layer 5 (the size of the chip positioning groove 15 is slightly larger than the size of the chip layer 5 to facilitate the extension of the pins of the chip layer 5), multiple subunit support platforms 13 and subunit clamping blocks 14 are provided and detachably connected to the subunit support base 12, so that the subunit support platform 13 and subunit clamping blocks 14 can be installed after the chip layer 5 is inserted.

[0035] Specifically, two sub-unit clamping blocks 14 are provided, one horizontally and one vertically; four sub-unit support platforms 13 are provided, one diagonally disposed at the chip positioning groove 15. The sub-unit clamping blocks 14 are mainly used to position the chip layer 5 horizontally and vertically; the sub-unit support platform 13 is mainly used to control the thickness of the interconnection layer between the chip layer 5 and the metal buffer layer 3. Therefore, in this embodiment, the sub-unit clamping block 14 is rectangular as a whole, and the inner end surface is flat, and contacts the side wall of the chip layer 5 to form a limit. The inner end of the sub-unit support platform 13 is formed with a first limit surface 16 and a second limit surface 17. The second limit surface 17 is higher than the first limit surface 16, and the second limit surface 17 and the first limit surface 16 are transitioned by a horizontal step surface. Among them, the first limit surface 16 is used for diagonal limit of the chip layer 5, and the first limit surface 16 is provided with a right-angle groove to engage the diagonal of the chip layer 5. The stepped surface is used to support the bottom surface of the metal buffer layer 3 so that a preset distance exists between the metal buffer layer 3 and the chip layer 5 , thereby accurately controlling the thickness of the interconnection layer.

[0036] In this embodiment, the sub-unit clamping block 14 is disposed in the mounting groove of the sub-unit supporting base 12 to directly limit the chip layer 5 in the horizontal and vertical directions.

[0037] The subunit support platform 13 is installed on the upper surface of the subunit support base 12, so the lower surface of the subunit support platform 13 is in close contact with the upper surface of the subunit support base 12. There are two ways to control the thickness of the interconnect layer: one way is to place the chip layer 5 as a whole in the chip positioning groove 15. When the chip layer 5 is installed in place, the distance between the upper surface of the chip layer 5 and the upper surface of the subunit support base 12 is determined. Therefore, as long as the thickness of the step surface of the subunit support platform 13 is determined, the thickness of the interconnect layer can be accurately controlled. The other way is to make the lower surface of the chip layer 5 flush with the lower surface of the subunit support platform 13. In this case, the right-angle groove is not a cross-section, and its retained plate structure supports the chip layer 5. Therefore, the distance between the upper surface of the chip layer 5 and the upper surface of the subunit support base 12 is also determined (plate structure thickness + chip layer 5 thickness), and the thickness of the interconnect layer can still be accurately controlled.

[0038] In this embodiment, the second method is preferably adopted, that is, the plate structure retained by the right-angle groove supports the chip layer 5 and is consistent with the chip module fixture.

[0039] It should be noted that in this embodiment, a plurality of bolt holes 18 are provided on the subunit support base 12, and bolt grooves are provided on the subunit clamping block 14 and the subunit support platform 13. The subunit clamping block 14, the subunit support platform 13, etc. are firmly fixed to the subunit support base 12 by means of hexagon socket bolts 19 to ensure the accuracy and quality of the subunit packaging.

[0040] The chip module fixture structure is similar to the subunit fixture, specifically comprising a module support base 20, a module support platform 21, and a module clamping block 22. The module support base 20 includes a module positioning slot 23, where the subunit is positioned during packaging. The module support platform 21 and module clamping block 22 control the thickness of the interconnect layer between the subunit and the upper and lower ceramic liner plates 1 and 7, further limiting the subunit's horizontal freedom. Multiple module support platforms 21 and module clamping blocks 22 are also provided and removably connected to the module support base 20.

[0041] In order to improve the packaging efficiency and quality, the sub-unit needs to encapsulate the ceramic liner at the upper and lower layers at the same time, and complete the reflow or sintering in one time. Therefore, in this embodiment, the size of the module positioning groove 23 matches the lower ceramic liner 7 (slightly larger than the ceramic liner). During packaging, the lower ceramic liner 7 is placed in the module positioning groove 23. The setting of the module clamping block 22 is similar to the sub-unit clamping block 14 and will not be repeated here. The inner end of the module support platform 21 is formed with a third limiting surface 24 and a fourth limiting surface 25. The fourth limiting surface 25 is higher than the third limiting surface 24, and the fourth limiting surface 25 and the third limiting surface 24 are transitioned by a horizontal step surface. Among them, the fourth limiting surface 25 is used to limit the diagonal position of the upper ceramic liner 1. The third limiting surface 24 and the fourth limiting surface 25 are both provided with right-angle grooves to diagonally clamp the metal buffer layer 3 and the upper ceramic liner 1 respectively. The stepped surface is used to support the lower surface of the upper ceramic liner 1 so that a preset distance exists between the upper ceramic liner 1 and the metal buffer layer 3, thereby accurately controlling the thickness of the interconnection layer.

[0042] Similarly, the module support platform 21 is mounted on the upper surface of the module support base 20, with the lower surface of the module support platform 21 in close contact with the upper surface of the module support base 20. Since the lower surface of the metal buffer layer 3 in the subunit is flush with the lower surface of the module support platform 21, the right-angled groove of the third limiting surface 24 is not a cross-section, and its retained plate structure supports the metal buffer layer 3. Therefore, the distance between the upper surface of the metal buffer layer 3 and the upper surface of the module support base 20 is also determined (plate structure thickness + metal buffer layer 3 thickness). By setting the thickness between the step surface and the lower surface of the module support platform 21, the thickness of the interconnection layer between the metal buffer layer 3 and the upper ceramic liner 1 can be accurately controlled. As for the lower ceramic liner 7, since the distance between the lower surface of the chip layer 5 of the subunit and the upper surface of the module support base 20 is also determined, the thickness of the module positioning groove 23 can also be accurately controlled to control the thickness of the lower surface of the chip layer 5 and the lower ceramic liner 7. Ultimately, the thickness of the interconnection layer between the upper ceramic liner 1, the lower ceramic liner 7, and the subunit is simultaneously guaranteed, ensuring the packaging precision and quality.

[0043] Similarly, a plurality of bolt holes 18 are provided on the module support base 20, and a plurality of bolt slots are provided on the module clamping block 22 and the module support platform 21. The module clamping block 22, the module support platform 21, etc. are firmly fixed to the module support base 20 by means of hexagon socket bolts 19.

[0044] The fixture provided in this embodiment enables the flip-chip packaging of double-sided heat dissipation chip modules. The upper and lower ceramic backing plates can be reflow-connected in a single process, simplifying the process flow and reducing costs, further improving the reliability of double-sided heat dissipation flip-chip power devices. Furthermore, the support platform eliminates the problem of interconnect layer tilting after reflow or soldering, reducing thermal stress issues caused by mismatched thermal expansion coefficients between material layers, such as chip warpage and bending of the upper and lower backing plates.

[0045] Example 2:

[0046] The second embodiment of the present invention provides a double-sided heat dissipation flip chip power device packaging process, which is completed using the fixture provided in the first embodiment. Figure 4 As shown, the following steps are included:

[0047] S1, connecting the chip layer 5 and the metal buffer layer 3 through the intermediate high-temperature solder layer 4 to encapsulate them into a submodule;

[0048] S2, the upper layer and the lower layer of the submodule are respectively connected and packaged with the upper ceramic liner 1 through the upper solder layer 2 and the lower ceramic liner 7 through the lower solder layer 6, and the process is completed by one reflow or sintering.

[0049] Through a flip-chip packaging method, the metal buffer layer 3 interconnects with the collector electrode of the chip layer 5. Because the entire collector electrode of the chip layer 5 can be used for interconnection, the metal buffer layer 3 can be larger than the chip layer 5, increasing the heat dissipation area and reducing chip warpage. Furthermore, in this method, the gate and auxiliary electrodes are packaged in a leadless manner, effectively reducing gate parasitic inductance and package size. This process simplifies the process flow, reduces costs, and further improves the reliability of double-sided heat dissipation flip-chip power devices.

[0050] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A double-sided heat dissipation flip chip power device packaging fixture, wherein the chip includes an upper ceramic liner, an upper solder layer, a metal buffer layer, an intermediate high-temperature solder layer, a chip layer, a lower solder layer, and a lower ceramic liner, which are arranged in order from top to bottom. The fixture is characterized in that: The packaging fixture includes a sub-unit fixture and a chip module fixture, which are used for packaging the sub-unit and the chip module respectively; The subunit fixture includes a subunit support base, a subunit support platform, and a subunit clamping block. The subunit support base is provided with a chip positioning groove. During packaging, the chip layer is located at the position of the chip positioning groove. The subunit support platform and the subunit clamping block are provided in plurality and are detachably connected to the subunit support base to control the thickness of the intermediate high-temperature solder layer formed between the chip layer and the metal buffer layer, while limiting the horizontal freedom of the chip layer. The chip module fixture includes a module support base, a module support platform and a module clamping block. The module support base is provided with a module positioning groove. During packaging, the subunit composed of the chip layer and the metal buffer layer is located at the module positioning groove. The module support platform and the module clamping block are provided in plurality and are detachably connected to the module support base. The module support platform and the module clamping block are used to control the thickness of the upper solder layer between the subunit and the upper ceramic liner and the lower solder layer between the lower ceramic liner, while limiting the horizontal freedom of the subunit. The subunit clamping blocks and the module clamping blocks are both arranged horizontally and vertically; The subunit support platforms are respectively arranged diagonally and obliquely at the chip positioning grooves, and the module support platforms are respectively arranged diagonally and obliquely at the module positioning grooves; a first limiting surface and a second limiting surface are formed at the inner end of the subunit support platform, the second limiting surface is higher than the first limiting surface, and the second limiting surface and the first limiting surface are transitioned by a horizontal step surface, the first limiting surface is provided with a right-angle groove to engage and limit the diagonal position of the chip layer, and the step surface of the subunit support platform is used to support the lower surface of the metal buffer layer so that a preset distance is provided between the metal buffer layer and the chip layer; A third limiting surface and a fourth limiting surface are formed at the inner end of the module support platform. The fourth limiting surface is higher than the third limiting surface, and a horizontal step surface transitions between the fourth limiting surface and the third limiting surface. The third limiting surface and the fourth limiting surface are both provided with right-angle grooves to respectively engage and limit the diagonal positions of the metal buffer layer and the upper ceramic liner. The step surface of the module support platform is used to support the lower surface of the upper ceramic liner so that a preset distance is provided between the upper ceramic liner and the metal buffer layer. The size of the module positioning groove matches the lower ceramic liner. During packaging, the lower ceramic liner is placed in the module positioning groove. The module positioning groove has a preset thickness so that the chip layer and the lower ceramic liner have a preset distance.

2. A double-sided heat dissipation flip chip power device packaging fixture according to claim 1, characterized in that: The subunit clamping block and the module clamping block are rectangular in shape as a whole, and the inner end surfaces are flat, so as to clamp and limit the components.

3. The double-sided heat dissipation flip chip power device packaging fixture according to claim 1, characterized in that: The subunit clamping block is arranged in the mounting groove of the subunit support base; the module clamping block is arranged in the mounting groove of the module support base.

4. The double-sided heat dissipation flip chip power device packaging fixture according to claim 1, characterized in that: The subunit support base and the module support base are each provided with a plurality of bolt holes, and the subunit clamping block, the subunit support platform, the module clamping block, and the module support platform are each provided with bolt slots, and the subunit clamping block, the subunit support platform, the module clamping block, and the module support platform are all fixed at the corresponding bolt hole positions by bolts.

5. A double-sided heat dissipation flip chip power device packaging process, using the double-sided heat dissipation flip chip power device packaging fixture according to any one of claims 1 to 4, characterized in that: The steps include: S1, connecting the chip layer and the metal buffer layer through the intermediate high-temperature solder layer to encapsulate them into a submodule; S2, the upper layer and the lower layer of the submodule are respectively connected and packaged with the upper ceramic liner through the upper solder layer and the lower ceramic liner through the lower solder layer, and the reflow or sintering is completed in one step.

Images