Semiconductor element and method for producing the same

Abstract

The present disclosure provides a semiconductor device having an interconnect and a method of manufacturing the same. The semiconductor device has a first source / drain structure disposed on a carrier substrate, and a backside contact disposed on and electrically connected to the first source / drain structure. The semiconductor device also has an interconnect disposed on the backside contact. The interconnect has a lower redistribution layer electrically connected to the backside contact, and an upper redistribution layer disposed on the lower redistribution layer. The interconnect also has an interconnect frame disposed between and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect further has a passivation structure disposed around the interconnect frame.

Description

Technical Field

[0001] This application claims priority and benefits from U.S. Official Application No. 17 / 345,871, filed June 11, 2021, the contents of which are incorporated herein by reference in their entirety.

[0002] This disclosure relates to a semiconductor device and a method for fabricating the same. In particular, it relates to a semiconductor device having an interconnect portion and a method for fabricating the same. Background Technology

[0003] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a larger number of integrated circuits. Due to the miniaturization of semiconductor components, different types and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0004] However, the fabrication and integration of these semiconductor devices involve many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the fabrication and integration of semiconductor devices can lead to multiple defects and may increase manufacturing costs and time due to the additional fabrication steps. Therefore, there is a need for continuous improvement of the semiconductor device manufacturing process to address these defects and enhance its performance.

[0005] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art to this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0006] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first source / drain structure disposed on a carrier substrate; and a rear contact point disposed on and electrically connected to the first source / drain structure. The semiconductor device also includes an interconnect portion disposed on the rear contact point. The interconnect portion includes a lower redistribution layer electrically connected to the rear contact point; and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also includes an interconnect frame disposed between the lower redistribution layer and the upper redistribution layer, and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect portion further includes a passivation structure disposed around the interconnect frame.

[0007] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first source / drain structure disposed on a carrier substrate; and a rear contact point disposed on and electrically connected to the first source / drain structure. The semiconductor device also includes an interconnect portion disposed on the rear contact point. The interconnect portion includes a lower redistribution layer electrically connected to the rear contact point; and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also includes a first interconnect conductor and a second interconnect conductor extending parallel between the lower and upper redistribution layers. The lower and upper redistribution layers are electrically connected via the first and second interconnect conductors. The interconnect portion further includes a first passivation pad and a second passivation pad disposed around the first and second interconnect conductors, respectively.

[0008] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a sacrificial source / drain structure on a first carrier substrate; and forming a redistribution structure on the sacrificial source / drain structure. The method also includes attaching the redistribution structure to a second carrier substrate; and removing the first carrier substrate after attaching the redistribution structure to the second carrier substrate. The method further includes replacing the sacrificial source / drain structure with a first source / drain structure; and forming a rear contact point on the first source / drain structure and electrically connecting it to the first source / drain structure. Furthermore, the method includes forming an interconnect portion on the rear contact point. The step of forming the interconnect portion includes forming a lower redistribution layer electrically connected to the rear contact point; forming an interconnect structure on the lower redistribution layer and electrically connected to the lower redistribution layer; and forming an upper redistribution layer on the interconnect structure and electrically connected to the interconnect structure.

[0009] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a device substrate and an interconnect portion disposed on the device substrate. The interconnect portion includes a lower redistribution layer electrically connected to a rear contact point and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also includes an interconnect frame disposed between the lower redistribution layer and the upper redistribution layer and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect portion further includes a passivation structure disposed around the interconnect frame.

[0010] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a device substrate; an interconnect portion disposed on the device substrate. The interconnect portion includes a lower redistribution layer electrically connected to the rear contact point; and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also has a first interconnect conductor and a second interconnect conductor extending parallel between the lower and upper redistribution layers. The lower and upper redistribution layers are electrically connected via the first and second interconnect conductors. The interconnect portion further includes a first passivation pad and a second passivation pad disposed around the first and second interconnect conductors, respectively.

[0011] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a device substrate on a carrier substrate; and forming an interconnect portion on the device substrate. The step of forming the interconnect portion includes forming a lower redistribution layer electrically connected to the rear contact point; forming an interconnect structure on the lower redistribution layer and electrically connected to the lower redistribution layer; and forming an upper redistribution layer on the interconnect structure and electrically connected to the interconnect structure.

[0012] This disclosure provides some embodiments of a semiconductor device and a method for fabricating the same. In some embodiments, the semiconductor device has a back-end contact and an interconnect. The back-end contact is disposed on and electrically connected to a source / drain structure, and the interconnect is disposed on and electrically connected to the back-end contact. In some embodiments, the interconnect has an upper redistribution layer and an interconnect structure. The upper redistribution layer is disposed on a lower redistribution layer, and the interconnect structure is disposed between the lower and upper redistribution layers and electrically connected to both layers. By forming the interconnect on the back-end contact, the back-end-of-line (BEOL) routing is simplified. This achieves a modular design for the interconnect and the back-end contact. Furthermore, the method for fabricating the semiconductor device is simple and significantly reduces the manufacturing cost and time.

[0013] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, enabling a better understanding of the detailed description that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or designs of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the spirit and scope of this disclosure as defined by the appended claims. Attached Figure Description

[0014] When referring to the embodiments and claims in conjunction with the drawings, a more comprehensive understanding of the disclosure of this application can be obtained. The same element symbols in the drawings refer to the same elements.

[0015] Figure 1 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0016] Figure 2 This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0017] Figure 3 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0018] Figure 4 This is a flowchart illustrating an intermediate stage in the formation of an interconnect during the formation of a semiconductor element, according to some embodiments of this disclosure.

[0019] Figure 5 This is a flowchart illustrating an intermediate stage in the formation of an interconnect during the formation of a semiconductor element, according to some embodiments of this disclosure.

[0020] Figure 6 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a semiconductor layer on a first carrier substrate during the formation of a semiconductor element, according to some embodiments of the present disclosure.

[0021] Figure 7 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where the semiconductor layer is etched during the formation of a semiconductor element to form a plurality of fin structures.

[0022] Figure 8 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stage of forming an insulating structure between the fin structures during the formation of a semiconductor element.

[0023] Figure 9 This is a top view schematic diagram illustrating some embodiments of the present disclosure where a gate structure is formed across the fin structure and a plurality of intermediate stages are formed at both sides of the gate structure during the formation of a semiconductor element.

[0024] Figure 10 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 9 The section A-A' represents an intermediate stage in the formation of a semiconductor device.

[0025] Figure 11 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 9 The section A-A' represents an intermediate stage in the formation of a semiconductor device.

[0026] Figure 12 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure during the intermediate stage of forming a source / drain structure and multiple sacrificial source / drain structures on the etched fin structure during semiconductor device formation.

[0027] Figure 13 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure of forming a front contact point and a redistribution structure during the formation of a semiconductor device at an intermediate stage between the source / drain structure and the sacrificial source / drain structure.

[0028] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device, in which the redistribution structure is attached to a second carrier substrate.

[0029] Figure 15 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device, in which the first carrier substrate is removed.

[0030] Figure 16 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a patterned mask on the source / drain structure during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0031] Figure 17 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device, in which some portions of the fin structure exposed by the patterned mask are removed.

[0032] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage during the formation of a semiconductor device in some embodiments of the present disclosure, where the sacrificial source / drain structure is removed.

[0033] Figure 19 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple alternative source / drain structures during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0034] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple back-side contacts during semiconductor device formation, according to some embodiments of the present disclosure.

[0035] Figure 21 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a redistributed structure on the rear contact point during the formation of a semiconductor element, according to some embodiments of the present disclosure.

[0036] Figure 22 This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure in which a redistribution layer and a lower portion of a passivation structure are formed during the formation of a semiconductor device at an intermediate stage of the redistribution structure.

[0037] Figure 23 This is a cross-sectional schematic diagram illustrating an intermediate stage in which a lower portion of a dielectric structure and a lower portion of an interconnect framework are formed on the lower redistribution layer during the formation of some embodiments of the present disclosure.

[0038] Figure 24 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an upper portion of the passivation structure, an upper portion of the dielectric structure, and an upper portion of the interconnect frame during the formation of some embodiments of the present disclosure.

[0039] Figure 25 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an energy-removable layer with multiple openings on the underlying redistribution layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0040] Figure 26 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a semiconductor device, in which a passivation layer is formed to liner the opening and extends over the energy-removable layer.

[0041] Figure 27 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure where the passivation layer is etched during semiconductor device formation to form a plurality of passivation pads on the sidewalls of the opening.

[0042] Figure 28 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of multiple interconnect conductors in the opening during the formation of a semiconductor element, according to some embodiments of the present disclosure.

[0043] Figure 29 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of an upper redistribution layer on the energy-removable layer during the formation of a semiconductor device, according to some embodiments of the present disclosure.

[0044] The reference numerals in the attached figures are explained as follows:

[0045] 10: Preparation method

[0046] 100A: Semiconductor Components

[0047] 100B: Semiconductor Components

[0048] 101: First carrier substrate

[0049] 103: Etching stop layer

[0050] 105: Semiconductor layer

[0051] 105': Grassroots

[0052] 105A: Fin structure

[0053] 105B: Fin structure

[0054] 105C: Fin structure

[0055] 107: Patterned Masking

[0056] 109: Insulation Structure

[0057] 111: Gate structure

[0058] 113C: Passage Area

[0059] 113SD: Source / Drain Region

[0060] 116: Depression

[0061] 119A: Source / Drain Structure

[0062] 119B: Source / Drain Structure

[0063] 119C: Source / Drain Structure

[0064] 121A: Seed layer

[0065] 121B: Seed layer

[0066] 121C: Seed layer

[0067] 123: Dielectric layer

[0068] 123T: Upper surface

[0069] 125: Dielectric layer

[0070] 127: Front contact point

[0071] 129: Conductive layer

[0072] 131: Conductive layer

[0073] 133: Dielectric layer

[0074] 135: Conductive layer

[0075] 140: Redistributed Structure

[0076] 201: Carrier substrate

[0077] 203: Patterned Masking

[0078] 206: Opening

[0079] 207: Lower part

[0080] 208: Opening

[0081] 211B: Source / Drain Structure

[0082] 211C: Source / Drain Structure

[0083] 213B: Rear contact point

[0084] 213C: Rear contact point

[0085] 215: Conductive layer

[0086] 217: Dielectric layer

[0087] 219: Conductive layer

[0088] 221: Conductive layer

[0089] 240: Redistributed Structure

[0090] 300: Interconnection Section

[0091] 301: Lower redistribution layer

[0092] 303: Lower part

[0093] 306: Opening

[0094] 307: Lower part

[0095] 309: Through hole part

[0096] 311: Line section

[0097] 313: Through hole part

[0098] 315: Upper part

[0099] 317: Upper part

[0100] 319: Through hole part

[0101] 321: Through hole part

[0102] 323: Through hole part

[0103] 325: Interconnection Framework

[0104] 327: Upper redistribution layer

[0105] 400: Interconnection Section

[0106] 401: Lower redistribution layer

[0107] 403: Energy-Removable Layer

[0108] 406: Opening

[0109] 408: Opening

[0110] 411: Passivation layer

[0111] 411A: Passivation gasket

[0112] 411B: Passivation gasket

[0113] 413A: Interconnecting conductor

[0114] 413B: Interconnecting conductor

[0115] 427: Upper redistribution layer

[0116] 430: Air gap structure

[0117] 430A: Air gap

[0118] 430B: Air gap

[0119] 430C: Air gap

[0120] S11: Steps

[0121] S13: Steps

[0122] S15: Steps

[0123] S17: Steps

[0124] S19: Steps

[0125] S21: Steps

[0126] S23: Steps

[0127] S25: Steps

[0128] S25-1: Steps

[0129] S31: Sub-step

[0130] S33: Sub-step

[0131] S35: Sub-step

[0132] S37: Sub-step

[0133] S25-2: Steps

[0134] S41: Sub-step

[0135] S43: Sub-step

[0136] S45: Sub-step

[0137] S47: Sub-step

[0138] S49: Sub-step

[0139] S51: Sub-step

[0140] S53: Sub-step

[0141] S55: Sub-step

[0142] T1: Upper surface

[0143] T2: Upper surface

[0144] T3: Upper surface Detailed Implementation

[0145] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0146] Furthermore, for ease of explanation, this document may use spatial relative terms such as "beneath," "below," "lower," "above," and "upper" to describe the relationship between one element or feature shown in the figures and another (other) element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0147] Figure 1 This is a cross-sectional schematic diagram illustrating a semiconductor device 100A according to some embodiments of the present disclosure. In some embodiments, the semiconductor device 100A includes a carrier substrate 201 and a redistribution structure 140 disposed on the carrier substrate 201. As described, the redistribution structure 140 includes two dielectric layers 133, 125 and three conductive layers 135, 131, 129. In other embodiments, the redistribution structure 140 may include any number of dielectric layers, conductive layers, and vias.

[0148] Furthermore, the semiconductor device 100A includes a dielectric layer 123 disposed on the redistribution structure 140; and a plurality of source / drain structures 119A, 211B, 211C and a plurality of seed layers 121A, 121B, and 121C disposed in the dielectric layer 123. In some embodiments, the source / drain structures 119A, 211B, and 211C are respectively disposed on the seed layers 121A, 121B, and 121C. Although Figure 1Only three source / drain structures are shown, but it should be understood that this is for ease of description and any number of source / drain structures may be used depending on the functional requirements of the semiconductor device 100A.

[0149] In some embodiments, the semiconductor element 100A further includes a front contact point 127 disposed between the seed layer 121A and the conductive layer 129 of the redistribution structure 140. In some embodiments, the source / drain structure 119A is electrically connected to the carrier substrate 210 via the seed layer 121A, the front contact point 127, and the conductive layers 129, 131, and 133 of the redistribution structure 140. In some embodiments, the source / drain structures 211B and 211C are electrically insulated from the redistribution structure 140.

[0150] In some embodiments, semiconductor element 100A includes an insulating structure 109 disposed on dielectric layer 123; a fin structure 105A and rear contact points 213B, 213C, surrounded by insulating structure 109. Furthermore, fin structure 105A is disposed on source / drain structure 119, and rear contact points 213B, 213C are disposed on source / drain structures 211B, 211C, respectively. Additionally, semiconductor element 100A includes a patterned mask 203 disposed on fin structure 105A; and a redistribution structure 240 disposed on insulating structure 109 and patterned mask 203. As described, redistribution structure 240 includes three conductive layers 215, 219, 221 and a dielectric layer 217. In other embodiments, redistribution structure 240 may include any number of conductive layers, vias, and dielectric layers.

[0151] Please refer to the following: Figure 1 According to some embodiments, an interconnect portion 300 is disposed on the redistribution structure 240. In some embodiments, the interconnect portion 300 includes a lower redistribution layer 301, an upper redistribution layer 327, and an interconnect frame 325, the interconnect frame 325 being disposed between the lower redistribution layer 301 and the upper redistribution layer 327, and electrically connected to the lower redistribution layer 301 and the upper redistribution layer 327. Furthermore, according to some embodiments, the lower redistribution layer 301 is electrically connected to the source / drain structures 211B and 211C via the redistribution structure 240 and rear contact points 213B and 213C.

[0152] Both the lower redistribution layer 301 and the upper redistribution layer 327 may include one or more dielectric portions (not shown) and one or more conductive portions (not shown), the number of dielectric portions and the number of conductive portions depending on the wiring requirements of the redistribution layer. In some embodiments, the interconnect portion 300 also includes a dielectric structure and a passivation structure disposed between the lower redistribution layer 301 and the upper redistribution layer 327. In some embodiments, the interconnect frame 325 is disposed in the dielectric structure, and the dielectric structure is surrounded by the passivation structure. In some embodiments, according to some embodiments, the dielectric structure includes a lower portion 307 and an upper portion 317, and the passivation structure includes a lower portion 303 and an upper portion 315.

[0153] As described, the interconnect frame 325 includes two vias 309 and 313, three vias 319, 313 and 323, and a wire portion 311. The two vias 309 and 313 extend vertically through a lower portion 307 of the dielectric structure, the three vias 319, 313 and 323 extend vertically through an upper portion 317 of the dielectric structure, and the wire portion 311 extends horizontally between the vias 309 and 321. In other embodiments, the interconnect frame 325 may include any number of wire portions and vias. Figure 1 As shown, according to some embodiments, through holes 319 and 323 are respectively disposed on through holes 309 and 313, and are electrically connected to through holes 309 and 313 respectively.

[0154] Figure 2 This is a cross-sectional schematic diagram illustrating a semiconductor element 100B according to some embodiments of the present disclosure. Semiconductor element 100B is similar to semiconductor element 100A, and the same element number indicates the same element, and some details or detailed descriptions of the same element are not repeated.

[0155] In some embodiments, the semiconductor element 100B includes an interconnect portion 400 disposed on the redistribution structure 240. In some embodiments, the interconnect portion 400 includes a lower redistribution layer 401, an upper redistribution layer 427, and interconnect conductors 413A and 413B, which extend parallel to each other between the lower redistribution layer 401 and the upper redistribution layer 427. In some embodiments, the upper redistribution layer 427 and the lower redistribution layer 401 are electrically connected via interconnect conductors 413A and 413B. Furthermore, according to some embodiments, the lower redistribution layer 401 is electrically connected to the source / drain structures 211B and 211C via the redistribution structure 240 and rear contact points 213B and 213C.

[0156] Both the lower redistribution layer 401 and the upper redistribution layer 427 may include one or more dielectric portions (not shown) and one or more conductive portions (not shown), the number of dielectric portions and the number of conductive portions depending on the wiring requirements of the redistribution layer. In some embodiments, the interconnect portion 400 also includes a passivation pad 411A and a passivation pad 411B, the passivation pad 411A surrounding the interconnect conductor 413A, and the passivation pad 411B surrounding the interconnect conductor 413B. Furthermore, the passivation pads 411A and 411B are surrounded by an air gap structure 430.

[0157] In some embodiments, the air gap structure 430 includes air gaps 430A, 430B, and 430C. For example... Figure 2 As shown, interconnect conductor 413A is disposed between air gaps 430A and 430B in air gap structure 430, and interconnect conductor 413B is disposed between air gaps 430B and 430C in air gap structure 430. Although in Figure 2 The sectional view shows three air gaps 430A, 430B, and 430C, but the three air gaps are interconnected in other sectional views.

[0158] In some embodiments, the sidewalls of interconnect conductors 413A and 413B are completely covered by passivation pads 411A and 411B, respectively, so that the passivation pads 411A and 411B directly contact the lower redistribution layer 401 and the upper redistribution layer 427. In other words, the first interconnect conductors 413A and 413B are separated from the air gap structure 430 by the passivation pads 411A and 411B, respectively. As described, the interconnect portion 400 of the semiconductor device 100B includes two interconnect conductors 413A and 413B. In other embodiments, the interconnect portion 400 may include any number of interconnect conductors.

[0159] Figure 3 This is a flowchart illustrating a method 10 for fabricating semiconductor elements (e.g., semiconductor elements 100A and 100B) according to some embodiments of the present disclosure. According to some embodiments, the fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23 and S25. Figure 4 This is a flowchart illustrating multiple sub-steps of step S25-1 corresponding to step S25 in preparation method 10. Step S25-1 includes sub-steps S31, S33, S35, and S37. Figure 5 This is a flowchart illustrating multiple sub-steps of step S25-2 corresponding to step S25 in preparation method 10. Step S25-2 includes sub-steps S41, S43, S45, S47, S49, S51, S53, and S55. Figure 3 Steps S11 to S25 Figure 4 Sub-steps S31 to S37 and Figure 5Sub-steps S41 to S55 are briefly introduced for the first time, and then explained in detail with reference to the following diagrams.

[0160] like Figure 6 As shown, according to some embodiments, an etch stop layer 103 and a semiconductor layer 105 may be sequentially formed on a first carrier substrate 101. In some embodiments, the first carrier substrate 101 serves as a temporary substrate. During subsequent processing steps, the temporary substrate provides mechanical and structural support, such as those processing steps described in detail later. In some embodiments, the first carrier substrate 101 comprises a semiconductor material, a ceramic material, a polymeric material, a metallic material, other applicable materials, or combinations thereof. In some embodiments, the first carrier substrate 101 is a glass substrate.

[0161] In some embodiments, the etch stop layer 103 comprises silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials. Furthermore, the fabrication technique of the etch stop layer 103 may include a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a spin coating process, or other suitable processes. In some embodiments, the semiconductor layer 105 comprises polycrystalline silicon, amorphous silicon, and / or a semiconducting material, and its fabrication technique may include a deposition process, such as a CVD process, a PVD process, or an ALD process. Furthermore, according to some embodiments, a patterned mask 107 is formed on the semiconductor layer 105. The fabrication technique of the patterned mask 107 may include a deposition process followed by a patterning process.

[0162] Next, as Figure 7 As shown, according to some embodiments, an etching process is performed on a semiconductor layer 105 using a patterned mask 107 as a mask. As a result, a base layer 105' and a plurality of fin structures 105A, 105B, 105C on the base layer 105' are obtained. The etching process can be a dry etching process or a wet etching process.

[0163] In some embodiments, the semiconductor layer 105 is etched using a dry etching process. The dry etching process includes using a fluorine-based etching gas, such as SF6 or C. x F y NF3 or a combination thereof. The etching process can be a time-controlled process and continues until the fin structures 105A, 105B, 1045C reach a predetermined height. In some other embodiments, each fin structure 105A, 105B, 105C has a width that gradually widens from top to bottom.

[0164] like Figure 8As shown, according to some embodiments, after the fin structures 105A, 105B, and 105C are formed, the patterned mask 107 can be removed, and an insulating structure 109 is formed between the fin structures 105A, 105B, and 105C. In some embodiments, the insulating structure 109 is a shallow trench isolation (STI) structure surrounding the lower portion of each fin structure 105A, 105B, and 105C. In some embodiments, the lower portions of each fin structure 105A, 105B, and 105C are surrounded by the insulating structure 109, while the upper portions of each fin structure 105A, 105B, and 105C protrude from the insulating structure 109.

[0165] The insulating structure 109 is configured to avoid electrical interference or crosstalk. In some embodiments, the insulating structure 109 comprises silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials with a low-k dielectric constant. Furthermore, the fabrication technique of the insulating structure 109 may include a deposition process followed by an etching process.

[0166] Next, as Figures 9 to 11 As shown, according to some embodiments, a gate structure 111 is formed to extend across fin structures 105A, 105B, and 105C and over an insulating structure 109, and recesses portions of the fin structures 105A, 105B, and 105C adjacent to the gate structure 111 to form a plurality of recesses 116 on both sides of the fin structures 105A, 105B, and 105C. In some embodiments, the gate structure 111 is formed on a channel region 113C of the fin structures 105A, 105B, and 105C, and the recesses 116 are formed on a source / drain region 113SD of the fin structures 105A, 105B, and 105C.

[0167] In some embodiments, the gate structure 111 includes a gate dielectric layer (not shown) and a gate electrode layer (not shown), the gate electrode layer being disposed on the gate dielectric layer. Furthermore, the fabrication technology of the gate structure 111 may include a gate first process, a gate last process, or a combination thereof. The gate first process, the gate last process, or a combination thereof includes a deposition process, a patterning process, an etching process, or a combination thereof. After the gate structure 111 is formed, the recess 116 may be formed, and the fabrication technology of the recess 116 may include an etching process, including a wet etching process, a dry etching process, or a combination thereof.

[0168] Then, as Figure 12 As shown, according to some embodiments, source / drain structures 119A, 119B, and 119C are formed in the recess 116 on portions of the fin structures 105A, 105B, and 105C in the source / drain region 113SD. It should be understood that... Figure 1 , Figure 2 as well as Figures 12 to 29 This is a cross-sectional view along a line segment of the source / drain region 113SD of the tangential fin structures 105A, 105B, and 105C. In some embodiments, a strained material is grown in the recess 116 using an epitaxial process to form the source / drain structures 119A, 119B, and 119C. In some embodiments, the strained material of the source / drain structures 119A, 119B, and 119C comprises Ge, SiGe, InAs, InGaAs, InSb, GaAs, GaSb, InAlP, InP, or the like.

[0169] Please refer to the following: Figure 12 According to some embodiments, seed layers 121A, 121B, and 121C are formed on source / drain structures 119A, 119B, and 119C, and a dielectric layer 123 is formed to cover the seed layers 121A, 121B, and 121C and the insulating structure 109. At least one of the source / drain structures 119A, 119B, and 119C may be a sacrificial source / drain structure, which will be replaced by a substitute source / drain structure in subsequent processes. In some embodiments, source / drain structures 119B and 119C are sacrificial source / drain structures, and seed layers 121A, 121B, and 121C are formed to assist in subsequent inversion of structures, backside removal of sacrificial source / drain structures 119B and 119C, and growth of the substitute source / drain structure. The corresponding steps are illustrated in... Figure 3 Step S11 in preparation method 10 shown.

[0170] Seed layers 121A, 121B, and 121C may have an etch rate relatively lower than that of sacrificial source / drain structures 119B and 119C using a given etchant, so that the sacrificial source / drain structures 119B and 119C can be effectively removed, while leaving seed layers 121B and 121C from which at least a portion of the alternative source / drain structures can be grown. In other words, seed layers 121B and 121C can serve as an etch termination in the etching process of sacrificial source / drain structures 119B and 119C. For example, seed layers 121A, 121B, and 121C contain Si or SiGe, with 10% less Ge than the material of sacrificial source / drain structures 119B and 119C.

[0171] Furthermore, the dielectric layer 123 may be an interlayer dielectric (ILD) structure, including a single layer or multiple layers. In some embodiments, the dielectric layer 123 comprises silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borosilicate glass (BPSG), a low dielectric constant dielectric material, and / or other suitable dielectric materials. Examples of low dielectric constant dielectric materials include, but are not limited to, fluorinated silica glass (FSG), carbon-doped silicon oxide, amorphous fluorinated carbon, parylene, bis-benzocyclobutenes (BCB), or polyimide. Furthermore, the fabrication technology of the dielectric layer 123 may include a CVD process, a PVD process, an ALD process, a spin coating process, or other suitable processes.

[0172] like Figure 13 As shown, in some embodiments, after the dielectric layer 123 is formed, a front contact 127 is formed on the source / drain structure 119A, and a redistribution structure 140 is formed on the front contact 127. The corresponding steps are illustrated in... Figure 3 Steps S13 and S15 in the preparation method 10 shown. In some embodiments, the redistribution structure 140 includes conductive layers 129, 131, 135 and dielectric layers 125, 133.

[0173] In some embodiments, the lower portion of the front contact 127 is embedded in the dielectric layer 123, while the upper portion of the front contact 127 is surrounded by the dielectric layer 125 of the redistribution structure 140. In some embodiments, the front contact 127 and the conductive layers 129, 131, 135 comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof, while the dielectric layers 125, 133 comprise silicon oxide, silicon nitride, silicon oxynitride, or other dielectric materials with low dielectric constants. The fabrication of the front contact 127 and the redistribution structure 140 includes multiple deposition processes and multiple etching processes. Although the front contact point 127 and the conductive layers 129, 131, 135 are shown to be separated from each other by a identifiable interface therebetween, when the front contact point 127 and the conductive layers 129, 131, 135 contain the same or similar materials, the front contact point 127 and the conductive layers 129, 131, 135 can be continuously connected to each other without a identifiable interface therebetween.

[0174] like Figure 14 As shown, in some embodiments, after the redistribution structure 140 is formed, Figure 13The structure is flipped upside down and placed on a carrier substrate 201. In some embodiments, the redistribution structure 140 is attached to the carrier substrate 201 by an adhesive layer (not shown). The corresponding steps are illustrated in... Figure 3 Step S17 in preparation method 10 shown.

[0175] The carrier substrate 201 is similar to the first carrier substrate 101, both providing mechanical and structural support during subsequent processing steps. In some embodiments, the carrier substrate 201 is part of an integrated circuit (IC) chip, including various passive and active microelectronic components such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, fin field-effect transistors (FinFETs), other suitable IC components, or combinations thereof. In these examples, the source / drain structure 119A is electrically connected to multiple components in the carrier substrate 201 via front contact 127 and redistribution structure 140.

[0176] Next, as Figure 15 As shown, according to some embodiments, the first carrier substrate 101 and the etch stop layer 103 are removed. The corresponding steps are illustrated in... Figure 3 Step S19 of the fabrication method 10 shown. In some embodiments, the first carrier substrate 101 and the etch stop layer 103 are removed by a planarization process. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, an etching process, or a combination thereof.

[0177] Next, as Figure 16 As shown, according to some embodiments, the base layer 105' is removed while some portions of the fin structures 105A, 105B, and 105C in the source / drain region 113SD are retained (see reference). Figure 9 In some embodiments, the substrate 105' is removed by a planarization process, such as an etching process, a polishing process, or a combination thereof. In some embodiments, the planarization process is performed until the insulating structure 109 is exposed.

[0178] Since the source / drain structure 119A is not designed to be replaced in subsequent processes, a patterned mask 203 is formed to cover the portion of the fin structure 105A on the source / drain structure 119A to protect the source / drain structure 119A from the effects of subsequent processing steps. Some materials used to form the patterned mask 203 are similar to or the same as those used to form the patterned mask 107, and their detailed description will not be repeated herein.

[0179] Then, as Figure 17 As shown, according to some embodiments, portions of the fin structures 105B and 105C are removed by an etching process. This results in a plurality of openings 206 in the insulating structure 109. In some embodiments, the etching process forming the openings 206 includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, portions of the insulating structure 109 adjacent to the fin structures 105B and 105C, along with the fin structures 105B and 105C, are removed to expose the dielectric layer 123 and a portion of the source / drain structures 119B and 119C via the openings 206.

[0180] Next, as Figure 18 As shown, according to some embodiments, source / drain structures 119B, 119C are removed by an etching process. This results in a plurality of openings 208 in the dielectric layer 123. In some embodiments, the etching process forming the openings 208 includes a wet etching process, a dry etching process, or a combination thereof. In some embodiments, at least a portion of each seed layer 121B, 121C is exposed via the openings 208. In some embodiments, fin structures 105A, 105B, 105C are located in channel region 113C (see reference...). Figure 9 Some of the sidewalls of the portion of the structure are exposed by the opening 208.

[0181] like Figure 19 As shown, according to some embodiments, after the aperture 208 is formed, source / drain structures 211B and 211C (also represented as alternative source / drain structures) grow from seed layers 121B and 121C, respectively. The corresponding steps are illustrated in... Figure 3 Step S21 in the fabrication method 10 shown. In some embodiments, the source / drain structures 211B, 211C and the seed layers 121B, 121C comprise similar high-quality materials, resulting in improved performance of multiple transistor-based devices containing the source / drain structures 211B, 211C.

[0182] In some embodiments, source / drain structures 211B and 211C extend into the opening 206 to cover a portion of the dielectric layer 123. In some embodiments, the upper surface T2 of source / drain structure 211B and the upper surface T3 of source / drain structure 211C are both higher than the upper surface 123T of dielectric layer 123. In some embodiments, the upper surface T2 of source / drain structure 211B and the upper surface T3 of source / drain structure 211C are both larger than the upper surface T1 of source / drain structure 119A.

[0183] Next, as Figure 20 As shown, according to some embodiments, rear contact points 213B and 213C are formed on source / drain structures 211B and 211C. The corresponding steps are illustrated in... Figure 3 Step S23 in the preparation method 10 shown. Some materials and processes used to form the rear contact points 213B and 213C are similar to or the same as those used to form the front contact point 127, and their detailed description will not be repeated here.

[0184] Then, as Figure 21 As shown, according to some embodiments, a redistribution structure 240 is formed on rear contact points 213B, 213C. In some embodiments, the redistribution structure 240 includes conductive layers 215, 219, 221 and a dielectric layer 217. Some materials and processes used to form the redistribution structure 240 are similar to or the same as those used to form the redistribution structure 140, and their detailed descriptions will not be repeated herein.

[0185] Next, as Figure 22 As shown, according to some embodiments, a redistribution layer 301 is formed on the redistribution structure 240. According to some embodiments, the corresponding steps are illustrated in... Figure 4 Sub-step S31 in step S25-1 shown is... Figure 3 The initial step of step S25 in the process. The lower redistribution layer 301 may include one or more dielectric portions (not shown) and one or more conductive portions (not shown), and the fabrication technology of the lower redistribution layer 301 may include multiple deposition processes and multiple etching processes. In some embodiments, the lower redistribution layer 301 is electrically connected to the source / drain structures 211B and 211C via the redistribution structure 240 and the rear contact points 213B and 213C.

[0186] Please refer to the following: Figure 22According to some embodiments, a lower portion 303 of a passivation structure is formed on a lower redistribution layer 301. In some embodiments, an opening 306 exposing the lower redistribution layer 301 is surrounded by the lower portion 303 of the passivation structure. In some embodiments, the lower portion 303 of the passivation structure comprises silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials, and the fabrication technique of the lower portion 303 of the passivation structure includes a deposition process and a subsequent etching process. The deposition process may include a CVD process, a PVD process, or an ALD process, and the etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0187] Next, as Figure 23 As shown, according to some embodiments, a lower portion 207 of a dielectric structure is formed in an opening 306, and via portions 309, 313 and a line portion 311 are formed in the lower portion 207 of the dielectric structure. In some embodiments, the lower portion of a dielectric structure comprises a dielectric material with a low dielectric constant, and its fabrication technique includes a deposition process, such as CVD, PVD, or ALD. In some embodiments, via portions 309, 313, and line portion 311 comprise a conductive material, copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof, and the fabrication technique of via portions 309, 313, and line portion 311 includes an etching process and a subsequent deposition process. The etching process may include a wet etching process, a dry etching process, or a combination thereof, and the deposition process may include a CVD process, a PVD process, or an ALD process. After the deposition process, a planarization process, such as a CMP process, may be performed.

[0188] Although the through-hole portion 309 and the wire portion 311 are shown to be separated from each other by a identifiable interface, when the through-hole portion 309 and the wire portion 311 contain the same or similar materials, the through-hole portion 309 and the wire portion 311 can be continuously connected to each other without a identifiable interface. For example, the through-hole portion 309 and the wire portion 311 are manufactured by simultaneously filling a dual damascene opening with a conductive material.

[0189] Then, as Figure 24 As shown, according to some embodiments, an upper portion 315 of the passivation structure is formed on a lower portion 303 of the passivation structure, an upper portion 317 of the dielectric structure is formed on a lower portion 307 of the dielectric structure, and via portions 319, 321, and 323 are formed in the upper portion 317 of the dielectric structure. Therefore, the dielectric structure is surrounded by the passivation structure, and an interconnect frame 325 including via portions 309, 313, 319, 321, and 323 and a line portion 311 is formed in the dielectric structure. The corresponding steps are illustrated in... Figure 4Sub-steps S33 and S35 in step S25-1 are shown. Some materials used to form the upper part 315 of the passivation structure, the upper part 317 of the dielectric structure, and the through-hole portions 319, 321, and 323 are similar to or the same as the materials used to form the lower part 303 of the passivation structure, the lower part 307 of the dielectric structure, and the through-hole portions 319 and 313, and their detailed descriptions will not be repeated here.

[0190] Please refer back to this page. Figure 1 A redistribution layer 327 is formed on the dielectric structure and the passivation structure. The corresponding steps are illustrated in... Figure 4 The sub-step S37 in step S25-1 shown. The upper redistribution layer 327 may include one or more dielectric portions (not shown) and one or more conductive portions (not shown), and the fabrication technology of the upper redistribution layer 327 may include multiple deposition processes and multiple etching processes.

[0191] After the upper redistribution layer 327 is formed, a semiconductor device 100A having interconnect portions 300 is obtained. In some embodiments, a passivation structure including a lower portion 303 and an upper portion 315 is sandwiched between the lower redistribution layer 301 and the upper redistribution layer 327, and directly contacts the lower redistribution layer 301 and the upper redistribution layer 327. In some embodiments, the interconnect frame 325 is separated from the passivation structure by a dielectric structure. It should be understood that the interconnect frame 325 is electrically connected to the lower redistribution layer 301 and the upper redistribution layer 327.

[0192] According to some embodiments, Figures 25 to 29 Example from Figure 21 The intermediate stages of forming the semiconductor device 100B continue. The corresponding steps are illustrated in... Figure 5 Sub-steps S41 to S55 in step S25-2 shown.

[0193] like Figure 25 As shown, according to some embodiments, after the redistribution structure 240 is formed, a lower redistribution layer 401 is formed on the redistribution structure 240, and an energy-removable layer having openings 406, 408 is formed on the lower redistribution layer 401. The corresponding steps are illustrated in... Figure 5 The sub-steps S41, S43, and S45 in step S25-2 are shown. The lower redistribution layer 401 can be similar to the lower redistribution layer 301 as described above, and its description will not be repeated in the text.

[0194] In some embodiments, the energy-removable layer 403 has a base material and a biodegradable pore-forming material that is substantially removed upon exposure to an energy source (i.e., a heat source). In some embodiments, the base material comprises hydrogen silsesquioxane (HSQ), methylsilsesquioxane (MSQ), porous polyarylether (PAE), porous SiLK, or porous SiO2, while the biodegradable pore-forming material comprises a porogen organic compound that provides porosity to the space that would otherwise be occupied by the energy-removable layer 403 in subsequent processes.

[0195] The fabrication technique for the energy-removable layer 403 may include a deposition process, such as a CVD process, a PVD process, or an ALD process. After the deposition process, a portion of the energy-removable layer 403 is removed by an etching process to expose the openings 406, 408 of the underlying redistribution layer 401. The etching process may include a wet etching process, a dry etching process, or a combination thereof.

[0196] Next, a passivation layer 411 is deposited to back up the openings 406 and 408, and extends over the energy-removable layer 403. The corresponding steps are illustrated in... Figure 5 Sub-step S47 in step S25-2 shown. In some embodiments, the sidewalls of openings 406 and 408 and the lower surfaces of openings 406 and 408 (e.g., the exposed surfaces of the lower redistribution layer 401) are covered by a passivation layer 411. In some embodiments, the passivation layer 411 comprises silicon oxide, silicon nitride, silicon oxynitride, and / or other suitable materials, and the deposition process for forming the passivation layer 411 includes a CVD process, a PVD process, or an ALD process.

[0197] Next, as Figure 27 As shown, according to some embodiments, the passivation layer 411 is etched to form passivation pads 411A and 411B on the sidewalls of the openings 406 and 408. The corresponding steps are illustrated in... Figure 5 Sub-step S49 in step S25-2 shown. In some embodiments, the etching process is an isotropic etching process that vertically removes the same number of passivation layers 411 at all locations, leaving passivation pads 411A, 411B on each sidewall of the energy-removable layer 403. In some embodiments, the etching process is a dry etching process.

[0198] like Figure 28As shown, according to some embodiments, interconnecting conductors 413A and 413B are respectively formed in the remaining portions of openings 406 and 408. The corresponding steps are illustrated in... Figure 5 Sub-step S51 in step S25-2 shown. In some embodiments, interconnect conductors 413A and 413B comprise a conductive material, such as copper, tungsten, aluminum, titanium, tantalum, gold, silver, or a combination thereof. Furthermore, the fabrication technology of interconnect conductors 413A and 413B may include a deposition process (e.g., CVD, PVD, or ALD) followed by a planarization process (e.g., CMP).

[0199] Next, as Figure 29 As shown, according to some embodiments, a redistribution layer 427 is formed on the energy-removable layer 403. The corresponding steps are illustrated in... Figure 5 The sub-step S53 in step S25-2 shown. The upper redistribution layer 427 may include one or more dielectric portions (not shown) and one or more conductive portions (not shown), and the fabrication technology of the upper redistribution layer 427 may include multiple deposition processes and multiple etching processes.

[0200] Please refer back to this page. Figure 2 According to some embodiments, in Figure 29 A heat treatment process is performed on the structure to transform the energy-removable layer 403 into an air-gap structure 430. The corresponding steps are illustrated in... Figure 5 Sub-step S55 in step S25-2 is shown. In some embodiments, the air gap structure 430 includes air gaps 430A, 430B, and 430C. Although air gaps 430A, 430B, and 430C are... Figure 2 In the sectional view, they are separated from each other, but in other sectional views, air gaps 430A, 430B, and 430C can be solidly connected.

[0201] In some embodiments, a thermal processing step is used to remove the biodegradable pore-forming material of the energy-removable layer 403, thereby forming multiple pores. After the biodegradable pore-forming material is removed, the pores are filled with air to obtain an air gap structure 430. In other embodiments, the thermal processing step can be replaced by a photoprocessing step, an electron beam processing step, a combination thereof, or other applicable energy processing steps. For example, ultraviolet light or laser light can be used to remove the biodegradable pore-forming material of the energy-removable layer 403 to obtain the air gap structure 430. After forming the air gap structure 430, a semiconductor device 100B having interconnects 400 is obtained.

[0202] This disclosure provides some embodiments of semiconductor devices 100A and 100B and methods for fabricating the same. In some embodiments, each semiconductor device 100A or 100B has a rear contact point (e.g., rear contact points 213B and 213C) and an interconnect portion (e.g., interconnect portion 300 of semiconductor device 100A and interconnect portion 400 of semiconductor device 100B). The rear contact point is disposed on and electrically connected to a source / drain structure, and the interconnect portion is disposed on and electrically connected to the aforementioned rear contact point. In some embodiments, the interconnect has an upper redistribution layer (e.g., upper redistribution layer 327 of semiconductor element 100A and upper redistribution layer 427 of semiconductor element 100B) and an interconnect structure (e.g., interconnect frame 325 of semiconductor element 100A and interconnect conductors 413A, 413B of semiconductor element 100B). The upper redistribution layer is disposed on a lower redistribution layer (e.g., lower redistribution layer 301 of semiconductor element 100A and lower redistribution layer 401 of semiconductor element 100B). The interconnect structure is disposed between the lower redistribution layer and the upper redistribution layer and is electrically connected to the lower redistribution layer and the upper redistribution layer. By forming the interconnect at the rear contact point, the back-end-of-line (BEOL) routing is simplified. Accordingly, a modular design of the interconnect and the rear contact point is achieved. Furthermore, the method for fabricating the semiconductor element is simple and significantly reduces the manufacturing cost and time of the semiconductor element.

[0203] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first source / drain structure disposed on a carrier substrate; and a rear contact point disposed on and electrically connected to the first source / drain structure. The semiconductor device also includes an interconnect portion disposed on the rear contact point. The interconnect portion includes a lower redistribution layer electrically connected to the rear contact point; and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also includes an interconnect frame disposed between the lower redistribution layer and the upper redistribution layer, and electrically connected to the lower redistribution layer and the upper redistribution layer. The interconnect portion further includes a passivation structure disposed around the interconnect frame.

[0204] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a first source / drain structure disposed on a carrier substrate; and a rear contact point disposed on and electrically connected to the first source / drain structure. The semiconductor device also includes an interconnect portion disposed on the rear contact point. The interconnect portion includes a lower redistribution layer electrically connected to the rear contact point; and an upper redistribution layer disposed on the lower redistribution layer. The interconnect portion also includes a first interconnect conductor and a second interconnect conductor extending parallel between the lower and upper redistribution layers. The lower and upper redistribution layers are electrically connected via the first and second interconnect conductors. The interconnect portion further includes a first passivation pad and a second passivation pad disposed around the first and second interconnect conductors, respectively.

[0205] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a sacrificial source / drain structure on a first carrier substrate; and forming a redistribution structure on the sacrificial source / drain structure. The method also includes attaching the redistribution structure to a second carrier substrate; and removing the first carrier substrate after attaching the redistribution structure to the second carrier substrate. The method further includes replacing the sacrificial source / drain structure with a first source / drain structure; and forming a rear contact point on the first source / drain structure and electrically connecting it to the first source / drain structure. Furthermore, the method includes forming an interconnect portion on the rear contact point. The step of forming the interconnect portion includes forming a lower redistribution layer electrically connected to the rear contact point; forming an interconnect structure on the lower redistribution layer and electrically connected to the lower redistribution layer; and forming an upper redistribution layer on the interconnect structure and electrically connected to the interconnect structure.

[0206] The embodiments described in this disclosure have several advantageous features. By forming an interconnect on a rear contact point that is electrically connected to a source / drain structure, the back-end wiring is simplified. Accordingly, a modular design is achieved.

[0207] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives may be made without departing from the spirit and scope of this disclosure as defined in the claims. For example, many of the processes described above may be implemented using different methods, and other processes or combinations thereof may be substituted for many of the processes described above.

[0208] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material composition, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material composition, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used according to this disclosure. Accordingly, such processes, machinery, manufacturing, material composition, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor element, comprising: A first source / drain structure is disposed on a carrier substrate; A rear contact point is disposed on the first source / drain structure and electrically connected to the first source / drain structure; An interconnection portion is disposed on the rear contact point, wherein the interconnection portion includes: A redistribution layer is electrically connected to the rear contact point; An upper redistribution layer is set on top of the lower redistribution layer; An interconnect frame is disposed between the lower redistribution layer and the upper redistribution layer, and electrically connected to the lower redistribution layer and the upper redistribution layer; and A passivated structure is set around the interconnect framework; A second source / drain structure is disposed between the interconnect portion and the carrier substrate; and A front contact point is disposed between the second source / drain structure and the carrier substrate, wherein the second source / drain structure is electrically connected to the carrier substrate via the front contact point.

2. The semiconductor device of claim 1, wherein the passivation structure is sandwiched between the lower redistribution layer and the upper redistribution layer.

3. The semiconductor device of claim 1, wherein the interconnect further includes a dielectric structure sandwiched between the lower redistribution layer and the upper redistribution layer, wherein the interconnect frame is separated from the passivation structure by the dielectric structure.

4. The semiconductor element of claim 3, wherein the interconnect frame of the interconnect portion comprises: A first through-hole extends vertically through the lower part of the dielectric structure; A second through-hole extends vertically through the upper part of the dielectric structure; as well as A wire extends horizontally between the first through-hole portion and the second through-hole portion, wherein the first through-hole portion and the second through-hole portion are electrically connected by the wire.

5. The semiconductor device of claim 1, further comprising a redistribution structure disposed between the rear contact point and the lower redistribution layer of the interconnect, wherein the first source / drain structure is electrically connected to the lower redistribution layer via the redistribution structure, and the second source / drain structure is electrically insulated from the redistribution structure.

6. The semiconductor device of claim 1, wherein an upper surface of the first source / drain structure is higher than an upper surface of the second source / drain region.

7. A semiconductor element, comprising: A first source / drain structure is disposed on a carrier substrate; A rear contact point is disposed on the first source / drain region and electrically connected to the first source / drain structure; An interconnection portion is disposed on the rear contact point, wherein the interconnection portion includes: A redistribution layer is electrically connected to the rear contact point; An upper redistribution layer is set on top of the lower redistribution layer; A first interconnect conductor and a second interconnect conductor extend parallel between the lower redistribution layer and the upper redistribution layer, wherein the lower redistribution layer and the upper redistribution layer are electrically connected by the first interconnect conductor and the second interconnect conductor; and A first passivation pad and a second passivation pad are respectively disposed around the first interconnect conductor and the second interconnect conductor; A second source / drain region is disposed between the interconnect and the carrier substrate; and A front contact point is disposed between the second source / drain structure and the carrier substrate, wherein the second source / drain structure is electrically connected to the carrier substrate via the front contact point.

8. The semiconductor device of claim 7, wherein the first passivation pad and the second passivation pad are in direct contact with the lower redistribution layer and the upper redistribution layer.

9. The semiconductor device of claim 7, wherein an air gap is provided between the first passivation pad and the second passivation pad.

10. The semiconductor device of claim 7, wherein both the first passivation pad and the second passivation pad are surrounded by a portion of an air gap structure.

11. The semiconductor device of claim 10, wherein the first interconnect conductor and the second interconnect conductor are separated from the air gap structure by means of the first passivation pad and the second passivation pad, respectively.

12. The semiconductor device of claim 7, further comprising a dielectric layer disposed between the carrier substrate and the interconnect, wherein the first source / drain structure and the second source / drain structure are disposed in the dielectric layer, wherein a portion of the second source / drain structure extends to cover an upper surface of the dielectric layer.

13. A method for fabricating a semiconductor device, comprising: A sacrificial source / drain structure is formed on a first carrier substrate; A redistributed structure is formed on the sacrificial source / drain structure; The redistribution structure is attached to a second carrier substrate; After the redistribution structure is attached to the second carrier substrate, the first carrier substrate is removed; The sacrificial source / drain structure is replaced with a first source / drain structure; A rear contact point is formed on the first source / drain structure and electrically connected to the first source / drain structure; An interconnect portion is formed at the rear contact point, wherein the step of forming the interconnect portion includes: A redistribution layer is formed to be electrically connected to the rear contact point; An interconnect structure is formed on the lower redistribution layer and electrically connected to the lower redistribution layer; and An upper redistribution layer is formed on the interconnect structure and electrically connected to the interconnect structure; A second source / drain structure is formed on the first carrier substrate; A front contact point is formed on the second source / drain structure and electrically connected to the second source / drain structure; and The redistribution structure is formed on the front contact point and electrically connected to the front contact point.

14. The method of fabricating a semiconductor element as claimed in claim 13, wherein the second source / drain structure is electrically connected to the second carrier substrate via the front contact point.

15. The method for fabricating a semiconductor element as claimed in claim 13, wherein the step of forming the interconnect structure of the interconnect portion comprises: A passivation structure and a dielectric structure are formed on the lower redistribution layer, wherein the dielectric structure is surrounded by the passivation structure; as well as An interconnection framework is formed in the dielectric structure.

16. The method for fabricating a semiconductor element as claimed in claim 13, wherein the step of forming the interconnect structure of the interconnect portion comprises: An energy-removable layer is formed on the lower redistribution layer; The energy-removable layer is etched to form a first aperture and a second aperture, thereby exposing the lower redistribution layer; A first passivation liner and a second passivation liner are formed on each sidewall of the first opening and on each sidewall of the second opening, respectively. as well as A first interconnect conductor is formed in the first opening and surrounded by the first passivation pad, and a second interconnect conductor is formed in the second opening and surrounded by the second passivation pad.

17. The method of fabricating a semiconductor device as claimed in claim 16, further comprising, after the formation of the upper redistribution layer, performing a heat treatment to transform the energy-removable layer into an air gap structure.

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