Three-dimensional memory devices and methods of making the same

Abstract

A three-dimensional memory device includes a substrate and a memory stack structure disposed on the substrate. The memory stack structure includes a plurality of groups of conductive-dielectric layer pairs. The memory stack structure has a first region and a second region. The conductive-dielectric layer pairs in an upper half of the first region are stacked in a staircase shape with a lower half having first sidewalls that are cut flush with each other. The conductive-dielectric layer pairs in an upper half of the second region have second sidewalls that are cut flush with each other with a lower half stacked in a staircase shape. In this way, the three-dimensional memory device can form the memory stack structure through a simplified fabrication process and avoid problems such as collapse or structural defects for memory stack structures having a high aspect ratio.

Description

Technical Field

[0001] This invention belongs to the field of storage devices, and in particular relates to a three-dimensional storage device and its manufacturing method. Background Technology

[0002] In modern electronic products, memory plays an indispensable and crucial role. Besides storing user data, memory is also responsible for storing program code executed by the central processing unit (CPU) and information that needs to be temporarily saved during computation. Memory can be divided into volatile memory and non-volatile memory. Common volatile memory includes dynamic random access memory (DRAM) and static random access memory (SRAM), whose data is lost after power is turned off and must be re-entered when power is restored. Non-volatile memory includes read-only memory (ROM) and flash memory, whose stored data persists even when power is cut off, allowing for direct retrieval of previously stored valid data upon power restoration.

[0003] NAND flash memory has advantages such as small size, low power consumption, fast write speed, and low manufacturing cost, making it the most widely used non-volatile memory. With the advancement of semiconductor manufacturing processes, NAND flash memory has shifted from a planar structure to a three-dimensional (3D) stacked structure to achieve higher cell density per unit wafer area and meet the demand for higher storage capacity.

[0004] Three-dimensional NAND memory devices typically include a staircase structure formed on one or more sides of the memory stack to fan out word lines of each layer for electrical connection to interconnect structures (such as word line contact plugs). However, as the number of layers in the memory stack increases, the related fabrication processes and device structures need to be further improved to maintain good device performance while simplifying the fabrication process. Summary of the Invention

[0005] The present invention aims to provide a three-dimensional storage device, the storage stacking structure of which includes a stepped upper half disposed in a first region, a stepped lower half disposed in a second region, and a first etch stop layer and a second etch stop layer disposed on a substrate, between the stepped upper half and the stepped lower half, respectively. In this way, problems such as collapse or structural defects of the storage stacking structure with a large aspect ratio can be avoided.

[0006] The present invention aims to provide a method for fabricating a three-dimensional storage device, wherein a first stepped structure is formed in the upper half of a first region of a storage stack structure, and a second stepped structure is formed in the lower half of a second region of the storage stack structure, wherein the first stepped structure and the second stepped structure each have the same number of conductive-dielectric layer pairs. Therefore, the fabrication method of the present invention can simultaneously fabricate the first stepped structure in the first region and the second stepped structure in the second region using the same fabrication process, significantly reducing the number of etching cycles and the thickness of the photoresist layer used, and efficiently simplifying the fabrication process of the storage stack structure.

[0007] An embodiment of the present invention provides a three-dimensional storage device, including a substrate and a storage stack structure disposed on the substrate. The storage stack structure includes multiple pairs of conductive-dielectric layers, wherein the storage stack structure has a first region and a second region. The conductive-dielectric layer pairs in the upper half of the first region are stacked in a stepped shape, and the conductive-dielectric layer pairs in the lower half of the first region have first sidewalls that are flush with each other. The conductive-dielectric layer pairs in the upper half of the second region have second sidewalls that are flush with each other, and the conductive-dielectric layer pairs in the lower half of the second region are stacked in a stepped shape.

[0008] An embodiment of the present invention provides a method for fabricating a three-dimensional storage device, comprising the following steps. First, a substrate is provided, and a storage stack structure is formed on the substrate. The storage stack structure includes multiple sets of conductive-dielectric layer pairs, wherein the storage stack structure has a first region and a second region. The conductive-dielectric layer pairs in the upper half of the first region are stacked in a stepped manner, and the conductive-dielectric layer pairs in the lower half of the first region have mutually aligned first sidewalls. The conductive-dielectric layer pairs in the upper half of the second region have mutually aligned second sidewalls, and the conductive-dielectric layer pairs in the lower half of the second region are stacked in a stepped manner. Attached Figure Description

[0009] The accompanying drawings are provided to give a more in-depth understanding of this embodiment and are incorporated herein by reference as a whole. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams for illustrative and drafting purposes, and relative dimensions and scales have been adjusted. The same symbols represent corresponding or similar features in different embodiments.

[0010] Figure 1 This is a top view schematic diagram of a three-dimensional storage device;

[0011] Figure 2 for Figure 1 A cross-sectional view along tangents A-A' and B-B';

[0012] Figure 3 This is a top view of a three-dimensional storage device after the formation of the first mask layer.

[0013] Figure 4 for Figure 3 A cross-sectional view along tangents A-A' and B-B';

[0014] Figure 5 This is a cross-sectional view of a three-dimensional storage device after the etching process.

[0015] Figure 6 This is a top view of the three-dimensional storage device after the second mask layer has been formed.

[0016] Figure 7 for Figure 6 A cross-sectional view along tangents A-A' and B-B';

[0017] Figure 8 This is a cross-sectional view of a three-dimensional storage device after the etching process.

[0018] Figure 9 This is a schematic cross-sectional view of a three-dimensional storage device after the formation of the third mask layer.

[0019] Figure 10 This is a cross-sectional view of a three-dimensional storage device after the etching process.

[0020] Figure 11 This is a cross-sectional schematic diagram of a 3D storage device after the mask trimming fabrication process.

[0021] Figure 12 This is a cross-sectional view of a three-dimensional storage device after the etching process.

[0022] The reference numerals in the attached figures are explained as follows:

[0023] 100 - Three-dimensional memory device, 110 - Substrate, 111 - Memory array region, 113 - Word line contact region, 120 - Memory stack structure, 121 - Conductive layer, 123 - Dielectric layer, 125 - Conductive-dielectric layer pair, 130 - Channel structure, 131 - Dielectric layer, 133 - Channel layer, 135 - Fill layer, 137 - Channel plug, 141 - First plug, 143 - Second plug, 150a, 150b - First region, 151 - Lower half of the first region, 161 - Lower half of the second region, 152 - Upper half of the first region, 162 - Upper half of the second region, 153 - First sidewall, 154 - First vertical sidewall, 155 - Second vertical sidewall, 160a, 160b - Second region, 163 - Second sidewall, 164 - Third vertical sidewall, 165 - Fourth vertical sidewall, 171 - First etch stop layer, 173 - Second etch stop layer, 180 - Insulating layer, 190 - Interlayer dielectric layer, 200 - Word line contact plug, 201 - First word line contact plug, 203 - Second word line contact plug, 210 - Second insulating layer, 220 - First mask layer, 222 - First opening, 224 - Second opening, 230 - Third mask layer, 232 - Third opening, 234 - Fourth opening, 236 - Fifth opening, 238 - Sixth opening, 240 - Second mask layer, 240a - Trimmed second mask layer, 242 - Seventh opening, 244 - Eighth opening, 246 - Ninth opening, 273 - Second etch stop material layer, 248 - First stepped structure, 249 - Second stepped structure, D1 - First direction, D2 - Second direction, D3 - Third direction, G1 - First distance, G2 - Second distance, G3 - Third distance, G4 - Fourth distance, H1 - Height difference. Detailed Implementation

[0024] To enable those skilled in the art to further understand this invention, several preferred embodiments are listed below, and the composition and desired effects of the invention are explained in detail with reference to the accompanying drawings. Those skilled in the art can, without departing from the spirit of the invention, substitute, recombine, or mix features from the following embodiments to complete other embodiments.

[0025] Figures 1 to 2 The illustrations are schematic diagrams of a three-dimensional storage device 100 according to an embodiment of the present invention, showing a top view and a cross-sectional view of the three-dimensional storage device 100. Please refer to... Figure 1 and Figure 2As shown, the three-dimensional memory device 100 includes a substrate 110 and a memory stack structure 120 disposed on the substrate 110. The substrate 110 is, for example, a silicon substrate, a silicon-containing substrate, an epitaxial silicon substrate, a silicon-on-insulator substrate, or a substrate made of other suitable materials. In one embodiment, an additional spacer layer (not shown), such as a silicon oxide layer, may be provided between the substrate 110 and the memory stack structure 120, but this is not a limitation.

[0026] The substrate 110 includes an adjacent memory array region 111 and a word line contact region 113, with the word line contact region 113 surrounding the memory array region 111. Figure 1 As shown, but not limited thereto. The memory stack structure 120 disposed on the substrate 110 includes multiple conductive layers 121 and multiple dielectric layers 123 alternately stacked along a first direction D1 (e.g., a direction perpendicular to the substrate 110). Each conductive layer 121 and each dielectric layer 123 simultaneously covers the memory array region 111 and the word line contact region 113, and each conductive layer 121 and the dielectric layer 123 above it together form a set of conductive-dielectric layer pairs 125, such as... Figure 2 As shown. The conductive layer 121 includes, for example, a conductive material, such as any metallic or non-metallic conductive material or any combination thereof, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium-tungsten (Ti / W), titanium and titanium nitride (Ti / TiN), polysilicon, doped silicon, metal silicide, etc., while the dielectric layer 123 includes, for example, a dielectric material, such as silicon oxide (SiO2). x It may be any dielectric material such as silicon nitride (SiN), silicon oxynitride (SiON), or any combination thereof, but is not limited thereto.

[0027] Furthermore, the three-dimensional storage device 100 also includes multiple channel structures 130 disposed within the memory array region 111, wherein each channel structure 130 may be cylindrical. The channel structures are disposed within the storage stack structure 120 and extend through the storage stack structure 120 along a first direction D1, respectively electrically connected to a first plug 141 disposed within the substrate 110 and a second plug 143 disposed on the top of the storage stack structure 120. Each channel structure 130 includes a dielectric layer 131, a channel layer 133, and a filling layer 135 filling the remaining space of the channel hole, disposed along the sidewall of a channel hole (not shown). The channel layer 133 comprises a semiconductor material, which may be polysilicon. The dielectric layer 131 comprises a dielectric material, which is a dielectric material with a composite layer structure, such as a dielectric material comprising an oxide-nitride-oxide (ONO, not shown) structure. The filling layer 135 also comprises a dielectric material, such as silicon oxide. Thus, the channel structure 130, the conductive layer 121, the first plug 141, and the second plug 143 (which serve as the source and base, respectively) can together form a transistor. The intersection of each channel structure 130 and each conductive layer 121 can serve as a memory cell, and each conductive layer 121 serves as a word line, which is used to control the writing and reading of data in each memory cell.

[0028] It should be specifically noted that the storage stack structure 120 has two first regions 150a and 150b arranged side-by-side in the second direction D2 within the word line contact area 113, and two second regions 160a and 160b arranged side-by-side in the third direction D3 (perpendicular to the second direction D2). Thus, the two first regions 150a and 150b can be located on opposite sides (left and right) of the channel structure 130, while the two second regions 160a and 160b can be located on the other two opposite sides (upper and lower) of the channel structure 130. Figure 1As shown. The two first regions 150a and 150b, and the two second regions 160a and 160b, can each be divided into a lower half 151 of the first region, a lower half 161 of the second region, and an upper half 152 of the first region and an upper half 162 of the second region, arranged sequentially along the first direction D1. Preferably, the lower half 151 of the first region, the lower half 161 of the second region, the upper half 152 of the first region, and the lower half 162 of the second region are formed by stacking the same number of conductive-dielectric layer pairs 125. Furthermore, a first etch stop layer 171 is additionally provided between the lower half 151 of the first region and the substrate 110, and between the lower half 161 of the second region and the substrate 110. A second etch stop layer 173 is additionally provided between the upper half 152 of the first region and the lower half 151 of the first region, and between the upper half 162 of the second region and the lower half 161 of the second region, as shown. Figure 2 As shown.

[0029] In one embodiment, the first etch stop layer 171 and the second etch stop layer 173 comprise a dielectric material, such as alumina (Al2O3), that has etch selectivity with the dielectric layer 123. Preferably, the first etch stop layer 171 and the second etch stop layer 173 comprise the same dielectric material, but this is not a limitation. Furthermore, in another embodiment, each channel structure 130 may also be divided into a lower half and an upper half sequentially arranged along the first direction D1, and the lower half and the upper half are physically connected by a channel plug 137. The channel plug 137 is, for example, located between the upper half 152 of the first region and the lower half of the first region 151, or between the lower half 161 of the second region and the upper half 162 of the second region, such as... Figure 2 As shown, but not limited to.

[0030] Furthermore, it should be noted that the conductive-dielectric layer pairs 125 in the lower half 151 of the first region have mutually flush first sidewalls 153. These first sidewalls 153 extend vertically along the first direction D1 and are located between the second etch stop layer 173 and the first etch stop layer 171, and can be flush with the sidewall of the first etch stop layer 171. The conductive-dielectric layer pairs 125 in the upper half 152 of the first region gradually decrease in size from bottom to top, stacking in a stepped shape. Specifically, the stepped shape of the upper half 152 of the two first regions is formed by any two adjacent conductive-dielectric layer pairs 125 gradually receding from their flush sidewalls towards the channel structure 130, exposing a portion of the top surface of the dielectric layer 123 of the lower conductive-dielectric layer pair 125. Figure 2As shown. Preferably, the conductive-dielectric layer pair 125 between the upper halves 152 of the two first regions has a height difference H1. Meanwhile, the vertical sidewalls closest to the channel structure 130 in the upper halves 152 of the two first regions are the first vertical sidewall 154 and the second vertical sidewall 155, respectively. The first distance G1 between the first vertical sidewall 154 and the channel structure 130 and the second distance G2 between the second vertical sidewall 155 and the channel structure 130 are different. For example, the upper half 152 of the first region located on the right side of the channel structure 130 can have a relatively large minimum spacing (i.e., the second distance G2), but this is not a limitation.

[0031] On the other hand, the conductive-dielectric layer pairs 125 in each upper half 162 of the second region also have mutually aligned second sidewalls 163; the second sidewalls 163 also extend vertically along the first direction D1 and are aligned with the sidewalls of the second etch stop layer 173; while the conductive-dielectric layer pairs 125 in each lower half 161 of the two second regions are stacked in a stepped shape. Specifically, the stepped shape of the lower half 161 of the two second regions is formed by any two adjacent conductive-dielectric layer pairs 125 gradually receding from bottom to top from the sidewalls aligned with the first etch stop layer 171, exposing a portion of the top surface of the dielectric layer 123 of the lower conductive-dielectric layer pair 125, as shown below. Figure 2 As shown. Preferably, the conductive-dielectric layer pair 125 between the lower halves 161 of the two second regions also has a height difference H1. Meanwhile, the vertical sidewalls closest to the channel structure 130 in the lower halves 161 of the two second regions are the third vertical sidewall 164 and the fourth vertical sidewall 165, respectively. The third distance G3 between the third vertical sidewall 164 and the channel structure 130 and the fourth distance G4 between the fourth vertical sidewall 165 and the channel structure 130 can also be different. For example, the lower halves 161 of the second region located on the upper side of the channel structure 130 can have a relatively large minimum spacing (i.e., the fourth distance G4), but this is not a limitation.

[0032] In other words, in this embodiment, the first sidewalls 153 formed by the conductive-dielectric layer pairs 125 in the two first regions 150a and 150b, and the upper half 152 of the first regions, will not overlap with the second sidewalls 163 formed by the conductive-dielectric layer pairs 125 in the two second regions 160a and 160b, and the lower half 161 of the second regions. Furthermore, the upper half 152 of the two first regions, or the lower half 161 of the two second regions, may have a height difference H1 and different distances. Thus, the storage stack structure 120 can have a more diverse stepped structure; for example, the first regions 150a and 150b, and the second regions 160a and 160b may each have different stepped structures, allowing the subsequently manufactured plugs to retain relatively sufficient manufacturing space (process window) to facilitate the fan-out of each word line. However, those skilled in the art will readily understand that the specific configuration of the two first regions and the two second regions, or the differences in height or distance between them, are merely illustrative examples and can be further improved according to actual device requirements, without being limited to the foregoing.

[0033] For example Figure 2 As shown, the three-dimensional storage device 100 also includes an insulating layer 180 and an interlayer dielectric layer 190 sequentially disposed above the storage stack structure 120, and a plurality of word line contact plugs 200 passing through the interlayer dielectric layer 190, the insulating layer 180, and the dielectric layer 123 of each conductive-dielectric layer pair 125, respectively. The plurality of word line contact plugs 200 are in direct contact with and electrically connected to the conductive layer 121. Specifically, the insulating layer 180 is conformally covered on the storage stack structure 120, between the storage stack structure 120 and the interlayer dielectric layer 190, to directly contact the sidewalls of each conductive-dielectric layer pair 125, the first etch stop layer 171, and the second etch stop layer 173, while the interlayer dielectric layer 190 completely covers the substrate 110 and has a substantially flush surface. In one embodiment, the insulating layer 180 and the interlayer dielectric layer 190 may each comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. Preferably, the insulating layer 180 may comprise a dielectric material with high density but poor cavity-filling ability, such as silicon nitride, to improve the protective effect of the insulating layer 180 on the sidewalls of 125 for each conductive-dielectric layer. The interlayer dielectric layer 190 may comprise a dielectric material different from that of the insulating layer 180, such as silicon oxide, but not necessarily thereto. The word line contact plug 200 may comprise, for example, a conductive material, such as aluminum, titanium, tantalum, tungsten, niobium, molybdenum, copper, etc., preferably tungsten, but not necessarily thereto.

[0034] Furthermore, the word line contact plug 200 includes: a plurality of first word line contact plugs 201 and a plurality of second word line contact plugs 203.

[0035] Multiple first word line contact plugs 201 respectively contact each step of the upper half 152 of the two first regions. Multiple second word line contact plugs 203 respectively contact each step of the lower half 161 of the two second regions. The first word line contact plugs 201 are electrically connected to the conductive layer 121 of each conductive-dielectric layer pair 125 of the upper half 152 of the first region. The second word line contact plugs 203 are electrically connected to the conductive layer 121 of each conductive-dielectric layer pair 125 of the lower half 161 of the second region. Thus, the extension length of the second word line contact plugs 203 in the first direction D1 can be greater than the extension length of the first word line contact plugs 201 in the first direction D1, such as... Figure 2 As shown. Meanwhile, because there is a stepped height difference between the conductive-dielectric layer pairs 125 of the upper half 152 of the first region and the lower half 161 of the second region, each first word line contact plug 201 electrically connected to the upper half 152 of the first region and each second word line contact plug electrically connected to the lower half 161 of the second region are of unequal length, such as... Figure 2 As shown.

[0036] Therefore, the three-dimensional storage device 100 of this embodiment can intersect with each conductive layer 121 in the storage stack structure 120 through its channel structure 130, and control the writing and reading of data through each conductive layer 121 (which serves as word lines respectively). It should be noted that since the storage stack structure 120 of this embodiment has stepped upper and stepped lower halves disposed in different regions (i.e., the first regions 150a, 150b and the second regions 160a, 160b), the conductive layers 121 (i.e., the word lines) of the storage stack structure 120 can alternately fan out from the upper and lower halves of the different regions in sequence, which can effectively increase the manufacturing space of the word line contact plug 200. Furthermore, since the upper half 152 of the first regions 150a and 150b and the lower half 161 of the second regions 160a and 160b have different stepped structures, and the upper half 152 of the first regions 150a and 150b and the lower half 161 of the second regions 160a and 160b have the same number of stacked conductive-dielectric layer pairs 125, it is possible to fabricate the stepped structure of the upper half 152 of the first region and the stepped structure of the lower half 161 of the second region simultaneously through the same fabrication process, thereby simplifying the fabrication process of the storage stack structure 120. On the other hand, this embodiment provides a first etch stop line 171 between the storage stack structure 120 and the substrate 100, and a second etch stop layer 173 between the upper half 162 of the second region and the lower half 161 of the second region, and between the upper half 152 of the first region and the lower half 151 of the first region. Furthermore, channel plugs 137 for connecting the lower half and upper half of the channel structure 130 can be additionally provided in each channel structure 130. This effectively avoids problems such as collapse or structural defects in the storage stack structure 120 with a large aspect ratio. With this configuration, the three-dimensional storage device 100 of this embodiment can achieve more optimized structural integrity, thereby improving its component performance.

[0037] In order to enable those skilled in the art to implement the three-dimensional storage device 100 described in the foregoing embodiments of the present invention, the manufacturing method of the three-dimensional storage device 100 is further described in detail below.

[0038] Please refer to Figures 3 to 12 The diagram illustrates the steps of a method for manufacturing a three-dimensional storage device 100 according to an embodiment of the present invention, wherein... Figure 3 and Figure 6 The first diagram is a top view of the three-dimensional storage device 100 at different manufacturing stages, while the other diagrams are cross-sectional views of the three-dimensional storage device 100 at different manufacturing stages. First, as... Figure 3 and Figure 4As shown, a substrate 110 is provided, and then a first etch stop layer 171, multiple sets of conductive-dielectric layer pairs 125, a second etch stop material layer 273, multiple sets of conductive-dielectric layer pairs 125, and a second insulating layer 210 are sequentially formed on the substrate 110. Preferably, the number of conductive-dielectric layer pairs 125 stacked above and below the second etch stop material layer 273 is the same, but this is not a limitation. Furthermore, multiple channel structures 130 are formed on the substrate 110. Each channel structure 130 has, for example, a columnar shape. The channel structure penetrates the second insulating layer 210, the conductive-dielectric layer pairs 125, the second etch stop material layer 273, and the first etch stop layer 171 to electrically connect to a first plug 141 disposed within the substrate 110. The details of each channel structure 130 include a dielectric layer 131, a channel layer 133, and a fill layer 135 that fills the remaining space of the channel hole (not shown) disposed along the sidewall of the channel hole, but this is not a limitation.

[0039] In one embodiment, each channel structure 130 can be further divided into a lower half and an upper half sequentially arranged along a first direction D1, and the lower half and the upper half of the channel structure 130 are physically connected by a channel plug 137. The formation of the channel structure 130 includes, for example, the following steps: after forming a first etch stop layer 171 and multiple sets of conductive-dielectric layer pairs 125, first etching a channel hole (not shown) through the first etch stop layer 171, and then forming a channel plug 137 therein; then, forming a second etch stop material layer 273 and multiple sets of conductive-dielectric layer pairs 125, and etching another channel hole (not shown) through the second etch stop layer 173, and then forming a channel plug 137 therein. Thus, the channel plug 137 and the channel layer 133 are in direct contact with each other and can together form a U-shaped structure. The dielectric layer 131 is disposed on the outer wall of the U-shaped structure, while the filling layer 135 fills the inner space of the U-shaped structure. Figure 4 As shown.

[0040] Next, a first mask layer 220 (e.g., including a photoresist material and other suitable materials) is formed on the substrate 110. The first mask layer 220 covers the second insulating layer 210, wherein the first mask layer 220 has two first openings 222 extending in the second direction D2. The two first openings 222 respectively expose portions of the second insulating layer 210 located above and below the memory array region 111 (e.g., where the second regions 160a and 160b are predetermined), such as... Figure 3 , Figure 4 As shown.

[0041] like Figure 5As shown, a first etching process, such as a dry etching process or a wet etching process, is performed using a first mask layer 220 to remove the first opening 222, exposing the portion of the second insulating layer 210 and the conductive-dielectric layer pair 125 below it. It should be noted that the first etching process uses a second etch stop material layer 273 as the etch stop layer. Therefore, the conductive-dielectric layer pair 125 located above the second etch stop material layer 273 and below the portion of the second insulating layer 210 is removed, forming two second openings 224. One sidewall of the second opening 224 is the second sidewall 163 of the second regions 160 and 160a in the aforementioned embodiment (please refer to [reference]). Figure 2 (As shown). Furthermore, the second etch stop material layer 273 is also partially removed to form the second etch stop layer 173. Those skilled in the art will understand that, viewed from a top view (not shown), the two second openings 224 should be located above and below the memory array region 111, respectively. Then, the first mask layer 220 is completely removed.

[0042] like Figure 6 Such as Figure 7 As shown, a third mask layer 230 (e.g., including a photoresist material and other suitable materials) is formed on the substrate 110. The third mask layer 230 covers the second insulating layer 210 and fills one of the second openings 224. The third mask layer 230 has a third opening 232 extending in a second direction D2 and a fourth opening 234 extending in a third direction D3, wherein the third opening 232 overlaps with the second opening 224 and exposes the dielectric layer 123 of the conductive-dielectric layer pair 125 below the second etch stop layer 173, while the fourth opening 234 intersects with the third opening 232 and exposes a portion of the second insulating layer 210 located on the left side of the memory array region 111.

[0043] Next, as Figure 8 As shown, a second etching process, such as a dry etching process or a wet etching process, is performed using a third mask layer 230. From the bottom of the third opening 232, a pair of conductive-dielectric layers 125 below the second etch stop layer 173 is partially removed downwards. Simultaneously, from the bottom of the fourth opening 234, the second insulating layer 210 and the pair of conductive-dielectric layers 125 below it are partially removed downwards. This further forms a fifth opening 236 and a sixth opening 238, as shown... Figure 8 As shown. Those skilled in the art will understand that, viewed from a top view (not shown), the fifth opening 236 and the sixth opening 238 should be located below and to the left of the memory array region 111, respectively. Then, the third mask layer 230 is completely removed.

[0044] like Figures 9 to 12As shown, a trim-etching process is performed. First, as... Figure 9 As shown, a second mask layer 240 (e.g., including a photoresist material and other suitable materials) is formed on a substrate 110. The second mask layer 240 covers the second insulating layer 210 and the sidewalls of the second opening 224, the fifth opening 236, and the sixth opening 238. The second mask layer 240 further has a seventh opening 242 that exposes a portion of the second insulating layer 210 located to the right of the memory array region 111. Those skilled in the art will understand that, viewed from a top view (not shown), the seventh opening 242 extends in a third direction D3, parallel to the sixth opening 238. In one embodiment, after the formation of the second mask layer 240, a pre-trimming fabrication process may be selectively performed on the second mask layer 240, for example, by thinning it using a dry etching process or a wet etching process to fine-tune the thickness of the second mask layer 240, so as to more efficiently control the dimensions of the portions exposed from the second mask layer 240, but is not limited thereto.

[0045] like Figure 10 As shown, a third etching process, such as a dry etching process or a wet etching process, is performed using the second mask layer 240. Two sets of conductive-dielectric layer pairs 125 are removed downwards from the portions exposed by the second mask layer 240. This forms two eighth openings 244 and two ninth openings 246. The two eighth openings 244 are located above and below the memory array region 111, respectively, and there is a height difference H1 between the bottom surfaces of the two eighth openings 244 and a set of conductive-dielectric layer pairs 125. The two ninth openings 246 are located on the left and right sides of the memory array region 111, respectively, and there is also a height difference H1 between the bottom surfaces of the two ninth openings 246 and a set of conductive-dielectric layer pairs 125. Figure 10 As shown.

[0046] like Figure 11 As shown, a mask trimming fabrication process is performed on the second mask layer 240, for example, by using a dry etching process or a wet etching process to partially remove the second mask layer 240, forming a trimmed second mask layer 240a, to expose the top surface of the conductive-dielectric layer pair 125 on both sides of the eighth opening 244 and the ninth opening 246. Then, as... Figure 12As shown, a fourth etching process, such as a dry etching process or a wet etching process, is performed using the modified second mask layer 240a. Two sets of conductive-dielectric layer pairs 125 are then partially removed downwards from the bottom surfaces of the exposed conductive-dielectric layer pairs 125 and the eighth opening 244 and the ninth opening 246, respectively, forming two first stepped structures 248 and two second stepped structures 249. Those skilled in the art will understand that, viewed from a top view (not shown), the two first stepped structures 248 are located below and above the memory array region 111, respectively, and are situated between the second etch stop layer 173 and the first etch stop layer 171 in the first direction D1; while the two second stepped structures 249 are located to the left and right of the memory array region 111, respectively, and are situated between the second insulating layer 210 and the second etch stop layer 173 in the first direction D1. Then, the modified second mask layer 240a is completely removed.

[0047] Thus, repeat the process. Figures 9 to 12 The trim-etching process shown can further etch the first stepped structure 248 and the second stepped structure 249 into the upper half 152 of the first region and the lower half 161 of the second region in the aforementioned embodiment, thereby forming a structure as shown in the figure. Figure 1 and Figure 2 The storage stack structure 120 is shown. Then, an insulating layer 180, an interlayer dielectric layer 190, and word line contact plugs 200 that directly contact and electrically connect the conductive-dielectric layer pairs 125 are sequentially formed on the storage stack structure 120. Thus, the fabrication of the three-dimensional storage device 100 in this embodiment is completed.

[0048] It should be specifically noted that, according to the fabrication method of this embodiment, a second etch stop layer 173 and a first etch stop layer 171 are first formed between the conductive-dielectric layer pairs 125 and between the conductive-dielectric layer pairs 125 and the substrate 110, so as to divide the details of the stacked conductive-dielectric layer pairs 125 into an upper half (between the second insulating layer 210 and the second etch stop layer 173) and a lower half (between the second etch stop layer 173 and the first etch stop layer 171), and preferably, the number of conductive-dielectric layer pairs 125 stacked in the upper half and the lower half is the same, but not limited thereto. Next, a portion of all conductive-dielectric layer pairs 125 above the second etch stop layer 173 in the specific region is removed in one step using the first etching process. In this way, the lower half of the conductive-dielectric layer pairs 125 in the specific region and the upper half of the conductive-dielectric layer pairs 125 in the remaining regions can be etched simultaneously in the subsequent trimming-etching cycle. In this way, the purpose of fanning out each conductive layer 121 can be achieved with fewer trim-etch cycles, which can effectively shorten the fabrication time of the storage stack structure 120 and reduce the initial thickness of the mask layer (such as the second mask layer 240) used in each trim-etch fabrication process.

[0049] Furthermore, in this embodiment, before performing the trimming-etching cycle, a pair of conductive-dielectric layers 125 on one side of the memory array region 111 can be selectively removed using the second etching process. For example, the third mask layer 230 can partially cover the positions on the memory stack structure 120 where the second region 160b and the first region 150b are to be formed. Only the pair of conductive-dielectric layers 125 below the memory array region 111 (such as the position where the second region 160a is to be formed) and / or to the left (such as the position where the first region 150a is to be formed) is removed, without removing the pair of conductive-dielectric layers 125 above the memory array region 111 (such as the position where the second region 160b is to be formed) and / or to the right (such as the position where the first region 150b is to be formed). This allows for a height difference H1 between a set of conductive-dielectric layer pairs 125 between the stepped structures (such as the first stepped structure 248 and the second stepped structure 249) formed below and above the memory array region 111, and / or on the left and right sides, respectively, further increasing the difference between the stepped structures formed in different regions and improving the fabrication space for subsequent word line contact plugs 200.

[0050] In general, this invention uses an etch stop layer to divide stacked conductive-dielectric layer pairs into upper and lower halves, preferably with the same number of conductive-dielectric layer pairs stacked in the upper and lower halves. Then, the upper and lower conductive-dielectric layer pairs are pre-etched (e.g., using the first and second etching processes) to define multiple regions with different top surface heights, followed by a trimming-etching process to create a stepped structure in each region. This allows for the simultaneous formation of stepped structures in the upper and lower halves of different regions using the same mask layer, enabling the fabrication method of this invention to achieve the fan-out of each conductive layer in the memory stack structure with fewer trimming-etching cycles. Furthermore, the etch stop layer prevents memory stack structures with large aspect ratios from collapsing or developing structural defects. Thus, the three-dimensional memory device of this invention achieves optimized structural integrity and improves its component performance.

[0051] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A three-dimensional storage device, characterized in that, include: Substrate; and storage stacking structure; The storage stack structure is disposed on the substrate; The storage stack structure includes: multiple sets of conductive-dielectric layer pairs; The storage stack structure has a first region and a second region; The conductive-dielectric layer pairs in the upper half of the first region are stacked in a stepped manner; The lower half of the first region has a pair of conductive-dielectric layers with mutually flush first sidewalls; The upper half of the second region has a pair of conductive-dielectric layers with mutually flush second sidewalls; The conductive-dielectric layers in the lower half of the second region are stacked in a stepped manner; Multiple channel structures, the channel structures running through the storage stack structure; The first region and the second region are located on the first side and the second side of the channel structure, respectively, and the first side and the second side are perpendicular to each other.

2. The three-dimensional storage device according to claim 1, characterized in that, Also includes: A first etch stop layer is disposed on the substrate, located between the substrate and the memory stack structure; A second etch stop layer is disposed between the lower half of the first region and the upper half of the first region; The second etch stop layer is also disposed between the lower half of the second region and the upper half of the second region.

3. The three-dimensional storage device according to claim 2, characterized in that, The first etch stop layer and the second etch stop layer are made of the same material.

4. The three-dimensional storage device according to claim 2, characterized in that, The first sidewall is in a direction perpendicular to the substrate and is located between the second etch stop layer and the first etch stop layer.

5. The three-dimensional storage device according to claim 1, characterized in that, The first sidewall is not on the same plane as the second sidewall in a direction perpendicular to the substrate.

6. The three-dimensional storage device according to claim 1, characterized in that, The conductive-dielectric layer pair includes: a conductive layer; the three-dimensional storage device further includes: An interlayer dielectric layer covers the memory stack structure; and Multiple word line contact plugs passing through the interlayer dielectric layer; The word line contact plugs are in direct contact with the conductive layers of each of the conductive-dielectric layer pairs.

7. The three-dimensional storage device according to claim 6, characterized in that, The word line contact plug further includes: a plurality of first word line contact plugs and a plurality of second word line contact plugs; The first word line contact plug respectively contacts the conductive layer of each of the conductive-dielectric layer pairs in the upper half of the first region; The second word line contact plug respectively contacts the conductive layer of each of the conductive-dielectric layer pairs in the lower half of the second region.

8. The three-dimensional storage device according to claim 7, characterized in that, The upper half of the first region and the lower half of the second region each have the same number of stacked conductive-dielectric layer pairs.

9. The three-dimensional storage device according to claim 7, characterized in that, The extension length of the second word line contact plug in the direction perpendicular to the substrate is greater than the extension length of the first word line contact plug in the direction perpendicular to the substrate.

10. The three-dimensional storage device according to claim 1, characterized in that, Also includes: The first region has two parts, located on both sides of the channel structure; There is a height difference between the conductive-dielectric layer pairs in the upper halves of the two first regions; The second region has two areas, located on the other two sides of the channel structure, respectively; There is a height difference between the conductive-dielectric layer pairs in the lower halves of the two second regions.

11. The three-dimensional storage device according to claim 1, characterized in that, The channel structure also includes a channel plug; The channel plug is positioned between the upper and lower halves of the first region or the second region.

12. A method for manufacturing a three-dimensional storage device, characterized in that, include: Provide substrate; as well as A memory stack structure is formed on the substrate. The memory stack structure includes multiple sets of conductive-dielectric layer pairs. The memory stack structure has a first region and a second region. The conductive-dielectric layer pairs in the upper half of the first region are stacked in a stepped manner. The conductive-dielectric layer pairs in the lower half of the first region have first sidewalls that are flush with each other. The conductive-dielectric layer pairs in the upper half of the second region have second sidewalls that are flush with each other. The conductive-dielectric layer pairs in the lower half of the second region are stacked in a stepped manner. Also includes: Multiple channel structures are formed in the storage stack structure; The channel structure extends through the storage stack structure, wherein the first region and the second region are located on the first side and the second side of the channel structure, respectively, and the first side and the second side are perpendicular to each other.

13. The method for manufacturing a three-dimensional storage device according to claim 12, characterized in that, Also includes: A first etch stop layer is formed on the substrate, the first etch stop layer being located between the substrate and the memory stack structure; as well as A second etch stop layer is formed on the substrate, the second etch stop layer being located between the lower half of the first region and the upper half of the first region, and between the lower half of the second region and the upper half of the second region.

14. The method for manufacturing a three-dimensional storage device according to claim 12, characterized in that, Also includes: A first mask layer is formed on the substrate; The substrate is etched using the first mask layer to form the second sidewall of the second region; Remove the first mask layer; A second mask layer is formed on the substrate; as well as The substrate is trimmed and etched using the second mask layer to form the upper half of the second region and the lower half of the first region.

15. The method for manufacturing a three-dimensional storage device according to claim 12, characterized in that, Also includes: A third mask layer is formed on the substrate; The third mask layer covers the conductive-dielectric layer pair in the first region and the second region; A second etching process is performed on the substrate through the third mask layer to remove one pair of conductive-dielectric layers.

16. The method for manufacturing a three-dimensional storage device according to claim 15, characterized in that, The storage stack structure has two first regions, which are located on opposite sides of the channel structure, and the conductive-dielectric layer pair between the two first regions has a height difference.

17. The method for manufacturing a three-dimensional storage device according to claim 14, characterized in that, The trimming-etching process also includes: A third etching process is performed on the substrate through the second mask layer to remove the two sets of conductive-dielectric layer pairs. A mask trimming process is performed on the second mask layer, partially removing the second mask layer to form a trimmed second mask layer; and The substrate is subjected to a fourth etching process through the modified second mask layer to remove the two sets of conductive-dielectric layer pairs.

18. The method for manufacturing a three-dimensional storage device according to claim 17, characterized in that, The trimming-etching process also includes: Before the third etching process, the second mask layer is pre-trimmed to adjust its thickness.

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