Self-clamping IGBT with three-gate structure and manufacturing method thereof

Abstract

The present application belongs to the technical field of power semiconductor devices, and particularly relates to a self-clamping IGBT with a three-gate structure and a manufacturing method thereof. The present application utilizes the potential of the floating P region (14) to provide a bias potential for the split gate (11), thereby forming an electron accumulation ability below the trench, enhancing the conductance modulation effect, and thus enhancing the forward conduction capability of the device. Compared with the traditional split gate structure, the introduction of the self-bias structure is beneficial to simultaneously improving the conduction capability and switching performance of the device, eliminating the negative effects brought by the split gate, improving the switching loss and switching speed, optimizing the forward conduction capability of the device, and improving the compromise characteristics between the forward conduction voltage drop and the turn-off loss of the device. In addition, the three-split gate structure integrates the capacitance into the IGBT structure, further improving the integration of the device, and reducing the parasitic parameters caused by the metal wiring.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductor devices, and particularly relates to a self-clamping insulated gate bipolar transistor with a three-gate structure. BACKGROUND

[0002] The emergence of electric energy has promoted the rapid development of modern social science and technology, and how to more efficiently handle electric energy has always been a popular topic of scientific research all over the world. Efficient use of electric energy highly depends on power electronic systems, and the core electronic components of various power electronic systems are semiconductor power devices. Semiconductor power devices are widely used in various household appliances, various industrial equipment and other fields dominated by electric power. In the 21st century, global warming has attracted more and more attention, and energy saving and emission reduction and improvement of energy utilization efficiency are becoming increasingly important. Today, the proportion of clean and renewable energy is increasing, and society has higher expectations for energy conversion efficiency, and higher requirements for the performance of power semiconductor devices, which are the core of energy control.

[0003] Insulated gate bipolar transistors (IGBTs) are a new generation of power electronic devices because they combine the advantages of field effect transistors (MOSFETs) and bipolar junction transistors (BJTs). They have the advantages of MOSFETs, such as easy driving, low input impedance, and fast switching speed, and the advantages of BJTs, such as large on-state current density, low on-state voltage drop, small loss, and good stability. Thus, they have developed into one of the core electronic components in modern power electronic circuits and are widely used in transportation, power grids, communications, household appliances, and aerospace fields. The use of IGBTs has greatly improved the performance of power electronic systems.

[0004] Since the invention of IGBTs, people have been committed to improving the performance of IGBTs. After more than 20 years of development, multiple generations of IGBT device structures have been proposed, and the performance of the devices has been steadily improved. Traditional trench IGBTs (such as Figure 1 ) change the gate from a horizontal planar MOS to a vertical trench MOS structure, which not only improves the power density and structural design space, but also eliminates the adverse effects of the JFET region and the latch-up effect caused by the parasitic NPN. Shielded gate trench IGBTs (such as Figure 2 ) based on trench IGBTs have lower gate capacitance, thus having faster switching speed and lower switching loss. Moreover, compared with the high peak electric field at the bottom of the traditional trench gate structure, the SGT structure has the advantage of optimizing the electric field to increase the withstand voltage, thus the SGT-IGBT has greater application value in high-reliability high-performance application fields. Figure 2A cell structure of a conventional SGT-IGBT device is shown. The IGBT is an insulated gate controlled structure, and the gate forms a channel while attracting electrons in the non-channel region through the gate voltage to form an electron accumulation layer, further reducing the forward conduction voltage drop. However, in the SGT-IGBT, since the shield gate is connected to the emitter, it cannot attract electrons to form an electron accumulation layer, and the channel electron injection efficiency is reduced, so the conductance modulation effect is weaker than that of the conventional trench IGBT, and the forward conduction voltage drop is increased. SUMMARY

[0005] In order to reduce the on-state voltage drop of the device and improve the performance of the device, the present application provides a self-clamping split gate IGBT with a three-gate structure, as shown in the structural diagram Figure 3 The structure draws a potential in the floating P region 14, charges the capacitor through the polysilicon diode when the IGBT is blocked, and uses the voltage on the capacitor to provide a self-biased potential for the split gate (SG) when the IGBT is turned on, so that an electron accumulation is formed under the split gate 11 trench, thereby enhancing the forward conduction capability of the IGBT device. And by introducing a dielectric layer 12 between the split gate 11 and the emitter trench 13, the capacitor integration between the split gate 11 and the emitter is realized. Its equivalent circuit is shown in Figure 4 At the same time, the split gate 11 forms an internal field plate structure when it is blocked, optimizes the peak electric field at the bottom of the trench, and improves the forward voltage resistance capability of the IGBT. And the existence of the split gate 11 weakens the capacitive effect between the gate and the collector, accelerates the switching speed of the IGBT, reduces the switching loss of the device, and further optimizes the characteristics of the device.

[0006] The technical scheme of the present application is:

[0007] A self-clamping split gate bipolar transistor, comprising a collector metal 10, a P-type collector region 9, an N-type electric field stopping layer 8, an N-drift region 7 and an active region which are sequentially stacked from bottom to top; the active region comprises P-type base regions 4-1 and P regions 4-2 located at both ends of the upper surface of the N-drift region 7, a trench gate structure located between the P-type base regions 4-1 and the P regions 4-2, a floating P region 14, and a trench emitter structure, wherein the floating P region 14 is located between the trench gate structure and the trench emitter structure, the trench gate structure is in contact with the P-type base regions 4-1, and the trench emitter structure is in contact with the P regions 4-2, and the lower surface junction depths of the trench gate structure, the floating P region 14 and the trench emitter structure are greater than the lower surface junction depths of the P-type base regions 4-1 and the P regions 4-2;

[0008] The upper surface of the P-type base region 4-1 is provided with a P+ emitter region 2 and an N+ emitter region 3 in parallel, wherein the N+ emitter region 3 is located on the side close to the trench gate structure, and a first metal 1-1 is provided on the upper surfaces of the P+ emitter region 2 and the N+ emitter region 3;

[0009] The trench gate structure comprises a trench gate 5, a first trench emitter 13, a split gate 11, a dielectric layer 12 and an oxide layer 6, wherein the trench gate 5 and the first trench emitter 13 are arranged side by side at the upper part of the trench gate structure, the split gate 11 is located directly below the trench gate 5 and the first trench emitter 13, and the trench gate 5 and the first trench emitter 13 are isolated by the oxide layer 6; the trench gate 5 is located close to the P-type base region 4-1 and is isolated from the P-type base region 4-1, the N+ emitter region 3 and the N- drift region 7 by the oxide layer 6; the first trench emitter 13 is isolated from the floating P region 14 by the oxide layer 6; the split gate 11 is isolated from the N- drift region 7 and the floating P region 14 by the oxide layer 6; the split gate 11 is isolated from the trench gate 5 and the first trench emitter 13 by the dielectric layer 12;

[0010] The upper layer of the floating P region 14 has a P+ ohmic contact region 18 adjacent to the trench emitter structure; the P+ ohmic contact region 18 is in contact with the trench emitter structure, the upper surface of the P+ ohmic contact region 18 has a second metal 1-2, the upper surface of the floating P region 14 adjacent to the second metal 17 has a field oxide layer 17, the field oxide layer 17 is in contact with the second metal 1-2 but has a spacing with the trench gate structure, and a polysilicon diode is provided on the upper surface of the field oxide layer 17; the polysilicon diode comprises a polysilicon diode P+ region 16 and a polysilicon diode N+ region 15, and the polysilicon diode P+ region 16 is in contact with the second metal 1-2;

[0011] The trench emitter structure comprises a second trench emitter 20 and an oxide layer 6, wherein the oxide layer 6 isolates the second trench emitter 20 from the floating P region 14, the P+ ohmic contact region 18, the P region 4-2 and the N- drift region 7; the upper surface of the second trench emitter 20 has a third metal 1-3;

[0012] The upper surface of the P region 4-2 has an N+ contact region 19, and the N+ contact region 19 is in contact with the trench emitter structure; the third metal also covers the upper surface of the N+ contact region 19;

[0013] A polysilicon diode is connected in series between the split polysilicon gate 11 and the floating P region 13, the structure of the diode is located on the field oxide layer 17 on the surface of the floating P region 13, and the diode comprises an N-type polysilicon region 15, a P-type polysilicon region 16, a diode floating P connection metal 1-2, the N-type region 15 of the diode is connected to the split polysilicon gate 11, the P-type region 16 of the diode is connected to the floating P region 13 through the metal layer 1-2 and the ohmic contact P+ region 18, and an internal integrated capacitor structure is formed between the split polysilicon gate 11 and the first trench emitter 13 through the high dielectric constant dielectric layer 12.

[0014] In the above scheme, the potential of the floating P region 14 is taken as the capacitor charging through the polycrystalline PN junction, the capacitor voltage is raised, and the self-bias of the split gate is realized. This structure can improve the forward conduction characteristics on the basis of the traditional split gate structure, and is compatible with the control circuit of the traditional IGBT. In addition, the three-split gate structure integrates the capacitor into the IGBT structure, further improving the integration of the device, and reducing the parasitic parameters caused by metal wiring.

[0015] Further, the N-BL buried layer 21 is also provided between the P region 4-2 and the N+ contact region 19, and the N-BL buried layer is introduced into the P region of the clamping PN junction to form a clamping PMOS structure. The structure can provide a hole extraction channel during the off process, ensuring the floating P clamping while improving the off extraction speed of the device, further improving the dynamic characteristics of the device.

[0016] Further, the trench width of the trench emitter structure is smaller than the trench width of the trench gate structure, and the junction depth of the trench emitter structure is smaller than the junction depth of the trench gate structure, that is, the bottom of the trench emitter structure has a spacing with the bottom of the floating P region 14, while the bottom of the trench gate structure is flush with the bottom of the floating P region 14. The emitter trench etching window is reduced, and the trench depth can be further reduced while the gate trench is manufactured synchronously. At the same time, the floating P region and the clamping P region are manufactured by the same process step, saving the process step.

[0017] Further, the second trench emitter 20 is divided into a third trench emitter 20-1, a fourth trench emitter 20-2, and a fifth trench emitter 20-3, and the third trench emitter 20-1 is symmetrical with the trench gate 5, the fourth trench emitter 20-2 is symmetrical with the split gate 11, and the fifth trench emitter 20-3 is symmetrical with the first trench emitter 13. The process consistency of this scheme is better, the emitter trench and the gate trench are symmetrical, and they can be realized by a unified process step.

[0018] Further, the shallow trench gate structure is also provided at the position adjacent to the trench gate structure on the upper layer of the floating P region 12, and the width and the junction depth of the shallow trench gate structure are smaller than those of the trench gate structure; the shallow trench gate structure and the trench gate structure have a spacing, and the gate of the shallow trench gate structure is connected to the upper surface of the floating P region 14 between the shallow trench gate structure and the trench gate structure by metal. The shallow trench structure is introduced on the right side of the trench gate 5 by using the load effect, and is connected with the SG. The metal connection is made between the top of the narrow channel formed by the metal and the top of the shallow trench SG, which improves the integration and realizes the controllable PN junction.

[0019] Furthermore, the N-drift region 7 also includes P-pillars 23, which together with the N-drift region 7 form an N / P pillar superjunction drift region. The P-pillars 23 are achieved through trench filling, with similar doping concentrations, and the doping concentration is set to 1×10⁻⁶. 14 cm -3 -5×10 16 cm -3 The pillar width is 2μm-12μm, and the drift region thickness is reduced by 20-30% according to the withstand voltage requirements. The introduction of the superjunction structure is beneficial to improving the withstand voltage and trade-off performance of the device. At the same time, the laterally depleted drift pillar region assists in the longitudinal depletion layer expansion during device switching, further improving the switching speed of the device.

[0020] Furthermore, the N-type electric field blocking layer 8 is formed by hydrogen implantation, with the number of hydrogen implantations set to four, each using 1×10⁻⁶ hydrogen atoms. 12 cm -3 -1×10 15 cm -3 The implantation dose and implantation energy are within the range of 20-200 keV. Hydrogen implantation, due to its advantages of deep implantation at lower energies and lower annealing temperatures, is well-suited to replace high-temperature pre-diffusion processes for deep implantation of IGBTs. The N-drift region formed by the field stop layer of hydrogen implantation and the NN-junction of the N+FS layer have a gentler concentration gradient, which can effectively increase the dynamic avalanche tolerance of the device.

[0021] Furthermore, the collector region P region 9 also has an N region 24, which is arranged side by side with the collector region P region 9, and the N region (24) is located below the P region 4-2. Introducing a portion of the N region 24 into the collector region P region 9 realizes an RC-IGBT structure, thereby integrating the diodes within the IGBT module into the IGBT structure. The introduction of the N region into the collector region integrates the diodes within the IGBT module into the IGBT structure, improving the module integration.

[0022] Furthermore, the materials of the structure include silicon, silicon carbide, gallium nitride, gallium oxide, diamond, etc.

[0023] The method for fabricating the self-clamping split insulated gate bipolar transistor of the present invention includes:

[0024] Step 1: Select an N-type lightly doped FZ silicon wafer of a certain thickness and concentration as the N-drift region 7 of the device; grow a field oxide layer, such as... Figure 12 As shown;

[0025] Step 2: Photolithography. The floating P-region 14 of the device is fabricated by high-temperature ion implantation of P-type impurities followed by annealing. A pre-oxide layer is grown on the silicon wafer surface, such as... Figure 13 As shown;

[0026] Step 3: Active region is formed by field oxidation etching through photolithography, as shown in Figure 14 ;

[0027] Step 4: Trenches are etched through photolithography, and sacrificial oxide is grown for removing surface contamination after etching, and then trench oxide layer 6 is formed by thermal oxidation, as shown in Figure 15 ;

[0028] Step 5: N-doped polysilicon is deposited, and etched through photolithography to form gate polysilicon 5, 14 and substrate 15 of polysilicon PN diode, as shown in Figure 16 ;

[0029] Step 6: Oxide shielding layer a is first formed by thermal oxidation, and oxide layer on the surface of 5 and upper polysilicon in 5 are etched through photolithography, and high dielectric constant dielectric layer is deposited to form SGT gate polysilicon 11, as shown in Figure 17 ;

[0030] Step 7: Oxide isolation layer is formed by thermal oxidation, and then deposition is performed again, followed by intermediate etching and oxide isolation, to form polysilicon gate 5, emitter 13, and gate electrode formed by metal connection, as shown in Figure 18 , 19 ;

[0031] Step 8: P-type base region 4-1 and 4-2 of the device are made by high-temperature ion implantation of P-type impurities and annealing through photolithography, as shown in Figure 20 ;

[0032] Step 9: N+ emitter region 3 of the device is made by high-temperature ion implantation of N-type impurities and annealing, as shown in Figure 21 ;

[0033] Step 10: P+ emitter region 2, floating P ohmic contact region 18, P region 16 in polysilicon PN junction and N+ region 19 of the device are made by high-temperature ion implantation of P-type impurities and annealing, as shown in Figure 22 ;

[0034] Step 11: Emitter electrode 1-1 and metal connection 1-2 connecting polysilicon diode P region 16 and floating P ohmic contact region 18 are formed by Al metal deposition, and metal 1-3 connecting trench emitter 20 is formed, as shown in Figure 23 ;

[0035] Step 12: The silicon wafer is flipped, and the thickness of the silicon wafer is thinned, and N-type field stop layer 8 and P-type collector region 9 formed on the lower surface thereof are formed by high-energy ion implantation of N-type impurities and ion implantation of P-type impurities and annealing on the back surface of the silicon wafer, as shown in Figure 24 ;

[0036] Step 13: depositing metal on the back surface of the silicon wafer to form a metal collector 10 on the lower surface of the P-type collector region 9. Thus, a self-clamping split-gate bipolar transistor with a three-gate structure is prepared. Figure 25

[0037] For simplicity of description, the above device structure and preparation method are described by taking an N-channel IGBT device as an example, but the present application is also applicable to the preparation of a P-channel IGBT device.

[0038] The principle of the present application is described by taking an N-channel self-clamping split IGBT as an example:

[0039] When the gate electrode 5 is connected to a high potential higher than the threshold voltage of the device, the collector 10 is connected to a high potential, and the emitter 1-1, 1-2, 1-3 and the trench emitter 13 are connected to a low potential, the device works in the on state, the P+ collector region 9 injects holes into the N- drift region 7, and the N+ emitter region 3 injects electrons into the N- drift region 7, the existence of the electron-hole pairs causes the occurrence of the conductive modulation effect in the drift region.

[0040] The floating P ohmic contact region 18 above the P region 16 and the floating P region 14 is connected by the metal 1-2, the potential below the floating P region 14 is clamped by the reverse-biased PN junction composed of the P region 4-2 and the N- drift region 7, and this potential charges the integrated capacitor through the PN diode. Since the diode can maintain the charge on the capacitor and the floating P region has a relatively stable clamping voltage, the N region 15 of the diode is maintained at a stable value, and since the N region 15 of the diode is connected to the SG gate 11, the SG gate also has a stable potential, which attracts electrons near the SG gate to accumulate to form an electron accumulation layer, which improves the injection efficiency of the channel and further improves the conductive modulation effect of the drift region, thereby reducing the forward on-state voltage drop of the device.

[0041] The self-bias split gate 11 is isolated from the polysilicon structures 5 and 13 above by the high-dielectric-constant dielectric layer 12, and the capacitance value between the self-bias split gate 11 and the split emitter 13 can be adjusted by changing the deposition thickness and the corresponding area of the high-dielectric-constant dielectric layer. The split trench gate 5 and the split emitter 13 are prepared by the deposition-intermediate etching-oxidation isolation method, and the three split gate structures integrate the capacitor into the IGBT structure, further improving the integration of the device and reducing the parasitic parameters caused by metal wiring.

[0042] ​The beneficial effect of the present application is that the present application utilizes the potential of the floating P region 14 to provide a bias potential for the split gate 11, thereby forming an electron accumulation ability under the trench, enhancing the conductance modulation effect, and thus enhancing the forward conduction capability of the device. Compared with the conventional split gate structure, the introduction of the self-bias structure is beneficial to simultaneously improve the conduction capability and switching performance of the device, eliminates the negative effects brought by the split gate, improves the switching loss and enhances the switching speed, and also optimizes the forward conduction capability of the device, improves the compromise characteristics between the forward conduction voltage drop and the off-state loss of the device. In addition, the three-split gate structure integrates the capacitor into the IGBT structure, further improves the integration of the device, and reduces the parasitic parameters caused by the metal wiring.

[0043] The gate oxide layer 6 around the split polysilicon gate 11 is not limited by the threshold voltage design, so its thickness can be further increased to improve the voltage resistance and oxide layer reliability of the device, and improve the performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0044] Figure 1 is a schematic diagram of a cell structure of a conventional trench gate IGBT;

[0045] Figure 2 is a schematic diagram of a cell structure of a conventional shield gate trench IGBT;

[0046] Figure 3 is a schematic diagram of a self-clamping split gate IGBT cell structure with a three-gate structure provided by embodiment 1 of the present application;

[0047] Figure 4 is an equivalent circuit diagram of a self-clamping split gate IGBT cell structure with a three-gate structure provided by embodiment 1 of the present application;

[0048] Figure 5 is a schematic diagram of an IGBT cell structure with a PMOS clamping structure provided by embodiment 2 of the present application;

[0049] Figure 6 is a schematic diagram of an IGBT cell structure with a shallow trench emitter provided by embodiment 3 of the present application;

[0050] Figure 7 is a schematic diagram of an IGBT cell structure with an emitter trench and a gate trench symmetrical structure provided by embodiment 4 of the present application;

[0051] Figure 8 is a schematic diagram of an IGBT cell structure with a shallow trench internal inversion layer diode structure provided by embodiment 5 of the present application;

[0052] Figure 9 is a schematic diagram of an IGBT cell structure with an N / P column super junction structure replacing the N-drift region provided by embodiment 6 of the present application.

[0053] Figure 10 is a schematic diagram of an IGBT cell structure provided by embodiment 7 of the present application, in which a thick FS layer is introduced between the N-drift region and the P+ collector region by hydrogen implantation;

[0054] Figure 11 is a schematic diagram of an IGBT cell structure provided by embodiment 8 of the present application, in which a back collector region RC structure is introduced.

[0055] Figure 12-25 is a schematic diagram of a device structure obtained in a step of the manufacturing method of the present application. DETAILED DESCRIPTION

[0056] The present application will be described in detail below with reference to the accompanying drawings and embodiments.

[0057] Embodiment 1

[0058] A self-clamping split-gate bipolar transistor with a triple-gate structure, the cell structure of which is as shown in Figure 3As shown, it comprises: collector metal 10, collector region 9, N-type field stop layer 8, N-drift region 7, P-type base region 4-1, P-type clamping region 4-2, N+ emitter region 3, floating P region 14, polycrystalline diode N+ region 15 and P+ region 16, emitter ohmic contact metal 1-1, floating P region and polycrystalline diode contact metal 1-2, clamping P region ohmic contact metal 1-3, emitter ohmic contact P+ region 2, floating P region ohmic contact P+ region 18, clamping P region ohmic contact P+ region 19, trench polysilicon gate 5, trench polysilicon split emitter 13, trench polysilicon self-bias split gate 11, trench emitter 20, high dielectric constant dielectric layer 12, trench oxide layer 6; collector metal 10 is located on the back of P-type collector region 9, N-type field stop layer 8 is located on the front of P-type collector region 9, N-drift region 7 is located on the front of N-type field stop layer 8; P-type base region 4-1 is located above N-drift region 1 and on one side of trench gate 5; trench gate 5 and trench polysilicon split emitter 13 are adjacent to each other and located above self-bias split gate 5, split emitter 13 and self-bias split gate 11 are directly high dielectric constant dielectric layer 12; P-type floating region 14 is located between trench emitter 13 and trench emitter 20; polycrystalline diode 15 and 16 are located above P-type floating region 14 and are separated by field oxide layer 17, and metal 1-2 connects polycrystalline diode P+ region 16 and P-type floating region 14; N+ emitter region 3 is located on the top layer of P-type base region 4-1 and is separated from N-drift region 7 by P-type base region 4-1; P clamping structure is located above N-drift region 7 and on one side of emitter trench 20, P region 4-2 and P+ region 19 are located above the drift region, P+ region 19 is in ohmic contact with metal 1-3, and metal 18 is connected with the emitter. The structure forms a capacitor structure through the emitter 13, high-K dielectric layer 12 and self-bias split gate 11, so that C is integrated between the split gate 11 and the emitter polysilicon 13, realizing the integration of bias capacitor in the IGBT structure.

[0059] In the embodiment, the doping concentration of P-type base region 4-1 and 4-2 is 3×10 16 cm -3 ~2×10 17 cm -3 , and the depth is 3~3.5μm; the doping concentration of N+ emitter region 3 is 5×10 18 cm -3 ~1×10 21 cm -3 , and the depth is 0.2~0.5μm; the thickness of gate dielectric layer 6 is 80~120nm; the depth of trench gate electrode 5 is 4~6μm; the depth of split emitter 13 is 4~6μm; the depth of split gate electrode 11 is 0.5~2μm; the depth of trench emitter 20 is 5~8μm; the doping concentration of N-drift region 7 is 5×10 12cm -3 ~2×10 14 cm -3 The thickness is 60–700 μm; the doping concentration of the N-type electric field blocking layer 8 is 5 × 10⁻⁶. 15 cm -3 ~5×10 16 cm -3 The thickness is 5–20 μm; the doping concentration of the P-type collector region 9 is 1 × 10⁻⁶. 17 cm -3 ~1×10 19 cm -3 The thickness is 0.5–5 μm; the cell width is 20–40 μm. The high dielectric constant material 12 can be selected from alumina, hafnium oxide, zirconium dioxide, titanium dioxide, lanthanum trioxide, lutetium trioxide, niobium pentoxide, tantalum pentoxide, etc.; the cell width is 20–40 μm.

[0060] Example 2

[0061] An embodiment of a self-clamped split insulated gate bipolar transistor with a three-gate structure, such as Figure 5 As shown, based on Example 1, an N-BL buried layer 21 is introduced into the P region of the clamped PN junction to form a clamped PMOS structure. This structure can provide a hole extraction channel during the turn-off process, which improves the turn-off extraction speed of the device while ensuring the clamping of the floating P region, and further enhances the dynamic characteristics of the device.

[0062] Example 3

[0063] An embodiment of a self-clamped split insulated gate bipolar transistor with a three-gate structure, such as Figure 6 As shown, based on Example 1, the emitter trench etching window is reduced, and its trench depth can be further reduced while being fabricated simultaneously with the gate trench. At the same time, the floating P region and the clamped P region are fabricated through the same process step, saving process steps.

[0064] Example 4

[0065] An embodiment of a self-clamped split insulated gate bipolar transistor with a three-gate structure, such as Figure 7 As shown, based on Example 1, the emitter trench is split into two. The thickness of the emitter 11-2 at the bottom of the trench is the same as the thickness of the separate gate electrode 11-1, which is 0.5 to 2 μm. The thickness of the emitter 20 at the top is the same as the thickness of the trench gate electrode 5, which is 4 to 6 μm.

[0066] Compared with Example 1, this scheme has better process consistency, and the emitter trench and gate trench are symmetrical, which can be achieved through a unified process step.

[0067] Example 5

[0068] A self-clamping split-gate bipolar transistor with a three-gate structure, as shown in Figure 8 Fig. 6, introduces a shallow trench structure on the right side of the split emitter 13 based on embodiment 4, and connects it with the SG, and forms a metal connection at the top of the narrow channel with the shallow trench SG, which improves the integration and realizes the controllable PN junction.

[0069] Embodiment 6

[0070] A self-clamping split-gate bipolar transistor with a three-gate structure, as shown in Figure 9 Fig. 7, replaces the N-drift region 7 with a higher concentration N / P column super junction structure based on embodiment 4, the N column 7 is the substrate, and the P column 23 is realized by trench filling single crystal silicon or multiple epitaxial ion implantation, both have similar concentrations, and the doping concentration is set to 1×10 14 cm -3 -2×10 16 cm -3 , the column width is 2-12 μm, and the drift region thickness is reduced by 20-30% according to the voltage requirement.

[0071] Compared with embodiment 1, the introduction of the super junction structure is beneficial to improve the voltage resistance and compromise performance of the device, and the lateral depletion drift column region assists the expansion of the longitudinal depletion layer during the switching of the device, which further improves the switching speed of the device.

[0072] Embodiment 7

[0073] A self-clamping split-gate bipolar transistor with a three-gate structure, as shown in Figure 10 Fig. 8, introduces a thick FS layer 8 between the N-drift region and the P+ collector region based on embodiment 1, and the hydrogen implantation process has the advantages of large implantation depth at low energy and low annealing temperature, which is very suitable for replacing the high-temperature pre-diffusion process to form the deep implantation of the IGBT. The number of back high-energy H implantation is set to four, and the implantation dose is selected in the range of 1×10 12 cm -3 -1×10 15 cm -3 , and the implantation energy is selected as 20-200 keV.

[0074] Compared with embodiment 1, the N-drift region formed by the hydrogen-implanted field stop layer and the NN-junction of the N+FS layer have a slower concentration gradient, which can effectively increase the dynamic avalanche resistance of the device.

[0075] Embodiment 8

[0076] A self-clamping split-gate bipolar transistor with a three-gate structure, as shown inFigure 11 As shown, on the basis of embodiment 1, a part of N region 24 is introduced in the collector region P region 9 to realize RC-IGBT structure, so as to integrate the diode in the IGBT module into the IGBT structure. The N region 24 is realized by back injection, and the doping concentration is 1×10 17 cm -3 ~1×10 19 cm -3 .

[0077] Compared with embodiment 1, the introduction of the collector region N region integrates the diode in the IGBT module into the IGBT structure, and improves the module integration.

Claims

1. A self-clamping IGBT with a three-gate structure, comprising a collector metal (10), a P-type collector region (9), an N-type electric field blocking layer (8), an N-drift region (7), and an active region stacked sequentially from bottom to top; the active region includes a P-type base region (4-1) and a P-region (4-2) located at both ends of the upper surface of the N-drift region (7), a trench gate structure located between the P-type base region (4-1) and the P-region (4-2), a floating P-region (14), and a trench emitter structure, wherein the floating P-region (14) is located between the trench gate structure and the trench emitter structure, the trench gate structure is in contact with the P-type base region (4-1), the trench emitter structure is in contact with the P-region (4-2), and the lower surface junction depth of the trench gate structure, the floating P-region (14), and the trench emitter structure is greater than the lower surface junction depth of the P-type base region (4-1) and the P-region (4-2); The upper surface of the P-type base region (4-1) is provided with a P+ emitter region (2) and an N+ emitter region (3) arranged side by side, wherein the N+ emitter region (3) is located on the side close to the trench gate structure, and a first metal (1-1) is provided on the upper surface of the P+ emitter region (2) and the N+ emitter region (3). The trench gate structure includes a trench gate (5), a first trench emitter (13), a split gate (11), a dielectric layer (12), and an oxide layer (6). The trench gate (5) and the first trench emitter (13) are arranged side by side on the upper part of the trench gate structure, and the split gate (11) is located directly below the trench gate (5) and the first trench emitter (13). The trench gate (5) and the first trench emitter (13) are isolated by the oxide layer (6). The trench gate (5) is located near the first trench emitter (13). The P-type base region (4-1) is isolated from the P-type base region (4-1), the N+ emitter region (3), and the N- drift region (7) by an oxide layer (6); the first trench emitter (13) is isolated from the floating P region (14) by an oxide layer (6); the split gate (11) is isolated from the N- drift region (7) and the floating P region (14) by an oxide layer (6); the split gate (11) is isolated from the trench gate (5) and the first trench emitter (13) by a dielectric layer (12); The upper layer of the floating P region (14) adjacent to the trench emitter structure has a P+ ohmic contact region (18); the P+ ohmic contact region (18) is in contact with the trench emitter structure, the upper surface of the P+ ohmic contact region (18) has a second metal (1-2), the upper surface of the floating P region (14) adjacent to the second metal (1-2) has a field oxide layer (17), the field oxide layer (17) is in contact with the second metal (1-2) but has a gap with the trench gate structure, and a polysilicon diode is on the upper surface of the field oxide layer (17); the polysilicon diode includes a polysilicon diode P+ region (16) and a polysilicon diode N+ region (15), the polysilicon diode P+ region (16) is in contact with the second metal (1-2); The trench emitter structure includes a second trench emitter (20) and an oxide layer (6), wherein the oxide layer (6) isolates the second trench emitter (20) from the floating P region (14), the P+ ohmic contact region (18), the P region (4-2), and the N- drift region (7); the upper surface of the second trench emitter (20) has a third metal (1-3). The upper surface of the P region (4-2) has an N+ contact region (19), which is in contact with the trench emitter structure; the third metal also covers the upper surface of the N+ contact region (19); The split gate (11), dielectric layer (12) and first trench emitter (13) form an internally integrated capacitor structure. The split gate (11) is electrically connected to the N+ region (15) of the polysilicon diode, thereby charging the capacitor with the potential of the floating P region (14) to achieve self-biasing of the split gate.

2. The self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: There is also an N-BL buried layer (21) between the P region (4-2) and the N+ contact region (19), thereby forming a clamped PMOS structure that provides a hole extraction channel during the turn-off process.

3. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: The trench width of the trench emitter structure is smaller than the trench width of the trench gate structure, and the junction depth of the trench emitter structure is smaller than the junction depth of the trench gate structure. That is, there is a gap between the bottom of the trench emitter structure and the bottom of the floating P region (14), while the bottom of the trench gate structure is flush with the bottom of the floating P region (14).

4. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: The second trench emitter (20) is split into a third trench emitter (20-1), a fourth trench emitter (20-2), and a fifth trench emitter (20-3). The third trench emitter (20-1) and the trench gate (5), the fourth trench emitter (20-2) and the split gate (11), and the fifth trench emitter (20-3) and the first trench emitter (13) are in a symmetrical structure.

5. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: A shallow trench gate structure is also present in the upper layer of the floating P region (14) adjacent to the trench gate structure. The shallow trench gate structure refers to a shallow trench gate structure whose width and junction depth are both smaller than those of the trench gate structure. There is a gap between the shallow trench gate structure and the trench gate structure, and the gate of the shallow trench gate structure is connected to the upper surface of the floating P region (14) located between the shallow trench gate structure and the trench gate structure by a metal connection.

6. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: The N-drift region (7) also has a P-pillar (23), and the P-pillar (23) and the N-drift region (7) form an N / P-pillar superjunction drift region.

7. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: The N-type electric field blocking layer (8) is formed by hydrogen implantation, with the number of hydrogen implantations set to four, each using 1×10⁻⁶ hydrogen peroxide. 12 cm -3 -1×10 15 cm -3 The injection dose and injection energy are within the range of 20-200 keV.

8. A self-clamping IGBT with a three-gate structure according to claim 1, characterized in that: The P-type collector area (9) also has an N-type collector area (24), which is arranged in parallel with the P-type collector area (9) and is located below the P-type collector area (4-2).

9. A method for fabricating a self-clamping IGBT with a three-gate structure as described in claim 1, characterized in that, Includes the following steps: Step 1: Select an N-type lightly doped FZ silicon wafer with set thickness and concentration as the N-drift region of the device (7) according to the requirements, and grow a field oxygen layer on its surface; Step 2: Using photolithography, the floating P-region of the device is fabricated by high-temperature ion implantation of P-type impurities and annealing (14), and a pre-oxidation layer is grown on the silicon wafer surface; Step 3: Form the active region by photolithography etching of field oxygen; Step 4: Through photolithography, trenches are etched and sacrificial oxygen is grown to remove surface contaminants after etching, followed by thermal oxidation to form an oxide layer 6; Step 5: Deposit N-doped polysilicon and etch it using photolithography to form the trench gate structure, trench emitter structure, and substrate of the polysilicon diode; Step 6: First, thermal oxidation is performed to form an oxide shielding layer. Then, photolithography is used to etch away the oxide layer on the surface of the trench gate structure and the polysilicon in the upper layer of the trench gate structure. A split gate (11) is formed at the bottom of the trench gate structure, and a high dielectric constant dielectric layer is deposited to form a dielectric layer (12). Step 7: Perform thermal oxidation to form an oxide isolation layer and deposit it again, then perform intermediate etching and oxide isolation to form a trench gate (5) and a first trench emitter (13). Step 8: Photolithography, using high-temperature ion implantation of P-type impurities and annealing to fabricate the P-type base region (4-1) and P region (4-2) of the device. Step 9: Fabricate the N+ emitter region of the device by high-temperature ion implantation of N-type impurities and annealing (3); Step 10: The P+ emitter region (2), P+ ohmic contact region (18), P+ region (16) of the polysilicon diode, and N+ contact region (19) on the P region (4-2) are fabricated by high-temperature ion implantation of P-type impurities and annealing. Step 11: Perform Al metal deposition to form a first metal (1-1) and a second metal (1-2) connecting the P-type region (16) and the P+ ohmic contact region (18) in the diode, and a third metal (1-3) connecting the second trench emitter (20). Step 12: Flip the silicon wafer, reduce the thickness of the silicon wafer, and form an N-type electric field blocking layer (8) and a P-type collector region (9) by high-energy ion implantation of N-type impurities and ion implantation of P-type impurities on the back of the silicon wafer and annealing. Step 13: Deposit metal on the back side of the silicon wafer to form collector metal (10) on the lower surface of the P-type collector region (9).

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