Pfet structures and methods of forming the same

Abstract

The application provides a pFET structure and a forming method thereof. The forming method comprises the following steps: providing a semiconductor substrate, a first dielectric layer and a second dielectric layer with a certain thickness are sequentially formed on the surface of the semiconductor substrate, a channel material layer is formed in the first dielectric layer, the second dielectric layer and the semiconductor substrate, and the top surface of the channel material layer is higher than the surface of the second dielectric layer; removing the second dielectric layer, wherein part of the channel material layer is oxidized; removing the oxidized part of the channel material layer and consuming part of the first dielectric layer; removing the remaining first dielectric layer and part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate, and a channel layer is formed. The forming method of the application can greatly improve the thickness uniformity of the channel layer.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a pFET structure and a forming method thereof. BACKGROUND

[0002] With the improvement of the integration of semiconductor devices, the critical dimension of the transistor is continuously reduced, and the design of three-dimensional structures such as fin field effect transistor (Fin FET) has become a hot spot in the field. The fin field effect transistor is a new multi-gate device, which generally has a plurality of thin fins extending vertically upward from the substrate, a channel of the fin field effect transistor is formed in the fin, a gate structure is formed on the fin, and a source region and a drain region are formed in the fins on both sides of the gate structure. SiGe is formed in the source / drain region by epitaxial growth, which can generate compressive stress on the pFET channel, thereby effectively improving the carrier mobility of the pFET channel and achieving the improvement of the performance of the device.

[0003] With the further reduction of the technology node of semiconductor manufacturing, the improvement of channel carrier mobility by strain engineering technology shows limitations. Therefore, in order to improve the performance of the device, it has become an effective method to generate strain when the channel itself is formed. In the pFET (p-channel MosFET), it has been proved that the replacement of Si with SiGe to form a SiGe / Si double channel can effectively improve the performance of the device.

[0004] However, when a SiGe channel layer with a larger width is formed by using the existing process, the height of the surface gradually decreases from the middle to the edge, and when the width of the SiGe channel layer in the device dense area (Dense) or the device sparse area (ISO) is large, there is a large height difference (loading) between the surfaces of the SiGe channel layers in the device dense area and the device sparse area, which finally affects the height of the gate. SUMMARY

[0005] The technical problem to be solved by the present application is that the thickness uniformity of the channel layer formed by the prior art is poor.

[0006] To solve the above technical problem, the present application provides a forming method of a pFET structure, comprising: providing a semiconductor substrate, a first dielectric layer and a second dielectric layer with a certain thickness are sequentially formed on the surface of the semiconductor substrate, a channel material layer is formed in the first dielectric layer, the second dielectric layer and the semiconductor substrate, and the top surface of the channel material layer is higher than the surface of the second dielectric layer; removing the second dielectric layer, wherein part of the channel material layer is oxidized; removing the oxidized part of the channel material layer and consuming part of the first dielectric layer; removing the remaining first dielectric layer and part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate, and a channel layer is formed.

[0007] In the embodiment of the present application, the thickness of the mask layer is not less than 40 angstroms.

[0008] In the embodiment of the present application, the second dielectric layer is removed by a wet etching process, and the etching solution of the wet etching process comprises a phosphoric acid aqueous solution, wherein the mass fraction of the phosphoric acid is 50%-90%.

[0009] In the embodiment of the present application, the oxidized part of the channel material layer is removed by cleaning with a hydrofluoric acid aqueous solution, and the volume ratio of the hydrofluoric acid to water is 1:(100-500).

[0010] In the embodiment of the present application, after the oxidized part of the channel material layer is removed, the thickness of the remaining first dielectric layer is greater than 20 angstroms.

[0011] In the embodiment of the present application, the process of forming the channel layer comprises: removing part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the remaining first dielectric layer; and removing the remaining first dielectric layer, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate.

[0012] In the embodiment of the present application, part of the channel material layer is removed by a chemical mechanical polishing process, and the polishing selectivity ratio of the channel material layer to the first dielectric layer is greater than 10:1.

[0013] In the embodiment of the present application, the remaining first dielectric layer is removed by a chemical mechanical polishing process or a dry etching process or a wet etching process, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate; when the chemical mechanical polishing process is used, the polishing selectivity ratio of the channel material layer to the first dielectric layer is (0.9-1):(0.9-1); and when the dry etching process or the wet etching process is used, the etching selectivity ratio of the channel material layer to the first dielectric layer is (0.9-1):(0.9-1).

[0014] In the embodiment of the present application, the material of the first dielectric layer comprises silicon oxide, the material of the second dielectric layer comprises silicon nitride, and the material of the channel material layer comprises silicon germanium.

[0015] In the embodiment of the present application, the pFET comprises a device dense area and a device sparse area, and the device dense area and / or the device sparse area comprises a channel layer with a width greater than 300 nm.

[0016] In the embodiment of the present application, after the channel layer is formed, the method further comprises: forming a protection layer on the channel layer and the surface of the semiconductor substrate; and etching part of the protection layer, the channel layer and the semiconductor substrate to form a fin.

[0017] In the embodiment of the present application, the material of the protective layer comprises monocrystalline silicon.

[0018] The present application also provides a pFET structure formed by the method for forming a pFET structure, comprising: a semiconductor substrate; a fin located on the surface of the semiconductor substrate, comprising a channel layer and a protective layer stacked in sequence, and the thickness of the channel layer is uniform.

[0019] Compared with the prior art, the method for forming a pFET structure has the following beneficial effects:

[0020] The first dielectric layer and the second dielectric layer with specific thicknesses are sequentially formed on the surface of the semiconductor substrate, and a channel material layer is formed in the first dielectric layer, the second dielectric layer and the semiconductor substrate. After the second dielectric layer is removed, the channel material layer is processed to remove the oxidized part of the channel material layer, only part of the first dielectric layer is consumed in this process, and then the remaining first dielectric layer and part of the channel material layer are removed to form a channel layer. Each process step is linked together to improve the thickness uniformity of the channel layer.

[0021] The remaining first dielectric layer and part of the channel material layer are removed by using a step-by-step process, which further improves the thickness uniformity of the channel layer. BRIEF DESCRIPTION OF DRAWINGS

[0022] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the several views of the drawings represent similar structures. A person of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, and other embodiments can also achieve the same purpose of the invention in the present application. It should be understood that the drawings are not drawn to scale. Among them:

[0023] Figures 1 to 5 It is a structure schematic diagram corresponding to each step in the method for forming a pFET structure;

[0024] Figure 6 It is a flowchart of the method for forming a pFET structure in the embodiment of the present application;

[0025] Figures 7-13 It is a structure schematic diagram corresponding to each step in the method for forming a pFET structure in the embodiment of the present application. DETAILED DESCRIPTION

[0026] The following description provides specific applications and requirements of the present application, which is intended to enable those skilled in the art to make and use the present application. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Thus, the present application is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the claims.

[0027] When a pFET structure is fabricated by a conventional process, the effective height of the gate in the pFET structure often fails to meet the standard. Through the study of the pFET structure, it is found that one of the important reasons for the failure of the effective height of the gate is that the thickness uniformity of the channel layer is poor, and the height of the channel layer surface gradually decreases from the middle to the edge. When the pFET includes a device dense region and a device sparse region, there can also be a large height difference (loading) between the channel layer surfaces of the device dense region and the device sparse region.

[0028] Further, the formation process of the channel layer is studied as follows to obtain the factors affecting the thickness uniformity of the channel layer and the height difference between the channel layer surfaces of the device dense region and the device sparse region.

[0029] Reference Figure 1 A method for forming a pFET structure, wherein the pFET structure can include a device sparse region 11 and a device dense region 12, the device sparse region 11 refers to a region with a lower device density, and the device dense region 12 refers to a region with a higher device density, and therefore, the density of the channel layer of the device sparse region 11 is lower than that of the device dense region 12. The forming method comprises: providing a semiconductor substrate 10, the surface of the semiconductor substrate 10 is sequentially formed with a silicon oxide layer 20 and a silicon nitride layer 30, and a trench 40 is formed in the silicon oxide layer 20, the silicon nitride layer 30 and the semiconductor substrate 10. The width of the trench 40 of the device sparse region 11 is greater than 300 nm, and the width of the trench 40 of the device dense region 12 is much smaller than 300 nm.

[0030] Reference Figure 2SiGe layer 50 is formed by epitaxial growth in the trench 40. The surface of the SiGe layer 50 formed by epitaxial growth has a recess, and the width w of the recess is related to the size of the trench 40, i.e. the larger the size of the trench 40, the larger the width w of the recess. Since the size of the trench 40 in the device sparse region 11 is much larger than that in the device dense region 12, the width w of the recess in the surface of the SiGe layer 50 in the device sparse region 11 is larger. After planarizing the SiGe layer 50 in the device sparse region 11 and the device dense region 12, the morphology of the channel layer formed is quite different.

[0031] Referring to Figure 3 The silicon nitride layer 30 is removed. Since the SiGe layer 50 is prone to oxidation, the surface of the SiGe layer 50 is oxidized to form an oxide film 60 when the silicon nitride layer 30 is removed.

[0032] Referring to Figure 4 and Figure 5 The SiGe layer 50 is planarized by a chemical-mechanical planarization (CMP) process. During the CMP, the silicon oxide layer 20 acts as a barrier layer, so the polishing rate of the silicon oxide layer 20 is extremely low. However, the material of the oxide film 60 is the same as that of the silicon oxide layer 20, so the polishing rate of the oxide film 60 by the CMP is also extremely low, and thus it is difficult to remove the oxide film 60 in the CMP process. Finally, the height of the surface of the channel layer 51 formed in the device sparse region 11 gradually decreases from the middle to the edge, and there is a large height difference between the surfaces of the channel layers 51 in the device sparse region 11 and the device dense region 12, which seriously affects the performance of the device.

[0033] In view of this, the technical scheme of the present application provides a method for forming a pFET structure. A first dielectric layer and a second dielectric layer of specific thicknesses are sequentially formed on the surface of a semiconductor substrate, and a channel material layer is formed in the first dielectric layer, the second dielectric layer and the semiconductor substrate. After the second dielectric layer is removed, a process step of removing the oxidized part of the channel material layer is added, and then the top surface of the channel material layer is made coplanar with the surface of the semiconductor substrate, which greatly improves the thickness uniformity of the channel layer.

[0034] It should be noted that the thickness uniformity of the channel layer in the technical solution of the present application can refer to the thickness uniformity of different positions of the same channel layer, the thickness uniformity between different channel layers in the same region, such as the thickness uniformity between different channel layers in the device dense region or the thickness uniformity between different channel layers in the device sparse region, or the thickness uniformity between channel layers of different regions, such as the thickness uniformity between the channel layer of the device dense region and the channel layer of the device sparse region.

[0035] The forming method of the pFET structure of the technical solution of the present application is described in detail below through specific embodiments and drawings.

[0036] Reference Figure 6 The forming method of the pFET structure of the embodiment of the present application comprises:

[0037] Step S1: providing a semiconductor substrate, a first dielectric layer and a second dielectric layer of a certain thickness are sequentially formed on the surface of the semiconductor substrate, a channel material layer is formed in the first dielectric layer, the second dielectric layer and the semiconductor substrate, and the top surface of the channel material layer is higher than the surface of the second dielectric layer;

[0038] Step S2: removing the second dielectric layer, wherein part of the channel material layer is oxidized;

[0039] Step S3: removing the oxidized part of the channel material layer and consuming part of the first dielectric layer;

[0040] Step S4: removing the remaining first dielectric layer and part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate, and a channel layer is formed.

[0041] The pFET structure of the embodiment of the present application comprises a device sparse region 110 and a device dense region 120, which can be defined as described above and will not be described here. In other embodiments, the pFET structure can not distinguish between the device sparse region 110 and the device dense region 120, and the actual needs can be designed.

[0042] Reference Figure 7 A semiconductor substrate 100 is provided, which can be a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon-on-insulator or a germanium-on-insulator, etc., and can also be a substrate comprising other elemental semiconductors or compound semiconductors, such as silicon carbide, gallium arsenide, indium antimonide, gallium phosphide, gallium antimonide, aluminum gallium arsenide, indium gallium arsenide, gallium antimony phosphide, or indium phosphide, etc. In the embodiment of the present application, the material of the semiconductor substrate 100 is silicon.

[0043] The surface of the semiconductor substrate 100 is sequentially formed with a first dielectric layer 200 and a second dielectric layer 300 with specific thicknesses. The first dielectric layer 200 acts as a mask layer in the patterning process and functions as a barrier layer in the subsequent planarization process. The second dielectric layer 300 acts as a mask layer in the patterning process and protects the first dielectric layer from being consumed in the process of forming the channel material layer.

[0044] The first dielectric layer 200, the second dielectric layer 300 and the semiconductor substrate 100 are formed with a channel material layer 400, and the top surface of the channel material layer 400 is higher than the surface of the dielectric layer 300. The method of forming the channel material layer 400 can include sequentially depositing a first dielectric material layer and a second dielectric material layer with specific thicknesses on the surface of the semiconductor substrate 100; etching part of the first dielectric material layer, the second dielectric material layer and the semiconductor substrate to form trenches in the device sparse region 110 and the device dense region 120, the device sparse region 110 and / or the device dense region 120 including a channel layer with a width greater than 300 nm. In the embodiment of the present application, the device sparse region 110 includes a trench with a width greater than 300 nm, and the trench width of the device dense region 120 is much smaller than 300 nm; the channel material layer 400 is formed in the trench by an epitaxial growth process, wherein the surface of the channel material layer 400 formed in the device sparse region 110 has a relatively wide recess, and the recess of the surface of the channel material layer 400 formed in the device dense region 120 is relatively narrow.

[0045] In the subsequent process, the first dielectric layer 200 needs to be removed step by step, so the thickness of the first dielectric layer 200 needs to be within a specific range, to avoid the first dielectric layer 200 being completely consumed in one step process due to its too small thickness, or the first dielectric layer 200 having an excessively large thickness, i.e., an invalid thickness, which increases the removal time and the process cost. In the embodiment of the present application, the thickness of the first dielectric layer 200 is not less than 40 angstroms, for example, the thickness of the first dielectric layer 200 can be within the range of 40 angstroms-500 angstroms, which matches the subsequent process, ensures that the first dielectric layer 200 will not be consumed in one step process, and reduces the invalid thickness of the first dielectric layer 200 to the minimum, thereby balancing the removal time and reducing the process cost.

[0046] The material of the first dielectric layer 200 can include silicon oxide, the material of the second dielectric layer 300 can include silicon nitride, and the material of the channel material layer 400 can include silicon germanium.

[0047] Reference Figure 8, the second dielectric layer 300 is removed. In removing the second dielectric layer 300, the thickness of the first dielectric layer 200 is not consumed as much as possible, so as not to affect the subsequent process. In the embodiment of the present application, the second dielectric layer 300 is removed by a wet etching process, and the etching solution of the wet etching process includes a phosphoric acid aqueous solution, wherein the mass fraction of the phosphoric acid is 50%-90%. In the process of wet etching, only the second dielectric layer 300 can be etched, and the first dielectric layer 200 is almost not affected.

[0048] Since the surface of the channel material layer 400 has no shielding object, when the second dielectric layer 300 is removed by the wet etching process, the channel material layer 400 is inevitably affected, and part of the channel material layer 400 is oxidized to form an oxide film 500. Since the oxide film 500 is not easy to remove, it will affect the morphology of the channel material layer 400 after planarization.

[0049] Referring to Figure 9 , after the second dielectric layer 300 is removed, a process of removing the oxide film 500 is added, that is, the oxidized part of the channel material layer 400 is removed. When the oxide film 500 is removed, attention should be paid to not consume too much of the first dielectric layer 200, so as to ensure that the thickness of the remaining first dielectric layer 200 is above 20 angstroms, for example, between 20 angstroms and 40 angstroms, to meet the thickness requirement of the first dielectric layer 200 for the subsequent planarization process.

[0050] In the embodiment of the present application, the oxidized part of the channel material layer 400 is removed by cleaning with a hydrofluoric acid aqueous solution, and the volume ratio of the hydrofluoric acid to water is 1:(100-500).

[0051] Then, the remaining first dielectric layer 200 and part of the channel material layer 400 are removed, so that the top surface of the channel material layer 400 is coplanar with the surface of the semiconductor substrate 100, and a channel layer is formed.

[0052] Specifically, referring to Figure 10 , part of the channel material layer 400 is removed, so that the top surface of the channel material layer 400 is coplanar with the surface of the remaining first dielectric layer 200, and the remaining first dielectric layer 200 plays a role of a barrier layer in this process. Since the oxidized part of the channel material layer 400 has been removed by the foregoing process, the recess on the surface of the channel material layer 400 can be easily removed, so that the channel material layer 400 has a relatively flat surface. In some embodiments, part of the channel material layer 400 is removed by a chemical mechanical polishing process, and the polishing selectivity ratio of the channel material layer 400 to the first dielectric layer 200 is greater than 10:1.

[0053] Reference is made to Figure 11 , the remaining first dielectric layer 200 is removed, and the top surface of the channel material layer 400 is made coplanar with the surface of the semiconductor substrate 100, forming a channel layer 410. The remaining first dielectric layer 200 can be removed by a chemical mechanical polishing process or a dry etching process or a wet etching process, and the top surface of the channel material layer 400 is made coplanar with the surface of the semiconductor substrate 100. When the chemical mechanical polishing process is used, the polishing selectivity ratio of the channel material layer 400 and the first dielectric layer 200 is (0.9-1):(0.9-1), and the surface of the channel layer 410 formed is relatively flat; when the dry etching process or the wet etching process is used, the etching selectivity ratio of the channel material layer 400 and the first dielectric layer 200 is (0.9-1):(0.9-1), and the surface of the channel layer 410 formed has fewer defects.

[0054] The embodiments of the present application form a channel layer by increasing the thickness of the first dielectric layer, adding a process step of removing the oxidized part of the channel material layer, and removing the remaining first dielectric layer and part of the channel material layer in steps, which are closely related to each other and together improve the flatness and thickness uniformity of the channel layer.

[0055] Reference is made to Figure 12 , after the channel layer is formed, further comprising: forming a protective layer 600 on the channel layer 410 and the surface of the semiconductor substrate 100. The material of the protective layer 600 can include single crystal silicon. Reference is made to Figure 13 , etching part of the protective layer 600, the channel layer 410 and the semiconductor substrate 100 to form a fin. Since the channel layer 410 formed by the foregoing process has excellent thickness uniformity, the fin formed has excellent height uniformity, further making the subsequently formed gate have the same effective height, and improving the performance of the device.

[0056] Reference is made to Figure 13 , the embodiments of the present application also provide a pFET structure formed by the above process, comprising: a semiconductor substrate 100; a fin located on the surface of the semiconductor substrate 100, comprising a channel layer 410 and a protective layer 600 stacked in turn, and the thickness of the channel layer 410 is uniform. In some embodiments, the material of the channel layer 410 includes silicon germanium, and the material of the protective layer 600 includes single crystal silicon.

[0057] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only in an exemplary manner and can not be limiting. Although not explicitly stated here, those skilled in the art can understand that the present application intends to encompass various reasonable changes, improvements and modifications to the embodiments. These changes, improvements and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0058] It should be understood that the term "and / or" as used herein encompasses any and all combinations of one or more of the associated listed items.

[0059] Similarly, it should be understood that, when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements can also be present. In contrast, the term "directly on" means that there are no intervening elements present. It will also be understood that, when a term is used in this disclosure in a certain context, that does not exclude the use of that term in another context.

[0060] It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments can be termed a second element in other embodiments without departing from the teachings of this disclosure. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0061] In addition, the specification of this application describes example embodiments by reference to idealized illustrative cross-sectional and / or plan and / or perspective views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, the example embodiments should not be construed as limited to the precise shapes and regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the example embodiments.

Claims

1. A method of forming a pFET structure, the method comprising: The method comprises: providing a semiconductor substrate, a surface of the semiconductor substrate sequentially forms a first dielectric layer and a second dielectric layer with a certain thickness, the first dielectric layer, the second dielectric layer and the semiconductor substrate form a channel material layer, and a top surface of the channel material layer is higher than a surface of the second dielectric layer; removing the second dielectric layer, wherein part of the channel material layer is oxidized; removing the oxidized part of the channel material layer and consuming part of the first dielectric layer; removing the remaining first dielectric layer and part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate, and a channel layer is formed.

2. The method of forming a pFET structure of claim 1, wherein, The thickness of the first dielectric layer is not less than 40 angstroms.

3. The method of forming a pFET structure of claim 1, wherein, The second dielectric layer is removed by a wet etching process, and the etching solution of the wet etching process comprises a phosphoric acid aqueous solution, wherein the mass fraction of the phosphoric acid is 50%-90%.

4. The method of forming a pFET structure of claim 1, wherein, The oxidized part of the channel material layer is removed by cleaning with a hydrofluoric acid aqueous solution, and the volume ratio of the hydrofluoric acid to water is 1: (100-500).

5. The method of forming a pFET structure of claim 1, wherein, After removing the oxidized part of the channel material layer, the thickness of the remaining first dielectric layer is more than 20 angstroms.

6. The method of forming a pFET structure of claim 1, wherein, The method for forming the channel layer comprises: removing part of the channel material layer, so that the top surface of the channel material layer is coplanar with the surface of the remaining first dielectric layer; removing the remaining first dielectric layer, and making the top surface of the channel material layer coplanar with the surface of the semiconductor substrate.

7. The method of forming a pFET structure of claim 6, wherein, Part of the channel material layer is removed by a chemical mechanical polishing process, and the polishing selectivity ratio of the channel material layer to the first dielectric layer is greater than 10:

1.

8. The method of forming a pFET structure of claim 6, wherein, The remaining first dielectric layer is removed by a chemical mechanical polishing process, a dry etching process or a wet etching process, and the top surface of the channel material layer is coplanar with the surface of the semiconductor substrate, when the chemical mechanical polishing process is used, the polishing selectivity ratio of the channel material layer to the first dielectric layer is (0.9-1):(0.9-1); when the dry etching process or the wet etching process is used, the etching selectivity ratio of the channel material layer to the first dielectric layer is (0.9-1):(0.9-1).

9. The method of forming a pFET structure of claim 1, wherein, The material of the first dielectric layer comprises silicon oxide, the material of the second dielectric layer comprises silicon nitride, and the material of the channel material layer comprises silicon germanium.

10. The method of forming a pFET structure of claim 1, wherein, The pFET comprises a device dense area and a device sparse area, wherein the device dense area and / or the device sparse area comprises a channel layer with a width greater than 300 nm.

11. The method of forming a pFET structure of claim 1, wherein, After forming the channel layer, the method further comprises: forming a protective layer on the surface of the channel layer and the semiconductor substrate; etching part of the protective layer, the channel layer and the semiconductor substrate to form a fin.

12. The method of forming a pFET structure of claim 11, wherein, The material of the protective layer comprises monocrystalline silicon.

13. A pFET structure, characterized by, The method for forming the pFET structure of claim 11 or 12 comprises: a semiconductor substrate; a fin located on the surface of the semiconductor substrate, comprising a channel layer and a protective layer stacked in sequence, and the thickness of the channel layer is uniform.

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