A fully two-dimensional ferroelectric ultra-steep slope transistor, its fabrication method and application

Abstract

This invention relates to a fully two-dimensional ferroelectric ultra-steep slope transistor, its fabrication method, and its applications. The transistor comprises a three-layer fully two-dimensional heterostructure consisting of a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional semiconductor channel layer stacked sequentially. The source and drain are located on the two-dimensional conductive layer; the gate is located on the two-dimensional conductive layer and is not in contact with the two-dimensional ferroelectric AgInP2Se6 layer or the channel layer. This fully two-dimensional ferroelectric ultra-steep slope transistor exhibits an ultra-steep subthreshold swing, extremely low operating voltage, and ultra-fast operating frequency, providing a new path for the development of future large-scale integrated circuits. In one embodiment, the transistor's subthreshold swing at room temperature can reach as low as 10 mV / decade, breaking the theoretical limit of traditional field-effect transistors (60 mV / decade), and its operating voltage can reach as low as 0.1 V.

Description

Technical Field

[0001] This invention relates to the field of next-generation microelectronic devices and integrated circuits, and in particular to a fully two-dimensional ferroelectric ultra-steep slope transistor, its fabrication method, and its application. Background Technology

[0002] With the emergence of new technologies such as the Internet of Things, artificial intelligence, and autonomous driving, data acquisition and processing capabilities have been greatly enhanced, leading to higher demands on next-generation transistors and electronic chips: smaller size, lower power consumption, and higher performance. The development of traditional epitaxial semiconductors such as Si and Ge, and their devices, has encountered bottlenecks. Due to the short-channel effect, the size of Si-based transistors cannot be further reduced, and Moore's Law is gradually failing. Although the development of fin-type and 3D transistors can greatly increase the number of transistors on a single chip, it also makes the manufacturing process extremely complex. On the other hand, due to the Boltzmann distribution limitation, the subthreshold swing of Si-based transistors cannot exceed its theoretical limit of 60mV / Dec, preventing further reductions in device power consumption.

[0003] In recent years, two-dimensional layered materials, represented by graphene and transition metal chalcogenides, have become the most promising candidate material systems for next-generation information applications due to their unique physical properties such as atomic layer thickness, van der Waals interactions, mechanical flexibility, and strong photo-matter interactions. Two-dimensional semiconductors have atomic-level surface smoothness, with all electrons localized in atomically thick channels, resulting in transistors that exhibit excellent gate voltage coupling and high carrier mobility at extremely small sizes.

[0004] Meanwhile, ferroelectric materials exhibit spontaneous polarization within a certain temperature range. This is due to the non-coincidence of positive and negative charge centers in their crystal lattice, allowing them to generate an electric dipole moment even without an external electric field. Furthermore, this spontaneous polarization can change direction under the influence of an external electric field. Therefore, researchers have explored using ferroelectric materials as gate materials in field-effect transistors (FETs), applying an external electric field to control the source and drain currents. Since the saturation current in an FET is directly proportional to the dielectric constant of the gate material, and ferroelectric materials have a higher dielectric constant than the gate insulator materials in traditional FETs, this can increase device current and improve device response speed, making them suitable for ultra-high-speed integrated circuits.

[0005] Integrating ferroelectric materials into the gate stack of traditional transistors can generate effective negative capacitance, thereby overcoming the Boltzmann limitation and reducing subthreshold swing and operating voltage. With the discovery of two-dimensional ferroelectric materials (such as CuInP2S6 and α-In2Se3), ferroelectric transistors based on van der Waals heterostructures have become a new research hotspot. Their excellent properties, such as atomic layer thickness, absence of surface dangling bonds, high polarization electric field and holding force, and flexibility, enable the application of micro-sized, highly steep, and low-power electronic devices. Simultaneously, the combination of two-dimensional semiconductors and ferroelectric materials can also solve the problem of integrating computing transistors with memory, constructing dual-function chips for signal processing and storage operations, and realizing future technological applications such as brain-like neural perception and data computing. Summary of the Invention

[0006] To address the technical problems existing in the prior art, the primary objective of this invention is to provide a novel all-two-dimensional ferroelectric ultra-steep-slope transistor that is smaller in size, consumes less power, and operates at higher speeds. This invention provides at least the following technical solutions.

[0007] A fully two-dimensional ferroelectric ultra-steep slope transistor includes a three-layer fully two-dimensional heterostructure, a source, a drain, and a gate. The three-layer fully two-dimensional heterostructure consists of a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional semiconductor channel layer. The few-layer two-dimensional ferroelectric AgInP2Se6 layer is located on the two-dimensional conductive layer, and the few-layer two-dimensional semiconductor channel layer is located on the two-dimensional ferroelectric AgInP2Se6 layer. The source and drain are located on the two-dimensional conductive layer. The gate is located on the two-dimensional conductive layer and does not contact the two-dimensional ferroelectric AgInP2Se6 layer or the channel layer.

[0008] Furthermore, the thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1–100 nm.

[0009] Furthermore, the two-dimensional conductive layer is selected as a graphene layer, and the thickness of the graphene layer is 1-20 nm.

[0010] Furthermore, the two-dimensional semiconductor channel layer is selected from two-dimensional TMDs channel layers or graphene layers, the two-dimensional TMDs channel layer is selected from two-dimensional MoS2 layers, and the thickness of the two-dimensional semiconductor channel layer is 1-50 nm.

[0011] Furthermore, the gate, source, and drain are selected as Cr / Au electrodes or Ti / Au electrodes, the thickness of the Cr layer and Ti layer is 1-10 nm, and the thickness of the Au layer is 30-100 nm.

[0012] The present invention also provides a transistor for use in integrated circuits, wherein the transistor is selected from the above-mentioned all-two-dimensional ferroelectric ultra-slope transistor.

[0013] This invention also provides a method for fabricating a fully two-dimensional ferroelectric ultra-steep slope transistor, comprising the following steps:

[0014] A few-layer two-dimensional conductive material layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional channel material layer were obtained by mechanical exfoliation.

[0015] A PVA dry transfer process was used to transfer the target two-dimensional ferroelectric AgInP2Se6 layer onto the two-dimensional conductive material layer, thereby obtaining a high-quality two-dimensional conductive material layer-two-dimensional ferroelectric AgInP2Se6 layer interface.

[0016] Using a PVA dry transfer process, the two-dimensional TMDs channel layer is transferred to the two-dimensional ferroelectric AgInP2Se6 layer to obtain a three-layer full two-dimensional heterostructure.

[0017] Metal electrodes are fabricated on the above three-layer all-two-dimensional heterostructure, wherein a gate metal is deposited on the two-dimensional conductive layer material layer, and the gate metal does not contact the two-dimensional ferroelectric AgInP2Se6 layer and the two-dimensional channel material layer; a source metal and a drain metal are deposited on the two-dimensional channel material layer, and the source metal and the drain metal do not contact the two-dimensional ferroelectric AgInP2Se6 layer and the two-dimensional channel material layer.

[0018] Furthermore, the thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1–100 nm; the two-dimensional TMDs channel layer is selected from two-dimensional MoS2 or graphene layers, and the thickness of the two-dimensional TMDs channel layer is 1–50 nm.

[0019] Furthermore, the few-layer two-dimensional conductive material layer is selected as a graphene layer, and the thickness of the graphene layer is 1-20 nm.

[0020] Furthermore, the PVA dry transfer process also includes transferring the thin layer above the selected target layer, setting the heating stage temperature to 50-100°C, holding it at that temperature for 5-20 minutes, then immersing it in water, rinsing it with deionized water, and drying it with a nitrogen gun to obtain a high-quality thin layer-target layer interface.

[0021] Furthermore, after depositing the gate metal, source metal, and drain metal, the metal is annealed in an inert gas atmosphere at a temperature of 100–200°C for 10–60 minutes.

[0022] Furthermore, before using the mechanical stripping method, the SiO2 / Si substrate was soaked in acetone solution, isopropanol solution, and deionized water in sequence, and after each soaking, it was placed in an ultrasonic cleaner for ultrasonic cleaning. The ultrasonic power was 10%, and the ultrasonic time was 1 to 20 minutes.

[0023] Compared with the prior art, the present invention has at least the following beneficial effects:

[0024] This invention provides a fully two-dimensional ferroelectric ultra-steep slope transistor with smaller size, lower power consumption, and higher speed. The transistor uses a two-dimensional AgInP2Se6 layer with excellent ferroelectric properties to construct a three-layer fully two-dimensional heterostructure consisting of a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional semiconductor channel layer. The transistor exhibits an ultra-steep subthreshold swing, extremely low operating voltage, and ultra-fast operating frequency, providing a new path for the development of future large-scale integrated circuits.

[0025] Another aspect of the present invention provides a method for fabricating a fully two-dimensional ferroelectric ultra-steep-slope transistor. This method is simple and easy to implement, and can yield transistor devices of smaller size. In one embodiment of the present invention, the transistor achieved a subthreshold swing of as low as 10 mV / decade at room temperature, breaking the theoretical limit (60 mV / decade) of traditional field-effect transistors, and its operating voltage can reach as low as 0.1 V. The solution provided by this invention has significant application prospects in future high-frequency, high-speed, extremely small-size, and ultra-low-power semiconductor chips and integrated circuits. Attached Figure Description

[0026] Figure 1 This is an optical microscope image of the fully two-dimensional ferroelectric transistor of Example 1.

[0027] Figure 2 This is a schematic diagram of the structure of the fully two-dimensional ferroelectric transistor in Example 1.

[0028] Figure 3 The PFM phase diagram of AgInP2Se6, a two-dimensional ferroelectric material, is shown in Example 1.

[0029] Figure 4 The images show the Raman spectra and mapping diagrams of AgInP2Se6 and the three-layer fully two-dimensional heterojunction in Example 1.

[0030] Figure 5 The transfer curve is shown for the fully two-dimensional ferroelectric transistor of Example 1. Detailed Implementation

[0031] The technical solutions in the embodiments of the present invention will now be clearly and completely described with reference to the accompanying drawings. The described embodiments are merely some, not all, of the embodiments of the present invention. Other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are all within the scope of protection of the present invention. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials, unless otherwise specified, can be obtained from publicly available commercial channels.

[0032] This specification uses spatially relative terms such as “below,” “under,” “down,” “above,” “above,” and “upper” to explain the positioning of one element relative to a second element. These terms are intended to cover different orientations of the device, except for those different from those shown in the figures.

[0033] Furthermore, the use of terms such as "first" and "second" to describe various elements, layers, regions, and sections is not intended to be restrictive. The use of terms such as "having," "containing," "including," and "comprises" are open-ended terms, indicating the presence of the stated elements or features, but not excluding additional elements or features, unless the context explicitly states otherwise.

[0034] See Figure 1 and Figure 2 One embodiment of the present invention provides a fully two-dimensional ferroelectric ultra-steep slope transistor, which includes a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, a few-layer two-dimensional semiconductor channel layer, a source, a drain, and a gate. The two-dimensional conductive layer is disposed on a substrate, the substrate being a SiO2 / Si substrate, and the two-dimensional conductive layer is a graphene layer with a thickness of 1–20 nm.

[0035] A few-layer two-dimensional ferroelectric AgInP2Se6 layer is disposed on a few-layer two-dimensional conductive layer, and the thickness of the few-layer two-dimensional ferroelectric AgInP2Se6 layer is selected from 1 to 50 nm. The few-layer two-dimensional semiconductor channel layer is selected from a few-layer two-dimensional TMDs channel layer or a graphene layer, and the thickness of the few-layer two-dimensional semiconductor channel layer is selected from 1 to 50 nm. In a preferred embodiment, the few-layer two-dimensional TMDs channel layer is selected from two-dimensional MoS2. The gate is located on the two-dimensional conductive layer and does not contact the two-dimensional ferroelectric AgInP2Se6 layer or the channel layer; the source and drain are located on the two-dimensional channel layer and do not contact the two-dimensional ferroelectric AgInP2Se6 layer or the two-dimensional conductive layer. The gate, source, and drain are selected from Cr / Au layers or Ti / Au layers, wherein the thickness of the Cr layer is 1 to 10 nm, and the thickness of the Au layer is 30 to 100 nm.

[0036] Example 1

[0037] Step 1: Soak the SiO2 / Si substrate sequentially with acetone solution, isopropanol solution, and deionized water, and after each soaking, place it in an ultrasonic cleaner for ultrasonic cleaning. The ultrasonic power is 10% and the ultrasonic time is 5 minutes.

[0038] Step 2: Transfer a large-area thin-layer graphene using a mechanical exfoliation method. A relatively large area of ​​graphene with a thickness of 10 nm and a relatively flat surface is selected as the few-layer two-dimensional conductive layer.

[0039] Step 3: Cut a PVA / PDMS material of appropriate size, peel off the two-dimensional ferroelectric material AgInP2Se6, and select AgInP2Se6 with a thickness of 10nm and relatively flat as the two-dimensional ferroelectric layer.

[0040] Step 4: Using a transfer platform, transfer the selected AgInP2Se6 thin layer onto the selected graphene. Adjust the heating stage temperature to 60°C for 10 minutes. Then immerse it in water, wash it with deionized water, and dry it with a nitrogen gun to obtain a high-quality graphene-AgInP2Se6 interface.

[0041] Step 5: Using the same PVA dry transfer technology, the prepared two-dimensional MoS2 is transferred to the above AgInP2Se6-graphene heterostructure. The material is adhered tightly and the temperature of the heating stage is adjusted to 60°C for 10 minutes. Then it is immersed in water, washed with deionized water, and dried with a nitrogen gun to obtain a clean and undamaged three-layer full two-dimensional heterostructure.

[0042] Step 6: Using a maskless ultraviolet lithography machine and electron beam evaporation technology, electrodes are fabricated in the above three-layer all-two-dimensional heterojunction. Cr / Au electrodes are deposited at both ends of the two-dimensional MoS2 as the source and drain electrodes, respectively. Note that the source and drain electrodes must not contact the two-dimensional ferroelectric layer AgInP2Se6 and the graphene layer. A Cr / Au electrode is deposited at one end of the graphene layer as the gate electrode, and it must not contact the ferroelectric layer AgInP2Se6 and the two-dimensional MoS2.

[0043] Step 7: Finally, place the prepared device on the heating stage in the glove box, set the temperature to 150℃, and the duration to 60 minutes to improve the contact quality of the electrodes and obtain a high-performance novel all-two-dimensional transistor.

[0044] The piezoelectric phase diagram (PFM) of the ferroelectric two-dimensional material AgInP2Se6 obtained in Example 1 is shown below. Figure 3 As shown, this two-dimensional AgInP2Se6 exhibits excellent ferroelectric properties. Figure 4 Figure (a) shows the Raman spectrum of the two-dimensional AgInP2Se6 ferroelectric material, and Figure (b) shows the mapping diagram of the three-layer full two-dimensional heterostructure. It can be seen that the material used in the full two-dimensional heterostructure has high crystal quality.

[0045] By performing electrical transport measurements such as the transfer output of the device, such as Figure 5The transfer curves shown demonstrate that the fully two-dimensional ferroelectric field-effect transistor developed in this invention exhibits an ultra-steep subthreshold swing, extremely low operating voltage, and ultra-fast operating frequency, providing a new path for the development of future large-scale integrated circuits. The device achieves a subthreshold swing as low as 10mV / decade at room temperature, breaking the theoretical limit of 60mV / decade for traditional field-effect transistors, and its operating voltage can be as low as 0.1V.

[0046] The above embodiments are preferred embodiments of the present invention, but the embodiments of the present invention are not limited to the above embodiments. Any changes, modifications, substitutions, combinations, or simplifications made without departing from the spirit and principle of the present invention shall be considered equivalent substitutions and shall be included within the protection scope of the present invention.

Claims

1. A fully two-dimensional ferroelectric ultra-steep slope transistor, characterized in that, The device comprises a three-layer fully two-dimensional heterostructure, a source, a drain, and a gate. The three-layer fully two-dimensional heterostructure consists of a few-layer two-dimensional conductive layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional semiconductor channel layer. The few-layer two-dimensional ferroelectric AgInP2Se6 layer is located on the two-dimensional conductive layer, and the few-layer two-dimensional semiconductor channel layer is located on the two-dimensional ferroelectric AgInP2Se6 layer. The source and drain are located on the two-dimensional conductive layer. The gate is located on the two-dimensional conductive layer and does not contact the two-dimensional ferroelectric AgInP2Se6 layer or the channel layer. The thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1~100 nm, and the two-dimensional conductive layer is a graphene layer. Specifically, a PVA dry transfer process is used to transfer the target two-dimensional ferroelectric AgInP2Se6 layer onto the two-dimensional conductive layer. The heating stage temperature is set at 50~100℃ and held for 5~20 minutes to obtain a high-quality two-dimensional conductive layer-two-dimensional ferroelectric AgInP2Se6 layer interface. A PVA dry transfer process is also used to transfer the two-dimensional semiconductor channel layer onto the two-dimensional ferroelectric AgInP2Se6 layer. The heating stage temperature is set at 50~100℃ and held for 5~20 minutes to obtain a three-layer fully two-dimensional heterostructure. After setting the gate metal, source metal, and drain metal, anneal in an inert gas atmosphere at a temperature of 100~200℃ for 10~60 minutes.

2. The transistor according to claim 1, characterized in that, The thickness of the two-dimensional conductive layer is 1~20nm.

3. The transistor according to claim 1 or 2, characterized in that, The two-dimensional semiconductor channel layer is selected from two-dimensional TMDs channel layers or graphene layers. The two-dimensional TMDs channel layer is selected from two-dimensional MoS2 layers. The thickness of the two-dimensional semiconductor channel layer is 1~50nm.

4. The transistor according to claim 1 or 2, characterized in that, The gate, source, and drain are selected from Cr / Au electrodes or Ti / Au electrodes, with the thickness of the Cr and Ti layers being 1~10nm and the thickness of the Au layer being 30~100nm.

5. A transistor used in integrated circuits, characterized in that, The transistor is selected from any one of claims 1 to 4.

6. A method for fabricating a fully two-dimensional ferroelectric ultra-steep slope transistor, characterized in that, Includes the following steps: A few-layer two-dimensional conductive material layer, a few-layer two-dimensional ferroelectric AgInP2Se6 layer, and a few-layer two-dimensional channel material layer were obtained by mechanical exfoliation. Using a PVA dry transfer process, the target two-dimensional ferroelectric AgInP2Se6 layer is transferred onto the two-dimensional conductive material layer. The heating stage temperature is set to 50~100℃ and held for 5~20 minutes to obtain a high-quality interface between the two-dimensional conductive material layer and the two-dimensional ferroelectric AgInP2Se6 layer. Using a PVA dry transfer process, the two-dimensional semiconductor channel layer is transferred to the two-dimensional ferroelectric AgInP2Se6 layer. The heating stage temperature is set to 50~100℃ and held for 5~20 minutes to obtain a three-layer full two-dimensional heterostructure. Metal electrodes are fabricated on the above three-layer all-two-dimensional heterostructure, wherein a gate metal is deposited on the two-dimensional conductive material layer, and the gate metal does not contact the two-dimensional ferroelectric AgInP2Se6 layer and the two-dimensional semiconductor channel material layer; a source metal and a drain metal are deposited on the two-dimensional semiconductor channel material layer, and the source metal and the drain metal do not contact the two-dimensional ferroelectric AgInP2Se6 layer; after the gate metal, source metal and drain metal are deposited, they are annealed in an inert gas atmosphere at a temperature of 100~200℃ for 10~60 minutes. The thickness of the two-dimensional ferroelectric AgInP2Se6 layer is 1~100nm, and the few-layer two-dimensional conductive material layer is a graphene layer.

7. The method for fabricating a transistor according to claim 6, characterized in that, The two-dimensional channel material layer is selected from two-dimensional MoS2 or graphene layers, and the thickness of the two-dimensional channel material layer is 1~50nm; the thickness of the two-dimensional conductive material layer is 1~20nm.

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