Keyboard and its self-adaptive method, electronic computing device-readable medium and program

Abstract

The present invention discloses a keyboard adaptable to line aging, an adaptive method for the keyboard, a computer-readable medium storing a program, and a computer program product. A processor alternately feeds a scan signal to each scan line in a scan round. The processor detects a return signal on a corresponding return line in response to the conduction state of one of the switching elements, and selects at least one of the plurality of scan lines as a test line. During a first period when the scan signal is maintained on the test line, the processor detects the start point of the first period and the start point of the return signal corresponding to the first period to obtain a time difference, and the processor determines whether to update the response time parameter corresponding to the test line stored in the memory according to the time difference and the response time parameter corresponding to the test line stored in the memory.

Description

Technical Field

[0001] The present invention relates to keyboard scanning technology, and in particular to a keyboard adaptable to line aging, an adaptive method for the keyboard, a computer-readable medium storing a program related to the adaptive method for the keyboard, and a computer program product. Background Art

[0002] A computer keyboard is one of the essential human-computer interface input devices for a personal computer, and most of the circuits of a computer keyboard adopt a matrix key switch circuit. Its advantages are simple circuit, fast operation, and low cost. Currently, most matrix key switches adopt processes such as printed circuit board layout (PCBA layout) or membrane screen printing. There are impedance, parasitic capacitance, and distributed capacitance in the wiring circuit.

[0003] Figure 1 For the circuit diagram of the existing matrix key switch. Please refer to Figure 1 , the circuit 100 of the matrix key switch usually includes a switch element SW, a scan line 102, and a return line 101. The switch element SW is coupled to the intersection of the scan line 102 and the return line 101.

[0004] The impedance of the above wiring can be represented by an equivalent resistance R eq The above parasitic capacitance and distributed capacitance can be represented by an equivalent capacitance C eq to represent.

[0005] The operation mode of the circuit 100 of the existing matrix key switch is to input a low-potential signal to the scan line 102 during a scan period. If the switch element SW is pressed during the scan period, the scan line 102 and the return line 101 connected to the switch element SW form a conduction state, and the low-potential signal input to the scan line 102 will be transmitted to the return line 101. Therefore, by detecting the potential of the return line 101, it can be known whether the switch element SW is pressed.

[0006] Please also refer to Figure 1 and Figure 2 , Figure 2 shows the voltage state diagram 200 of the cross-voltage V eq of the equivalent capacitance C ceq responding to the pressing state of the switch element SW. During the period 201 in Figure 2 , V ceqMaintained at the reference potential Vcc. If the switch element SW is pressed during the scanning period, then V ceq begins to drop. When the line ages, the equivalent resistance R eq representing the impedance of the trace and the equivalent capacitance C eq representing the parasitic capacitance and the distributed capacitance increase in value. The increased value of the equivalent resistance R eq and the value of the equivalent capacitance C eq cause the duration of the V ceq drop 202 to become longer, interfering with the potential detection of the return line 101 during the scanning period, thereby causing an error in detecting the pressing of the switch element SW and reducing the accuracy of detecting the pressing of the switch element SW. SUMMARY OF THE INVENTION

[0007] In view of this, the present invention provides a keyboard that adapts to line aging, an adaptive method for a keyboard, a computer-readable medium storing a program, and a computer program product, which improve the problems of the prior art.

[0008] The present invention provides a keyboard that adapts to line aging. The keyboard that adapts to line aging includes a scanning circuit. The scanning circuit includes a plurality of scanning lines, a plurality of return lines, and a plurality of switch elements. These switch elements are respectively coupled to the intersections of these scanning lines and these return lines. The keyboard that adapts to line aging further includes a processor and a memory. The memory stores a plurality of response time parameters respectively corresponding to these scanning lines. The processor is coupled to the scanning circuit and the memory to alternately feed scanning signals to each scanning line in a scanning round. The processor also responds to the conduction state of one of the switch elements, detects a return signal on the corresponding return line, and selects at least one of these scanning lines as a test line. During a first period in which the test line maintains the scanning signal, the processor detects the start point of the first period to the start point of the return signal corresponding to the return signal within the first period to obtain a time difference. The processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory, where the duration of the first period is a first time.

[0009] The present invention provides an adaptive method for a keyboard, which is executed by a processor. The keyboard includes a scanning circuit, which includes a plurality of scanning lines, a plurality of feedback lines, and a plurality of switching elements respectively coupled to the intersections of the scanning lines and the feedback lines. The adaptive method for the keyboard includes: setting a parameter set, where the parameter set includes a plurality of response time parameters of the scanning lines. Selecting at least one of the scanning lines as a test line in a scanning round. Feeding a scanning signal to each scanning line in turn during the scanning round, and detecting a feedback signal on the corresponding feedback line in response to the conduction state of one of the switching elements. During a first period when the test line maintains the scanning signal, the processor detects the time difference between the start point of the first period and the start point of the feedback signal corresponding to the first period to obtain a time difference. The processor determines whether to update the response time parameter corresponding to the test line stored in the memory according to the time difference and the response time parameter corresponding to the test line stored in the memory. The length of the first period is a first time.

[0010] The present invention provides a computer-readable medium storing a program and a computer program product. When an electronic computing device with a processor loads and executes the program, it can complete the above-mentioned adaptive method for the keyboard.

[0011] Based on the above, the adaptive keyboard for line aging, the adaptive method for the keyboard, the computer-readable medium storing a program, and the computer program product provided by the present invention enable the processor to determine whether to update the response time parameter corresponding to the test line stored in the memory according to the time difference between the start point of the first period and the start point of the feedback signal corresponding to the first period and the response time parameter corresponding to the test line stored in the memory. Accordingly, not only can the processor feed a scanning signal to each scanning line at an appropriate time to increase the accuracy of detecting the pressing of the switching element, but also in the case of keyboard line aging, the response time parameter can be updated accordingly to maintain the accuracy of detecting the pressing of the switching element of the keyboard and adapt to line aging. Description of the Drawings

[0012] Figure 1 It is a circuit diagram of an existing matrix key switch.

[0013] Figure 2 It is a schematic diagram of the voltage state of the equivalent capacitor in response to the pressing state of the switching element.

[0014] Figure 3 It is a circuit diagram of an adaptive keyboard for line aging according to an embodiment of the present invention.

[0015] Figure 4 It is a timing diagram of the scanning signal according to an embodiment of the present invention.

[0016] Figure 5Schematic diagram of the correspondence between the scanning signal timing and the response time parameter of the scanning line according to an embodiment of the present invention.

[0017] Figure 6 Flowchart of the adaptive method for a keyboard according to an embodiment of the present invention.

[0018] Figure 7 Flowchart of the adaptive method for a keyboard according to an embodiment of the present invention.

[0019] Among them, the reference numerals of the drawings:

[0020] 100 Circuit of the matrix key switch

[0021] 101 Feedback line

[0022] 102 Scanning line

[0023] R eq Equivalent resistance

[0024] C eq Equivalent capacitance

[0025] 200 Schematic diagram of the voltage state

[0026] V ceq Cross voltage

[0027] During 201 and 202

[0028] 300 Keyboard circuit

[0029] 301 Processor

[0030] 302 Memory

[0031] 303 Scanning circuit

[0032] S1 to S4, SN Scanning lines

[0033] R1 to R4 Feedback lines

[0034] SW, SW11, SW12, SW13, SW14, SW21, SW22, SW23, SW24, SW31, SW32, SW33, SW34, SW41, SW42, SW43, SW44 Switch elements

[0035] Rc1 to Rc4 Reference resistors

[0036] Vcc Reference potential

[0037] 401, 402, 403, 404 Scanning intervals

[0038] 405, 406 Time points

[0039] td time difference

[0040] Memory locations 501, 502, 503, 504

[0041] Response time parameters PS1, PS2, PS3, PS4

[0042] Steps S501 to S507 Detailed implementation mode

[0043] The above and other technical contents, features and technical effects of the present invention will be clearly presented in the following detailed description of the embodiments with reference to the accompanying drawings of the specification. The thickness or size of each element in the accompanying drawings of the specification is represented in an exaggerated, omitted or schematic manner for the understanding and reading of those skilled in the art, and the size of each element is not completely its actual size, and is not used to limit the implementation conditions of the present invention. Therefore, it does not have technical substantial significance. Any modification of the structure, change of the proportional relationship or adjustment of the size, without affecting the technical effects that the present invention can produce and the purpose that can be achieved, should still fall within the scope covered by the technical content disclosed in the present invention. The same reference numerals will be used to represent the same or similar elements in all the accompanying drawings of the specification. The term "coupled" or "connected" mentioned in the following embodiments may refer to any direct or indirect connection means.

[0044] Figure 3 The keyboard circuit diagram of adaptive line aging according to an embodiment of the present invention. Please refer to Figure 3 , the keyboard circuit 300 of adaptive line aging includes a scanning circuit 303, a processor 301 and a memory 302.

[0045] The scanning circuit 303 includes N scanning lines, M return lines and a plurality of switching elements, where M and N are positive integers. For example, M can be 5 and N can be 4. For the convenience of description, the N scanning lines in this embodiment are described by four scanning lines S1 to S4, and the M return lines are described by four return lines R1 to R4.

[0046] In this embodiment, a switching element is coupled at the intersection of each scanning line and each return line. For example: a switching element SW11 is coupled at the intersection of the scanning line S1 and the return line R1, a switching element SW21 is coupled at the intersection of the scanning line S1 and the return line R2, a switching element SW12 is coupled at the intersection of the scanning line S2 and the return line R1, and so on.

[0047] The scanning circuit 303 of this embodiment is also provided with a plurality of reference resistors Rc1 to Rc4 respectively coupled to the return lines R1 to R4, so that the return lines R1 to R4 are respectively connected to the reference potential Vcc via the reference resistors Rc1 to Rc4.

[0048] The memory 302 stores a plurality of response time parameters respectively corresponding to the scan lines S1 to S4. The processor 301 is coupled to the scan circuit 303 and the memory 302. The following will describe in detail, in conjunction with the accompanying drawings of the specification, the adaptive method of the keyboard according to the embodiments of the present invention and how the various hardware components of the keyboard circuit 300 with adaptive line aging cooperate with each other.

[0049] Figure 4 It is a timing diagram of scan signals according to an embodiment of the present invention. Figure 6 It is a flowchart of the adaptive method of the keyboard according to an embodiment of the present invention. Please refer to Figure 3 、 Figure 4 and Figure 6 . Since four scan lines S1 to S4 are used for illustration here, in the following description, Figure 4 the scan line SN in

[0050] is the scan line S4. Figure 6 As shown in

[0051] To prevent the aging of the keyboard circuit from affecting the accuracy of detecting the depression of the switching elements SW11 to SW44. As shown in Figure 6 In step S502, the processor 301 selects at least one of the scan lines S1 to S4 as a test line in a scan round. In the same scan round, the remaining scan lines that are not selected as the test line are called non-test lines. Here, taking the scan line S1 as the test line as an example, the scan lines S2 to S4 are non-test lines.

[0052] In step S503, the processor 301 alternately feeds scan signals to each scan line in the scan round and, in response to the conduction state of one of the switching elements, detects a feedback signal on the corresponding feedback line. For example, as shown in Figure 4 the scan interval 401 of the scan line S1 as the test line maintains a first period, that is to say, within the first period maintained by the scan interval 401, the processor 301 inputs a scan signal with a low logic level to the scan line S1. The scan intervals 402 to 404 of each non-test line (in this example, the scan lines S2 to S4) maintain a second period different from the first period, that is to say, within the second period maintained by the scan intervals 402 to 404, the processor 301 inputs scan signals with a low logic level to the scan lines S2 to S4 respectively.

[0053] Among scan intervals 401, 402, 403, and 404, the processor 301 inputs scan signals at a low logic level to scan lines S1 to S4 respectively. At time point 405 within scan interval 401, when the switch element SW21 coupled at the intersection of scan line S1 and feedback line R2 is pressed, the processor 301 can receive and detect a feedback signal at a low logic level from the feedback line R2 corresponding to the switch element SW21.

[0054] Subsequently, in step S504, based on the time difference between the start point of the first period and the start point of the feedback signal and the reaction time parameter stored in the memory 302 corresponding to the test line (scan line S1), the processor 301 can determine whether to update the reaction time parameter stored in the memory 302 corresponding to the test line. For example, as Figure 4 shown, when within the first period (scan interval 401) of inputting a scan signal at a low logic level to scan line S1, the processor 301 receives and detects a feedback signal at time point 405, the processor 301 calculates the time difference td between the start point of the first period (i.e., time point 406) and the start point of the feedback signal corresponding to the first period (i.e., time point 405). The processor 301 then determines whether to update the reaction time parameter stored in the memory 302 corresponding to the test line (scan line S1) based on the time difference td and the reaction time parameter stored in the memory 302 corresponding to the test line (scan line S1).

[0055] When within the first period (scan interval 401) of inputting a scan signal at a low logic level to the test line (scan line S1), the processor 301 does not receive and detect a feedback signal, that is, within the first period (scan interval 401) of scan line S1, the switch elements SW11, SW21, SW31, and SW41 coupled to scan line S1 are not pressed and / or triggered, the processor 301 will, after the first period, select at least one of the non - test lines (scan lines S2 to SN) as the test line for the next scan round and perform the next scan round according to the above steps. In each scan cycle, the processor 301 alternately feeds scan signals to each of the scan lines S1 to S4 and alternately uses each of the scan lines S1 to S4 as the test line to perform a scan round. The scan rounds usually continuously loop so that the processor 301 can detect when a switch element is pressed. When each of the scan lines S1 to S4 has been selected as the test line and the current scan round is completed, a scan cycle ends.

[0056] Figure 5 Schematic diagram corresponding to the scan signal timing and the reaction time parameter of the scan line for another embodiment of the present invention. Please refer to Figures 3 to 6。In this embodiment, the memory location 501 in the memory 302 stores the response time parameter PS1 corresponding to the scan line S1, the memory location 502 stores the response time parameter PS2 corresponding to the scan line S2, the memory location 503 stores the response time parameter PS3 corresponding to the scan line S3, and the memory location 504 stores the response time parameter PS4 corresponding to the scan line S4. Taking the case where the processor 301 selects the scan line S1 as the test line as an example, the processor 301 inputs a scan signal with a low logic level to the scan line S1 and maintains it for a first time, that is, the time length of the above-mentioned first period is the above-mentioned first time. At the same time, the scan lines S2 to S4 are non-test lines, and the processor 301 inputs a scan signal with a low logic level to the scan lines S2 to S4 and maintains it for a second time respectively, that is, the time length of the above-mentioned second period is the above-mentioned second time.

[0057] The processor 301 determines the above-mentioned first time and second time according to the response time parameters (PS1 to PS4 in this example) corresponding to the scan lines S1 to S4 stored in the memory 302. For example, when the test line is the scan line S1, the first time can be several times (such as three times, ten times or twenty times) the response time parameter PS1 of the scan line S1. It should be noted that the relationship between the first time and the response time parameter PS1 in the present invention is not limited to the above multiples. In other embodiments, the first time can be a specific function of the response time parameter PS1 of the scan line S1. As long as the first time is greater than or equal to the allowable range of the response time parameter corresponding to the test line stored in the memory 302, so that within the first period, when the switching element coupled to the test line is pressed, the processor 301 can detect the feedback signal.

[0058] For non-test lines (scan lines S2 to S4), the processor 301 uses the response time parameters PS2 to PS4 corresponding to the non-test lines (scan lines S2 to S4) in the memory 302 as the second time for maintaining the scan signal on each of the scan lines S2 to S4.

[0059] Furthermore, among the non-test lines S2 to S4 of the scan lines, the second time of the scan line S2 can be the response time parameter PS2, the second time of the scan line S3 can be the response time parameter PS3, and the second time of the scan line S4 can be the response time parameter PS4.

[0060] In this embodiment, the processor 301 uses several times the response time parameter corresponding to the scan line (test line) stored in the memory 302 as the first time, and directly uses the response time parameter corresponding to other scan lines (non-test lines) stored in the memory 302 as the second time. For example, the response time parameters PS1 to PS4 corresponding to the scan lines S1 to S4 are all 30 microseconds (μs), the scan line S1 is the test line, and the scan lines S2 to S4 are non-test lines. The above-mentioned first time corresponding to the test line (scan line S1) can be 600 μs (twenty times of PS1), and the second times corresponding to the non-test lines (scan lines S2 to S4) can all be 30 μs. Another example is that the response time parameter PS1 is 30 μs, PS2 is 40 μs, PS3 is 35 μs, and PS4 is 50 μs. The above-mentioned first time can be 600 μs (twenty times of PS1), the second time of the scan line S2 is 40 μs, the second time of the scan line S3 is 35 μs, and the second time of the scan line S4 is 50 μs.

[0061] In some embodiments, the processor 301 uses the response time parameter stored in the memory 302 as a basis and adds an allowable value as the second time. For example, PS1 is 30 μs, PS2 is 40 μs, PS3 is 35 μs, and PS4 is 50 μs. The above-mentioned first time is 600 μs (twenty times of PS1). The second time of the scan line S2 is 60 μs, the second time of the scan line S3 is 53 μs, and the second time of the scan line S4 is 75 μs.

[0062] It should be noted that although in the above embodiments, the processor 301 inputs a low logic level signal to the scan lines S1 to S4 and reads the feedback signal indicating that the feedback line R2 is a low logic level signal. Those skilled in the art to which the present invention pertains can also make slight modifications Figure 3 to the disclosed circuit, and make the processor 301 input a high logic level signal to the scan lines S1 to S4 and read the feedback signal indicating that the feedback line R2 is a high logic level signal with the same logic level as the input signal.

[0063] In the embodiment of the present invention, in order to enable all the scan lines S1 to S4 to execute the above-mentioned anti-aging update program, the processor 301 executes multiple scan rounds in one scan cycle, and the scan lines selected as test lines in each scan round in the scan cycle are different from each other. For example, in the first scan round, the scan line S1 is selected as the test line, and in the second scan round, the scan line S2 is selected as the test line, and so on. It is worth mentioning that the present invention may not need to select the test lines in the order of the scan lines S1 to S4. It can be selected in any order such as S2, S4, S1, S3, etc., as long as all the scan lines can be selected as test lines for scanning.

[0064] Since the aging of the keyboard circuit has always existed and will only become more serious over time. Take Figure 3 the keyboard circuit 300 shown in the figure. The scanning circuit 303 includes 4 scanning lines S1 to S4. If, from the beginning, in order to prevent the aging of the keyboard circuit, the processor 301 scans each scanning line (test line and non-test line) with a relatively long fixed time (for example, 600 μs), then one scanning cycle takes 2400 microseconds (4 × 600 μs = 2400 μs). In the embodiment of the present invention, the processor 301 uses several times the response time parameter corresponding to the test line stored in the memory 302 as the scanning time (the first time) for the test line, and directly uses the response time parameter corresponding to the non-test line stored in the memory 302 as the scanning time (the second time). Taking the example content of the above embodiment, the response time parameter PS1 corresponding to the test line (scanning line S1) is 30 μs, and the response time parameters PS2, PS3, and PS4 corresponding to the non-test lines (scanning lines S2 to S4) are 40 μs, 35 μs, and 50 μs respectively. The first time for the test line can be twenty times the response time parameter PS1 (600 μs), and the second time for each non-test line can be the corresponding response time parameters PS2, PS3, and PS4 of them (that is, 40 μs, 35 μs, and 50 μs respectively). In this embodiment, only 725 microseconds (600 μs + 40 μs + 35 μs + 50 μs = 725 μs) are required to complete one scanning cycle. Therefore, the present invention can improve and reduce the time required to complete one scanning cycle, and improve the key response time.

[0065] Furthermore, when the keyboard circuit ages to a certain extent, even if the scanning lines are scanned with a relatively long fixed time, it will still cause Figure 1 and Figure 2 the problem of incorrect detection of the pressing of the switch element SW described. In the embodiment of the present invention, since the response time parameter of the scanning line changes dynamically with the aging of the keyboard circuit, and the first time is selected as several times (such as three times) the response time parameter of the scanning line, the problem of continuous aging of the keyboard circuit can be overcome.

[0066] In an embodiment of the present invention, when the processor 301 compares the time difference td with the response time parameter corresponding to the test line stored in the memory 302, if the time difference td is greater than the response time parameter corresponding to the test line, it is necessary to update the response time parameter corresponding to the test line stored in the memory 302. This indicates that aging has occurred in the test line. Therefore, it can be reasonably inferred that there is a certain probability that other scan lines also have aging phenomena. Therefore, the processor 301 can select at least two of the scan lines as test lines in subsequent other scan rounds until all the scan lines that have not been selected as the test line in this scan cycle are selected, so as to accelerate the detection of aging of the test line.

[0067] For example, as Figure 4 shown, in a certain scan round, the processor 301 selects the scan line S1 as the test line. During the first period, when the processor 301 reads the feedback signal at the time point 405, the processor 301 calculates the time difference td between the start point (time point 406) of the first period (in this example, the scan interval 401) and the start point (time point 405) of the feedback signal corresponding to the first period. Then, the processor 301 determines whether to update the response time parameter PS1 corresponding to the test line S1 stored in the memory 302 according to the time difference td and the response time parameter PS1 corresponding to the test line S1 stored in the memory 302. If the processor 301 determines that it is necessary to update the response time parameter PS1 of the test line S1, it means that aging has occurred in the scan line S1. At the beginning of the next scan round, the processor 301 selects two scan lines different from the scan line S1 (for example, the scan line S2 and the scan line S3) as the test lines. The processor 301 inputs scan signals with a low logic level to the scan lines S2 and S3 for a time longer than the response time parameter PS2 and longer than the response time parameter PS3 respectively to determine whether the response time parameters PS2 and PS3 of the test lines S2 and S3 need to be updated, so as to know whether aging has occurred in the test lines S2 and S3. As for how to determine whether it is necessary to update the response time parameters PS2 and PS3 of the test lines S2 and S3, the method has been described in detail above and will not be repeated here.

[0068] Figure 7 It is a flowchart of the adaptive method of the keyboard according to an embodiment of the present invention. Please refer to Figures 3 to 7 at the same time. In this embodiment, the step S504 of Figure 6 is implemented through steps S505 to S507, where Figure 7 steps S501 to S503 of Figure 6Steps S501 to S503 will not be elaborated further. After step S503, that is, in the scanning round, the scanning signal is fed to each scanning line in turn, and in response to the conduction state of one of the switching elements, after the return signal is detected on the corresponding return line, step S505 is executed. In step S505, the processor 301 compares the time difference td between the start point of the first period (time point 406) and the start point of the return signal corresponding to the first period (time point 405) with the response time parameter corresponding to the test line stored in the memory. That is, the processor 301 calculates the time difference td between the start point of the first period (time point 406) and the start point of the return signal corresponding to the first period (time point 405), and then compares the time difference td with the response time parameter corresponding to the test line. When the time difference td is greater than the response time parameter corresponding to the test line, the processor 301 executes step S506. In step S506, the processor 301 sets the time difference td as the response time parameter corresponding to the test line, that is, updates the response time parameter corresponding to the test line stored in the memory 302, and sets the response time parameter corresponding to the test line as the above time difference td. When the time difference td is less than or equal to the response time parameter of the test line, the processor 301 executes step S507, and the processor 301 does not update the response time parameter corresponding to the test line stored in the memory 302.

[0069] In an embodiment of the present invention, the processor 301 can compare the relationship between the time difference td and the response time parameter corresponding to the test line stored in the memory, and then determine whether the condition of line aging occurs, and decide whether to update the response time parameter corresponding to the test line stored in the memory 302.

[0070] For example, taking the processor 301 selecting the scanning line S1 as the test line as an example. After the processor 301 calculates the time difference td according to the above steps, the processor 301 compares the time difference td with the response time parameter PS1 corresponding to the scanning line S1 stored in the memory 302 (step S505). When the processor 301 determines that the value of the time difference td is greater than the response time parameter PS1 of the test line S1, the scanning line S1 can be regarded as having the phenomenon of line aging, and the processor 301 writes the value of the time difference td into the memory location 501 of the memory 302 to update the response time parameter PS1 corresponding to the scanning line S1.

[0071] When the time difference td is greater than the stored response time parameter, the processor 301 sets the time difference td as the response time parameter corresponding to the test line. It should be noted that in other embodiments, specific mathematical operations can also be performed on the time difference td and the stored response time parameter according to requirements and then compared to determine whether to update the response time parameter corresponding to the test line stored in the memory 302.

[0072] In other embodiments of the present invention, after the processor 301 executes step S505, when the time difference td is greater than the response time parameter corresponding to the test line, the processor 301 updates the response time parameter corresponding to the test line by a multiple (such as three times) of the value of the time difference td, or updates the response time parameter corresponding to the test line by a function (such as a linear function) of the value of the time difference td.

[0073] In an embodiment of the present invention, the processor 301 may upload the response time parameters of each scan line stored in the memory 302 to a personal computer (PC) or any computer device, so that the PC or any computer device diagnoses the aging degree of the keyboard circuit according to the magnitudes of the response time parameters corresponding to the current respective scan lines. In some embodiments, the processor 301 further diagnoses the aging speed of each scan line by calculating the update frequency of the response time parameter corresponding to each scan line within a specific time and calculating the rate of change of the response time parameter with respect to time, so that the PC or any computer device can make the diagnosis.

[0074] In an embodiment of the present invention, after the keyboard has not been pressed and used for a period of time, the processor 301 may first stop the above program of selecting a test line to detect the aging of the test line. Then the processor 301 pre-detects the conduction states of these switching elements and starts a scan round in response to the conduction of any one of the switching elements. It should be noted that the present invention is not limited thereto. In other embodiments, the keyboard may determine the time points for stopping and restarting the above program of selecting a test line to detect the aging of the test line in an interrupt or polling manner.

[0075] In this specification, the term "electronic computing device-readable medium" generally refers to a non-volatile and non-transitory medium, such as a read-only memory (ROM), a flash memory, a floppy disk, a hard disk, a compact disk (CD), a digital versatile disc (DVD), a USB flash drive, a database accessible via a network, or any other storage medium known to those skilled in the technical field to which the present invention pertains and having the same function. Such and various other forms of electronic computing device-readable media may involve carrying one or more sequences of one or more instructions to the processor 301 for execution. Such instructions embodied on the medium are generally referred to as "electronic computing device program code" or "electronic computing device program product", and the "electronic computing device program code" or "electronic computing device program product" may be a file capable of being transmitted over a network and may also be stored in a non-transitory electronic computing device-readable storage medium. When executed, such instructions may enable the processor 301 to perform the steps or functions described in the present invention.

[0076] In summary, the keyboard with adaptive line aging, the adaptive method of the keyboard, the computer-readable medium storing a program, and the computer device program product provided by the present invention enable the processor to detect the start point of the first period of the test line (such as Figure 4 time point 406) to the start point of the feedback signal corresponding to the first period (such as Figure 4 time point 405) to obtain a time difference. The processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory, which can not only enable the processor to feed the scan signal to each scan line at an appropriate time, increasing the accuracy of detecting the pressing of the switching element, but also update the response time parameter correspondingly in the case of keyboard line aging to maintain the accuracy of detecting the pressing of the switching element of the keyboard and improve the key response time. Further, the processor uploads the response time parameters corresponding to each scan line stored in the memory, the update frequency of the response time parameter corresponding to each scan line at a specific time, and the rate of change of the response time parameter with respect to time to a personal computer or any computer device, and can also diagnose the degree and speed of aging of each scan line.

Claims

1. An adaptive keyboard for line aging, characterized in that The keyboard adapted to line aging includes: A scanning circuit, including a plurality of scanning lines, a plurality of feedback lines, and a plurality of switching elements, wherein the plurality of switching elements are respectively coupled to intersections of the plurality of scanning lines and the plurality of feedback lines; A memory for storing a plurality of response time parameters respectively corresponding to the plurality of scanning lines; And A processor, coupled to the scanning circuit and the memory, the processor alternately feeds scanning signals to each of the plurality of scanning lines in a scanning round, selects at least one of the plurality of scanning lines as a test line, and in response to a conduction state of one of the plurality of switching elements coupled to the test line, detects a feedback signal on the corresponding feedback line; during a first period when the test line maintains the scanning signal, the processor detects a time difference from a start point of the first period to a start point of the feedback signal corresponding to the first period, and the processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory.

2. The keyboard for adaptively aging the circuit according to claim 1, wherein When the time difference is greater than the response time parameter corresponding to the test line stored in the memory, the processor updates the response time parameter corresponding to the test line stored in the memory with the time difference.

3. The keyboard for adapting to line aging according to claim 2, wherein The processor selects at least two of the plurality of scanning lines as the test line to perform subsequent other scanning rounds until all the plurality of scanning lines that have not been selected as the test line in the scanning cycle are selected.

4. The keyboard for adapting to line aging according to claim 1, characterized in that, When the time difference is less than or equal to the response time parameter corresponding to the test line stored in the memory, the processor does not update the response time parameter corresponding to the test line stored in the memory.

5. The keyboard for adaptively aging the circuit according to claim 1, wherein The plurality of scanning lines include the test line and a plurality of non-test lines, the processor maintains a second period for the scanning signals of each of the plurality of non-test lines, and the second period of each of the plurality of non-test lines respectively corresponds to the response time parameter corresponding to each of the plurality of non-test lines stored in the memory.

6. The keyboard for adaptively aging the circuit according to claim 1, characterized in that, The feedback signal indicates that the corresponding feedback line has the same logic level as the scanning signal.

7. The keyboard for adaptively aging the circuit according to claim 1, wherein The processor performs a plurality of the scanning rounds in a scanning cycle, and the scanning lines selected as the test line in each of the scanning rounds in the scanning cycle are different from each other.

8. The keyboard for adaptively aging the circuit according to claim 7, characterized in that, The processor selects the test line for each of the scanning rounds in the scanning cycle according to the arrangement order of the plurality of scanning lines.

9. The keyboard for adaptively aging the circuit according to claim 1, wherein, The processor pre-detects the conduction state of the plurality of switching elements and starts the scanning round in response to the conduction of any one of the plurality of switching elements.

10. The keyboard for adaptively aging the circuit according to claim 1, wherein The first period maintains a first time, and the processor sets the first time based on the response time parameter corresponding to the test line stored in the memory.

11. An adaptive method for a keyboard, executed by a processor, the keyboard including a scanning circuit, the scanning circuit including a plurality of scanning lines, a plurality of return lines, and a plurality of switching elements respectively coupled to intersections of the plurality of scanning lines and the plurality of return lines, characterized in that, The adaptive method of the keyboard includes: Setting a parameter set, the parameter set including a plurality of response time parameters of the plurality of scanning lines; Selecting at least one of the plurality of scanning lines as a test line in a scanning round; The processor alternately feeds a scan signal to each of the scan lines during the scan round, and detects a feedback signal on a corresponding feedback line in response to the conduction state of one of the plurality of switching elements coupled to the test line. During a first period in which the scan signal is maintained on the test line, the processor detects the start point of the first period and the start point of the feedback signal corresponding to the first period to obtain a time difference. The processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory.

12. The adaptive method of the keyboard according to claim 11, characterized in that, The processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory further includes: when the time difference is greater than the response time parameter corresponding to the test line stored in the memory, the processor updates the response time parameter corresponding to the test line stored in the memory with the time difference.

13. The adaptive method of the keyboard according to claim 12, wherein It further includes: selecting at least two of the plurality of scan lines as the test lines to perform subsequent other scan rounds until all of the plurality of scan lines that have not been selected as the test lines in the current scan cycle are selected.

14. The adaptive method of the keyboard according to claim 11, characterized in that, The processor determines whether to update the response time parameter corresponding to the test line stored in the memory based on the time difference and the response time parameter corresponding to the test line stored in the memory further includes: when the time difference is less than or equal to the response time parameter corresponding to the test line stored in the memory, the processor does not update the response time parameter corresponding to the test line stored in the memory.

15. The adaptive method of the keyboard according to claim 11, wherein The plurality of scan lines include the test line and a plurality of non-test lines. The processor maintains a second period for the scan signal of each of the plurality of non-test lines. The second period of each of the scan lines corresponds to the response time parameter corresponding to each of the plurality of non-test lines stored in the memory.

16. The adaptive method of the keyboard according to claim 11, characterized in that, The feedback signal indicates that the corresponding feedback line has the same logic level as the scan signal.

17. The adaptive method of the keyboard according to claim 11, wherein The scan round is executed multiple times in a scan cycle, and the scan lines selected in each scan round in the scan cycle are different from each other.

18. The adaptive method of the keyboard according to claim 17, wherein, The plurality of test lines are selected according to the arrangement order of the plurality of scan lines.

19. The adaptive method of the keyboard according to claim 11, wherein It further includes: pre-detecting the conduction states of the plurality of switching elements; and starting the scan round in response to the conduction of any one of the plurality of switching elements.

20. The adaptive method of a keyboard according to claim 11, characterized in that, The first period is maintained for a first time, and the processor sets the first time based on the response time parameter corresponding to the test line stored in the memory.

21. An internally stored program electronic computing device-readable medium, characterized in that, When an electronic device having a processor loads and executes the program, the method according to any one of claims 11 to 20 can be completed.

22. An electronic computing device program product having an electronic computing device program, characterized in that, After the electronic computing device loads and executes the program of the electronic computing device, the method described in any one of claims 11 to 20 can be completed.

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