A memory bank failure detection device and detection method

Abstract

The application discloses a memory bank fault detection device and method, relates to the field of memory fault detection of a computing device, and can timely determine the faulty memory bank when the memory is faulty, and improves the accuracy and timeliness of memory fault detection. The fault detection device comprises a memory management controller and a latch. An input end of the memory management controller is connected with the memory bank, and an output end of the memory management controller is connected with one input end of the latch. The memory management controller is used for detecting correctable errors (CE) of the memory bank and determining the number of the correctable errors (CE) of the memory bank. When the number of the correctable errors (CE) of the memory bank exceeds a preset threshold value, the memory management controller sends a latching signal to the latch.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of memory fault detection of a computing device, and particularly relates to a memory fault detection method and device for a memory of a computing device. BACKGROUND

[0002] Random Access Memory, also known as RAM, is an internal memory directly exchanging data with a processor (CPU), and is usually used as a temporary data storage medium for an operating system or other programs running. The memory can write or read information from any specified address at any time, and the memory is the most used and most valuable device in a computing device. However, with the evolution of memory architecture, in order to put more storage units in the same area of the silicon chip and perform faster read and write, the memory process is getting smaller and smaller, and the working frequency is getting higher and higher. In order to control the heat, the working voltage is forced to be continuously lowered, which continuously reduces the reliability of the memory medium itself and the failure rate. Currently, memory failure has become one of the most common failure sources in the computing device field. When the memory fails, it may cause the computing device to restart or crash abnormally, so it is particularly important to detect the health status of the memory. Monitoring the health status of the memory can identify risky memory in advance and handle it, thereby reducing the risk of computing device system downtime.

[0003] The memory is a passive device and cannot determine its own health status. Currently, the identification of the health status of the memory depends on the out-of-band management system (BMC) log record. However, this identification method is not intuitive. On the one hand, the operation and maintenance personnel cannot timely find the memory failure, and on the other hand, there is a possibility of mistakenly replacing the memory in the operation and maintenance process.

[0004] The failure of the memory can be divided into correctable error (CE) and uncorrectable error (UCE). The CE failure of the memory can be corrected by the central processor and will not affect the normal operation of the system. When the number of CE of the memory reaches a certain value, there is a risk of UCE. The UCE of the memory is a fault that cannot be corrected by the processor and will cause the server to restart or crash abnormally. Therefore, how to timely and accurately detect the correctable error (CE) of the memory has become a problem to be solved. SUMMARY

[0005] The embodiments of the present application provide a memory fault detection device and method, which improve the timeliness and accuracy of memory fault detection, are beneficial to timely determine the faulty memory and replace it, and reduce the risk of computing device downtime.

[0006] To achieve the above object, the application adopts the following technical scheme:

[0007] In a first aspect, a memory bank fault detection device is provided, which comprises a memory management controller and a latch, an input end of the memory management controller being connected to the memory bank, and an output end of the memory management controller being connected to an input end of the latch; the memory management controller is configured to detect correctable errors (CE) of the memory bank and determine a number of the correctable errors (CE) of the memory bank, and send a latch signal to the latch when the number of the correctable errors (CE) of the memory bank exceeds a preset threshold.

[0008] In the technical scheme, the memory bank is detected by the memory fault detection device, the memory management controller and the latch are arranged in the memory fault detection device, so that the fault information of the memory bank can be acquired by the memory management controller, and the number of the correctable errors (CE) of the memory bank can be determined from the fault information; when the number of the correctable errors (CE) of the memory bank exceeds the preset threshold, the memory management controller sends a latch signal to the latch, and the latch signal is used to indicate that the number of the correctable errors (CE) of the memory bank has reached a critical value, and the memory bank needs to be repaired or replaced in time; the latch signal sent by the memory management controller to the latch makes the CE errors of the memory bank be found in time, and the timeliness of the memory bank fault detection is enhanced, and the risk of the computing device being down is reduced.

[0009] In a possible implementation, the memory management controller further comprises a counter and a processor, wherein the counter is configured to count the number of the correctable errors (CE), and the processor is configured to compare the number of the correctable errors (CE) counted by the counter with a preset threshold, and send the latch signal to the latch when the number of the correctable errors (CE) is greater than the preset threshold.

[0010] In the possible implementation, the memory management controller further comprises the counter and the processor, the number of the correctable errors (CE) of the memory bank is counted by the counter, and the number is compared with the preset threshold by the processor, so that the counting of the number of the correctable errors (CE) of the memory bank is more accurate.

[0011] In a possible implementation, the memory management controller comprises a BIOS chip and a baseboard management controller (BMC), the BIOS chip is configured to acquire the fault information of the memory bank, and determine the number of correctable errors (CEs) according to the fault information of the memory bank, wherein the fault information of the memory bank comprises the number of CEs; the BIOS chip is further configured to send the number of CEs to the baseboard management controller (BMC); the baseboard management controller (BMC) is configured to receive the number of CEs sent by the BIOS chip, compare the number of CEs with a preset threshold, and send a latch signal to the latch in a case where the number of CEs is greater than the preset threshold.

[0012] In the possible implementation, another configuration of the memory management controller is further provided, that is, the BIOS chip and the baseboard management controller (BMC) of the computing device are used to implement the function of the memory management controller, thereby further reducing the cost of the memory bank fault detection apparatus.

[0013] In a possible implementation, the fault detection apparatus further comprises a memory, which is arranged in the memory bank or the memory management controller, and is configured to store the fault information of the memory bank.

[0014] In the possible implementation, the memory for storing the fault information of the memory bank is further arranged in the memory bank or the memory management controller, so that the fault information of the memory bank is not easily lost, and the maintenance of the memory bank is facilitated.

[0015] In a possible implementation, the memory bank comprises a plurality of memory banks, and the latch comprises a plurality of latches and corresponds to the plurality of memory banks in a one-to-one manner; in a case where the number of CEs exceeds the preset threshold, the memory management controller determines a target fault memory bank that exceeds the threshold, and sends a latch signal to the latch corresponding to the target fault memory bank; the target fault memory bank is one or more of the plurality of memory banks.

[0016] In the possible implementation, when the memory bank comprises a plurality of memory banks, a plurality of latches are arranged, and each latch is connected to each memory bank, so that the fault detection of the plurality of memory banks by the memory management controller is implemented, and the memory management controller can send a latch signal to the latch corresponding to the memory bank in a case where any memory bank fails, thereby achieving the detection of the fault of the plurality of memory banks.

[0017] In a possible implementation, the fault detection apparatus further comprises a state indicator, which is connected to the output end of the latch; the state indicator is configured to receive a high level output by the latch and send an alarm signal in a case where the latch receives the latch signal sent by the memory management controller.

[0018] In the possible implementation, the state indicator is arranged in the fault detection device, so that the fault of the memory stick is more intuitive.

[0019] In a possible implementation, the state indicator is an indicator light and / or a buzzer.

[0020] In the possible implementation, the state indicator is arranged as an indicator light or a buzzer, so that the fault information of the memory stick is characterized by a light signal or a sound signal, and the intuitiveness and effectiveness of the fault display of the memory stick are further improved.

[0021] In a possible implementation, the memory stick further comprises a PCB circuit board, and the state indicator is arranged on the PCB circuit board or on a slot of the computing device, the slot being used for mounting the memory stick.

[0022] In the possible implementation, the state indicator is arranged on the circuit board of the memory stick or the slot for mounting the memory stick, which is conducive to the installation and maintenance of the state indicator.

[0023] In a possible implementation, the computing device is a server.

[0024] In the possible implementation, the fault detection device can be applied to the server, so that the timeliness and accuracy of the memory fault detection of the server are improved, and the risk of downtime of the server is reduced.

[0025] In a second aspect, an embodiment of the present application provides a memory stick fault detection method, which is used in a memory stick fault detection device, the memory stick fault detection device comprising a memory management controller, a latch and a state indicator, an input end of the memory management controller being connected to the memory stick, an output end of the memory management controller being connected to an input end of a latch, and an output end of the latch being connected to a state indicator, and the method comprises the following steps:

[0026] S11: The memory fault detection device acquires fault information of the memory stick, and determines a number of correctable errors (CE) of the memory stick according to the fault information of the memory stick.

[0027] S12: In a case where the number of correctable errors (CE) of the memory stick is greater than a preset threshold value, the memory fault detection device determines a fault memory stick exceeding the threshold value, and sends a latch signal to a latch corresponding to the fault memory stick; the latch signal is used to make the state indicator send an alarm signal.

[0028] This technical solution, through its memory module fault detection method, enables the acquisition of memory module fault information and determines the number of correctable errors (CEs) from this information. When the number of correctable errors (CEs) exceeds a preset threshold, a latch signal is sent to the latch. This latch signal indicates that the number of correctable errors (CEs) of the memory module has reached a critical value, requiring timely repair or replacement of the memory module. This latch signal ensures that memory module CE errors can be detected promptly, enhancing the timeliness of memory module fault detection and reducing the risk of computing device downtime.

[0029] Thirdly, embodiments of this application provide a computer-readable storage medium storing at least one computer program, which is loaded and executed by a processor to implement the memory module fault detection method as described in the second aspect above.

[0030] Fourthly, embodiments of this application provide a computer program product or computer program that includes computer instructions stored in a computer-readable storage medium. A terminal's processor reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the terminal to perform the memory fault prediction method provided in the various optional implementations of the second aspect described above. Attached Figure Description

[0031] To more clearly illustrate the solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below.

[0032] Figure 1 This is a schematic diagram of memory fault detection in related technologies;

[0033] Figure 2 A schematic diagram of a memory module fault detection device provided in an embodiment of this application;

[0034] Figure 3 A schematic diagram of another memory module fault detection device provided in an embodiment of this application;

[0035] Figure 4 This application provides a connection diagram for detecting faults in multiple memory modules.

[0036] Figure 5 A schematic diagram of a detection circuit provided in an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of the installation of a status indicator provided in an embodiment of this application;

[0038] Figure 7A memory bank fault detection method flow chart is provided for the embodiments of the present application. DETAILED DESCRIPTION

[0039] The terms used in the embodiments of the present application are only used to explain the specific embodiments of the present application, and are not intended to limit the present application. The embodiments of the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0040] First, the special terms involved in the present application are introduced.

[0041] CPU: Central Processing Unit (CPU), is the operation and control core of the computing device, is the final execution unit of information processing and program running.

[0042] Register: The register is a storage device in the CPU used to temporarily store instructions, data and addresses. The register is a high-speed storage component with limited storage capacity, which can be used to temporarily store instructions, data and addresses.

[0043] BIOS: Basic Input Output System (BIOS), is a firmware that performs hardware initialization during power-on startup and provides runtime services for the operating system. BIOS is usually stored on a flash memory chip to facilitate BIOS updates.

[0044] BMC: Baseboard Management Controller (BMC), can perform firmware upgrade on the device, manage the running state of the device, and troubleshoot the device, etc. The baseboard management controller can maintain the program code in the memory in the computing device, including upgrading or restoring, etc. The baseboard management controller can also control the power supply circuit or clock circuit in the computing device, etc.

[0045] Row failure: a failure of a corrected error (CE) or an uncorrected error (UCE) that occurs in a row in the memory. The physical granularity of the memory, from large to small, is: Dimm, Rank, Device, Bank, Row / Column, Cell, Bit; and the relationship between the plurality of physical granularities is: each computer device can include a plurality of memory bars (Dimm), each memory bar has two memory columns (Rank), which are located on two sides of the memory, for example, two memory columns are memory column 0 (Rank0) and memory column 1 (Rank1). Wherein, a plurality of memory chips (Chip) can be configured on each memory column for storing data, the memory chip can also be referred to as a memory particle (Device), the memory chip can be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc., each memory chip can be divided into a plurality of storage arrays (Bank), and when the memory chip stores data, the data is written into a storage array in units of bits. In addition, a plurality of storage arrays can also be grouped into a storage array group (Bank Group), wherein the number of storage arrays in each storage array group can be the same, or can also be different. The storage array is composed of a large number of storage units (Cell), and the large number of storage units are arranged in a two-dimensional matrix form. As long as the row and column on the storage array are specified, a storage unit on the storage array can be located. The smallest unit of memory failure is the storage unit on the storage array. That is, the memory failure includes at least one of Dimm failure, Rank failure, Device failure, Bank failure, Row failure / Column failure, Cell failure and Bit failure.

[0046] Latch: a storage unit circuit sensitive to pulse level, which can change state under the action of a specific input pulse level, temporarily store signals to maintain a certain level state.

[0047] The computing device in the embodiment of the present application takes a server as an example. The existing fault detection method for the memory bar of the server can be specifically referred to Figure 1As shown, the processor 1 detects the CE of the memory bank, specifically, the processor 1 will record the corresponding fault information (including fault address, fault Dimm, fault Rank, Device, BankGroup, Bank, row / column, Cell fault, bit fault, etc.) into the register 2 of the processor, the register 2 counts the number of memory CE, when it exceeds the threshold, the processor 1 triggers an interrupt, the BIOS chip 3 will respond to this interrupt and collect all the memory-related fault information recorded in the register 2 in the interrupt service program and report it to the server out-of-band management system BMC, and the out-of-band management system BMC displays the memory error alarm of the fault memory bank corresponding slot based on the above fault information on its interface.

[0048] However, the above method requires the operation and maintenance personnel to pay attention to the interface of the BMC in real time, and cannot directly show the error state of the memory bank. On the one hand, if the operation and maintenance personnel do not observe the prompt of the BMC interface to the fault memory bank in time, the fault memory bank cannot be replaced or processed in time, and the server system will have the risk of downtime. On the one hand, since the operation and maintenance personnel cannot directly observe the error state of the memory bank, there is a risk of replacing the memory bank.

[0049] Therefore, the embodiment of the present application provides a memory bank fault detection device, by setting a detection device, when the processor detects a memory fault, the state indicating element in the detection device sends an alarm signal, so that the fault state of the memory bank can be directly observed. Figure 2 The architecture diagram of the memory bank fault detection device provided by the embodiment is shown.

[0050] Referring to Figure 2 As shown, the memory bank fault detection device 10 provided by the embodiment of the present application includes a memory management controller 13, a latch 11, and a state indicating element 12, wherein the input end of the memory management controller 13 is connected with the memory bank, the output end is connected with the input end of the latch 11, and the output end of the latch 11 is connected with the state indicating element 12.

[0051] Among them, the memory management controller 13 is used for reading the CE information of the memory bank and performing related actions.

[0052] The memory management controller 13 is configured to detect the correctable error (CE) of the memory stick. Specifically, the central processing unit inside the server has a certain error correction capability for memory data. Therefore, in general, when the number of CEs in the memory stick is within a certain range, the data stored in the memory stick is considered acceptable by the server, and the server does not have a risk of downtime. However, when the number of CEs in the memory stick exceeds a preset threshold, it is considered that there is a possibility of UCE in these memory CEs. Once the memory has UCE, the server will abnormally restart or be down. Therefore, the operation and maintenance personnel need to find out the memory stick with the risk of memory UCE and replace it in time. For example, when the storage capacity of the memory stick is 10 billion bits, the preset threshold can be set to 6000. The preset threshold is a preset value, which can be set in the memory management controller 13 according to the capacity of the specific memory stick.

[0053] The memory management controller 13 is configured to record the corresponding fault information (including fault address, fault type (including CE and UCE), fault Dimm, fault Rank, Device, BankGroup, Bank, row / column, Cell fault, bit fault, etc.) in the memory (not shown in the figure) in the memory management controller 13 when the CE fault in the memory is triggered by being accessed.

[0054] The memory can be arranged in the memory management controller 13, and the memory is configured to store and record the fault information of the memory. Optionally, the memory can be any one of a register, a DRAM (dynamic random access memory), and a SRAM (static random access memory).

[0055] Optionally, the memory can also be arranged in the memory stick 20, and the memory management controller 13 is further configured to directly access the memory in the memory stick to obtain the corresponding memory fault information.

[0056] The memory management controller 13 is further configured to count the number of CEs of the memory stick in the memory and compare the number of CEs of the memory stick with the preset threshold. When the number of CEs of the memory stick counted by the memory management controller 13 is greater than the preset threshold, the memory management controller 13 sends a latch signal to the latch 11, so that the latch 11 continuously outputs a high level.

[0057] Specifically, the memory management controller 13 is provided with a counter and a processor (not shown in the figure). The counter is configured to count the number of CEs of the memory stick in the memory in response to the command of the processor.

[0058] The processor is configured to send a command to the counter to count the number of CEs of the memory bank, and to compare the number of CEs counted by the counter with a preset threshold value, and when the number of CEs counted by the counter is greater than the preset threshold value, clear the data counted by the counter, and send a latch signal to the latch 11.

[0059] It should be noted that the preset threshold value can be set according to the working environment and memory capacity of the specific memory bank.

[0060] In an embodiment, the memory management controller 13 can include a BIOS chip 14 and a BMC 4, as shown in Figure 3 The input end of the BIOS chip 14 is connected to the memory bank 20, the BIOS chip 14 is connected to the BMC 4, the output end of the BMC 4 is connected to the input end of the latch 11, and the output end of the latch 11 is connected to the status indicator 12. It should be noted that the BIOS chip 14 and the BMC 4 can use the BIOS chip and the BMC that the computing device itself has, which can save costs.

[0061] The BIOS chip 14 is configured to store a BIOS program, and the BIOS program runs on the BIOS chip 14; the BIOS chip 14 is also configured to obtain fault information of the memory bank 20 and count the number of CEs of the memory bank.

[0062] The memory can be arranged in the BIOS chip 14, and the memory is configured to store and record the fault information of the memory. Alternatively, the memory can be any one of a register, a DRAM (Dynamic Random Access Memory), and a SRAM (Static Random Access Memory).

[0063] Alternatively, the memory is arranged on the memory bank 20, and the BIOS chip 14 is also configured to directly access the memory in the memory bank to obtain the corresponding memory fault information.

[0064] The BMC 4 is configured to receive all the memory fault information (including the number of CEs of the memory bank) reported by the BIOS chip 14, compare the number of CEs of the memory bank counted by the BIOS chip 14 with a preset threshold, and when the number of CEs of the memory bank is greater than the preset threshold value, send an interrupt signal to the BIOS chip 14 and a latch signal to the latch 11, so that the latch 11 continuously outputs a high level.

[0065] The BIOS chip 14 is also configured to, in response to the interrupt signal sent by the BMC 4, stop counting the number of CEs of the memory bank and clear the previous counting data.

[0066] It should be noted that the preset threshold value can be set according to the working environment and memory capacity of the specific memory bank.

[0067] In other embodiments, the memory management controller 13 may also be a BIOS chip 14 or a BMC4. In this case, the BIOS chip 14 or BMC4 performs the acquisition of memory module fault information, the statistics of the number of memory module CEs, and the comparison of the number of CEs with a preset threshold value, and sends a latch signal to the latch. Its execution principle is the same as that of the aforementioned embodiments.

[0068] The latch 11 is used to continuously output a high level after receiving the latch signal sent by the memory management controller 13, so that the status indicator 12 issues an alarm signal.

[0069] In one implementation, reference is made to Figure 4 The server can be equipped with multiple memory modules and multiple storage devices. Each storage device is used to store fault information of the corresponding memory module. In order to facilitate the monitoring of the health status of different memory modules, multiple latches can be set up. Each latch corresponds to a memory module and is connected to multiple status indicators. When the number of CE faults of any memory module counted by the memory management controller 13 exceeds its preset threshold, the memory management controller 13 searches for the faulty memory module that exceeds the threshold threshold through the memory fault information stored in the storage device and sends a latch signal to the latch corresponding to the faulty memory module.

[0070] Reference Figure 5 As shown, Figure 5 The circuit diagram shows that the two inputs of latch 11 are connected to VDD and one output of memory management controller 13, respectively. The output of latch 11 is connected to one end of status indicator 12, and the other end of status indicator 12 is grounded to Vss. VDD is the power supply voltage of latch 11. Depending on the type of latch 11 selected, VDD corresponds to different parameters. Optionally, latch 11 can be selected as an RS latch, 74L373, etc., as long as it can achieve the function of latching level. The specific type of latch 11 is not specifically limited here.

[0071] Specifically, under normal operating conditions, the output terminal ALERT_n of the memory management controller 13 connected to the latch 11 maintains a high-level signal. At this time, the latch 11 outputs an invalid signal. When the memory management controller 13 detects that the number of CE faults of the memory module exceeds a preset threshold, it considers the memory module to be faulty. At this time, the output terminal ALERT_n of the memory management controller 13 outputs a low level. After receiving the low-level signal, the latch 11 continuously outputs a high level, thereby causing the status indicator to work and issue an alarm signal.

[0072] Optionally, the state indicating member 12 can be any one of an indicating lamp, an LCD display screen, a digital tube, a buzzer, or other devices with warning functions, which are not particularly limited here.

[0073] Referring to Figure 6 , Figure 6 for installing a state indicating member on the memory bank, Figure 5 In the memory bank 20 is connected with the memory management controller 13 and receives detection of the memory management controller 13, the memory bank 20 includes: memory chips 16, a PCB board 17 and pins 18.

[0074] The memory chips 16 are used for storing data, the pins 18 are used for providing connection of the memory chips 16 with the memory management controller 13 and other components on the server, and the pins 18 are also used for fixing the memory bank 20 in the server. The PCB board 17 is used for realizing connection of the memory chips 16 with the memory management controller 13 and other components on the server, and the PCB board 17 is also used for providing support and fixation for the memory chips 16.

[0075] One embodiment of the present application sets the state indicating member 12 on the memory bank 20, which is convenient for directly observing the fault information of the memory bank, and directly sets the state indicating member 12 on the PCB board 17 of the memory bank, so that the power supply on the PCB board 17 can be directly used to provide power supply for the state indicating member 12.

[0076] Optionally, the state indicating member 12 can also be arranged on a plugboard connected with the memory bank 20 (not shown in the figure), as long as the position of the faulty memory bank can be found conveniently, and the installation position of the state indicating member 12 is not particularly limited here.

[0077] The memory bank detection device 10 provided by the above embodiment can directly observe the specific faulty memory bank through the alarm signal emitted by the state indicating member when the memory management controller 13 detects the memory bank fault, so that the faulty memory bank can be processed in time, the risk of mistaken replacement is eliminated, and the risk of server system downtime is reduced.

[0078] The embodiment of the present application also provides a memory bank fault detection method applied to the fault detection device provided by the above device embodiment, which refers to the method shown in Figure 7 The method includes the following steps.

[0079] S11: The memory fault detection device acquires the fault information of the memory bank, and determines the number of correctable errors CE of the memory bank according to the fault information of the memory bank.

[0080] S12: In a case where the number of correctable errors (CE) of the memory bank is greater than a preset threshold value, the memory fault detection device determines a fault memory bank exceeding the threshold value, and sends a latch signal to a latch corresponding to the fault memory bank; the latch signal is used to cause the state indicator to issue an alarm signal. In an embodiment, the memory bank fault detection device further comprises a memory management controller, a latch, and a state indicator, an input end of the memory management controller is connected to the memory bank, an output end of the memory management controller is connected to an input end of a latch, and an output end of the latch is connected to a state indicator. The memory management controller executes the above steps S11-S12.

[0081] In an implementation, the memory management controller can be selected from any one of a processor, a BIOS chip, a DSP chip, and a CPLD.

[0082] In an implementation, the memory management controller can further comprise a counter and a processor.

[0083] In an implementation, the memory management controller can further comprise a BIOS chip and a baseboard management controller (BMC).

[0084] The memory bank fault detection device described in the foregoing embodiments can be widely applied to different computing scenarios, such as, but not limited to, supercomputers, HPC (High Performance Computing), dense computing servers, and the like.

[0085] In an example embodiment, a computer readable storage medium is also provided, which stores at least one instruction, at least one program, a code set, or an instruction set, which is loaded and executed by a processor to implement all or part of the steps of the above memory bank fault detection method. For example, the computer readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0086] In an example embodiment, a computer program product or computer program is also provided, which comprises computer instructions stored in a computer readable storage medium. A processor of a computing device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions to cause the computing device to perform all or part of the above memory bank fault detection method. Figure 7All or part of the steps of the method shown in any embodiment.

[0087] In some embodiments, the method shown in the embodiments of the present application can be implemented as computer program instructions encoded in a machine-readable format on a computer-readable storage medium or on other non-transitory media or articles.

[0088] In a specific application, the computing device can be a server or a personal computer (PC).

[0089] It should be understood that other functions of the corresponding computing device constitute non-core points of the present application, and therefore will not be described herein. The above is only a preferred embodiment of the present application, and it should be noted that for those skilled in the art, without departing from the principles of the present application, a number of improvements and refinements can be made, which should be considered as the protection scope of the present application.

Claims

1. A fault detection device for a memory module, used in a computing device, characterized in that, The fault detection device includes a memory management controller and a latch. The input terminal of the memory management controller is connected to the memory module, and the output terminal of the memory management controller is connected to one input terminal of the latch. The memory management controller is used to detect correctable errors (CEs) of the memory module and determine the number of correctable errors (CEs) of the memory module. If the number of correctable errors (CEs) of the memory module exceeds a preset threshold, the memory management controller sends a latch signal to the latch. The preset threshold is set in advance according to the operating environment and memory capacity of the memory module. The fault detection device also includes a status indicator, which is connected to the output terminal of the latch. The memory modules are multiple, and the latches are multiple and correspond one-to-one with the memory modules. When the number of correctable errors (CEs) exceeds the preset threshold, the memory management controller determines the target faulty memory module that exceeds the threshold and sends a latch signal to the latch corresponding to the target faulty memory module; wherein the target faulty memory module is one or more of the multiple memory modules. When the memory module is operating normally, the output terminal of the memory management controller connected to the latch maintains a high-level signal; when the memory module malfunctions, the output terminal of the memory management controller connected to the latch outputs a low level, and the latch, upon receiving the low-level signal, continuously outputs a high level.

2. The fault detection device according to claim 1, characterized in that, The memory management controller includes a counter and a processor. The counter is used to count the number of correctable errors (CEs). The processor is used to compare the number of correctable errors (CEs) counted by the counter with a preset threshold value. If the number of CEs is greater than the preset threshold value, a latch signal is sent to the latch.

3. The fault detection device according to claim 1, characterized in that, The memory management controller includes a BIOS chip and a baseboard management controller (BMC). The BIOS chip is used to acquire fault information of the memory module and determine the number of correctable errors (CEs) based on the fault information of the memory module, wherein the fault information of the memory module includes the number of correctable errors (CEs). The BIOS chip is also used to send the number of correctable error CEs to the baseboard management controller (BMC). The baseboard management controller (BMC) receives the number of correctable errors (CEs) sent by the BIOS chip and compares the number of correctable errors (CEs) with a preset threshold. When the number of CEs is greater than the preset threshold, a latch signal is sent to the latch.

4. The fault detection device according to any one of claims 1-3, characterized in that, The fault detection device further includes a memory, which is disposed in the memory module or the memory management controller, and is used to store and record fault information of the memory module.

5. The fault detection device according to any one of claims 1-3, characterized in that, The status indicator is used to: receive a high-level output from the latch and issue an alarm signal when the latch receives a latch signal sent by the memory management controller.

6. The fault detection device according to any one of claims 1-3, characterized in that, The status indicator is an indicator light and / or a buzzer.

7. The fault detection device according to any one of claims 1-3, characterized in that, The memory module also includes a PCB circuit board, and the status indicator is disposed on the PCB circuit board or on a slot of the computing device, the slot being used to install the memory module.

8. The fault detection device according to any one of claims 1-3, characterized in that, The computing device is a server.

9. A method for detecting memory module faults, used in a memory module fault detection device, the memory module fault detection device comprising a memory management controller, a latch, and a status indicator, wherein the input terminal of the memory management controller is connected to the memory module, the output terminal of the memory management controller is connected to the input terminal of a latch, and the output terminal of the latch is connected to a status indicator, characterized in that, The method includes the following steps: S11: The memory fault detection device acquires the fault information of the memory module, and determines the number of correctable errors (CEs) of the memory module based on the fault information of the memory module; S12: When the number of correctable errors (CEs) of the memory module exceeds a preset threshold, the memory fault detection device identifies a faulty memory module that exceeds the threshold and sends a latch signal to the latch corresponding to the faulty memory module; the latch signal is used to: cause the status indicator to issue an alarm signal; wherein, the preset threshold is set in advance according to the working environment and memory capacity of the memory module; The memory modules are multiple, and the latches are multiple and correspond one-to-one with the memory modules. When the number of correctable errors (CEs) exceeds the preset threshold, a target faulty memory module that exceeds the threshold is identified, and a latch signal is sent to the latch corresponding to the target faulty memory module. The target faulty memory module is one or more of the multiple memory modules. When the memory module is operating normally, the output terminal of the memory management controller connected to the latch maintains a high-level signal; when the memory module malfunctions, the output terminal of the memory management controller connected to the latch outputs a low level, and the latch, upon receiving the low-level signal, continuously outputs a high level.

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