An encapsulation mechanism for integrated circuit package testing and its encapsulation method

Abstract

The present invention discloses a packaging mechanism and a packaging method for integrated circuit packaging and testing, including a substrate. In the middle of the upper end of the substrate, a limiting mechanism is fixedly connected. In the middle of the upper end of the limiting mechanism, a chip body is movably inserted. At the front and rear of the upper end of the substrate, two insertion rods are fixedly connected respectively. At the left and right of the upper end of the substrate, a number of pins are fixedly connected at equal distances. At the upper parts of the left and right ends of the substrate, support rods are fixedly connected respectively. At the lower end of the substrate, a positioning mechanism is movably inserted. The outer surfaces of the four insertion rods are jointly movably inserted with an upper cover mechanism. The lower end of the upper cover mechanism is in close contact with the substrate but not connected. A heat dissipation shell is fixedly connected to the upper end of the upper cover mechanism. A number of the pins are all connected to the chip body through a number of metal wires. For the packaging mechanism and the packaging method for integrated circuit packaging and testing of the present invention, the overall device has good packaging effect and excellent heat dissipation effect.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and particularly relates to a packaging mechanism and a packaging method for integrated circuit packaging and testing. Background Art

[0002] Integrated circuit packaging not only plays the role of electrically connecting the bonding points inside the integrated circuit chip to the outside, but also provides a stable and reliable working environment for the integrated circuit chip, plays a mechanical or environmental protection role for the integrated circuit chip, so that the integrated circuit chip can perform normal functions and ensure its high stability and reliability.

[0003] However, the following problems still exist in the prior art: 1. After the integrated circuit is packaged, it is necessary to ensure the heat dissipation effect of its chip to avoid overheating of the chip affecting its use. In the prior art, the heat dissipation effect of the chip is not good; 2. The existing packaged integrated circuits are all fixed by soldering the pins, which is not convenient for replacement; 3. The packaging effect quality of the existing devices is not high. Summary of the Invention

[0004] The main purpose of the present invention is to provide a packaging mechanism and a packaging method for integrated circuit packaging and testing, which can effectively solve the problems in the background art.

[0005] To achieve the above purpose, the technical solution adopted by the present invention is as follows:

[0006] A packaging mechanism for integrated circuit packaging and testing includes a substrate. In the middle of the upper end of the substrate, a limiting mechanism is fixedly connected. In the middle of the upper end of the limiting mechanism, a chip body is movably inserted. At the front and rear of the upper end of the substrate, two inserting rods are fixedly connected respectively. At the left and right of the upper end of the substrate, a number of pins are fixedly connected at equal distances. At the upper left and upper right of the substrate, support rods are fixedly connected respectively. At the lower end of the substrate, a positioning mechanism is movably inserted. The outer surfaces of the four inserting rods are jointly movably inserted with an upper cover mechanism. The lower end of the upper cover mechanism is in close contact with the substrate but not connected. At the upper end of the upper cover mechanism, a heat dissipation shell is fixedly connected. A number of the pins are all connected to the chip body through a number of metal wires.

[0007] Preferably, the limiting mechanism includes a connecting seat. In the middle of the upper end of the connecting seat, a through groove is opened. At the front and rear of the upper end of the connecting seat, two connecting grooves are opened respectively, and positioning blocks are fixedly inserted in the four connecting grooves. At the left and right of the upper end of the connecting seat, grooves are opened. The connecting seat is fixedly connected to the substrate.

[0008] Preferably, the upper cover mechanism includes a housing. A fixing groove is formed in the middle of the lower end of the housing. The middle of the upper groove wall in the fixing groove is fixedly connected with a thermal interface plate. A plurality of insertion grooves are equidistantly formed in the left and right parts of the lower end of the housing. Two insertion holes are formed in the front and rear parts of the lower end of the housing. The four insertion holes are respectively movably inserted and connected with four insertion rods.

[0009] Preferably, a plurality of the insertion grooves are respectively movably inserted and connected with a plurality of pins. The thermal interface plate is in close contact with but not connected to the chip body.

[0010] Preferably, the heat dissipation shell includes a shell body. A plurality of second heat dissipation grooves are equidistantly formed in the left and right ends of the shell body. A plurality of first heat dissipation grooves are equidistantly formed in the front and rear ends of the shell body. The shell body is fixedly connected with the upper cover mechanism.

[0011] Preferably, the positioning mechanism includes fixing rods. There are two fixing rods in total. A plurality of insertion columns are fixedly penetrated and connected in the middle of the lower ends of the two fixing rods at equal distances. Connecting columns are fixedly connected to the middle of the lower ends of the insertion columns. A second support plate is fixedly connected to the middle between the two fixing rods. A first support plate is fixedly connected to the front and rear parts between the fixing rods. Both the first support plate and the second support plate are in close contact with but not connected to the lower end of the substrate.

[0012] Preferably, the insertion columns are respectively movably inserted and connected with a plurality of pins.

[0013] A packaging method for a packaging mechanism of integrated circuit packaging and testing includes the following steps:

[0014] Step 1, installation of the chip: Interpenetrate the chip body and the connection seat, and make the lower end of the chip body closely contact with the upper end of the substrate. Then connect the chip body to a plurality of pins through metal wires. Bend the upper part of the positioning block so that the upper part of the positioning block bends and closely contacts with the upper end of the chip body, thereby improving the installation and fixing effect of the chip body.

[0015] Step 2, installation of the upper shell: Insert the housing through the four insertion holes and the four insertion rods. Push the housing downward so that the lower end of the housing closely contacts with the substrate, and make a plurality of insertion grooves respectively interpenetrate with a plurality of pins. At the same time, make the thermal interface plate closely contact with the upper end of the chip body, thereby protecting the chip body through the housing.

[0016] Step 3, installation of the base: Insert the substrate between the two fixing rods, and make the lower end of the substrate closely contact with the upper ends of the two first support plates and the second support plate. At the same time, insert the lower parts of a plurality of pins into a plurality of insertion columns, thereby facilitating the installation and disassembly of the substrate.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] 1. The present invention sets an upper cover mechanism and a heat dissipation shell, and the lower end of the thermal interface plate is tightly attached to the upper end of the chip body. The thermal interface plate fills the micro gap generated when the chip body and the shell are in contact, thereby reducing thermal resistance and improving the heat dissipation performance of the device. When in use, the heat of the chip body will be introduced into the upper end of the thermal interface plate and then introduced into the shell by the thermal interface plate, so that the chip body can quickly dissipate heat.

[0019] 2. By setting up a positioning mechanism, several connecting columns are inserted together with the circuit board, so that the positioning mechanism is installed on the circuit board, and the lower parts of several pins are inserted together with several insertion columns, and the substrate is pushed so that the substrate is inserted between the two fixing rods, thereby facilitating the installation and disassembly of the substrate, thereby facilitating the replacement of the substrate.

[0020] 3. By setting a limiting mechanism, the chip body and the through groove are inserted together, the upper part of the positioning block is bent, so that the upper part of the positioning block is bent, and the positioning block and the upper end of the chip body are tightly attached together, so as to limit the chip body, thereby improving the stability of the chip body installation and improving the packaging effect of the chip body. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is an overall structural diagram of a packaging mechanism for integrated circuit packaging and testing of the present invention;

[0022] Figure 2 A structural diagram of a limiting mechanism of a packaging mechanism for integrated circuit packaging testing of the present invention;

[0023] Figure 3 A bottom view of an upper cover mechanism of a packaging mechanism for integrated circuit packaging and testing of the present invention;

[0024] Figure 4 A bottom view of a heat dissipation shell of a packaging mechanism for integrated circuit packaging and testing of the present invention;

[0025] Figure 5 A structural diagram of a positioning mechanism of a packaging mechanism for integrated circuit packaging testing of the present invention;

[0026] Figure 6 The present invention is a structural cross-sectional view of a packaging mechanism for integrated circuit packaging testing.

[0027] In the figure: 1, substrate; 2, limiting mechanism; 3, chip body; 4, inserting rod; 5, pin; 6, support rod; 7, positioning mechanism; 8, upper cover mechanism; 9, heat dissipation shell; 21, connecting seat; 22, through slot; 23, connecting groove; 24, positioning block; 25, groove; 81, outer shell; 82, fixing groove; 83, inserting slot; 84, inserting hole; 85, thermal interface plate; 91, housing; 92, first heat dissipation slot; 93, second heat dissipation slot; 71, fixing rod; 72, inserting column; 73, connecting column; 74, first support plate; 75, second support plate. Specific embodiments

[0028] In order to make the technical means, creative features, achieved purposes and functions of the present invention easy to understand, the present invention will be further described below in conjunction with specific embodiments.

[0029] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "front end", "rear end", "both ends", "one end", "the other end", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0030] In the description of the present invention, it should be noted that unless otherwise clearly specified and defined, the terms "installation", "provided with", "connection", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the communication inside two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0031] As Figures 1-6 shown, a packaging mechanism for integrated circuit packaging and testing includes a substrate 1. In the middle of the upper end of the substrate 1, a limiting mechanism 2 is fixedly connected. In the middle of the upper end of the limiting mechanism 2, a chip body 3 is movably inserted. At the front and rear of the upper end of the substrate 1, two inserting rods 4 are fixedly connected respectively. At the left and right of the upper end of the substrate 1, a number of pins 5 are fixedly connected at equal distances. At the upper left and upper right of the substrate 1, support rods 6 are fixedly connected respectively. At the lower end of the substrate 1, a positioning mechanism 7 is movably inserted. The outer surfaces of the four inserting rods 4 are jointly movably inserted with an upper cover mechanism 8. The lower end of the upper cover mechanism 8 is in close contact with the substrate 1 but not connected. The upper end of the upper cover mechanism 8 is fixedly connected with a heat dissipation shell 9. A number of pins 5 are all connected to the chip body 3 through a number of metal wires.

[0032] The limiting mechanism 2 includes a connecting seat 21. A through groove 22 is formed in the middle of the upper end of the connecting seat 21. By providing the through groove 22, it is convenient to install the chip body 3. Two connecting grooves 23 are formed in both the front part and the rear part of the upper end of the connecting seat 21, and positioning blocks 24 are fixedly inserted and connected in the four connecting grooves 23. Grooves 25 are formed in both the left part and the right part of the upper end of the connecting seat 21. By providing the grooves 25, it is convenient for the chip body 3 to be connected to the pins 5. The connecting seat 21 is fixedly connected to the substrate 1; The upper cover mechanism 8 includes a housing 81. A fixing groove 82 is formed in the middle of the lower end of the housing 81. A thermal interface plate 85 is fixedly connected to the middle of the upper groove wall in the fixing groove 82. By providing the thermal interface plate 85, the heat dissipation effect of the chip body 3 is improved. A number of insertion grooves 83 are equidistantly formed in both the left part and the right part of the lower end of the housing 81. Two insertion holes 84 are formed in both the front part and the rear part of the lower end of the housing 81. The four insertion holes 84 are respectively movably inserted and connected with the four insertion rods 4; A number of insertion grooves 83 are respectively movably inserted and connected with a number of pins 5. The thermal interface plate 85 is in close contact with the chip body 3 but not connected; The heat dissipation shell 9 includes a shell body 91. A number of second heat dissipation grooves 93 are equidistantly formed in both the left end and the right end of the shell body 91. A number of first heat dissipation grooves 92 are equidistantly formed in both the front end and the rear end of the shell body 91. The shell body 91 is fixedly connected to the upper cover mechanism 8; The positioning mechanism 7 includes fixing rods 71. There are two fixing rods 71 in total. A number of insertion columns 72 are fixedly penetrated and connected at equal distances in the middle of the lower ends of the two fixing rods 71. Connecting columns 73 are fixedly connected to the middle of the lower ends of the insertion columns 72. A second support plate 75 is fixedly connected in the middle between the two fixing rods 71. A first support plate 74 is fixedly connected between the front part and the rear part of the fixing rods 71. Both the first support plate 74 and the second support plate 75 are in close contact with the lower end of the substrate 1 but not connected; The insertion columns 72 are respectively movably inserted and connected with a number of pins 5.

[0033] It should be noted that the present invention relates to a packaging mechanism and a packaging method for integrated circuit packaging and testing. The chip body 3 and the through groove 22 are interspersed with each other, and the lower end of the chip body 3 is closely attached to the upper end of the substrate 1. Then, the chip body 3 is connected to a plurality of pins 5 through metal wires. The upper part of the positioning block 24 is bent by moving it, so that the upper part of the positioning block 24 is bent and the positioning block 24 is closely attached to the upper end of the chip body 3, thereby limiting the chip body 3. Then, the outer shell 81 is interspersed with four through rods 4 through four through holes 84. The outer shell 81 is pushed, so that the outer shell 81 slides downward on the outer surface of the four through rods 4, and the lower end of the outer shell 81 is closely attached to the upper end of the substrate 1. At the same time, a plurality of through grooves 83 are respectively interspersed with a plurality of pins 5. When the outer shell 81 moves downward, it will drive the thermal interface plate 85 fixedly connected thereto to move downward, so that the lower end of the thermal interface plate 85 is closely attached to the upper end of the chip body 3. The thermal interface plate 85 fills the micro gaps generated when the chip body 3 and the outer shell 81 are in contact, reduces the thermal resistance, and improves the heat dissipation performance of the device. During use, the heat of the chip body 3 is introduced to the upper end of the thermal interface plate 85 and then introduced to the outer shell 81 by the thermal interface plate 85, so that the chip body 3 can dissipate heat quickly. A plurality of connecting columns 73 are all interspersed with the circuit board, so that the positioning mechanism 7 is installed on the circuit board. The lower parts of a plurality of pins 5 are interspersed with a plurality of through columns 72. The substrate 1 is pushed, so that the substrate 1 is interspersed between two fixed rods 71, and the lower end of the substrate 1 is closely attached to the upper ends of two first support plates 74 and a second support plate 75, thereby facilitating the installation and disassembly of the substrate 1.

[0034] The foregoing has shown and described the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and the descriptions in the specification are only used to illustrate the principles of the present invention. Without departing from the spirit and scope of the present invention, the present invention will have various changes and improvements, and these changes and improvements all fall within the scope of the present invention claimed. The scope of protection of the present invention is defined by the appended claims and their equivalents.

Claims

1. An encapsulation mechanism for integrated circuit packaging and testing, comprising a substrate (1), characterized in that: The middle part of the upper end of the substrate (1) is fixedly connected to a limiting mechanism (2); the front part and the rear end of the upper end of the substrate (1) are both fixedly connected to two insertion rods (4); the left part and the right part of the upper end of the substrate (1) are fixedly connected to a plurality of pins (5) at equal distances; the lower end of the substrate (1) is movably inserted and connected to a positioning mechanism (7); the outer surfaces of the four insertion rods (4) are movably inserted and connected to an upper cover mechanism (8); the lower end of the upper cover mechanism (8) is tightly attached to the substrate (1); the upper end of the upper cover mechanism (8) is fixedly connected to a heat dissipation shell (9); and the plurality of pins (5) are connected to the chip body (3) through a plurality of metal wires; The limiting mechanism (2) comprises a connecting seat (21), a through groove (22) is formed in the middle of the upper end of the connecting seat (21), two connecting grooves (23) are formed in the front and rear parts of the upper end of the connecting seat (21), and positioning blocks (24) are fixedly inserted and connected in the four connecting grooves (23), and the connecting seat (21) is fixedly connected to the base plate (1); The chip body (3) and the through groove (22) are inserted together, and the upper part of the positioning block (24) is bent, so that the upper part of the positioning block (24) is bent, and the positioning block (24) and the upper end of the chip body (3) are tightly attached together, thereby limiting the chip body (3); The positioning mechanism (7) comprises a fixing rod (71), wherein two fixing rods (71) are provided, and a plurality of interpenetrating columns (72) are fixedly connected and penetrated at equal distances in the middle of the lower ends of the two fixing rods (71), and a connecting column (73) is fixedly connected to the middle of the lower ends of the interpenetrating columns (72), and a supporting plate is fixedly connected between the two fixing rods (71), and the supporting plate is tightly attached to the lower end of the base plate (1), and the interpenetrating columns (72) are respectively movably interpenetratingly connected with a plurality of pins (5); The upper cover mechanism (8) comprises a shell (81), a fixing groove (82) is formed in the middle of the lower end of the shell (81), a thermal interface plate (85) is fixedly connected to the middle of the upper groove wall in the fixing groove (82), and the thermal interface plate (85) is in close contact with the chip body (3); The heat dissipation shell (9) comprises a shell (91), the shell (91) is provided with a plurality of heat dissipation slots, and the shell (91) is fixedly connected to the upper cover mechanism (8).

2. The packaging mechanism for integrated circuit packaging and testing according to claim 1, characterized in that: The left upper portion and the right upper portion of the connecting seat (21) are both provided with grooves (25).

3. The packaging mechanism for integrated circuit packaging and testing according to claim 1, characterized in that: The left and right lower ends of the shell (81) are provided with a plurality of insertion slots (83) at equal distances, and the front and rear lower ends of the shell (81) are provided with two insertion holes (84), and the four insertion holes (84) are respectively movably inserted and connected with four insertion rods (4).

4. The packaging mechanism for integrated circuit packaging and testing according to claim 3, characterized in that: A plurality of the insertion slots (83) are respectively movably inserted and connected with a plurality of pins (5).

5. The packaging mechanism for integrated circuit packaging and testing according to claim 1, characterized in that: A plurality of second heat dissipation slots (93) are evenly spaced apart at the left and right ends of the shell (91), and a plurality of first heat dissipation slots (92) are evenly spaced apart at the front and rear ends of the shell (91).

6. The packaging mechanism for integrated circuit packaging and testing according to claim 1, characterized in that: A second support plate (75) is fixedly connected in common at the middle between the two fixing rods (71). A first support plate (74) is fixedly connected at the front and rear between the fixing rods (71). Both the first support plate (74) and the second support plate (75) are in close contact with the lower end of the substrate (1).

7. A packaging method for a packaging mechanism of an integrated circuit packaging test according to any one of claims 1-6, characterized in that: The method includes the following steps: Step 1, installation of the chip: Interpenetrate the chip body (3) and the connection base (21), and make the lower end of the chip body (3) in close contact with the upper end of the substrate (1). Then connect the chip body (3) to a plurality of pins (5) through metal wires. Bend the upper part of the positioning block (24) so that the upper part of the positioning block (24) is bent and in close contact with the upper end of the chip body (3), thereby improving the installation and fixing effect of the chip body (3). Step 2, installation of the upper shell: Interpenetrate the outer shell (81) and four insertion rods (4) through four insertion holes (84). Push the outer shell (81) to make the outer shell (81) move downward and the lower end of the outer shell (81) in close contact with the substrate (1), so that a plurality of insertion grooves (83) are respectively interpenetrated with a plurality of pins (5). At the same time, make the thermal interface plate (85) in close contact with the upper end of the chip body (3), thereby protecting the chip body (3) through the outer shell (81). Step 3, installation of the base: Interpenetrate the substrate (1) between the two fixing rods (71), and make the lower end of the substrate (1) in close contact with the upper ends of the two first support plates (74) and the second support plate (75). At the same time, interpenetrate the lower parts of the plurality of pins (5) and a plurality of insertion columns (72), thereby facilitating the installation and disassembly of the substrate (1).

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