Semiconductor device and method for manufacturing the same

Abstract

The present application relates to a semiconductor device and a manufacturing method thereof, including: a substrate, a buried insulating layer, a semiconductor layer, at least two spaced-apart channel regions, an anode, a cathode contact region, and a cathode. Among them, a channel contact region is provided on the upper surface of the channel region, and an anode contact region is provided between two adjacent channel regions. When the semiconductor device conducts forwardly, the channel contact region can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device; when the semiconductor device conducts reversely, the reverse depletion layer formed by the semiconductor layer and each channel region can pinch off the conductive channel, making the entire anode in a closed state and reducing leakage; when the semiconductor device recovers reversely, the minority carriers holes generated in the channel contact region can recombine with the electron holes in the anode contact region and disappear, reducing the peak current of the entire device during reverse recovery and reducing the reverse recovery time at the same time.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for manufacturing the same. Background Art

[0002] With the development of semiconductor technology, the use of a Lateral Insulated-Gate Bipolar Transistor (LIGBT) as a power switching transistor has become a mainstream design in the market. Usually, when a LIGBT is used as a switching device, a high-voltage diode needs to be connected in parallel between its collector and emitter to add a current path, allowing excess current to return to the coil to protect the LIGBT. The reverse recovery of the high-voltage diode corresponds to the turn-on of the LIGBT. If the reverse recovery time is long and the LIGBT turns on before the high-voltage diode has recovered, the superposition of the two currents can easily damage the switching transistor.

[0003] However, the existing high-voltage diodes have a slow reverse recovery time and a large peak reverse recovery current during recovery, so they cannot meet the high-speed and low-loss switching requirements of switching devices. Summary of the Invention

[0004] Based on this, it is necessary to provide a semiconductor device and a method for manufacturing the same to shorten the reverse recovery time of the high-voltage diode and reduce the peak reverse recovery current.

[0005] To achieve the objectives of this application, the following technical solutions are adopted in this application:

[0006] A semiconductor device, comprising:

[0007] A substrate having a first conductivity type, and an insulating buried layer is provided on the upper surface within the substrate;

[0008] A semiconductor layer located on the upper surface of the insulating buried layer, having a second conductivity type, and the second conductivity type is opposite to the first conductivity type;

[0009] At least two spaced-apart channel regions located on the upper surface layer of the semiconductor layer, having a first conductivity type, a channel contact region with a heavily doped first conductivity type is provided on the upper surface layer of the channel region, and an anode contact region with a heavily doped second conductivity type is provided between two adjacent channel regions;

[0010] An anode located above the substrate, electrically connected to the channel contact region and the anode contact region respectively;

[0011] A cathode contact region with a heavily doped second conductivity type, located on the upper surface layer of the semiconductor layer and spaced from the channel region;

[0012] The cathode, located above the semiconductor layer, is electrically connected to the cathode contact region.

[0013] In one embodiment, the anode contact regions and the channel contact regions are arranged alternately, and the adjacent anode contact region and the channel contact region are in contact or spaced apart.

[0014] In one embodiment, the spacing between two adjacent channel regions is less than or equal to twice the junction depth of the channel region.

[0015] In one embodiment, the number of the channel regions is four, the channel contact regions are provided on the upper surface layer of each channel region, and the anode contact regions are provided between two adjacent channel regions.

[0016] In one embodiment, it further includes:

[0017] A buffer region, located in the upper surface layer of the semiconductor layer and spaced from the channel regions, has a second conductivity type; wherein, the cathode contact region is located on the upper surface of the buffer region.

[0018] In one embodiment, the junction depth of the channel region is less than or equal to the junction depth of the buffer region.

[0019] In one embodiment, it further includes:

[0020] A field oxide layer, located on the upper surface of the semiconductor layer, one side of the field oxide layer is in contact with the anode contact region, and the other side of the field oxide layer is in contact with the cathode contact region.

[0021] In one embodiment, it further includes:

[0022] An anode field plate, located on the upper surface of the field oxide layer and electrically connected to the anode; and / or

[0023] A cathode field plate, located on the upper surface of the field oxide layer and electrically connected to the cathode.

[0024] A method for manufacturing a semiconductor device, including:

[0025] Providing a substrate, the substrate has a first conductivity type, and an insulating buried layer is formed on the upper surface of the substrate;

[0026] Forming a semiconductor layer on the upper surface of the insulating buried layer, the semiconductor layer has a second conductivity type, and the second conductivity type is opposite to the first conductivity type;

[0027] At least two spaced-apart channel regions are formed on the upper surface layer of the semiconductor layer. The channel regions have a first conductivity type. A channel contact region with a heavily doped first conductivity type is formed on the upper surface layer of the channel regions. An anode contact region with a heavily doped second conductivity type is formed between two adjacent channel regions.

[0028] A cathode contact region with a heavily doped second conductivity type is formed in the upper surface layer of the semiconductor layer. The cathode contact region is spaced apart from the channel regions.

[0029] An anode and a cathode are formed above the substrate. The anode is electrically connected to the channel contact region and the anode contact region respectively, and the cathode is electrically connected to the cathode contact region.

[0030] In one embodiment, forming a cathode contact region with a heavily doped second conductivity type in the upper surface layer of the semiconductor layer, and the cathode contact region is spaced apart from the channel regions, further includes:

[0031] A buffer region with a second conductivity type is formed in the upper surface layer of the semiconductor layer. The buffer region is spaced apart from the channel regions.

[0032] The cathode contact region is formed on the upper surface layer of the buffer region.

[0033] The above semiconductor device and its manufacturing method, wherein the semiconductor device includes a substrate, an insulating buried layer, a semiconductor layer, at least two spaced-apart channel regions, an anode, a cathode contact region and a cathode. Among them, a channel contact region is provided on the upper surface layer of the channel region, and an anode contact region is provided between two adjacent channel regions. When the semiconductor device conducts forward, the channel contact region can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device. When the semiconductor device ends conduction and changes from forward conduction to reverse, the reverse depletion layer formed by the semiconductor layer and each channel region can pinch off the conductive channel, completely blocking the path for the minority holes generated by the channel contact region to inject into the device interior, making the entire anode in a closed state and reducing leakage. When the semiconductor device recovers in reverse, the minority holes generated by the channel contact region can recombine with the electron holes in the anode contact region and disappear, greatly reducing the number of holes injected into the interior due to conductivity modulation in the anode in the traditional structure, greatly reducing the peak current when the entire device recovers in reverse, and greatly reducing the reverse recovery time at the same time. Description of the Drawings

[0034] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0035] Figure 1 It is a schematic cross-sectional structure diagram of a semiconductor device in an embodiment;

[0036] Figure 2 It is a schematic cross-sectional structure diagram of a semiconductor device in an embodiment;

[0037] Figure 3 It is a schematic cross-sectional structure diagram of a semiconductor device in an embodiment;

[0038] Figure 4 It is a schematic cross-sectional structure diagram of a semiconductor device in an embodiment;

[0039] Figure 5 It is a flowchart of a method for manufacturing a semiconductor device in an embodiment. Detailed implementation manners

[0040] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant accompanying drawings. Embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to", or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, conductive types, and / or portions, these elements, components, regions, layers, conductive types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, conductive type, or portion from another element, component, region, layer, conductive type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, or portion discussed below may be denoted as the second element, component, region, layer, or portion; for example, the first conductive type may be referred to as the second conductive type, and similarly, the second conductive type may be referred to as the first conductive type; the first conductive type and the second conductive type are different conductive types, for example, the first conductive type may be P-type and the second conductive type may be N-type, or the first conductive type may be N-type and the second conductive type may be P-type.

[0043] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "on" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. In addition, the device may also include additional orientations (such as rotating 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0044] As used herein, the singular forms "a", "an", and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / include" or "has" etc. specify the presence of the stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.

[0045] As described in the background art, the reverse recovery time of a high-voltage diode is relatively slow, and the peak reverse recovery current during recovery is also very large. Therefore, it cannot meet the high-speed and low-loss switching requirements in switching devices. Through research by the inventors, it is found that the reason for this problem is that in traditional semiconductor devices, when the diode is forward-conducting, a large number of minority carrier holes are injected. These minority carrier holes will generate current for freewheeling. When the freewheeling stage ends, these holes still remain in the device. In addition, due to its high breakdown voltage characteristic and long drift region, there are also many intrinsic minority carriers stored in the drift region inside the device itself. Therefore, when the high-voltage diode switches from forward conduction to reverse cutoff, the reverse recovery time becomes very slow because the minority carriers cannot be recombined quickly, and the peak reverse recovery current during recovery is also very large. Thus, it cannot meet the high-speed and low-loss switching requirements in switching devices. Moreover, when the traditional semiconductor device is forward-conducting and needs to conduct a large current, due to the inability to achieve the conductivity modulation effect, it results in a large freewheeling loss and generates heat. When the device is in the breakdown state during the reverse recovery stage of the semiconductor device, the leakage current increases exponentially, especially with poor high-temperature characteristics. And traditional semiconductor devices usually use Schottky holes to realize the connection between the channel region and the anode, which increases the complexity of the process.

[0046] For the above reasons, the present application provides a semiconductor device. Figure 1 FIG. is a schematic structural diagram of a semiconductor device according to an embodiment. The semiconductor device 10 includes a substrate 101, a buried insulating layer 102, a semiconductor layer 103, at least two spaced-apart channel regions 104, a channel contact region 105, an anode contact region 106, a cathode contact region 107, an anode and a cathode ( Figure 1 The anode and the cathode are not shown).

[0047] In this embodiment, a buried insulating layer 102 is provided on the upper surface of the substrate 101, and the semiconductor layer 103 is located on the upper surface of the buried insulating layer 102. The semiconductor layer 103 is used to fabricate the device. Exemplarily, the semiconductor device is an SOI (Silicon-On-Insulator) device, the substrate 101 is a silicon substrate 101, and the buried insulating layer 102 is a buried oxide layer.

[0048] Among them, the substrate 101 has a first conductivity type, the semiconductor layer 103 has a second conductivity type, the second conductivity type is opposite to the first conductivity type, and the doping concentration of the semiconductor layer 103 is lower than the doping concentration of the substrate 101. One of the first conductivity type and the second conductivity type is a P type, and the other is an N type. For example, the first conductivity type is a P type and the second conductivity type is an N type; or, the first conductivity type is an N type and the second conductivity type is a P type.

[0049] Exemplarily, in this embodiment, the first conduction type is P-type and the second conduction type is N-type. The substrate 101 is a P-type substrate 101, and the semiconductor layer 103 is an N-type lightly doped semiconductor layer 103.

[0050] In this embodiment, at least two spaced-apart channel regions 104 are located on the upper surface layer of the semiconductor layer 103. A channel contact region 105 doped with the first conduction type at a high level is provided on the upper surface layer of the channel region 104, and an anode contact region 106 doped with the second conduction type at a high level is provided between two adjacent channel regions 104.

[0051] Among them, the channel region 104 is located on the upper surface layer of the semiconductor layer 103, and the upper surface of the channel region 104 is flush with the upper surface of the semiconductor layer 103. The channel region 104 is an island-shaped high-voltage well region doped with the first conduction type, serving as the substrate of the high-voltage diode, and is used to form a lateral conduction channel to conduct current. The conduction type of the channel region 104 is opposite to that of the semiconductor layer 103 and the doping concentration of the channel region 104 is higher than that of the semiconductor layer 103. For example, the conduction type of the semiconductor layer 103 is N-type lightly doped, and the conduction type of the channel region 104 is P-type. When the semiconductor device conducts forward, the channel region 104 and the substrate 101 form a connected current path, so that current flows from the anode through the channel region 104 and the substrate 101 to the cathode. When the semiconductor device conducts backward, the substrate 101 and the channel region 104 form a reverse depletion layer to pinch off the conduction channels formed between the channel regions 104.

[0052] Among them, the number of the channel regions 104 is at least two, and the adjacent channel regions 104 are spaced apart from each other to form at least two spaced-apart lateral conduction channels. Compared with the traditional high-voltage diode having only one channel region 104, in this embodiment, multiple channel regions 104 are formed in the same area. The multiple channel regions 104 are spaced apart from each other to form a segmented multiple lateral conduction channels, so that the lateral conduction channels between the adjacent channel regions 104 are more likely to be pinched off when the device conducts backward, thereby further accelerating the recombination rate of minority carriers (holes) on the channel contact region 105 during reverse recovery, so as to further improve the reverse recovery time of the device. In some embodiments, as Figure 1 shown, the number of the channel regions 104 is two, and the two adjacent channel regions 104 are spaced apart from each other to form two spaced-apart lateral conduction channels. In some embodiments, as Figure 2 shown, when the number of the channel regions 104 can be four, the four channel regions 104 form four lateral conduction channels.

[0053] Among them, when the number of channel regions 104 is larger, the projected area of each channel region 104 on the semiconductor layer 103 is smaller. During reverse conduction, pinch-off is more likely to occur between two adjacent channel regions 104, thereby further improving the reverse recovery time of the device. The number of channel regions 104 can be set according to the actual requirements of the reverse recovery time and the product size of the semiconductor device. When setting according to the product size, it can be specifically determined according to the area of the positive projection region of the anode. When the positive projection area of the anode on the semiconductor layer 103 is small, the number of channel regions 104 is small; when the positive projection area of the anode on the semiconductor layer 103 is large, the number of channel regions 104 is large.

[0054] Among them, the distance between two adjacent channel regions should meet the requirement that the anti-depletion layer formed by the semiconductor layer 103 and the channel region 104 pinch off the conductive channel formed by the anode contact region 106. In some embodiments, the distance between two adjacent channel regions 104 is less than or equal to twice the junction depth of the channel region 104. Generally, the lateral diffusion distance of the channel region 104 is 80% of the longitudinal junction depth. When adjusting the distance between two adjacent channel regions 104 to be less than or equal to twice the junction depth of the channel region 104, the pinch-off speed can be accurately controlled, and the reverse recovery time of the device can be improved. Among them, the junction depth of the channel region 104 refers to the depth of the channel region 104 in the direction from the semiconductor layer 103 to the substrate 101.

[0055] Among them, a channel contact region 105 with a heavily doped first conductivity type is provided in the upper surface layer of each channel region 104. The channel contact region 105 serves as an ohmic contact for the corresponding channel region 104, realizing a low-resistance electrical connection between the anode and the channel region 104. The channel contact region 105 can be used to generate minority holes with a heavily doped first conductivity type and inject them into the device interior. When the device conducts forward, the generated minority holes are injected into the channel region 104, which can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device during normal freewheeling; when the device changes from forward conduction to reverse, since the conduction channels between adjacent channel regions 104 are pinched off by the reverse depletion layer formed by the substrate 101 and the channel region 104, the path for the minority holes generated by the channel contact region 105 to be injected into the device interior is pinched off, and the anode is in a closed state, and the leakage current will be much smaller than that of a traditional Schottky fast recovery diode; during the reverse recovery stage, the remaining minority holes can disappear after recombining with electron-hole pairs. In some embodiments, multiple channel contact regions 105 can be provided in each channel region 104. The multiple channel contact regions 105 can increase the injection amount of minority holes into the device interior, further reduce the voltage drop during forward conduction, and thereby further reduce the overall power consumption during normal freewheeling. In some embodiments, one channel contact region 105 can be provided in each channel region 104. The lateral width of the channel contact region 105 is equal to the lateral width of the corresponding channel region 104, thereby increasing the injection amount of minority holes into the device interior, further reducing the voltage drop during forward conduction, and thereby further reducing the overall power consumption during normal freewheeling.

[0056] Among them, an anode contact region 106 with a heavily doped second conductivity type is provided between two adjacent channel regions 104. The anode contact region 106 has a heavily doped second conductivity type and serves as an ohmic contact for the anode of the semiconductor device. It can be used to generate electron-hole pairs with a heavily doped second conductivity type. The electron-hole pairs can recombine with minority holes during the reverse recovery of the device, so as to greatly reduce the number of holes internally injected due to conductance modulation at the anode of a traditional diode, thereby greatly reducing the peak current of the entire device during reverse recovery and accelerating the reverse recovery time. When the occupied area of the anode contact region 106 on the semiconductor layer 103 is larger, more electron-hole pairs can be generated, so that more electron-hole pairs are generated during the reverse recovery of the device, allowing the excess holes to be recombined faster, and making the reverse recovery time shorter.

[0057] In some embodiments, the anode contact regions 106 and the channel contact regions 105 are arranged alternately, and adjacent anode contact regions 106 and channel contact regions 105 are in contact or spaced apart. Among them, when the anode contact region 106 and the channel contact region 105 are in contact, the occupied area of the anode contact region 106 and the channel contact region 105 on the upper surface layer of the semiconductor layer 103 can be reduced, effectively reducing the lateral width of the device.

[0058] In this embodiment, the anode is located above the substrate 101 and is electrically connected to the channel contact region 105 and the anode contact region 106 respectively. Among them, the anode is connected to the channel contact region 105, so that the channel contact region 105 is connected to the anode voltage, and the channel contact region 105 is at the same potential as the anode; the anode is connected to the anode contact region 106, so that the anode contact region 106 is connected to the anode voltage, and the anode contact region 106 is at the same potential as the anode.

[0059] In this embodiment, the cathode contact region 107 doped with the second conductive type is located on the upper surface layer of the semiconductor layer 103 and is spaced from the channel region 104; the cathode is located above the semiconductor layer 103 and is electrically connected to the cathode contact region 107. Among them, the cathode contact region 107 has the same conductive type as the anode contact region 106, and the cathode contact region 107 serves as an ohmic contact of the cathode of the semiconductor device to achieve a low-resistance electrical connection between the cathode and the semiconductor layer 103.

[0060] When the semiconductor device conducts forward, the anode is connected to a high potential and the cathode is connected to a low potential. The current flows from the anode, through the channel contact region 105, the channel region 104, and the semiconductor layer 103 to the cathode contact region 107 and the cathode. The channel contact region 105 can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device; when the semiconductor device ends conduction and changes from forward conduction to reverse, the cathode is connected to a high potential, and the semiconductor device is in a high-voltage reverse bias state. The reverse depletion layer formed by the semiconductor layer 103 and each channel region 104 can pinch off the conductive channel, completely blocking the path for minority carrier holes generated by the channel contact region 105 to inject into the device interior, making the entire anode in a closed state and reducing leakage. Especially when the device operates at a high temperature, the advantage is more obvious; when the semiconductor device recovers in reverse, the minority carrier holes generated by the channel contact region 105 can recombine with the electron holes in the anode contact region 106 and disappear, greatly reducing the number of holes injected into the anode due to conductance modulation in the traditional structure, making the peak current of the entire device during reverse recovery greatly reduced, and at the same time greatly reducing the reverse recovery time.

[0061] In some embodiments, as Figure 3 and Figure 4 shown (where Figure 3 corresponds to Figure 1 , Figure 4 corresponds to Figure 2 ), the semiconductor device further includes a buffer region 200, which is located in the upper surface layer of the semiconductor layer 103 and is spaced from the channel region 104 and has the second conductive type; among them, the cathode contact region 107 is located on the upper surface layer of the buffer region 200.

[0062] Among them, the buffer region 200 has the same conductivity type as the semiconductor layer 103, and the doping concentration of the buffer region 200 is greater than that of the semiconductor layer 103, and the doping concentration of the buffer region 200 is less than that of the cathode contact region 107. Thus, the buffer region 200 plays a certain role in hole injection and breakdown voltage withstand of the device.

[0063] In some embodiments, the junction depth of the channel region 104 is less than or equal to that of the buffer region 200, which is beneficial to shortening the transport path of minority carriers during reverse recovery after pinch-off, and thus beneficial to the recombination of holes, improving the reverse recovery time of the device. Among them, the junction depth of the buffer region 200 refers to the depth of the buffer region 200 in the direction from the semiconductor layer 103 to the substrate 101.

[0064] In some embodiments, as Figure 3 and Figure 4 shown, the semiconductor device further includes a first conductive structure 201, a second conductive structure 202, and a third conductive structure 203.

[0065] The first conductive structure 201 is connected between the anode contact region 106 and the anode 108, and is used to realize the electrical connection between the anode contact region 106 and the anode 108.

[0066] The second conductive structure 202 is connected between the channel contact region 105 and the anode 108, and is used to realize the electrical connection between the channel contact region 105 and the anode 108.

[0067] The third conductive structure 203 is connected between the cathode contact region 107 and the cathode 109, and is used to realize the electrical connection between the cathode contact region 107 and the cathode 109.

[0068] Among them, the first conductive structure 201, the second conductive structure 202, and the third conductive structure 203 are formed of a conductive material, such as copper, aluminum, aluminum-silicon alloy, titanium, titanium nitride, tungsten, polysilicon, metal silicide, etc.

[0069] In some embodiments, as Figure 3 and Figure 4 shown, the first conductive structure 201 corresponds one-to-one with the anode contact region 106, and the second conductive structure 202 corresponds one-to-one with the channel contact region 105. Thus, multiple anode contact regions 106 correspond to multiple first conductive structures 201, and multiple channel contact regions 105 correspond to multiple second conductive structures 202, thereby reducing the equivalent resistance between the anode 108 and the anode contact region 106, and the channel contact region 105.

[0070] In some embodiments, the cathode contact region 107 may correspond to multiple third conductive structures 203, for example, corresponding to two third conductive structures 203. Multiple third conductive structures 203 can reduce the equivalent resistance between the cathode 109 and the cathode contact region 107.

[0071] In some embodiments, as Figure 3 and Figure 4 shown, the semiconductor device further includes a field oxide layer 204.

[0072] Among them, the field oxide layer 204 is located on the upper surface of the semiconductor layer 103. One side of the field oxide layer 204 is adjacent to and in contact with the anode contact region 106, and the other side of the field oxide layer 204 is adjacent to and in contact with the cathode contact region 107. The field oxide layer 204 is used to separate the channel region 104 and the cathode contact region 107 to ensure the normal operation of the semiconductor device. Exemplarily, the material of the field oxide layer 204 is an oxide of silicon, for example, it can be silicon dioxide.

[0073] In some embodiments, as Figure 3 and Figure 4 shown, the field oxide layer 204 is also used to isolate the high-voltage diode from an adjacent high-voltage diode, or isolate the high-voltage diode from other semiconductor devices.

[0074] In some embodiments, as Figure 3 and Figure 4 shown, the semiconductor device further includes an anode field plate 205 and / or a cathode field plate 206.

[0075] The anode field plate 205 is located on the upper surface of the field oxide layer 204 and is electrically connected to the anode 108.

[0076] The cathode field plate 206 is located on the upper surface of the field oxide layer 204 and is electrically connected to the cathode 109.

[0077] Among them, the anode field plate 205 is electrically connected to the anode 108 and has the same potential as the anode 108, and is used to adjust the electric field lines on the anode 108 side during reverse depletion to weaken the surface electric field; the cathode field plate 206 is electrically connected to the cathode 109 and has the same potential as the cathode 109, and is used to adjust the electric field lines on the cathode 109 side during reverse depletion to weaken the surface electric field. Specifically, when the device is under reverse voltage withstand, the cathode field plate 206 has the same potential as the cathode 109, and the anode field plate 205 has the same potential as the anode 108, so that the potential of the field oxide layer 204 has an approximately linear change from the cathode 109 to the anode 108, and the electric field distribution in the substrate 101 also has an approximately linear change accordingly. Thereby, it assists the substrate 101 to deplete, enables the reverse depletion rate to remain uniform, alleviates the problem of peak electric field caused by local electric field line aggregation, and improves the voltage withstand characteristics of the device. Exemplarily, the materials of the anode field plate 205 and the cathode field plate 206 can be polysilicon materials.

[0078] The semiconductor device provided by this embodiment includes a substrate 101, a buried insulating layer 102, a semiconductor layer 103, at least two channel regions 104 arranged at intervals, an anode 108, a cathode contact region 107, and a cathode 109. Among them, a channel contact region 105 is provided on the upper surface of the channel region 104, and an anode contact region 106 is provided between two adjacent channel regions 104. When the semiconductor device conducts forward, the channel contact region 105 can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device. When the semiconductor device ends conduction and changes from forward conduction to reverse, the reverse depletion layer formed by the semiconductor layer 103 and each channel region 104 can pinch off the conductive channel, completely sealing the path for minority carrier holes generated by the channel contact region 105 to inject into the device interior, making the entire anode 108 in a closed state and reducing leakage. When the semiconductor device recovers in reverse, the minority carrier holes generated by the channel contact region 105 can recombine with the electron holes in the anode contact region 106 and disappear, greatly reducing the number of holes injected into the interior due to conductance modulation in the anode 108 in the traditional structure, greatly reducing the peak current of the entire device during reverse recovery, and at the same time greatly reducing the reverse recovery time.

[0079] It should be noted that the above embodiments should not be limited to the specific shapes of the regions shown here, but include shape deviations caused by, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the figures are substantially schematic, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present invention.

[0080] Figure 5 A method for manufacturing a semiconductor device according to an embodiment is shown, which is used to manufacture the semiconductor device in the above embodiment and includes step 101-step 105.

[0081] Step 101: Provide a substrate. The substrate has a first conductivity type, and a buried insulating layer is formed on the upper surface of the substrate.

[0082] Step 102: Form a semiconductor layer on the upper surface of the buried insulating layer. The semiconductor layer has a second conductivity type, and the second conductivity type is opposite to the first conductivity type.

[0083] Step 103: Form at least two channel regions arranged at intervals on the upper surface of the semiconductor layer. The channel regions have a first conductivity type. Form a channel contact region doped heavily with the first conductivity type on the upper surface of the channel regions, and form an anode contact region doped heavily with the second conductivity type between two adjacent channel regions.

[0084] Step 104: Form a cathode contact region with a heavily doped second conductivity type on the upper surface layer of the semiconductor layer, and the cathode contact region is disposed at an interval from the channel region.

[0085] Step 105: Form an anode and a cathode above the substrate. The anode is electrically connected to the channel contact region and the anode contact region respectively, and the cathode is electrically connected to the cathode contact region.

[0086] Among them, the descriptions of the substrate, the buried insulating layer, the semiconductor layer, the channel region, the anode, the cathode contact region and the cathode refer to the relevant descriptions in the above embodiments, and will not be elaborated here. It should be noted that the preparation methods of the substrate, the buried insulating layer, the semiconductor layer, the channel region, the anode, the cathode contact region and the cathode can be traditional preparation methods, and are not further limited in this embodiment.

[0087] In some embodiments, step 104 further includes:

[0088] Step 201: Form a buffer region with a second conductivity type on the upper surface layer of the semiconductor layer, and the buffer region is spaced apart from the channel region.

[0089] Step 202: Form the cathode contact region on the upper surface layer of the buffer region.

[0090] Among them, the descriptions of the buffer region and the cathode contact region refer to the relevant descriptions in the above embodiments, and will not be elaborated here. It should be noted that the preparation methods of the buffer region and the cathode contact region can be traditional preparation methods, and are not further limited in this embodiment.

[0091] In some embodiments, before step 105, the preparation method further includes:

[0092] Step 301: Form a planarization layer on the semiconductor layer, the channel region, the channel contact region, the anode contact region, and the cathode contact region. Etch contact holes in the regions corresponding to the channel contact region, the anode contact region, and the cathode contact region on the planarization layer, and fill the contact holes with a conductive medium to obtain a first conductive structure, a second conductive structure, and a third conductive structure.

[0093] Among them, the first conductive structure is connected between the anode contact region and the anode, and is used to realize the electrical connection between the anode contact region and the anode; the second conductive structure is connected between the channel contact region and the anode, and is used to realize the electrical connection between the channel contact region and the anode; the third conductive structure is connected between the cathode contact region and the cathode, and is used to realize the electrical connection between the cathode contact region and the cathode.

[0094] Among them, the descriptions of the first conductive structure, the second conductive structure, and the third conductive structure refer to the relevant descriptions in the above embodiments, and will not be elaborated here.

[0095] In some embodiments, the preparation method further includes:

[0096] Step 302: Form a field oxide layer position on the upper surface of the semiconductor layer. One side of the field oxide layer is adjacent to and in contact with the anode contact region, and the other side of the field oxide layer is adjacent to and in contact with the cathode contact region.

[0097] In some embodiments, the preparation method further includes Step 401 and / or Step 402.

[0098] Step 401: Form an anode field plate on the upper surface of the field oxide layer. The anode field plate is electrically connected to the anode.

[0099] Step 402: Form a cathode field plate on the upper surface of the field oxide layer. The cathode field plate is electrically connected to the cathode.

[0100] Among them, the descriptions of the anode field plate and the cathode field plate can be referred to the relevant descriptions in the above embodiments, and will not be elaborated here.

[0101] The preparation method provided in this embodiment includes providing a substrate, the substrate having a first conductivity type, and an insulating buried layer formed on the upper surface of the substrate; forming a semiconductor layer on the upper surface of the insulating buried layer, the semiconductor layer having a second conductivity type, and the second conductivity type being opposite to the first conductivity type; forming at least two spaced-apart channel regions on the upper surface layer of the semiconductor layer, the channel regions having the first conductivity type, forming a channel contact region with heavy doping of the first conductivity type on the upper surface layer of the channel regions, and forming an anode contact region with heavy doping of the second conductivity type between two adjacent channel regions; forming a cathode contact region with heavy doping of the second conductivity type in the upper surface layer of the semiconductor layer, the cathode contact region being spaced from the channel regions; forming an anode and a cathode above the substrate, the anode being electrically connected to the channel contact region and the anode contact region respectively, and the cathode being electrically connected to the cathode contact region. The semiconductor device is obtained by the preparation method. When the semiconductor device conducts forward, the channel contact region can reduce the conduction voltage drop, thereby reducing the overall power consumption of the device; when the semiconductor device ends conduction and changes from forward conduction to reverse, the reverse depletion layer formed by the semiconductor layer and each channel region can pinch off the conductive channel, completely blocking the path for minority holes generated by the channel contact region to inject into the device interior, making the entire anode in a closed state and reducing leakage; when the semiconductor device recovers reversely, the minority holes generated by the channel contact region can recombine with the electron holes in the anode contact region and disappear, greatly reducing the number of holes injected into the interior due to conductivity modulation in the anode in the traditional structure, making the peak current of the entire device during reverse recovery greatly reduced, and at the same time greatly reducing the reverse recovery time.

[0102] It should be understood that although Figure 5The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 5 At least some of the steps in Figure 5 may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0103] In the description of this specification, the descriptions referring to terms such as "in some embodiments" and "other embodiments" mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0104] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as within the scope described in this specification.

[0105] The above-described embodiments merely represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A semiconductor device, the semiconductor device being a high-voltage diode, characterized in that, Comprising: A substrate having a first conductivity type, on the upper surface of which an insulating buried layer is provided; A semiconductor layer located on the upper surface of the insulating buried layer, having a second conductivity type, which is opposite to the first conductivity type; At least two spaced-apart channel regions located on the upper surface layer of the semiconductor layer, having a first conductivity type. On the upper surface layer of the channel regions, a channel contact region heavily doped with the first conductivity type is provided. Between two adjacent channel regions, an anode contact region heavily doped with the second conductivity type is provided. The two sides of the anode contact region heavily doped with the second conductivity type are in contact with two adjacent channel regions. The distance between two adjacent channel regions is less than or equal to twice the junction depth of the channel regions. The distance between two adjacent channel regions satisfies the requirement that when the high-voltage diode changes from forward conduction to reverse cut-off, a depletion layer is formed between the semiconductor layer and the channel regions to pinch off the conductive channel formed by the anode contact region; An anode located above the substrate, electrically connected to the channel contact region and the anode contact region respectively; A cathode contact region heavily doped with the second conductivity type, located on the upper surface layer of the semiconductor layer and spaced from the channel regions; A cathode located above the semiconductor layer, electrically connected to the cathode contact region; the anode and the cathode are the anode and the cathode of the high-voltage diode respectively; the first conductivity type is P-type and the second conductivity type is N-type.

2. The semiconductor device according to claim 1, wherein, The anode contact regions and the channel contact regions are arranged alternately, and two adjacent anode contact regions and channel contact regions are in contact or spaced apart.

3. The semiconductor device according to claim 1, wherein The number of the channel regions is four. On the upper surface layer of each channel region, the channel contact region is provided, and between two adjacent channel regions, the anode contact region is provided.

4. The semiconductor device according to claim 1, wherein, Further comprising: A buffer region located in the upper surface layer of the semiconductor layer and spaced from the channel regions, having a second conductivity type; wherein, the cathode contact region is located on the upper surface layer of the buffer region.

5. The semiconductor device according to claim 4, wherein, The junction depth of the channel regions is less than or equal to the junction depth of the buffer region.

6. The semiconductor device according to claim 1, wherein Further comprising: A field oxide layer located on the upper surface of the semiconductor layer. One side of the field oxide layer is in contact with the channel contact region, and the other side of the field oxide layer is in contact with the cathode contact region.

7. The semiconductor device according to claim 6, wherein Further comprising: An anode field plate located on the upper surface of the field oxide layer, electrically connected to the anode; And / or, A cathode field plate located on the upper surface of the field oxide layer, electrically connected to the cathode.

8. A method for manufacturing a semiconductor device, the semiconductor device being a high-voltage diode, characterized in that, Comprising: Providing a substrate having a first conductivity type, on the upper surface of which an insulating buried layer is formed; Forming a semiconductor layer on the upper surface of the insulating buried layer, the semiconductor layer having a second conductivity type, which is opposite to the first conductivity type; Forming at least two spaced-apart channel regions on the upper surface layer of the semiconductor layer, the channel regions having a first conductivity type. Forming a channel contact region heavily doped with the first conductivity type on the upper surface layer of the channel regions, and forming an anode contact region heavily doped with the second conductivity type between two adjacent channel regions. The two sides of the anode contact region heavily doped with the second conductivity type are in contact with two adjacent channel regions; A cathode contact region that is heavily doped with a second conductivity type is formed in the upper surface layer of the semiconductor layer, and the cathode contact region is spaced apart from the channel region; An anode and a cathode are formed above the substrate. The anode is electrically connected to the channel contact region and the anode contact region respectively, and the cathode is electrically connected to the cathode contact region; the anode and the cathode are the anode and the cathode of the high-voltage diode respectively; the distance between two adjacent channel regions is less than or equal to twice the junction depth of the channel region, and the distance between two adjacent channel regions meets the requirement that when the high-voltage diode is reverse cutoff, a depletion layer is formed in the semiconductor layer and the channel region to pinch off the conductive channel formed by the anode contact region; the first conductivity type is P-type and the second conductivity type is N-type.

9. The preparation method according to claim 8, characterized in that, The step of forming a cathode contact region that is heavily doped with a second conductivity type in the upper surface layer of the semiconductor layer, with the cathode contact region spaced apart from the channel region, further includes: A buffer region of the second conductivity type is formed in the upper surface layer of the semiconductor layer, and the buffer region is spaced apart from the channel region; The cathode contact region is formed in the upper surface layer of the buffer region.

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