Ring oscillator circuit

Abstract

Various embodiments of the present disclosure relate to a ring oscillator circuit. In one embodiment, the ring oscillator circuit includes: a chain of cascaded coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node being configured to provide an oscillator supply voltage; a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node, the system supply voltage node being configured to provide a system supply voltage, the current generator circuit being configured to inject current into the oscillator supply voltage node; and a bias circuit including a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to an oscillator control signal indicating that the ring oscillator circuit is in an inactive operating state.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Italian Patent Application No. 102021000015647, filed on June 15, 2021, which is incorporated herein by reference. Technical Field

[0003] The present description relates to oscillator circuits, and in particular to ring oscillator circuits. Background Art

[0004] Ring oscillators are used in a wide range of electronic devices. For example, they can be used in digital circuits to generate internal clock reference signals (e.g., for state machines or central processing units (CPUs)). They can also be used in analog circuits to generate a timing basis (e.g., for switched capacitor filters, charge pump circuits, sample-and-hold circuits, etc.).

[0005] A current-starved ring oscillator is a conventional ring oscillator that includes a current limiter to control power consumption.

[0006] Advantages of a current-starved ring oscillator are high speed and / or low power consumption. Furthermore, considering a single (eg, fixed) oscillation frequency, temperature compensation can be implemented in a current-starved ring oscillator by appropriate scaling.

[0007] On the other hand, disadvantages of current-starved ring oscillators can include start / stop transients with uncontrolled frequency. Furthermore, conventional current-starved ring oscillators can be difficult to adjust (eg, compensate) over temperature for multiple oscillation frequencies.

[0008] Therefore, there is a need in the art to provide an improved current-starved ring oscillator that is easily tunable with temperature. In particular, it may be desirable to provide an improved current-starved ring oscillator that is easily tunable with temperature at different oscillation frequencies. Furthermore, it may be desirable to provide an improved current-starved ring oscillator that can provide fast start / stop operation (e.g., with reduced or almost non-existent start / stop transient phases). Summary of the Invention

[0009] Various embodiments provide ring oscillators. Various other embodiments provide improved current-starved ring oscillators.

[0010] In one or more embodiments, the ring oscillator may include a chain of inverter stages coupled in series between an oscillator supply voltage node and a reference voltage node. The oscillator supply voltage node may be configured to provide an oscillator supply voltage. The ring oscillator may include a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node, the system supply voltage node being configured to provide the system supply voltage. The current generator circuit may be configured to inject current into the oscillator supply voltage node. Each inverter stage may include a first low-side transistor and a second low-side transistor coupled in series between the reference voltage node and an output node of the corresponding inverter stage, and may include a first high-side transistor coupled between the oscillator supply voltage node and an output node of the corresponding inverter stage. The first low-side transistor and the first high-side transistor may have corresponding control terminals coupled to input nodes of the corresponding inverter stages to receive corresponding inverter control signals therefrom. The second low-side transistor may have a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage. The ring oscillator may further include a bias circuit comprising a first bias control transistor and a second bias control transistor coupled in series between a reference voltage node and an oscillator supply voltage node. The first bias control transistor may have a control terminal configured to receive an oscillator control signal indicating whether the ring oscillator circuit is in an active operating state or an inactive operating state, and the second bias control transistor may have a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage. The first bias control transistor may be configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal indicating that the ring oscillator circuit is in an inactive operating state.

[0011] Thus, one or more embodiments may facilitate temperature compensation of a ring oscillator and fast start / stop operation, resulting in reduced or almost non-existent start / stop transient phases.

[0012] In one or more embodiments, the conductivity of the first low-side transistor operated in the on-state may be higher than the conductivity of the corresponding second low-side transistor operated in the on-state.

[0013] In one or more embodiments, a conduction channel of the first low-side transistor may be shorter than a conduction channel of the corresponding second low-side transistor.

[0014] In one or more embodiments, each inverter stage may include a second high-side transistor coupled in series to the first high-side transistor between the oscillator supply voltage node and the output node of the corresponding inverter stage. The second high-side transistor may have a control terminal coupled to a reference voltage node.

[0015] In one or more embodiments, the second high-side transistor of the last inverter stage in the chain of cascade-coupled inverter stages may have a control terminal configured to receive the oscillator control signal.

[0016] In one or more embodiments, the conductivity of the first high-side transistor and / or the second high-side transistor operated in the on-state may be higher than the conductivity of the corresponding first low-side transistor operated in the on-state, and may be higher than the conductivity of the corresponding second low-side transistor operated in the on-state.

[0017] In one or more embodiments, a conduction channel of the first high-side transistor and / or the second high-side transistor may be shorter than a conduction channel of the corresponding first low-side transistor and may be shorter than a conduction channel of the corresponding second low-side transistor.

[0018] In one or more embodiments, a ring oscillator circuit may include an output control transistor coupled between an output node of the ring oscillator circuit and a reference voltage node. The output control transistor may have a control terminal configured to receive an oscillator control signal and may be configured to selectively couple the reference voltage node and the output node of the ring oscillator circuit in response to the oscillator control signal indicating that the ring oscillator circuit is in an inactive operating state.

[0019] In one or more embodiments, each inverter stage may include a plurality of second low-side transistors arranged in parallel. The second low-side transistors arranged in parallel may have different conductivity values ​​when operating in the on state. The second low-side transistors arranged in parallel may have corresponding control terminals that are selectively coupleable to the oscillator supply voltage node according to a corresponding frequency selection signal. The bias circuit may include a plurality of second bias control transistors arranged in parallel. The second bias control transistors arranged in parallel may have different conductivity values ​​when operating in the on state. The second bias control transistors arranged in parallel may have corresponding control terminals that are selectively coupleable to the oscillator supply voltage node according to a corresponding frequency selection signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings.

[0021] Figure 1 is an exemplary circuit diagram of a ring oscillator;

[0022] Figure 2 An exemplary circuit diagram of a portion of a ring oscillator;

[0023] Figure 3is an exemplary diagram of a possible temporal behavior of a signal in a balanced ring oscillator;

[0024] Figure 4 is an exemplary diagram of a possible temporal behavior of a signal in an unbalanced ring oscillator;

[0025] Figure 5 is an exemplary circuit diagram of a ring oscillator according to one or more embodiments of the present description;

[0026] Figure 6 is an exemplary circuit diagram of a portion of a ring oscillator according to one or more embodiments of the present description;

[0027] Figure 7 is an exemplary circuit diagram of a low-side portion of an inverter stage of a ring oscillator during a discharge phase of an oscillation cycle according to one or more embodiments of the present description;

[0028] Figure 8 is an exemplary circuit diagram of an inverter stage of a ring oscillator according to one or more embodiments of the present description; and

[0029] Figure 9 is an exemplary circuit diagram of a bias circuit for a ring oscillator according to one or more embodiments of the present description. DETAILED DESCRIPTION

[0030] In the following description, one or more specific details are provided to provide a deeper understanding of the examples of the embodiments of the present description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, well-known structures, materials, or operations are not shown or described in detail so as not to obscure certain aspects of the embodiments.

[0031] References to "an embodiment" or "one embodiment" in the context of this description are intended to indicate that a particular configuration, structure, or characteristic described with respect to that embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may appear in one or more points of this description do not necessarily refer to one and the same embodiment. Furthermore, in one or more embodiments, the particular configurations, structures, or characteristics may be combined in any appropriate manner.

[0032] The headings / reference numbers used herein are provided for convenience only and do not limit the scope of protection or the scope of the embodiments.

[0033] Throughout the drawings appended hereto, similar parts or elements are denoted by similar reference numerals / numbers unless the context indicates otherwise, and the corresponding descriptions will not be repeated for the sake of brevity.

[0034] As an introduction to the detailed description of the exemplary embodiments, reference may first be made to Figure 1 , Figure 1 is an exemplary circuit diagram of a current-starved ring oscillator 10 (also referred to simply as a ring oscillator in this description, for simplicity only).

[0035] The ring oscillator 10 comprises a chain of inverter stages 12, e.g. Figure 1 The five inverter stages 12 shown in FIG. A , 12 B , 12 C , 12 D , 12 E Each inverter stage 12 includes an input node and an output node, wherein the output node of each inverter stage in the chain is coupled to the input node of the subsequent inverter stage in the chain. The last inverter stage of the chain (e.g., 12 E ) is coupled to the output node of the first inverter stage of the chain (e.g. 12 A ) input node. The input (clock) signal CK received at the input node of the inverter stage is designated herein as CK A , CK B , CK C , CK D , CK E .like Figure 1 As illustrated in FIG, each inverter stage is coupled between an oscillator supply voltage node 14 and a common reference voltage node 16. The oscillator supply voltage node 14 may provide a common oscillator supply voltage V RO_SUPPLY , and the reference voltage node 16 can provide a common reference voltage V GND (eg, 0 V). Each inverter stage 12 may include a corresponding n-channel MOS transistor MN (eg, MN A MN B MN C MN D MN E ), an n-channel MOS transistor MN having a source terminal coupled to the reference voltage node 16 and having a drain terminal coupled to the output node of the corresponding inverter stage, and may include a corresponding p-channel MOS transistor MP (e.g., MP A 、MP B 、MP C 、MP D 、MP E), p-channel MOS transistor MP has a source terminal coupled to oscillator supply voltage node 14 and a drain terminal coupled to the output node of the corresponding inverter stage. The gate terminals of n-channel MOS transistor MN and p-channel MOS transistor MP can be coupled to the input node of the corresponding inverter stage. All transistors MN can have their body terminals connected to reference voltage node 16, and all transistors MP can have their body terminals connected to oscillator supply voltage node 14.

[0036] Capacitor C RO It can be coupled between the oscillator supply voltage node 14 and the common reference voltage node 16. It should be understood by those skilled in the art that the capacitor C RO This can be the inherent capacitance at node 14 or an external capacitor added for the purpose of increasing the capacitance value at node 14 to improve the oscillator supply voltage V RO_SUPPLY In one or more embodiments, the capacitor C RO This can be an external capacitor whose capacitance adds up to the intrinsic capacitance.

[0037] The ring oscillator 10 may include a current generator 18 coupled between the oscillator supply voltage node 14 and another supply voltage node 20 (eg, a system supply voltage node) that provides, for example, a current higher than the oscillator supply voltage V RO_SUPPLY High system supply voltage V DD The current generator 18 can force the current I OSC Flowing into (for example, the current I OSC ) into the oscillator supply voltage node 14, thereby controlling (eg, limiting) the oscillator current I OSC The oscillation amplitude (for example, in the last inverter stage 12 E The maximum signal amplitude at the output node of ) is limited to the oscillator supply voltage V at node 14 RO_SUPPLY . Voltage level V RO_SUPPLY It depends on the current I OSC The value and scaling of the inverter stage 12.

[0038] In such Figure 1 In the ring oscillator 10 shown in FIG. 1 , the oscillation frequency depends on the voltage V at the node 14. RO_SUPPLY and the capacitive load at the output node of each inverter stage 12. The global oscillation period T OSC Equal to the propagation delay T of each inverter stage D n times (ie T OSC =n*T D), n is the number of linked inverter stages 12 (for example, in the case where the ring oscillator 10 illustrated herein includes 5 inverter stages, T OSC =5*T D ). In the simplified model, the propagation delay T of each inverter stage 12 is D Equal to the sum of the two components, that is, the rising edge time T RE and falling edge time T FE :T D =T RE +T FE .

[0039] In conventional current-starved ring oscillators, providing satisfactory temperature compensation may rely on finding the correct tuning between different variables, leading to an ambiguous design procedure. For example, given an oscillation frequency F OSC , minimum system supply voltage V DD,min (at node 20) and power consumption level as target specifications, available design parameters may include current I OSC The value of and / or buffer scaling (eg, scaling of inverter stage 12).

[0040] In addition, in a conventional current-starved ring oscillator, the oscillation frequency F OSC The (dynamic) tuning (e.g., to provide oscillations at multiple frequencies) can be dependent on making the current I OSC The value of oscillator current I OSC A single value is valid for .

[0041] Furthermore, the operation of a conventional current-starved ring oscillator may include a startup transient during which the oscillator operates at a frequency that does not correspond to the target frequency (initial frequency). In some applications, fast oscillator start / stop operation may be desired (e.g., for charge pump circuits, or to generate timing phases for read circuitry in memory, etc.). A stabilization period may be requested after a stop or at startup to restart oscillation. The oscillator may be started periodically (e.g., to refresh internal voltages, such as the oscillator supply voltage V RO_SUPPLY ), but an additional oscillator (e.g., a low-power oscillator) may be required.

[0042] Refer to the discussion below Figure 2 、 Figure 3 and Figure 4 , you can further understand Figure 1 The operation of the ring oscillator 10 is illustrated in FIG.

[0043] Figure 2 is an exemplary circuit diagram of a portion of the ring oscillator 10, particularly illustrating the inverter stage 12C , 12 D and the corresponding input signal CK C , intermediate signal CK D and output signal CK E .also, Figure 2 The figure shows the inverter stage 12 C and 12 D The capacitance C at the output node OSC,C and C OSC,D (e.g., inherent capacitance), which affects the propagation delay T of the inverter stage D It should be understood that Figure 2 Reference is made to a portion of the ring oscillator 10 by way of example, and similar operations may occur in other portions of the ring oscillator 10 .

[0044] Figure 3 According to the first example Figure 2 The signal CK in the ring oscillator 10 shown in FIG. C (dashed line), CK D (solid line) and CK E (dash-dotted line) is an exemplary diagram of a possible time behavior in which, in a first example, the p-channel MOS transistor MP and the n-channel MOS transistor MN in the inverter stage 12 are balanced (eg, they have similar conductivity in the on-state).

[0045] In each of the (e.g. 5) time slots T D =T RE +T FE During this period, the amount of current drawn from the oscillator supply voltage node 14 is equal to I OSC , as long as the current I OSC is forced to flow into node 14 by current generator 18. This condition provides an equilibrium point in the oscillator supply voltage node 14, the oscillator supply voltage V RO_SUPPLY The reference voltage (eg, 0V) at node 16 and the system supply voltage V DD Between (for example, 0V <V RO_SUPPLY <V DD ). In this case, the current driven by each p-channel MOS transistor MP can be calculated as I P =C OSC *V RO_SUPPLY / T RE .

[0046] In each "commutation interval" T D The average current drawn from the oscillator supply voltage node 14 during the period can therefore be calculated as I P *T RE / T D =IOSC .

[0047] Therefore, if the commutation interval T D remains unchanged, since the current I P As the rise time T RE decreases; therefore, the falling edge time T FE Increase.

[0048] Figure 4 According to the second example Figure 2 The signal CK in the ring oscillator 10 illustrated in FIG. C (dashed line), CK D (solid line) and CK E (dash-dotted line) is an exemplary diagram of a possible time behavior of the p-channel MOS transistor MP and the n-channel MOS transistor MN in the inverter stage 12 in the second example, which is unbalanced. In particular, Figure 4 is an example of a case where the p-channel MOS transistor MP is (much) faster than the n-channel MOS transistor MN.

[0049] exist Figure 4 In the example shown in the figure, the rising edge time T RE Can be equivalent to the (total) commutation interval T D This condition can be approximated as if at least one n-channel MOS transistor is always conducting (i.e., in the on-state) at any stage of the oscillation. Given the above approximation, the n-channel MOS transistor should be polarized to sink the current I during the discharge phase. N , according to the following equation, the current I N = equal to the current I forced into the oscillator supply voltage node 14 OSC :

[0050] If T RE < <T FE , then I N *T FE / T D =I OSC →I N ≈I OSC

[0051] Therefore, unbalanced scaling of the p-channel MOS transistors and the n-channel MOS transistors of the inverter stage 12 (e.g., the p-channel MOS transistors are much more conductive than the n-channel MOS transistors) may have one or more of the following effects:

[0052] -In V RO_SUPPLY >0, the n-channel MOS transistor absorbs a current equal to I OSC The constant current I N ;

[0053] - Due to the short rise time T RE , the n-channel MOS transistor has its corresponding falling edge time slot T FE is biased to the oscillator supply voltage V RO_SUPPLY (e.g., is constantly biased to V RO_SUPPLY ) a gate terminal;

[0054] -Oscillator supply voltage V RO_SUPPLY Should be equal to the forcing current I OSC The gate-source voltage V required by an n-channel MOS transistor (e.g., at the drain terminal) GS ;

[0055] - Due to the size of n-channel MOS transistors, the transistors are at their zero point with a current level I N ≈I OSC operation, so the oscillator supply voltage V at node 14 RO_SUPPLY Compensation can be obtained for temperature changes.

[0056] In the context of this description, the definition of “zero bias” is based on the recognition that for any n-channel MOS transistor, one can define the drain current (I) as a function of the transistor dimensions (e.g., width-to-length ratio W / L). D ) value, where the gate-source voltage V GS In this bias point, if the n-channel MOS transistor is operated in a saturated state, the threshold voltage (V TH ) and the overdrive voltage (V OD =V GS -V TH ) compensate each other to maintain a constant drain current.

[0057] Therefore, in one or more embodiments, the p-channel MOS transistor is (much) faster than the n-channel MOS transistor, and the n-channel MOS transistor is faster relative to the current I OSC is biased at the zero point of , which can cause the oscillator supply voltage V at node 14 to RO_SUPPLY is constant with respect to temperature changes (zero-point voltage of n-channel MOS transistor), so due to the constant oscillator supply voltage V according to the following equation RO_SUPPLY and a constant oscillator current I OSC , the oscillation will be constant with respect to temperature changes:

[0058]

[0059]

[0060] Thus, one or more embodiments may involve Figure 5 The current-starved ring oscillator 50 is illustrated in FIG.

[0061] The ring oscillator 50 comprises a chain of inverter stages 52, e.g. Figure 5 The five inverter stages 52 shown in FIG. A , 52 B , 52C, 52 D , 52 E Each inverter stage 52 includes an input node and an output node, wherein the output node of each inverter stage in the chain is coupled to the input node of the subsequent inverter stage in the chain. The last inverter stage in the chain (e.g., 52 E ) is coupled to the output node of the first inverter stage of the chain (e.g. 52 A ) input node. The input (clock) signal CK received at the input node of the inverter stage is designated herein as CK A , CK B , CK C , CK D , CK E .like Figure 5 As illustrated in FIG, each inverter stage is coupled between an oscillator supply voltage node 54 and a common reference voltage node 56. The oscillator supply voltage node 54 may provide a common oscillator supply voltage V RO_SUPPLY , and the reference voltage node 56 can provide a common reference voltage V GND (e.g., 0V).

[0062] Each inverter stage 52 may include two n-channel MOS transistors N arranged in series between a reference voltage node 56 and an output node of the inverter stage. L (For example, N LA 、N LB 、N LC 、N LD 、N LE ) and N F (For example, N FA 、N FB 、N FC 、N FD 、N FE ). For example, transistor N F may have its source terminal coupled to reference voltage node 56 and have its source terminal coupled to a corresponding transistor N L The source terminal of transistor N is the drain terminal of L may have their drain terminals coupled to the output nodes of the corresponding inverter stages. L and N Fmay have its body terminal connected to reference voltage node 56. Transistor N F The gate terminal of transistor N can be coupled to the input node of the corresponding inverter stage. L The gate terminal of the oscillator can be coupled to the oscillator supply voltage node 54 to receive the oscillator supply voltage V RO_SUPPLY .

[0063] Each inverter stage 52 may include a p-channel MOS transistor P F1 (For example, P F1A 、P F1B 、P F1C 、P F1D 、P F1E ), p-channel MOS transistor P F1 has a source terminal coupled to the oscillator supply voltage node 54 and has a drain terminal coupled to the output node of the inverter stage. All transistors P F1 may have its body terminal connected to the oscillator supply voltage node 54. Transistor P F1 The gate terminal may be coupled to the input node of a corresponding inverter stage.

[0064] Optionally, each inverter stage 52 may include a corresponding transistor P F1 Another p-channel MOS transistor P arranged in series F2 (For example, P F2A 、P F2B 、P F2C 、P F2D 、P F2E ). For example, transistor P F1 may have its source terminal coupled to the oscillator supply voltage node 54 and have its source terminal coupled to the corresponding transistor P F2 The source terminal of transistor P is the drain terminal of F2 may have their drain terminals coupled to the output nodes of the corresponding inverter stages. F2 may have its body terminal connected to the oscillator supply voltage node 54. Transistor P F2 The gate terminal of the MOSFET can be coupled to a reference voltage node 56 to receive a reference voltage V GND (eg 0 V). Optionally, the further transistor P of the last inverter stage of the inverter chain F2 (For example, Figure 5 In the example of transistor P F2E ) can be configured to receive a control signal StartP generated as discussed below.

[0065] In one or more embodiments, transistor N L and NF can have different sizes because they are designed to play different roles in the switching activity of the inverter stage 52. In particular, transistor N L The channel may have a width W N and length L L . Transistor N F The channels can have the same width W N and a different (e.g., shorter) length L S Therefore, the low-side current flow line of each inverter stage 52 may include two n-channel MOS transistors, wherein the first resistive transistor N L does not oscillate and has to be constantly biased at V RO_SUPPLY The gate terminal of the second high conductivity transistor N F Oscillates, as driven by the corresponding signal CK. The second transistor N F It can be designed to have a low load for oscillation, thereby promoting oscillation at high frequencies.

[0066] In one or more embodiments, transistor P F1 and P F2 can have the same size because they are designed to play a similar role in the switching activity of the inverter stage 52. In particular, transistor P F1 The channel may have a width W P and length L min . Transistor P F2 The channels can have the same width W P and the same length L min .

[0067] In one or more embodiments, the p-channel MOS transistor P F1 and P F2 can be designed to operate in the on-state than the n-channel MOS transistor N L and N F conductive, for example, by increasing the length L min Select the length L L and L S Thus, the ring oscillator 50 may be substantially unbalanced.

[0068] In such Figure 5 In one or more embodiments illustrated in FIG, the ring oscillator 50 may include a bias circuit 500. The bias circuit 500 may include a current generator 58 coupled between the oscillator supply voltage node 54 and another supply voltage node 60 (e.g., a system supply voltage node), the supply voltage node 60 providing, for example, a current higher than the oscillator supply voltage V RO_SUPPLY High system supply voltage VDD The current generator 58 can force the current I OSC Flowing into the oscillator supply voltage node 54 (eg, the current generator 58 can be a current I OSC Injection node 54).

[0069] The bias circuit 500 may include an input terminal 502 configured to receive a control signal StartOsc. The control signal StartOsc may be asserted (e.g., set to 1) when the ring oscillator is desired to generate an oscillating output voltage, and may be deasserted (e.g., set to 0) when the ring oscillator is not desired to generate an oscillating output voltage. The bias circuit 500 may include an inverter circuit 504 configured to receive the control signal StartOsc and generate an output signal StartP that substantially corresponds to an inverted copy of the control signal StartOsc. The bias circuit 500 may include two n-channel MOS transistors N arranged in series between a reference voltage node 56 and an oscillator supply voltage node 54. LZ and N FZ For example, transistor N FZ may have a source terminal coupled to reference voltage node 56 and may have a source terminal coupled to transistor N LZ The source terminal of transistor N is the drain terminal of LZ may have a drain terminal coupled to the oscillator supply voltage node 54. Transistor N LZ and N FZ may have its body terminal connected to reference voltage node 56. Transistor N FZ The gate terminal of transistor N can be coupled to the output of inverter circuit 504 to receive control signal StartP. LZ The gate terminal of the oscillator can be coupled to the oscillator supply voltage node 54 to receive the oscillator supply voltage V RO_SUPPLY . Transistor N LZ and N FZ can be essentially scaled to the transistor pair NL and NF in the inverter stage 52. In particular, transistor N LZ The channel may have a width W N and length L L . Transistor N FZ The channels can have the same width W N and different lengths L S .

[0070] The bias circuit 500 may include a capacitor C coupled between the oscillator supply voltage node 54 and the common reference voltage node 56. RO As mentioned above, the capacitor C ROThis can be the inherent capacitance at node 54 or an external capacitor added for the purpose of increasing the capacitance value at node 54 to improve the oscillator supply voltage V RO_SUPPLY In one or more embodiments, the capacitor C RO This can be an external capacitor whose capacitance adds up to the intrinsic capacitance.

[0071] In one or more embodiments, the ring oscillator 50 may further include an n-channel MOS transistor 62 having a gate disposed at an output node of the ring oscillator 50 (e.g., an output terminal of the last inverter stage, herein represented by the inverter stage 52). E 50) and a reference voltage node 56. For example, transistor 62 may have a source terminal coupled to reference voltage node 56 and may have a drain terminal coupled to the output node of ring oscillator 50. A body terminal of transistor 62 may be connected to reference voltage node 56. A gate terminal of transistor 62 may be coupled to the output node of inverter circuit 504 to receive control signal StartP.

[0072] refer to Figure 6 and Figure 7 , you can further understand Figure 5 The operation of the ring oscillator 50 is illustrated in FIG. Figure 6 An exemplary circuit diagram of a portion of a ring oscillator 50, specifically an inverter stage 52 B and 52 C An exemplary circuit diagram of . Figure 7 is the inverter stage 52 B An exemplary circuit diagram of an equivalent representation of the low-side portion of FIG. 1 during the discharge phase of the corresponding oscillation cycle.

[0073] like Figure 7 As illustrated in FIG, during the oscillation of the ring oscillator 50, at a certain inverter stage (eg, the second inverter stage 52 B , purely as an example) in the low-side portion of the transistor N L and N F The gate terminal of the inverter is biased at V during the corresponding discharge phase (i.e., when the high-side portion of the inverter is in the non-conducting state and the low-side portion of the inverter is in the conducting state) RO_SUPPLY , because transistor N L is constantly biased at V RO_SUPPLY , and transistor N F Receive at V GND (e.g., 0V) and V RO_SUPPLY The driving signal CK switches between transistors N L and N FThe polarization of the series arrangement is equivalent to a pair of polarizers with length L EQ =L L +L S The equivalent series transistor of I OSC The equivalent transistor can be biased at I OSC The zero point below is biased, thereby providing the oscillator supply voltage V at the zero point. RO_SUPPLY temperature compensation.

[0074] In one or more embodiments, transistor N is driven by signal StartP. FZ The oscillator supply voltage V at node 54 can be turned off during oscillation of the ring oscillator 50 (e.g., when StartOsc=1 and StartP=0) and turned on when the ring oscillator 50 is inactive (e.g., when StartOsc=0 and StartP=1) to maintain the oscillator supply voltage V at node 54. RO_SUPPLY By making the oscillator supply voltage V RO_SUPPLY Biased very close to the oscillation operating voltage, the oscillation can quickly reach the nominal value upon activation of the ring oscillator 50. This can help reduce or even avoid transient (out-of-specification) phases when the ring oscillator 50 starts.

[0075] In one or more embodiments, a high oscillation frequency (eg, approximately 900 MHz) can be achieved by employing a series arrangement of two n-channel MOS transistors in the low-side portion of the inverter stage 52. In particular, a long channel (N L , with length L L ) MOS transistor does not switch and has to be constantly biased at V RO_SUPPLY The gate terminal has a short channel (N F , with length L S ) is switched under the control of the corresponding control signal CK, thereby providing a low load for oscillation at high frequency.

[0076] Furthermore, unbalanced scaling of the high-side p-channel MOS transistor and the low-side n-channel MOS transistor (eg, the p-channel transistor is more conductive than the n-channel transistor) may result in a fast rising edge and a slow falling edge of the signal CK.

[0077] Therefore, one or more embodiments can provide a clear design procedure for the design of the ring oscillator 50. In particular, the design procedure can set certain parameters of the ring oscillator 50 to target parameters. The target parameters can include the minimum system supply voltage V DD,min , oscillation frequency F OSC and / or power consumption level (e.g., oscillator current I OSCAfter setting the above parameters, the design procedure may include selecting the size W / L (width to length ratio) of the equivalent n-channel MOS transistor for the low-side portion of the inverter stage so as to obtain the minimum system supply voltage V at the zero bias point of the equivalent n-channel MOS transistor. DD,min Compatible oscillator supply voltage V RO_SUPPLY For example, V RO_SUPPLY can be chosen to be approximately equal to V DD,min -0.1V to maintain the current generator 58 in saturation. The width-to-length ratio W / L of the equivalent n-channel MOS transistor can be selected so that the current I OSC In the case of an equivalent n-channel MOS transistor, V RO_SUPPLY is the gate voltage at zero. In this phase, the switching transistor N F Length L S can be chosen to be short enough to achieve the capacitance target (C OSC ) to meet the desired oscillation frequency F OSC . Non-switching transistor N L Length L L can be chosen to be equal to the difference in length, L L =LL S As indicated in the following equation, an n-channel MOS transistor N can be selected F The capacitance is required to meet the desired oscillation frequency F OSC :

[0078]

[0079] In such Figure 8 In one or more of the embodiments illustrated in , ring oscillator 50 may be configured to provide operation at multiple (eg, selectable) oscillation frequencies while maintaining temperature compensation at any such frequency.

[0080] In particular, Figure 8 is an exemplary circuit diagram of a single inverter stage 52' that may be provided in the ring oscillator 50. It should be understood by those skilled in the art that the circuit diagram is provided for ease of illustration only. Figure 8 A single inverter stage 52' is illustrated in FIG, and the ring oscillator 50 may include a chain of inverter stages 52', as previously described with reference to FIG. Figure 5 In one or more embodiments, the low-side portion of each inverter stage 52 ′ may include two (or more) resistive n-channel MOS transistors N arranged in parallel. L1 、N L2 , instead of a single n-channel MOS transistor N L . Transistor N L1 and N L2 Can have the same width WN and different lengths L L1 and L L2 .

[0081] Transistor N L1 、N L2 The gate terminal of each transistor in is configured to receive a voltage V via a corresponding selectively activatable buffer (eg, inverter) circuit 801, 802. RO_SUPPLY For example, transistor N L1 The gate terminal of transistor N can be coupled to the output node of inverter 801 arranged between nodes 54 and 56, and the gate terminal can receive control signal F1 at the corresponding input node 801. L2 The gate terminal of can be coupled to the output node of an inverter 802 arranged between the node 54 and the node 56, which gate terminal can receive the control signal F2 at the corresponding input node 802. Thus, if F1=1 and F2=0, the inverter stage 52' is switched via the transistor N F and N L2 The series arrangement operates, and if F1=0 and F2=1, the inverting stage 52' is connected to the transistor N F and N L1 Since transistor N L1 、N L2 Available in different lengths and designed for different currents I OSC The value has a zero bias point, so I OSC2 ≠I OSC1 And F OSC2 ≠F OSC1 .

[0082] In the reference Figure 8 In one or more of the illustrated embodiments, the bias circuit may be modified accordingly to provide two (or more) resistive n-channel MOS transistors N arranged in parallel. LZ1 、N LZ2 To replace a single n-channel MOS transistor N LZ . Figure 9 FIG. 5 is an exemplary circuit diagram of the modified bias circuit 500 ′. Transistor N LZ1 and N LZ2 They can have the same width WN and different lengths L L1 and L L2 .

[0083] Transistor N LZ1 、N LZ2 The gate terminal of each transistor in is configured to receive a voltage V via a corresponding selectively activatable buffer (or inverter) circuit 801, 802. RO_SUPPLYFor example, transistor N LZ1 The gate terminal of transistor N can be coupled to the output node of inverter 801, and LZ2 The gate terminal of may be coupled to the output node of inverter 802 .

[0084] Those skilled in the art will appreciate that signal F1 or signal F2 can exhibit a high logic value (e.g., 1) depending on the selected oscillation frequency. In one or more embodiments, two or more resistive n-channel MOS transistors can be provided in parallel to provide two or more selectable oscillation frequencies. Additionally or alternatively, the oscillation frequency can be selected by operating a combination of such MOS transistors (e.g., depending on a combination of logic values ​​of control signals F1, F2, ...).

[0085] Thus, one or more embodiments may provide one or more of the following advantages:

[0086] - Clear design method for the oscillation frequency F OSC , power consumption and minimum system supply voltage V DD,min Achieving a good balance between

[0087] - Temperature compensation achieved by zero-biasing the low-side n-channel transistor;

[0088] - the possibility to tune the oscillator circuit to more than one frequency while maintaining temperature compensation; and

[0089] - Fast start / stop operation of the oscillator circuit without the need for additional circuit devices (e.g. without the need for an additional oscillator), since the oscillation frequency can be kept below zero when the oscillator starts, thus avoiding the risk of out-of-specification frequency of logic blocks receiving output signals from the oscillator circuit.

[0090] The details and embodiments may vary, even significantly, with respect to what has been described merely by way of example, without prejudice to the underlying principles and without departing from the scope of protection.

[0091] The scope of protection is determined by the appended claims.

[0092] Although the present invention has been described with reference to illustrative embodiments, this description is not intended to be interpreted in a limiting sense. Various modifications and combinations of the illustrative embodiments and other embodiments of the present invention will become apparent to those skilled in the art by reference to the description. Therefore, the appended claims are intended to cover any such modifications or embodiments.

Claims

1. A ring oscillator circuit, comprising: a chain of cascade-coupled inverter stages coupled between an oscillator supply voltage node and a reference voltage node, the oscillator supply voltage node being configured to provide an oscillator supply voltage; a current generator circuit coupled between the oscillator supply voltage node and a system supply voltage node, the system supply voltage node being configured to provide a system supply voltage, the current generator circuit being configured to inject current into the oscillator supply voltage node, wherein each inverter stage comprises a first low-side transistor and a second low-side transistor coupled in series between the reference voltage node and the output node of the corresponding inverter stage, and comprises a first high-side transistor coupled between the oscillator supply voltage node and the output node of the corresponding inverter stage, wherein the first low-side transistor and the first high-side transistor of each inverter stage have respective control terminals coupled to an input node of the respective inverter stage to receive a respective inverter control signal therefrom, and wherein the second low-side transistor of each inverter stage has a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage; as well as a bias circuit comprising a first bias control transistor and a second bias control transistor coupled in series between the reference voltage node and the oscillator supply voltage node, wherein the first bias control transistor has a control terminal configured to receive an oscillator control signal, the oscillator control signal indicating whether the ring oscillator circuit is in an active operating state or an inactive operating state, wherein the second bias control transistor has a control terminal coupled to the oscillator supply voltage node to receive the oscillator supply voltage, and The first bias control transistor is configured to selectively couple the reference voltage node and the oscillator supply voltage node in response to the oscillator control signal indicating that the ring oscillator circuit is in an inactive operating state. 2 . The ring oscillator circuit of claim 1 , wherein the conductivity of the first low-side transistor when operating in a conductive state is higher than the conductivity of the corresponding second low-side transistor when operating in a conductive state. 3 . The ring oscillator circuit of claim 1 , wherein a conduction channel of the first low-side transistor is shorter than a conduction channel of the corresponding second low-side transistor.

4. The ring oscillator circuit according to claim 1, wherein each inverter stage comprises a second high-side transistor coupled in series to the first high-side transistor between the oscillator supply voltage node and the output node of the corresponding inverter stage, and The second high-side transistor has a control terminal coupled to the reference voltage node. 5 . The ring oscillator circuit of claim 4 , wherein the second high-side transistor of the last inverter stage in the chain of cascade-coupled inverter stages has a control terminal configured to receive the oscillator control signal.

6. The ring oscillator circuit of claim 4 , wherein the conductivity of the first high-side transistor when operating in a conductive state is higher than the conductivity of the corresponding first low-side transistor when operating in a conductive state, and higher than the conductivity of the corresponding second low-side transistor when operating in a conductive state.

7. The ring oscillator circuit of claim 4 , wherein the conductivity of the second high-side transistor when operating in a conductive state is higher than the conductivity of the corresponding first low-side transistor when operating in a conductive state, and higher than the conductivity of the corresponding second low-side transistor when operating in a conductive state.

8. The ring oscillator circuit of claim 4 , wherein the conductivity of the first high-side transistor and the second high-side transistor when operated in a conductive state is higher than the conductivity of the corresponding first low-side transistor when operated in a conductive state, and is higher than the conductivity of the corresponding second low-side transistor when operated in a conductive state. 9 . The ring oscillator circuit of claim 4 , wherein a conduction channel of the first high-side transistor is shorter than a conduction channel of the corresponding first low-side transistor and shorter than a conduction channel of the corresponding second low-side transistor. 10 . The ring oscillator circuit of claim 4 , wherein a conduction channel of the second high-side transistor is shorter than a conduction channel of the corresponding first low-side transistor and shorter than a conduction channel of the corresponding second low-side transistor. 11 . The ring oscillator circuit of claim 4 , wherein the conduction channels of the first high-side transistor and the second high-side transistor are shorter than the conduction channel of the corresponding first low-side transistor and shorter than the conduction channel of the corresponding second low-side transistor. 12 . The ring oscillator circuit of claim 1 , further comprising an output control transistor coupled between an output node of the ring oscillator circuit and the reference voltage node.

13. The ring oscillator circuit according to claim 12, wherein the output control transistor has a control terminal configured to receive the oscillator control signal, and The output control transistor is configured to selectively couple the reference voltage node and the output node of the ring oscillator circuit in response to the oscillator control signal indicating that the ring oscillator circuit is in an inactive operating state.

14. The ring oscillator circuit of claim 1 , wherein each inverter stage comprises a plurality of second low-side transistors arranged in parallel, wherein the second low-side transistors arranged in parallel have different conductivity values ​​when operating in a conducting state, and wherein the second low-side transistors arranged in parallel have respective control terminals that are selectively coupleable to the oscillator supply voltage node in accordance with respective frequency select signals.

15. The ring oscillator circuit of claim 14 , wherein the bias circuit comprises a plurality of second bias control transistors arranged in parallel, wherein the second bias control transistors arranged in parallel have different conductivity values ​​when operating in a conductive state, and wherein the second bias control transistors arranged in parallel have respective control terminals that are selectively coupleable to the oscillator supply voltage node in accordance with the respective frequency selection signal.

16. The ring oscillator circuit of claim 1 , wherein the bias circuit comprises a plurality of second bias control transistors arranged in parallel, wherein the second bias control transistors arranged in parallel have different conductivity values ​​when operating in a conductive state, and wherein the second bias control transistors arranged in parallel have respective control terminals selectively coupleable to the oscillator supply voltage node in accordance with the respective frequency select signal.

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