An all-digital phase-locked loop architecture based on a phase discrimination algorithm

Abstract

The present invention proposes an all-digital phase-locked loop architecture based on a phase discrimination algorithm, which includes an interpolation-type automatic frequency calibration Ip-AFC module, a frequency calibration loop DFTFAL module based on discrete Fourier transform, a digital loop filter DLF, a numerically controlled oscillator DCO module, a programmable divider PGD, and an interpolator DPI. This architecture obtains a pre-tuning word corresponding to the phase-locked loop frequency control word through an automatic frequency calibration module based on an interpolation algorithm, enabling the phase-locked loop to quickly lock. By embedding an interpolation-type frequency prediction loop, the output frequency of the numerically controlled oscillator is compared with the reference frequency to obtain a frequency difference, thereby obtaining a corresponding calibration oscillation tuning control word, making the phase-locked loop lock more accurately and reducing loop noise.

Description

Technical Field

[0001] The present invention relates to integrated circuit design, and particularly to the overall structural design combining a fully digital phase-locked loop and an algorithm. Background Art

[0002] The fully digital phase-locked loop has received increasing attention due to its low power consumption and small area. However, in the design of the fully digital phase-locked loop, the time-to-digital converter is the most complex and power-consuming part. The time-to-digital converter generally converts the time / phase signal into a digital signal and performs frequency discrimination and phase discrimination in the fully digital phase-locked loop. Therefore, the present invention intends to adopt a loop architecture including a new phase discrimination algorithm, which on the one hand provides an oscillator control word to accelerate the locking time, and on the other hand provides an inhibition algorithm for the locked loop.

[0003] In the paper "Running DFT-Based PLL Algorithm for Frequency, Phase, and Amplitude Tracking in Aircraft Electrical Systems" by F. Cupertino, et al. (Reference 1), a phase-locked loop (PLL) structure based on the discrete Fourier transform (DFT) algorithm is proposed. A phase discrimination formula for calculating the frequency difference after frequency prediction through the discrete Fourier transform is proposed in the paper. The obtained frequency difference is then passed through a PI filter to obtain the oscillator control word, so as to stabilize the frequency output. This method can enable the oscillator output to be detected by the loop in time and the control word to be changed accordingly when the oscillator output changes due to external interference, so as to stabilize the loop output frequency. The PLL combined with the DFT algorithm proposed in the paper can be changed in real time and applied to n sample vectors of the signal. The structure mentioned in the paper has 3 phase signals as inputs, but is converted into 2 input signals through a 3-to-2 phase converter and then input into the formula for processing. However, the application background of this paper is a three-phase power system, and the output frequency is 360 - 900 Hz, with the output frequency being too low.

[0004] In the paper "An Ultra-Low-Power 2.4GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking" (Reference 2) by M. Riaz, et al., a structure of all-digital phase-locked loop without time-to-digital converter (TDC) is proposed. In the paper, a continuous frequency tracking loop is used to replace the time-to-digital converter, which can reduce power consumption and also reduce the influence of frequency offset after the loop is locked. The continuous frequency tracking loop in the paper uses a binary search algorithm to find the oscillator target tuning word. The all-digital phase-locked loop in the paper provides a tuning control word for the numerically controlled oscillator through the continuous frequency tracking loop to bring the output frequency to the target center frequency. This loop operates at the reference frequency, and the output frequency is fed back to the numerically controlled oscillator clock counter through a programmable frequency divider. The numerically controlled oscillator clock counter sends the output back to the continuous frequency tracking loop to compare the target value at the channel frequency. Once the frequency is locked to the target frequency, the frequency-locked loop stops working and enables the injection-locked controller. The injection-locked controller tunes the phase of the numerically controlled oscillator output by periodically injecting reference frequency pulses into the loop into the numerically controlled oscillator. This paper uses the designed frequency tracking loop, eliminating the use of the time-to-digital converter and reducing the power consumption of the loop. However, the binary search method is still used in the frequency tracking loop, and the locking speed of the frequency is not very ideal.

[0005] In the paper "Moving-Window DFT Based Frequency-Locked Loop for FM Demodulation" (Reference 3) by K. Milan, et al., a frequency-locked loop (FLL) based on moving-window discrete Fourier transform (MWDFT) is proposed, which is used to extract signal information from sinusoidal frequency modulation signals, track the frequency modulation carrier, and adaptively correct the fluctuations of the input frequency. In the paper, the on-chip 14-bit analog-to-digital converter (ADC) on the FPGA is used for signal sampling, and frequency prediction and calibration are performed through moving-window discrete Fourier transform (MWDFT). The sampling frequency range is 0 - 10 kHz. Summary of the Invention

[0006] Technical Problem: The purpose of the present invention is to provide an all-digital phase-locked loop architecture based on a phase discrimination algorithm, applying the differential discrete Fourier transform algorithm in the all-digital phase-locked loop. On the one hand, it includes the functions of phase discrimination and calculating the oscillator tuning control word to replace the digital time converter and accelerate the locking speed. On the other hand, it detects the fluctuations of the output frequency of the numerically controlled oscillator affected by process voltage temperature, etc., to reduce loop noise.

[0007] Technical solution: The all-digital phase-locked loop architecture based on the phase discrimination algorithm of the present invention includes: an interpolation type automatic frequency calibration Ip-AFC module, a frequency calibration loop DFTFAL module based on the discrete Fourier transform, a digital loop filter DLF, a numerically controlled oscillator DCO module, a programmable frequency divider PGD, and an interpolator DPI;

[0008] The interpolation type automatic frequency calibration Ip-AFC module pre-tunes the output frequency of the numerically controlled oscillator DCO module and inputs a predicted frequency control word into the numerically controlled oscillator DCO module;

[0009] The frequency calibration loop DFTFAL module based on the discrete Fourier transform performs real-time detection on the output frequency of the numerically controlled oscillator DCO module, filters it through the digital loop filter DLF, then inputs the calibration oscillator control word into the numerically controlled oscillator DCO module for frequency calibration; the programmable frequency divider PGD sets different frequency division ratios according to the required frequency, and then feeds back the frequency-divided output frequency of the numerically controlled oscillator DCO module to the frequency calibration loop DFTFAL based on the discrete Fourier transform.

[0010] Among them,

[0011] For the interpolation type automatic frequency calibration Ip-AFC module, the relationship between the phase-locked loop frequency control word and the output frequency is obtained according to the interpolation algorithm;

[0012]

[0013] where k i and b i are parameter values of the linear relationship in different situations; FCW is the phase-locked loop frequency control word, i is the number of tuning cycles, and then the corresponding oscillator frequency pre-tuning control word OTW p is obtained according to the required frequency. The obtained pre-tuning word is input into the numerically controlled oscillator, and an oscillator output near the target frequency can be obtained; here, an interpolator DPI inputs different interpolations to the comparison calculation module embedded in the interpolation type automatic frequency calibration Ip-AFC module according to the interpolation algorithm, and several groups of data can be obtained. According to the obtained data, the approximate relationship between the predicted phase-locked loop control word and the output frequency is fitted according to the linear relationship shown in formula (1). An accurate relationship can be fitted by obtaining 5 groups of data.

[0014] For the accurately fitted relational expression, first, the minimum control word (000) is input into the frequency pre-calculation module FCM. The numerically controlled oscillator DCO module outputs the minimum oscillation frequency according to the input control word. The frequency is returned to the frequency pre-calculation module FCM through the programmable frequency divider with the default division ratio set to 1, and this set of data is recorded. Then, the maximum control word (111) is input into the frequency pre-calculation module FCM. The numerically controlled oscillator DCO module outputs the maximum oscillation frequency according to the input control word. The frequency is returned to the frequency pre-calculation module FCM through the programmable frequency divider with the default division ratio set to 1, and this set of data is recorded again. According to the two sets of data obtained, the interpolator DPI inputs 3 appropriate phase-locked loop control words into the frequency pre-calculation module FCM. Finally, the 5 sets of data recorded are used in the comparison calculation module to obtain a suitable fitting curve through the interpolation algorithm.

[0015] The approximately relationship between the predicted phase-locked loop control word obtained by fitting and the output frequency is obtained, and the output frequency corresponding to the input phase-locked loop control word is obtained. Based on this output frequency, the oscillator output frequency tuning word actually required is obtained, and this tuning word is input into the numerically controlled oscillator to complete the pre-tuning of the output frequency.

[0016] For the frequency calibration loop DFTFAL module based on the discrete Fourier transform, according to the interpolated discrete Fourier transform IpDFT algorithm, the oscillator output obtained is frequency-estimated. According to the 5-bit DFT discrete points, the oscillator frequency output is calculated, and the discrete points are substituted into the formula:

[0017]

[0018] where X1 and X2 are the amplitudes of the signals before and after the jump respectively, ω0 is the signal frequency, are the phases of the signals before and after the jump respectively, is the Fourier transform parameter, P is the jump point, n is the current sequence length, L is the total sequence length, k is the current sequence number, and N is the sequence length corresponding to the Fourier transform;

[0019] And an inverse operation is performed to obtain the frequency estimation value as:

[0020]

[0021] where, is the frequency value estimated by the algorithm, is the intermediate value of the derivation;

[0022] Then, this frequency estimation value is compared and calibrated with the reference frequency to obtain the oscillator calibration tuning word OTW a .

[0023] Oscillator output frequency

[0024] f DCO = OTW p ·K p + OTW a ·K a (4)

[0025] Where OTW p and OTW a are the pre - tuning control word and the calibration tuning word of the numerically controlled oscillator respectively, and K p and K a are the pre - tuning gain and the calibration tuning gain respectively. The pre - tuning word quickly locks the loop frequency near the target frequency, and the calibration tuning word calibrates the output frequency with the reference frequency. The sum of the two gives the accurate target frequency.

[0026] Advantageous effects: Compared with the prior art, the present invention has the following advantageous effects:

[0027] 1) The present invention adopts the interpolation - type discrete Fourier transform (IpDFT) algorithm. This algorithm is more accurate than the discrete Fourier transform (DFT) for frequency prediction and can more timely sense the changes in the amplitude, phase, and frequency of the output signal, resulting in a greater improvement in loop noise suppression.

[0028] 2) The present invention is applied to a higher - frequency phase - locked loop system, and the output frequency is in the range of 7 GHz - 14 GHz, which can be applied in the field of wireless communication.

[0029] 3) The present invention is an all - digital phase - locked loop architecture, which can be better combined with and designed by algorithms. Moreover, the proposed new phase - discrimination structure avoids the use of time - to - digital converters, reducing the power consumption of the all - digital phase - locked loop. Description of the drawings

[0030] Figure 1 is a simplified overall architecture diagram of the proposed all - digital phase - locked loop (ADPLL),

[0031] Figure 2 is Figure 1 the internal architecture of Ip - AFC in

[0032] Figure 3 [[ID=5)]]is the operation flowchart of Ip - AFC,

[0033] Figure 4 is Figure 1 the internal architecture of DFTFAL in

[0034] Figure 5 is the operation flowchart of DFTFAL,

[0035] Figure 6 is the overall block diagram of the proposed all - digital phase - locked loop (ADPLL),

[0036] The figure includes: interpolation type automatic frequency calibration IP-AFC, DFT frequency calibration loop DFTFAL, digital low-pass filter DLF, digital controlled oscillator DCO, programmable frequency divider PGD,

[0037] Phase-locked loop frequency control word FCW, oscillator pre-tuning control word OTW p , oscillator calibration control word OTW a , reference frequency f ref 、DCO output frequency f DCO , the output frequency after frequency division f DCO-N ,

[0038] High-speed analog-to-digital converter ADC, DFT calculation module DFTCM, counter CNT, oscillation tuning word calculation module OTWCM, predicted frequency sequence f e (n), oscillator control word sequence OTW n , frequency difference Δf,

[0039] Frequency pre-calculation module FCM, comparison calculation module CCM, interpolator DPI, DETAILED DESCRIPTION

[0040] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0041] The all-digital phase-locked loop architecture of the present invention is as follows Figure 1 As shown, it includes an interpolation-type automatic frequency calibration loop, a DFT frequency prediction loop, a digital low-pass filter, a digitally controlled oscillator, and a programmable divider: the interpolation-type automatic frequency calibration loop is used to generate the oscillator frequency pre-tuning word, the DFT frequency prediction loop calibrates the output frequency of the digitally controlled oscillator, the digital low-pass filter filters out the redundant high-frequency components, and the digitally controlled oscillator outputs the required frequency according to the tuning control word provided previously. The programmable divider can set different division ratios according to different output frequencies to divide the oscillator output frequency and send it back to the DFT frequency prediction loop for comparison, and adjust the tuning control word accordingly to make the loop more accurately locked to the target frequency.

[0042] The DCO tuning frequency can be obtained from the following formula:

[0043] f DCO =OTW p ·K p +OTW a ·K a (1)

[0044] OTW p , OTW a are the pre-tuning control word and calibration tuning word of the digital controlled oscillator, Kp , K a are the pre-tuning gain and the calibration tuning gain respectively, and these gains can be derived from the loop model of the module.

[0045] First, the working mode of the Ip-AFC pre-tuning word generation module is introduced. Its schematic diagram is as shown in Figure 2 , and the working flow chart is as shown in Figure 3 . To obtain the relationship between the PLL frequency control word and the output frequency, first, the minimum control word and the maximum control word are respectively input into the loop to obtain the output frequencies of the two numerically controlled oscillators. At this time, the frequency division ratio is the default value of 1. Then, according to the interpolation algorithm, appropriate values are inserted into the controller to obtain the output of the new numerically controlled oscillator. According to the existing data, a set of linear relationships can be obtained:

[0046]

[0047] where k i and b i are the parameter values of the linear relationship in different situations, and the parameter values are recalculated before each tuning to eliminate the errors caused by environmental changes. According to the above relationships, the frequency corresponding to the input PLL control word can be obtained, and thus the oscillator pre-tuning word OTW p can be obtained. By inputting the pre-tuning word OTW p into the numerically controlled oscillator, an oscillator output frequency closer to the target frequency can be obtained. Using this interpolation algorithm for frequency pre-tuning is faster than the binary search method, and the relationship is recalculated every time a different frequency is changed. Therefore, the errors caused by environmental factor fluctuations can be eliminated, and the pre-tuning is more accurate.

[0048] Next, the working mechanism of the DFT frequency calibration loop DFTFAL is introduced. Its schematic diagram is as shown in Figure 4 , and the flow chart is as shown in Figure 5 . After the pre-tuning control word is input and the oscillator outputs the pre-tuned frequency, the DFT frequency calibration loop enters the working state. The output frequency f DCO-N of the numerically controlled oscillator is first sampled by a high-speed ADC, and the adjacent 5-bit DFT values are taken and substituted into the frequency estimation algorithm. The frequency estimation algorithm used in the present invention is an algorithm based on IpDFT. Since the oscillator output is a sine signal, there is the following expression:

[0049]

[0050] P is the point where the frequency jumps due to environmental factors. Then, after Fourier transform, the following can be obtained:

[0051]

[0052] Among them For the convenience of derivation, we set the parameters From this, we can obtain:

[0053]

[0054] Then set the parameter to b = cos(ω0), and the following relationship can be obtained:

[0055]

[0056] Substitute the 5-bit DFT value into the formula:

[0057] S k = W k η(7)

[0058] Among them η = [a1, a2, a3, a4, b], S(k i ),(i = 1, 2, 3, 4, 5) is the obtained 5-bit DFT value.

[0059] From this, we can obtain That is, the estimated value of the output frequency is obtained.

[0060] Then compare and calibrate the obtained estimated value of the output frequency with the result sampled by the reference frequency to obtain the frequency difference, and then calculate the oscillator calibration tuning control word OTW according to the frequency difference a .

[0061] The DFT frequency calibration loop keeps calibrating after pre-tuning, so that the calibration tuning word can be updated in real time. That is, the final numerically controlled oscillator frequency output of the loop is:

[0062] f DCO = OTW p ·K p + OTW a ·K a (8)

[0063] Because this loop also detects the frequency change when environmental variables such as voltage and temperature fluctuate, it can reduce the frequency error caused by the change of environmental parameters, and the obtained output frequency is more accurate.

[0064] The all-digital phase-locked loop based on the novel phase discrimination algorithm first quickly locks the output frequency of the loop through the interpolation-type automatic frequency calibration loop. Since only the output frequency is predicted and the numerically controlled oscillator outputs near the target frequency, this process omits the phase discrimination part such as the time-to-digital converter. After locking near the target frequency, the DFT frequency calibration loop is enabled to work. This loop estimates the actual output frequency of the oscillator through the IpDFT algorithm by means of an algorithm. This algorithm can accurately estimate the output frequency and can also accurately estimate the output frequency of the oscillator when the loop is affected by the outside world. Then, it is compared with the reference frequency. This process is the proposed novel phase discrimination algorithm process, which omits the phase discrimination process of the time-to-digital converter, reduces the overall loop power consumption, and has a certain inhibitory effect on the loop noise.

Claims

1. A fully digital phase-locked loop architecture based on a phase discrimination algorithm, characterized in that Including: An interpolation-type automatic frequency calibration Ip-AFC module, a frequency calibration loop DFTFAL module based on discrete Fourier transform, a digital loop filter DLF, a numerically controlled oscillator DCO module, a programmable divider PGD, and an interpolator DPI; The interpolation-type automatic frequency calibration Ip-AFC module pre-tunes the output frequency of the numerically controlled oscillator DCO module and inputs a predicted frequency control word into the numerically controlled oscillator DCO module; The frequency calibration loop DFTFAL module based on discrete Fourier transform detects the output frequency of the numerically controlled oscillator DCO module in real time, filters it through the digital loop filter DLF, then inputs the calibration oscillator control word into the numerically controlled oscillator DCO module and performs frequency calibration; The programmable divider PGD sets different division ratios according to the required frequency, and then feeds back the divided output frequency of the numerically controlled oscillator DCO module to the frequency calibration loop DFTFAL based on discrete Fourier transform; The interpolation-type automatic frequency calibration Ip-AFC module obtains the relationship between the phase-locked loop frequency control word and the output frequency according to the interpolation algorithm; where k i and b i are the parameter values of the linear relationship in different cases; FCW is the phase-locked loop frequency control word, i is the number of tuning cycles, and then the corresponding oscillator frequency pre-tuning control word OTW is obtained according to the required frequency p . By inputting the obtained pre-tuning word into the numerically controlled oscillator, an oscillator output near the target frequency can be obtained; here, there is an interpolator DPI that inputs different interpolations to the comparison calculation module embedded in the interpolated automatic frequency calibration Ip-AFC module according to the interpolation algorithm, and several groups of data can be obtained. According to the obtained data, the approximate relationship between the predicted phase-locked loop control word and the output frequency can be fitted according to the linear relationship shown in formula (1), and 5 groups of data can be used to fit an accurate relationship The frequency calibration loop DFTFAL module based on discrete Fourier transform estimates the frequency of the obtained oscillator output according to the interpolation-type discrete Fourier transform IpDFT algorithm. According to 5 DFT discrete points, the oscillator frequency output is calculated, and the discrete points are substituted into the formula: where X1 and X2 are the amplitudes of the signals before and after the jump respectively, ω0 is the signal frequency, are the phases of the signals before and after the jump respectively, is the Fourier transform parameter, P is the jump point, n is the current sequence length, L is the total sequence length, k is the current sequence number, N is the sequence length corresponding to the Fourier transform; And perform an inverse operation to obtain the frequency estimate value as: Among them, is the frequency value estimated by the algorithm, is the derived intermediate value; By comparing and calibrating this frequency estimate with the reference frequency, the oscillator calibration tuning word OTW can be obtained a .

2. The all-digital phase-locked loop architecture based on a phase discrimination algorithm according to claim 1, characterized in that: For the accurately fitted relationship, first input the minimum control word (000) into the frequency pre-calculation module FCM. The numerically controlled oscillator DCO module outputs the minimum oscillation frequency according to the input control word. The frequency is returned to the frequency pre-calculation module FCM through the programmable divider set to the default division ratio 1, and this set of data is recorded. Then input the maximum control word (111) into the frequency pre-calculation module FCM. The numerically controlled oscillator DCO module outputs the maximum oscillation frequency according to the input control word. The frequency is returned to the frequency pre-calculation module FCM through the programmable divider set to the default division ratio 1, and this set of data is recorded again. According to the two sets of obtained data, the interpolator DPI inputs 3 appropriate phase-locked loop control words into the frequency pre-calculation module FCM. Finally, the 5 sets of recorded data are in the comparison calculation module, and an appropriate fitting curve is obtained through the interpolation algorithm.

3. The all-digital phase-locked loop architecture based on a phase discrimination algorithm according to claim 1, characterized in that: The roughly obtained relationship between the predicted phase-locked loop control word and the output frequency by fitting is used to obtain the output frequency corresponding to the input phase-locked loop control word. Based on this output frequency, the actual required oscillator output frequency tuning word is obtained, and this tuning word is input into the numerically controlled oscillator to complete the pre-tuning of the output frequency.

4. A fully digital phase-locked loop architecture based on a phase discrimination algorithm according to claim 1, characterized in that: Oscillator output frequency f DCO = OTW p ·K p + OTW a ·K a (4) Among them, OTW p and OTW a are respectively the pre-tuning control word and the calibration tuning word of the numerically controlled oscillator. K p and K a are respectively the pre-tuning gain and the calibration tuning gain. The pre-tuning word quickly locks the loop frequency near the target frequency, and the calibration tuning word calibrates the output frequency with the reference frequency. The sum of the two gives the accurate target frequency.

Images