A noise shaping analog-to-digital converter circuit

Abstract

The application discloses a noise shaping analog-digital converter circuit, which comprises a residual voltage extraction amplification circuit, a residual voltage integration circuit and an analog-digital conversion unit. The residual voltage extraction amplification circuit is connected with the analog-digital conversion unit through the residual voltage integration circuit. In the overall structure, the residual voltage extraction amplification circuit is connected with a CDAC top plate, the residual voltage integration circuit performs integral processing on the residual voltage and outputs the residual voltage to the analog-digital conversion circuit to complete the overall circuit conversion work. The application adopts a combination of a dynamic amplifier and a switched capacitor to realize noise shaping, and has the advantages of small static power consumption, simple structure, good PVT stability and strong noise shaping capacity.

Description

TECHNICAL FIELD

[0001] The present application relates to a new noise shaping analog-to-digital converter circuit, belonging to the field of analog-to-digital converters. BACKGROUND

[0002] In the real world, there are various different analog signals; for example, light, electricity, magnetism, etc. When processing and analyzing and applying such signals, an analog-to-digital converter (ADC) is needed to convert the analog signal into a digital signal. As an important interface circuit, the ADC restricts the performance of the entire signal processing process. Depending on the application scenario, different requirements are placed on the performance of the ADC. The ADC in a data acquisition instrument needs to meet medium or low speed and medium accuracy; the ADC in the field of high-speed data acquisition needs to meet high speed and medium accuracy; and the analog-to-digital sensor in the field of multimedia and sensor measurement needs to meet low speed and high accuracy.

[0003] With the rapid development of deep sub-micron CMOS technology, the progress of the technology enables transistors to work at higher frequencies. However, smaller channel lengths and lower power supply voltages pose greater challenges to the design of analog circuits. In the current design of ADCs, researchers not only hope that the ADCs can have higher working frequencies, but also hope for high accuracy, low power consumption, and simpler circuit structures to achieve better performance

[0004] Among the many ADC architectures, although the SAR ADC architecture has the advantage of low power consumption, its accuracy is not high due to the noise of the comparator and the mismatch of the capacitor array. Therefore, the application of SAR ADCs has been greatly limited. The Sigma-Delta ADC has the advantage of high accuracy due to the use of noise shaping technology and oversampling technology. However, with the advancement of process nodes, the design of the operational amplifier in the Sigma-Delta ADC becomes more and more difficult, and it also has a large power consumption. Therefore, the new structure of NS SAR ADC, which is based on the SAR ADC architecture and combines the noise shaping technology and oversampling technology of the Sigma-Delta ADC, has become a new research hotspot for the development of high-performance ADCs.

[0005] The basic working principle of the current noise shaping SAR ADC is that it applies a method device (usually an integrator) with high and low frequency gain and low and high frequency gain in the closed loop feedback loop of the ADC, uses the negative feedback principle to shape the low frequency quantization noise to high frequency; combined with the oversampling technology, the in-band equivalent noise of the ADC can be greatly reduced, thereby improving the accuracy of the ADC. Like the Sigma-Delta ADC, the SAR ADC is also a closed-loop ADC, which has the natural condition for implementing noise shaping.

[0006] However, there are many ways to implement the integrator, mainly three kinds: (1) based on OTA noise shaping SARADC shaping ability, but the circuit design is difficult, high static power consumption, and process evolution compatibility is not good; (2) based on dynamic amplifier noise shaping SARADC has strong shaping ability and low static power consumption, but its stability is not good with process, power voltage and temperature (Process, Voltage and Temperature, PVT) change; (3) passive noise shaping SARADC simple structure, low power consumption, good PVT stability, but because there is a signal deletion problem caused by charge redistribution, so the noise shaping ability is weak. The present application can overcome the shortcomings of the prior art, further improve and improve the structure and performance of the noise shaping ADC circuit. SUMMARY

[0007] The present application adopts the combination of dynamic amplifier and switched capacitor to realize noise shaping, which has the advantages of small static power consumption, simple structure, good PVT stability and strong noise shaping ability. The present application divides the overall circuit into two parts, first, the first part is to sample and amplify the residual voltage after SARADC comparison, and store the amplified voltage in the capacitor; the second part is to perform charge redistribution and re-amplification on the residual voltage in the capacitor, and store it in the capacitor with delay function, and then make the residual signal after integration transmit to the next stage circuit through the simultaneous conduction of the switches connected between multiple capacitors.

[0008] The above object is achieved by the following technical solutions:

[0009] A noise shaping circuit structure is introduced for brief explanation of conversion operation using a single equivalent circuit, which consists of three parts: residual voltage extraction and amplification circuit, residual voltage integration circuit and analog-digital conversion unit. The residual voltage extraction and amplification circuit is connected with the analog-digital conversion unit through the residual voltage integration circuit. In the overall structure, the residual voltage extraction and amplification circuit is connected with the CDAC top plate, the residual voltage integration circuit integrates the residual voltage and outputs it to the analog-digital conversion circuit to complete the overall circuit conversion work.

[0010] The residual voltage extraction and amplification circuit comprises a dynamic amplifier G1 and a CMOS switch S5. The input end of the dynamic amplifier G1 is connected with the CMOS switch S5, and the output end is connected with the upper plate of the capacitor C1; one end of the CMOS switch S5 is connected with the input analog signal Vres(N) and is controlled by ΦC, and the other end is connected with the input end of the dynamic amplifier G1.

[0011] The residual voltage integration circuit is composed of switches S1, S2, S3, S4, S6, S7, dynamic comparator G2, capacitors C1, C2, C3, C4 and C5. One end of the switch S1 is connected with the upper plate of the capacitor C4, and the other end is connected with the common mode signal, which is controlled by ФA. One end of the switch S2 is connected with the upper plate of the capacitor C3, and the other end is connected with the upper plate of the capacitor C4, which is controlled by ФB. One end of the switch S3 is connected with the output of the dynamic amplifier, and the other end is connected with the upper plates of the capacitors C3 and C5, which is controlled by ФC. One end of the switch S4 is connected with the upper plate of the capacitor C2, and the other end is connected with the upper plate of the capacitor C5, which is controlled by ФD. One end of the switch S6 is connected with the input of the dynamic amplifier and the upper plate of the capacitor C2, and the other end is connected with the upper plate of the capacitor C1, which is controlled by ФD. One end of the switch S7 is connected with the upper plate of the capacitor C4, and the other end is connected with the input of the dynamic comparator G2, which is controlled by ФD. The input of the dynamic comparator G2 is connected with the upper plate of the capacitor C2, and the output is connected with the upper plates of the capacitors C5 and C3. The upper plate of the capacitor C1 is connected with the output of the dynamic amplifier G1, and the lower plate is connected with the common mode signal. The upper plate of the capacitor C2 is connected with the input of the dynamic comparator G2, and the lower plate is connected with the common mode signal. The upper plate of the capacitor C3 is connected with one end of the switch S3, and the lower plate is connected with the common mode signal. The upper plate of the capacitor C4 is connected with one end of the switch S1 and the switch S7, and the lower plate is connected with the common mode signal. The upper plate of the capacitor C5 is connected with one end of the switch S3, and the lower plate is connected with the common mode signal.

[0012] The analog-digital conversion unit comprises a comparator circuit and a digital logic circuit. The comparator circuit is a four-port input comparator, wherein the first positive input end is connected with the upper plate of the CDAC of the SARADC, wherein the second positive input end is connected with the output of the residual voltage integration circuit, the negative input end is connected with the negative half equivalent circuit, and the output end of the comparator is connected with the input end of the digital logic circuit to complete the final conversion.

[0013] The application adopts the combination of the dynamic amplifier and the switched capacitor to realize noise shaping, adopts the dynamic amplifier to amplify the residual signal to resist the signal attenuation problem caused by the charge redistribution between the capacitors, so that the low power consumption is realized while the good noise shaping transfer function is obtained, and the coefficients of the transfer function are related to the proportion of the capacitors, so that the good PVT characteristics are obtained while the structure is simple. BRIEF DESCRIPTION OF DRAWINGS

[0014] Fig. 1 It is the circuit structure block diagram of the application.

[0015] Fig. 2This is a block diagram of the circuit principle structure of the present invention. Detailed Implementation

[0016] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0017] like Figs. 1-2 As shown, a novel noise shaping circuit structure is described, wherein the phases of switches S1, S2, S3, S4, S5, S6, and S7 should maintain a certain correlation. In the first phase, reset switch S1 is closed, and switches S2, S3, S4, S5, S6, and S7 are open, causing the voltage on the upper plate of capacitor C4 to be reset to the common-mode voltage. In the second phase, switch S2 is closed, and switches S1, S3, S4, S5, S6, and S7 are open, at which time capacitors C3 and C4 undergo charge redistribution. In the third phase, switches S3 and S5 are closed, and switches S1, S2, S4, S6, and S7 are open, dynamic amplifier G1 charges the upper plate of capacitor C1, and dynamic amplifier G2 charges the upper plates of capacitors C3 and C5. In the fourth phase, switches S4, S6, and S7 are closed, while switches S1, S2, S3, and S5 are open. At this time, capacitors C1, C2, C4, and C5 undergo charge redistribution.

[0018] The basic working principle of the application is that when the switches S1, S2, S3, S4, S5, S6 and S7 are in the first phase, the overall circuit performs the reset work of the voltage on the capacitor. The voltage on the upper plate of the capacitor C4 is reset to the common mode level by the switch. When the switches S1, S2, S3, S4, S5, S6 and S7 are in the second phase, the switch S2 is closed, and the charge on the upper plate of the capacitor C3 and the capacitor C4 is redistributed, so that the amplified output voltage of the last period stored on the upper plate of the capacitor C3 is proportionally distributed to the upper plate of the capacitor C4, and the signal voltage delay processing of two periods is performed. When the switches S1, S2, S3, S4, S5, S6 and S7 are in the third phase, the switches S3 and S5 are closed, and the switches S1, S2, S4, S6 and S7 are opened. At this time, the dynamic amplifier extracts and amplifies the residual voltage on the top plate of the CDAC capacitor after the SARADC comparison to the upper plate of the capacitor C1. The dynamic amplifier G2 amplifies and stores the output voltage stored on the capacitor C2 in the last period to the upper plate of the capacitor C3 and the upper plate of the capacitor C5. The voltage on the upper plate of the capacitor C3 is delayed for one period of signal voltage storage. The dynamic amplifier makes the extracted residual signal have a multiple to resist the signal voltage attenuation problem caused by the charge redistribution of other capacitors. When the switches S1, S2, S3, S4, S5, S6 and S7 are in the fourth phase, the switches S4, S6 and S7 are closed, and the switches S1, S2, S3 and S5 are opened. The residual voltage delayed for two periods is stored on the upper plate of the capacitor C4, and the residual voltage delayed for one period is stored on the upper plate of the capacitor C5. Then, the upper plate of the capacitor C1, the upper plate of the capacitor C2, the upper plate of the capacitor C4 and the upper plate of the capacitor C5 are connected, realizing the charge redistribution among the four capacitors. Then, the residual voltage integration circuit outputs the voltage to the input end of the comparator in the analog-digital conversion circuit. Thus, the noise shaping function of the residual voltage is realized.

[0019] Of course, the above description is not a limitation of the application, and the application is not limited to the above examples. Changes, modifications, additions or substitutions made by those skilled in the art within the scope of the application should also be within the scope of the application.

Claims

1. A noise-shaping analog-to-digital converter circuit, characterized in that, include: The circuit consists of three parts: residual voltage extraction and amplification circuit, residual voltage integration circuit, and analog-to-digital conversion unit. The residual voltage extraction and amplification circuit is connected to the analog-to-digital conversion unit through the residual voltage integration circuit. The residual voltage extraction and amplification circuit is connected to the top board of the CDAC. The residual voltage integration circuit integrates the residual voltage and outputs it to the analog-to-digital conversion circuit to complete the overall circuit conversion. The residual voltage extraction and amplification circuit includes a dynamic amplifier G1 and a CMOS switch S5. The input terminal of the dynamic amplifier G1 is connected to the CMOS switch S5, and the output terminal is connected to the upper plate of the capacitor C1. One end of the CMOS switch S5 is connected to the input analog signal Vres, controlled by ФC, and the other end is connected to the input terminal of the dynamic amplifier G1. The analog-to-digital conversion unit includes a comparator circuit and a digital logic circuit. The comparator circuit is a four-port input comparator, wherein the first positive input terminal is connected to the upper plate of the SAR ADC CDAC, the second positive input terminal is connected to the output of the residual voltage integration circuit, the negative input terminal is connected to the negative half of the equivalent circuit, and the output terminal of the comparator is connected to the input terminal of the digital logic circuit to complete the final conversion. The residual voltage integration circuit comprises switches S1, S2, S3, S4, S6, and S7, a dynamic comparator G2, and capacitors C1, C2, C3, C4, and C5. Switch S1 is connected at one end to the upper plate of capacitor C4 and at the other end to the common-mode signal, controlled by ФA. Switch S2 is connected at one end to the upper plate of capacitor C3 and at the other end to the upper plate of capacitor C4, controlled by ФB. Switch S3 is connected at one end to the output of the dynamic amplifier and at the other end to the upper plates of capacitors C3 and C5, controlled by ФC. Switch S4 is connected at one end to the upper plate of capacitor C2 and at the other end to the upper plate of capacitor C5, controlled by ФD. Switch S6 is connected at one end to the input of the dynamic amplifier and the upper plate of capacitor C2, and at the other end to the capacitor... The upper plate of capacitor C1 is connected and controlled by ФD; one end of switch S7 is connected to the upper plate of capacitor C4, and the other end is connected to the input of dynamic amplifier G2, controlled by ФD; the input of dynamic amplifier G2 is connected to the upper plate of capacitor C2, and the output is connected to the upper plates of capacitors C5 and C3; the upper plate of capacitor C1 is connected to the output of dynamic amplifier G1, and the lower plate is connected to the common-mode signal; the upper plate of capacitor C2 is connected to the input of dynamic amplifier G2, and the lower plate is connected to the common-mode signal; the upper plate of capacitor C3 is connected to one end of switch S3, and the lower plate is connected to the common-mode signal; the upper plate of capacitor C4 is connected to one end of switches S1 and S7, and the lower plate is connected to the common-mode level; the upper plate of capacitor C5 is connected to one end of switch S3, and the lower plate is connected to the common-mode signal.

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