Verification device and method for multiple instruction protocol codes

Abstract

The present invention provides a verification device and method for multiple instruction protocol encodings, the device comprising: an instruction generation module, configured to obtain multiple instruction protocols, and generate a random combination instruction protocol based on the multiple instruction protocols; an instruction conversion module, configured to receive the combination instruction protocol, encode the combination instruction protocol, and generate data; an instruction verification module, configured to obtain the verification judgment standard corresponding to each instruction protocol in the combination instruction protocol; receive the data, decode the data, verify the decoded data according to the verification judgment standard, and generate a verification result. It is possible to use one device to verify the integrity and correctness of multiple instruction protocols at the same time, meet the needs of verifying multiple instruction protocols at the same time, reduce verification costs, and help improve the correctness of instruction protocol encoding. The verification method for multiple instruction protocol encodings also provided by the present invention can also achieve the above-mentioned effects.

Description

Technical Field

[0001] The present invention belongs to the field of computer technology, and in particular relates to a verification device and method for multiple instruction protocol codes. Background Art

[0002] At present, the granularity of the definition of instruction protocols is too coarse, and there is no distinction between command instructions and protocol instructions. Specific protocol instructions also do not distinguish between custom protocols and various standard protocols. At the same time, when verifying the instruction protocol, it is impossible to use one device to verify the integrity and correctness of multiple instruction formats at the same time, and it cannot be verified in real time. Most of them are recorded into files and verified by post-processing analysis. In addition, it is impossible to support high-frequency instruction protocol data verification, and no targeted verification is performed on the output frequency of the instruction protocol. Summary of the invention

[0003] Based on this, the present invention provides a verification device and method for multiple instruction protocol encodings, which solves the problems that one device cannot be used to simultaneously verify the integrity and correctness of multiple instruction formats during instruction protocol verification, cannot be verified in real time, cannot support high-frequency instruction protocol data verification and the correctness of special fields that are interrelated between instructions.

[0004] The embodiment of the present invention provides a verification device for multiple instruction protocol codes, the device comprising:

[0005] An instruction generation module is configured to obtain a plurality of instruction protocols and generate a random combination instruction protocol based on the plurality of instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol;

[0006] An instruction conversion module is configured to receive the combined instruction protocol, encode the combined instruction protocol, and generate data;

[0007] The instruction verification module is configured to obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; receive the data, decode the data, verify the decoded data according to the verification judgment standard, and generate a verification result.

[0008] Furthermore, the instruction conversion module includes:

[0009] an identification module, configured to identify the combined instruction protocol as a preset instruction protocol format;

[0010] An encoding module is configured to receive a combined instruction protocol identified as an instruction protocol format, encode the combined instruction protocol, and generate data;

[0011] The output module is configured to transmit the data to the instruction checking module.

[0012] Furthermore, the identification module is specifically configured as follows:

[0013] Identify a first transmission mode in which the combined instruction protocol is transmitted from the instruction generation module to the identification module, identify the instruction protocol type included in the combined instruction protocol, and identify the instruction character string in each instruction protocol;

[0014] The combined instruction protocol is sequentially stored according to the identified first transmission mode, the instruction protocol type and the instruction character string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format;

[0015] The stored combined instruction protocol in the instruction protocol format is sent to the encoding module.

[0016] Furthermore, the encoding module is specifically configured as follows:

[0017] Receiving a combined instruction protocol in the instruction protocol format;

[0018] Encode the instruction protocol type contained in the combined instruction protocol and the instruction character string in each instruction protocol, perform calculations on each instruction protocol to obtain a check code, and generate data corresponding to the combined instruction protocol according to the encoding result and the check code;

[0019] An output list is generated according to the first transmission mode of the combined instruction protocol transmitted from the instruction generation module to the identification module and data corresponding to the combined instruction protocol, and the output list is sent to the output module.

[0020] Furthermore, the output module is specifically configured as follows:

[0021] According to the first transmission mode, acquiring a second transmission mode between the output module and the instruction verification module, wherein the second transmission mode is the same as the first transmission mode;

[0022] The data is sent to the instruction checking module through the second transmission mode.

[0023] Furthermore, the instruction verification module is also configured to:

[0024] After the data verification is completed, a verification completion signal is generated, and the verification completion signal is used to control the operation of the instruction generation module to generate a random combination instruction protocol.

[0025] Furthermore, the device also includes:

[0026] The storage module is configured to store the instruction protocol and the corresponding verification judgment standard.

[0027] The embodiment of the present invention also provides a method for verifying multiple instruction protocol codes, the method comprising:

[0028] Acquire multiple instruction protocols, and generate a random combination instruction protocol based on the multiple instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol;

[0029] Encoding the combined instruction protocol to generate data;

[0030] Obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; decode the data, verify the data corresponding to each instruction protocol after decoding according to the verification judgment standard, and generate a verification result.

[0031] Furthermore, encoding the combined instruction protocol to generate data includes:

[0032] Identifying the combined instruction protocol as a preset instruction protocol format;

[0033] The combined instruction protocol is encoded to generate data.

[0034] Further, encoding the combined instruction protocol to generate data includes:

[0035] Identify the transmission mode of the combined instruction protocol, identify the instruction protocol type contained in the combined instruction protocol, and identify the instruction character string in each instruction protocol;

[0036] The combined instruction protocol is sequentially stored according to the identified transmission mode, the instruction protocol type and the instruction character string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format;

[0037] The step of encoding the combined instruction protocol to generate data includes:

[0038] The instruction protocol type contained in the combined instruction protocol and the instruction character string in each instruction protocol are encoded, and each instruction protocol is operated to obtain a check code, and data corresponding to the combined instruction protocol is generated according to the encoding result and the check code.

[0039] The verification device for multiple instruction protocol encodings provided by the present invention realizes the random combination of multiple instruction protocols through the instruction generation module; through the cooperation between the instruction conversion module, the instruction generation module and the instruction verification module, multi-threaded encoding is adopted to reduce the coupling degree, improve the processing efficiency, and support multiple serial ports to interact and verify simultaneously, so as to realize the verification of integrity and correctness of multiple instruction protocols with one device at the same time, and realize automatic closed-loop real-time verification at the same time, meet the demand of verifying multiple instruction protocols at the same time, and verify the distinguished command instructions and protocol instructions respectively, reduce the verification cost of manual operation, and can help improve the correctness of instruction protocol encoding. The verification method for multiple instruction protocol encodings also provided by the present invention can also achieve the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 A structural block diagram of a verification device for multiple instruction protocol encodings provided by an embodiment of the present invention;

[0042] Figure 2 for Figure 1 The structural block diagram of the instruction conversion module in the figure;

[0043] Figure 3 A structural block diagram of another verification device for multiple instruction protocol encodings provided by an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of a flow chart of a method for verifying multiple instruction protocol codes provided by an embodiment of the present invention;

[0045] Figure 5 for Figure 4 A schematic diagram of the process of encoding the combined instruction protocol to generate data. DETAILED DESCRIPTION

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" and any variations thereof in the specification and claims of the present application and the above-mentioned drawings are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0047] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0049] In the following description, use of suffixes such as “module,” “part,” or “unit” used to refer to elements is merely for facilitating description of the present application, and has no specific meaning by itself.

[0050] like Figure 1 As shown, it is a structural block diagram of a verification device 100 for encoding multiple instruction protocols provided in an embodiment of the present invention, and the device 100 includes: an instruction generation module 110, which is configured to obtain multiple instruction protocols and generate a random combination instruction protocol based on the multiple instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol.

[0051] Specifically, the command protocols acquired in the command generation module 110 include: user-defined command protocols, customized ASCII LOG protocols, customized binary LOG protocols, standard NMEA LOG protocols, and standard RTCM3.x LOG protocols. After acquiring the command protocols, the acquired command protocols are randomly combined to generate a combined command protocol. When generating a random combined command protocol when acquiring the command, the acquired command protocols can be the same type of protocols or different types of protocols. For example, 10 command protocols are randomly combined to generate a random combined command protocol as follows:

[0052] config undulation 0.0

[0053] mode base 40.078993938 116.236612846 58.0388

[0054] RANGEA COM1 1

[0055] GNGGA COM1 1

[0056] RTCM1006 COM1 10

[0057] RTCM1033 COM1 10

[0058] RTCM1075 COM1 0.1

[0059] RTCM1085 COM1 0.1

[0060] RTCM1095 COM1 0.1

[0061] RTCM1125 COM1 0.1

[0062] In this combined command protocol, the first two command protocols are command protocols, the third command protocol is a user-defined ASCII LOG protocol, the fourth command protocol is a standard NMEA LOG protocol, and the remaining command protocols are all standard RTCM3.x LOG protocols.

[0063] Among them, in the above command protocol, the command protocol has no data frequency attribute and is one-dimensional; other command protocols have device and data frequency attributes and are multi-dimensional, wherein the supported output time intervals from high to low can be 120 seconds, 100 seconds, 60 seconds, 30 seconds, 20 seconds, 10 seconds, 5 seconds, 2 seconds, 1 second, 0.1 second, 0.2 seconds, 0.5 seconds, 0.05 seconds, and 0.01 seconds. Take RANGEA COM1 1 in the above combined command protocol as an example to illustrate that other command protocols have device and data frequency attributes, wherein COM1 is the device name, such as when the RANGEA command protocol is sent to the board through the software on the PC side, after the RANGEA command protocol is sent to the board, the board will output it to the software on the PC side through the board's COM1 feedback; 1 is the frequency attribute, indicating that a RANGEA is output at an interval of 1 second.

[0064] The instruction conversion module 120 is configured to receive the combined instruction protocol, encode the combined instruction protocol, and generate data;

[0065] In some embodiments, Figure 2 As shown, the instruction conversion module 120 includes: an identification module 1201, configured to identify the combined instruction protocol as a preset instruction protocol format;

[0066] Furthermore, the identification module 1201 is specifically configured to: identify the first transmission mode in which the combined instruction protocol is transmitted from the instruction generation module 110 to the identification module 120, identify the instruction protocol type contained in the combined instruction protocol, and identify the instruction string in each instruction protocol; store the combined instruction protocol in sequence according to the identified first transmission mode, the instruction protocol type and the instruction string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format; and send the stored combined instruction protocol in the instruction protocol format to the encoding module.

[0067] Preferably, in actual applications, the instruction conversion module 120 can be run as an embedded program of the chip, and the instruction generation module 110 can be run as a Windows program on the PC side. The PC side and the chip communicate through the serial port, and when the combined instruction protocol is transmitted from the instruction generation module 110 to the identification module 120, multiple serial port interactions can be supported at the same time. The identification module 1201 of the instruction conversion module 120 listens to and identifies the instruction protocol input by the serial port, and stores the identified instruction protocol according to the serial port device number, instruction protocol type and the instruction string in each instruction protocol as a three-dimensional instruction protocol list, where the first dimension represents the serial port, the second dimension represents the instruction type, and the third dimension stores the specific instruction string.

[0068] Preferably, the first transmission mode in which the combined instruction protocol is transmitted from the instruction generation module to the identification module can be labeled and assigned a value, and the instruction protocol type can be labeled and assigned a value. When the identification module 1201 monitors and identifies the instruction protocol input by the serial port, the label of the first transmission mode of the instruction protocol and the label of the instruction protocol type are directly identified. As in the above example, the serial ports for communication between the PC and the chip include: serial port 1, serial port 2, serial port 3 and serial port 4, which are labeled and assigned values, such as serial port 1 is labeled as 1, with a value of 0; serial port 2 is labeled as 2, with a value of 1; serial port 3 is labeled as 3, with a value of 2 and serial port 4 is labeled as 4, with a value of 3; at the same time, the protocol of the instruction protocol type is labeled and assigned a value, such as the custom ASCII LOG protocol is labeled as 1, with a value of 0; the custom binary LOG protocol is labeled as 2, with a value of 1; the standard NMEA LOG protocol is labeled as 3, with a value of 2; the standard RTCM3.x The LOG protocol is marked as 4, with a value of 3; the user-defined command protocol is marked as 5, with a value of 4; the identified instruction protocol is stored as a three-dimensional instruction protocol list LIST[COMIndex][TypeIndex][StringIndex] according to the serial port device label, the instruction protocol type and the instruction string in each instruction protocol, wherein the first dimension represents the serial port label value COMIndex, the second dimension represents the instruction type label value TypeIndex, and the third dimension stores the specific instruction string. Then the stored three-dimensional instruction protocol list LIST[COMIndex][TypeIndex][StringIndex] is sent to the encoding module 1202.

[0069] The encoding module 1202 is configured to receive a combined instruction protocol identified as an instruction protocol format, encode the combined instruction protocol, and generate data;

[0070] Furthermore, the encoding module 1202 is specifically configured to: receive a combined instruction protocol in the instruction protocol format; encode the instruction protocol type contained in the combined instruction protocol and the instruction string in each instruction protocol, and perform operations on each instruction protocol to obtain a check code, and generate data corresponding to the combined instruction protocol based on the encoding result and the check code; generate an output list based on the first transmission mode of the combined instruction protocol transmitted from the instruction generation module 110 to the identification module 1201 and the data corresponding to the combined instruction protocol, and send the output list to the output module 1203.

[0071] Specifically, after receiving the three-dimensional instruction list, the encoding module 1202 labels the protocol of the instruction protocol type and encodes the instruction string in the corresponding instruction protocol, and performs operations on each instruction protocol to obtain a check code, and generates data corresponding to the combined instruction protocol according to the encoding result and the check code; then, according to the serial port label transmitted from the instruction generation module 110 to the identification module 1201 and the data corresponding to the combined instruction protocol, a two-dimensional output list OUTPUT[COMIndex][DATA] is generated and sent to the output module 1203. Among them, different types of instruction protocols use different check rules, that is, the methods of generating the end check code are different. The check rules used in this application are as follows:

[0072] The custom command protocol uses 8-bit CRC check; the custom ASCII LOG protocol uses 32-bit CRC check; the custom binary LOG protocol uses 32-bit CRC check; the standard NMEA protocol uses 8-bit CRC check; the standard RTCM3.x protocol uses 24-bit CRC check. The use of CRC check of different lengths is based on the difference points of the command protocol. The command protocol is short (80% of the command length is less than 10 characters) and the response real-time requirement is high, so the 8-bit CRC check not only meets the need for check integrity, but also reduces the consumption of generating CRC check code and improves processing efficiency; a complete LOG consists of three parts: the header common to all LOGs, the body of the LOG specific data structure and the CRC check end code, so a complete LOG is long, such as the LOG RANGEA will exceed 1Btyes in length. Therefore, a 32-bit CRC check is used to ensure the accuracy of the check. NMEA and RTCM3.x are official standard formats, so the CRC check rule is designed according to the official standard.

[0073] There are two types of commands: configuration commands and query commands. Configuration commands only output feedback about the execution of commands. For example, mode base is as follows:

[0074] $command,mode base,response:OK*4C

[0075] Only an 8-bit CRC check is added after the feedback to confirm that the command is executed normally and feedback is given.

[0076] In addition to outputting the feedback of the executed command, the query command also outputs the feedback result. The example mode is as follows:

[0077] $command,mode,response:OK*79

[0078] MODE,98,GPS,FINE,2204,270703000,0,0,18,839; mode base*6d

[0079] The first line indicates that the execution is correct, and the second line outputs the mode status. There is an 8-bit CRC check at the end of both lines to ensure the integrity of the feedback information.

[0080] In the LOG command, the NMEA protocol and the custom ASCII protocol commands are distinguished by the specific string in front of the command, such as the type of a NMEA protocol LOG and GNGGA logo, as follows:

[0081] $GNGGA,081311.00,4004.73986370,N,11614.19676030,E,7,28,0.66,64.0431,M,-7.6172,M,*60

[0082] The types of ASCII protocol LOG and PSRPOSA protocol LOG are as follows:

[0083] #PSRPOSA,COM1,0,98.0,FINE,2204,288872.000,25361823,6,18;SOL_COMPUTED,FIXEDPOS,40.07899772831,116.23 661267163,64.0431,-7.6172,WGS84,0.0000,0.0000,0.0000,"0",0.000,0.000,49,28,28,0,32,12,01,41*087827d3

[0084] The LOG of RTCM3.x protocol and custom binary protocol are distinguished by the ID field in the header. The data structure description of the header of the two protocols is listed separately. The header data structure of RTCM3.x protocol is as follows, where MsgNum identifies the type:

[0085] typedef struct

[0086] {

[0087] CRTCMUInt12 MsgNum; / / 12bits Message Number

[0088] CRTCMUInt12 RefStationID; / / 12bits Reference Station ID

[0089] CRTCMUInt30 EpochTime; / / 30bits GPS Epoch Time

[0090] CRTCMBit1 MultiMsgBit; / / 1bit Multiple Message Bit

[0091] CRTCMUInt3 IODS; / / Issue of Data Station

[0092] CRTCMBit7 Reserved; / / May be GNSS specific

[0093] CRTCMUInt2 ClockSteIn; / / Clock Steering Indicator

[0094] CRTCMUInt2 ExterClockIn; / / External Clock Indicator

[0095] CRTCMBit1 GnssDivSmoothIn; / / Smoothing Indicator

[0096] CRTCMBit3 GnssSmoothMask; / / GNSS Smoothing Interval

[0097] CRTCMBit32 GnssSatMaskH32; / / GNSS Satellite Mask

[0098] CRTCMBit32 GnssSatMaskL32; / / GNSS Satellite Mask

[0099] CRTCMBit32 GnssSigMask; / / GNSS Signal Mask;

[0100] }_PACKED_StUniLogHeader_t;

[0101] The header data structure of the custom binary protocol is as follows, where usMessageId identifies the type:

[0102] typedef struct

[0103] {

[0104] UCHAR ucSync1;

[0105] UCHAR ucSync2;

[0106] UCHAR ucSync3;

[0107] UCHAR ucIdleTime;

[0108] USHORT usMessageId;

[0109] USHORT usMessageLength;

[0110] UCHAR ucTimeRef;

[0111] UCHAR ucTimeStatus;

[0112] USHORT usWeek;

[0113] ULONG ulMilliseconds;

[0114] ULONG ulRes;

[0115] UCHAR ucRelVersion;

[0116] UCHAR ucLeepSec;

[0117] USHORT usDelayMs;

[0118] }_PACKED_StUniLogHeader_t;

[0119] The output module 1203 is configured to transmit the data to the instruction checking module.

[0120] Furthermore, the output module 1203 is specifically configured to: obtain a second transmission mode between the output module 1203 and the instruction verification module 130 according to the first transmission mode, wherein the second transmission mode is the same transmission mode as the first transmission mode; and send the data to the instruction verification module 130 via the second transmission mode.

[0121] Preferably, in actual applications, the verification module will be run in a Windows program on the same PC as the instruction generation module 110. After the output module 1203 receives the two-dimensional output list OUTPUT[COMIndex][DATA] output by the encoding module 1202, the serial port number transmitted from the instruction generation module 110 to the identification module 1201 is identified according to the combined instruction protocol, the same serial port between the output module 1203 and the instruction verification module 130 is identified, and then the data corresponding to the same serial port is sent to the instruction verification module through this serial port.

[0122] The instruction verification module 130 is configured to obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; receive the data, decode the data, verify the decoded data according to the verification judgment standard, and generate a verification result.

[0123] Preferably, the instruction generation module 110 is also configured to send the generated random combination instruction protocol to the instruction verification module 130, and the verification judgment standard corresponding to each instruction protocol in the combination instruction protocol obtained in the instruction verification module 130 can be obtained according to the combination instruction protocol, thereby improving the accuracy of obtaining the verification judgment standard.

[0124] Specifically, after the instruction verification module 130 decompresses the data, it verifies the data including integrity and correctness. When performing the integrity check, when verifying the integrity of the number of instructions in the combined instruction protocol, the verification is performed by verifying whether the number of instruction feedbacks is the same as the number of instruction protocols combined in the combined instruction protocol. If the number of instruction feedbacks received is less than the number of instruction protocols, it means that the combined instruction protocol is incomplete. When performing the correctness verification, after obtaining the verification judgment standard, compare whether the order of the combined instruction protocol output is consistent with the instruction combination order input by the combined instruction protocol. If they are consistent, the verification is passed; compare the legal value ranges of different fields in the instruction. If the values ​​are within the legal range, the verification is passed; whether the encoding is performed according to the instruction protocol format during encoding (such as whether there is a check code and whether the CRC check can be passed, etc.), if so, the verification is passed; whether it conforms to the transmission mode of the instruction type and the frequency range supported by the instruction type, such as the serial port type between the serial ports for communication between the PC and the chip, and the combined instruction protocol is transmitted from the PC to the chip. The frequency input to the chip is within the range supported by the command protocol; if it meets the requirements, it passes the verification; whether the string length of the command protocol meets the standard, if it meets the standard, it passes the verification; whether the assignment of the interrelated fields between the instructions is correct, etc. For example, in the RTCM3.x protocol, for the observation RTCM data of different satellite systems, if they are requested at the same time, the MultiMsgBit field of the data header of the last observation RTCM data needs to be set to 0, and the ultiMsgBit fields of the data headers of the previous observation RTCM data need to be set to 1. If so, the assignment of the interrelated fields is correct and passes the verification.

[0125] In some embodiments, the instruction checking module 130 is further configured to:

[0126] The verification time interval is dynamically determined according to the frequency of the command generation module 110 outputting the combined command protocol.

[0127] Specifically, the instruction protocol in the instruction combination generated by the instruction generation module 110 has an output time interval, so the verification time interval is dynamically determined in the instruction verification module 130, and the output of the instruction protocol can be verified. When the verification time interval is dynamically determined, it is determined based on the longest time of the instruction protocol interval when the instruction generation module 110 outputs the combined instruction protocol, such as being set to four times the longest time interval.

[0128] In some embodiments, the instruction checking module 130 is further configured to:

[0129] After the data verification is completed, a verification completion signal is generated, and the verification completion signal is used to control the operation of the instruction generation module to generate a random combination instruction protocol.

[0130] Specifically, after the verification is completed, the verification result is saved as a file and recorded by timestamp for easy tracking and analysis. At the same time, a verification completion signal is generated and transmitted to the instruction generation module 110. After receiving the verification completion signal, the instruction generation module 110 obtains multiple new instruction protocols, generates a random new combination instruction protocol based on the new multiple instruction protocols, and triggers the next cycle.

[0131] In some embodiments, Figure 3 As shown, the device 100 also includes: a storage module 140, which is configured to store the instruction protocol and the corresponding verification judgment standard.

[0132] Specifically, the instruction protocol and the corresponding verification judgment standard can be stored in the storage module 140, the instruction generation module 110 directly obtains the instruction protocol from the storage module 140, and the instruction verification module 130 directly obtains the instruction protocol and the corresponding verification judgment standard from the storage module 140.

[0133] The verification device for multiple instruction protocol encodings provided by the embodiment of the present invention realizes random combination of multiple instruction protocols by distinguishing command instructions and protocol instructions in the instruction generation module; through the cooperation between the instruction conversion module, the instruction generation module and the instruction verification module, multi-threaded encoding is adopted to reduce the coupling degree, improve processing efficiency, and support simultaneous interactive verification of multiple serial ports, so as to realize the verification of integrity and correctness of multiple instruction protocols simultaneously with one device, and realize automatic closed-loop real-time verification at the same time, which meets the demand of verifying multiple instruction protocols at the same time, reduces the verification cost of manual operation, and can help improve the correctness of instruction protocol encoding.

[0134] like Figure 4 FIG. 1 is a flow chart of a method for verifying multiple instruction protocol codes provided by an embodiment of the present invention, wherein the method comprises:

[0135] Step S10: acquiring a plurality of instruction protocols, and generating a random combination instruction protocol based on the plurality of instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol;

[0136] Step S20: Encode the combined instruction protocol to generate data;

[0137] Step S30: Obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; decode the data, and verify the data corresponding to each instruction protocol after decoding according to the verification judgment standard to generate a verification result.

[0138] For further information, see Figure 5 , the step S20 comprises:

[0139] Step S201: identifying the combined instruction protocol as a preset instruction protocol format;

[0140] Step S202: Encode the combined instruction protocol to generate data.

[0141] Specifically, the step S201 is: identifying the transmission mode of the combined instruction protocol, identifying the instruction protocol type contained in the combined instruction protocol, and identifying the instruction character string in each instruction protocol;

[0142] The combined instruction protocol is sequentially stored according to the identified transmission mode, the instruction protocol type and the instruction character string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format;

[0143] The step S202 is: encoding the instruction protocol type contained in the combined instruction protocol and the instruction character string in each instruction protocol, and performing calculations on each instruction protocol to obtain a check code, and generating data corresponding to the combined instruction protocol according to the encoding result and the check code.

[0144] The specific implementation process of the method provided in this embodiment can refer to the verification device 100 of various instruction protocol encodings, which will not be described in detail here.

[0145] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0146] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example. In actual applications, the above-mentioned functions can be distributed and completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above.

[0147] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.

Claims

1. A verification device for multiple instruction protocol codes, characterized in that: The device comprises: An instruction generation module is configured to obtain a plurality of instruction protocols and generate a random combination instruction protocol based on the plurality of instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol, and different types of instruction protocols use different verification rules; An instruction conversion module is configured to receive the combined instruction protocol, identify the instruction protocol type included in the combined instruction protocol, and identify the instruction string in each of the instruction protocols, encode the instruction protocol type and the instruction string to obtain an encoding result, and perform calculations on each of the instruction protocols to obtain a check code, and generate data corresponding to the combined instruction protocol according to the encoding result and the check code; The instruction verification module is configured to obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; receive the data, decode the data, verify the decoded data according to the verification judgment standard, and generate a verification result.

2. The verification device for multiple instruction protocol codes according to claim 1, characterized in that: The instruction conversion module comprises: an identification module, configured to identify the combined instruction protocol as a preset instruction protocol format; An encoding module is configured to receive a combined instruction protocol identified as an instruction protocol format, encode the combined instruction protocol, and generate data; The output module is configured to transmit the data to the instruction checking module.

3. The verification device for multiple instruction protocol codes according to claim 2, characterized in that: The identification module is specifically configured as follows: Identify a first transmission mode in which the combined instruction protocol is transmitted from the instruction generation module to the identification module; The combined instruction protocol is sequentially stored according to the identified first transmission mode, the instruction protocol type and the instruction character string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format; The stored combined instruction protocol in the instruction protocol format is sent to the encoding module.

4. The verification device for multiple instruction protocol codes according to claim 2, characterized in that: The encoding module is specifically configured as follows: Receiving a combined instruction protocol in the instruction protocol format; An output list is generated according to the first transmission mode of the combined instruction protocol transmitted from the instruction generation module to the identification module and data corresponding to the combined instruction protocol, and the output list is sent to the output module.

5. The verification device for multiple instruction protocol codes according to claim 3, characterized in that: The output module is specifically configured as follows: According to the first transmission mode, acquiring a second transmission mode between the output module and the instruction verification module, wherein the second transmission mode is the same as the first transmission mode; The data is sent to the instruction checking module through the second transmission mode.

6. The verification device for multiple instruction protocol codes according to claim 1, characterized in that: The instruction verification module is further configured to: After the data verification is completed, a verification completion signal is generated, and the verification completion signal is used to control the operation of the instruction generation module to generate a random combination instruction protocol.

7. The verification device for multiple instruction protocol codes according to claim 1, characterized in that: The device also includes: The storage module is configured to store the instruction protocol and the corresponding verification judgment standard.

8. A verification method for multiple instruction protocol codes, characterized in that: The method comprises: Acquire multiple instruction protocols, and generate a random combination instruction protocol based on the multiple instruction protocols, wherein the combination instruction protocol includes at least one type of instruction protocol, and different types of instruction protocols use different verification rules; Encode the combined instruction protocol, identify the instruction protocol type included in the combined instruction protocol, and identify the instruction string in each of the instruction protocols, encode the instruction protocol type and the instruction string to obtain an encoding result, and calculate each of the instruction protocols to obtain a check code, and generate data corresponding to the combined instruction protocol according to the encoding result and the check code; Obtain the verification judgment standard corresponding to each instruction protocol in the combined instruction protocol; decode the data, verify the data corresponding to each instruction protocol after decoding according to the verification judgment standard, and generate a verification result.

9. The verification method of multiple instruction protocol codes according to claim 8, characterized in that: The step of encoding the combined instruction protocol to generate data includes: Identifying the combined instruction protocol as a preset instruction protocol format; The combined instruction protocol is encoded to generate data.

10. The verification method of multiple instruction protocol codes according to claim 9, characterized in that: The step of encoding the combined instruction protocol to generate data includes: Identifying a transmission mode of the combined instruction protocol; The combined instruction protocol is stored in sequence according to the identified transmission mode, the instruction protocol type and the instruction character string in each instruction protocol to obtain a combined instruction protocol in an instruction protocol format.

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