Monitor and Image Display Method

Abstract

The present application provides a monitor and image display method, the monitor comprising: an SDI signal processing module for acquiring parameter information from an SDI signal and converting the SDI signal into a DP signal, the parameter information including VPID information; an EOTF processing module connected to the SDI signal processing module; a scaler signal processing module connected to the SDI signal processing module and the EOTF processing module; a backlight control module connected to the scaler signal processing module for generating backlight data corresponding to the VB1 signal and adjusting the backlight data according to the backlight adjustment signal; and a display processing module for generating and displaying an image corresponding to the SDI signal based on the VB1 signal and the adjusted backlight data. The present application improves the user experience of the monitor.

Description

Technical Field

[0001] The present application relates to the technical field of professional monitors, and in particular to a monitor and an image display method. Background Art

[0002] The SDI (Serial Digital Interface) monitor is a professional monitor widely used in the fields of broadcasting, film and television. When making a video program, the adjustment scheme of the VPID (Video Payload Identify) can be determined based on the playback effect of the SID signal source viewed on the SDI monitor. By adjusting the VPID according to the adjustment scheme, the video program can achieve a better viewing effect. Before adjusting the VPID, it is necessary to first configure the SDI monitor so that the VPID is consistent with the VPID of the video program, so that the SDI monitor can accurately restore the recording effect of the video program. In the related art, the SDI signal of the SID signal source is usually analyzed manually to obtain the VPID, and then the SDI monitor is manually configured according to the VPID. The configuration threshold and error rate of this configuration method are relatively high, resulting in poor accuracy of the monitor restoring the image of the video source. Summary of the Invention

[0003] In order to solve the technical problem that a monitor cannot automatically identify a VPID, the present application provides a monitor and an image display method.

[0004] In a first aspect, the present application provides a monitor, comprising:

[0005] An SDI signal processing module is used to obtain parameter information in the SDI signal and convert the SDI signal into a DP signal, wherein the parameter information includes VPID information;

[0006] An EOTF processing module, connected to the SDI signal processing module, configured to obtain EOTF parameters in the VPID information;

[0007] A scaler signal processing module is connected to the SDI signal processing module and the EOTF processing module, and is used to control the EOTF processing module to perform EOTF configuration, generate a backlight adjustment signal according to the EOTF parameters, and convert the DP signal into a VB1 signal;

[0008] a backlight control module connected to the Scaler signal processing module, configured to generate backlight data corresponding to the VB1 signal and adjust the backlight data according to the backlight adjustment signal;

[0009] The display processing module is used to generate and display an image corresponding to the SDI signal according to the VB1 signal and the adjusted backlight data.

[0010] In some embodiments, the SDI signal processing module includes:

[0011] An SDI input unit, configured to receive the SDI signal and obtain signal auxiliary information in the SDI signal;

[0012] An SDI driving unit, connected to the SDI input unit, configured to identify the SDI signal and send the SDI signal to the FPGA unit;

[0013] The FPGA unit is connected to the SDI driving unit and is used to parse the signal auxiliary information, obtain the parameter information, and send the SDI signal to the DP unit;

[0014] The DP unit is connected to the FPGA unit and is used to convert the SDI signal into a DP signal.

[0015] In some embodiments, the Scaler signal processing module is connected to the FPGA unit, and the FPGA unit is configured to trigger an interrupt level connected to the Scaler signal processing module according to a change in the EOTF parameters, and the Scaler signal processing module is configured to read the EOTF parameters according to the interrupt level.

[0016] In some embodiments, the Scaler signal processing module includes:

[0017] User operation interface, used to receive user operation instructions;

[0018] a processor unit connected to the user operation interface, and configured to communicate with the EOTF processing module and the Scale unit respectively according to the user operation interface;

[0019] The scale unit is connected to the processor unit and the SDI signal processing module, and is used to process the DP signal according to the control instruction of the processor unit to obtain the VB1 signal;

[0020] The VB1 processing unit is connected to the Scale unit and is used to send the VB1 signal to the backlight control module.

[0021] In some embodiments, the processor unit is configured to:

[0022] If the operation instruction is to start VPID identification, sending a first EOTF instruction to the EOTF processing module, so that the EOTF processing module parses EOTF parameters in the VPID information and configures a monitor according to the EOTF parameters;

[0023] If the operation instruction is to turn off VPID identification, obtain the EOTF parameters set in the OSD menu, send a second EOTF instruction to the EOTF processing module, so that the EOTF processing module does not parse the EOTF parameters in the VPID information, and configure the monitor according to the EOTF parameters set in the OSD menu.

[0024] In a second aspect, the present application provides an image display method, the method comprising:

[0025] Receive SDI signal;

[0026] In response to the SDI signal, acquiring parameter information in the SDI signal, and converting the SDI signal into a DP signal, the parameter information including VPID information;

[0027] Obtaining EOTF parameters in the VPID information;

[0028] Generate a backlight adjustment signal according to the EOTF parameter, and convert the DP signal into a VB1 signal;

[0029] generating backlight data corresponding to the VB1 signal, and adjusting the backlight data according to the backlight adjustment signal;

[0030] An image corresponding to the SDI signal is generated and displayed according to the VB1 signal and the adjusted backlight data.

[0031] In some embodiments, obtaining the EOTF parameters in the VPID information includes: parsing the VPID information according to the SMPTE protocol to obtain the EOTF parameters.

[0032] In some embodiments, converting the DP signal into a VB1 signal includes: performing signal format conversion on the DP signal, and performing image data processing on the converted signal according to the parameter information to obtain the VB1 signal.

[0033] In some embodiments, generating a backlight adjustment signal according to the EOTF parameter includes:

[0034] generating an interrupt level according to a change in the EOTF parameters;

[0035] The EOTF parameters are read multiple times in response to the interrupt level, and a backlight adjustment signal is generated based on the EOTF parameters read multiple times being consistent and different from the EOTF parameters stored last time.

[0036] In some embodiments, the VPID information includes resolution, refresh rate, scan mode, color space, EOTF parameters, signal range, bit depth, and sampling structure.

[0037] In a second aspect, the present application provides an image display method, the image display method comprising:

[0038] Receive SDI signal;

[0039] In response to the SDI signal, acquiring parameter information in the SDI signal, and converting the SDI signal into a DP signal, the parameter information including VPID information;

[0040] Obtaining EOTF parameters in the VPID information;

[0041] Generate a backlight adjustment signal according to the EOTF parameter, and convert the DP signal into a VB1 signal;

[0042] generating backlight data corresponding to the VB1 signal, and adjusting the backlight data according to the backlight adjustment signal;

[0043] An image corresponding to the SDI signal is generated and displayed according to the VB1 signal and the adjusted backlight data.

[0044] In some embodiments, obtaining the EOTF parameters in the VPID information includes:

[0045] Get the SMPTE protocol corresponding to the data format of the SDI signal;

[0046] The VPID information in the SDI signal is parsed according to the SMPTE protocol to obtain EOTF parameters.

[0047] In some embodiments, converting the DP signal into a VB1 signal includes: performing signal format conversion on the DP signal, and performing image data processing on the converted signal according to the parameter information to obtain the VB1 signal.

[0048] In some embodiments, generating a backlight adjustment signal according to the EOTF parameter includes:

[0049] generating an interrupt level according to a change in the EOTF parameters;

[0050] The EOTF parameters are read multiple times in response to the interrupt level, and a backlight adjustment signal is generated based on the EOTF parameters read multiple times being consistent and different from the EOTF parameters stored last time.

[0051] In some embodiments, obtaining parameter information in the SDI signal includes obtaining resolution, refresh rate, scanning mode, color space, EOTF parameters, signal range, bit depth and sampling structure in the SDI signal.

[0052] The monitor and image display method provided by this application have the following beneficial effects:

[0053] The monitor of the embodiment of the present application includes an SDI signal processing module, an EOTF processing module, a Scale signal processing module, a backlight control module, and a display processing module. The SDI signal processing module can automatically identify the VPID information in the SDI signal, and the EOTF processing module can parse the EFTO parameter in the VPID information. The Scale signal processing module can obtain the VB1 signal corresponding to the SDI signal based on the VPID information, and obtain the backlight adjustment signal based on the EFTO parameter. The backlight control module can obtain backlight data based on the backlight adjustment signal, and send the VB1 signal and backlight data to the display processing module to display the image corresponding to the SDI signal on the monitor. The embodiment of the present application enables the monitor to automatically identify the VPID information in the SPI signal, automatically configure based on the identified VPID information to generate the image corresponding to the SDI signal, and the displayed image restores the image of the video source with high accuracy. The present application reduces the difficulty of operating the monitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the implementation methods in the embodiments of the present application or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technology descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0055] Figure 1 Schematic diagram showing an overall structure of a monitor according to some embodiments;

[0056] Figure 2 Schematic diagram of the hardware architecture of a monitor according to some embodiments is exemplarily shown in FIG.

[0057] Figure 3 Schematic diagram of the software architecture of a monitor according to some embodiments is exemplarily shown in FIG.

[0058] Figure 4 hereinafter is a flow chart showing an image display method for a monitor according to some embodiments;

[0059] Figure 5 hereinafter is a flow chart showing a backlight adjustment method according to some embodiments;

[0060] Figure 6 Schematic diagrams of stacked screens according to some embodiments are exemplarily shown in FIG.

[0061] Figure 7 hereinafter is a flow chart showing an image display method for a monitor according to some embodiments;

[0062] Figure 8 hereinafter is a schematic diagram showing a flow chart of backlight adjustment according to some embodiments;

[0063] Figure 9 hereinafter is a schematic diagram showing a flow chart of backlight adjustment according to some embodiments;

[0064] Figure 10 Schematic diagram of the backlight adjustment process according to some embodiments is exemplarily shown in FIG. DETAILED DESCRIPTION

[0065] In order to make the purpose and implementation of this application clearer, the exemplary implementation of this application will be clearly and completely described below in conjunction with the drawings in the exemplary embodiments of this application. Obviously, the described exemplary embodiments are only part of the embodiments of this application, not all of the embodiments.

[0066] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.

[0067] In the specification and claims of this application and the accompanying drawings, the terms "first," "second," "third," etc. are used to distinguish similar or similar objects or entities, and are not necessarily intended to limit a particular order or sequence, unless otherwise noted. It should be understood that the terms used in this manner are interchangeable under appropriate circumstances.

[0068] The terms "comprise," "include," and "have," and any variations thereof, are intended to cover but not exclude inclusion; for example, a product or device comprising a list of components is not necessarily limited to all the components expressly listed but may include other components not expressly listed or inherent to such product or device.

[0069] To solve the technical problem that the monitor cannot automatically identify the VPID, this application provides a monitor, see Figure 1The monitor may include an SDI signal processing module 1, an EOTF (Electrical-Optical Transfer Function) processing module 2, a Scaler (display-specific chip) signal processing module 3, a backlight control module 4 and a display processing module 5.

[0070] For ease of description, the SDI signal processing module 1 can be referred to as module ①, the EOTF processing module 2 can be referred to as module ②, the Scaler signal processing module 3 can be referred to as module ③, the backlight control module 4 can be referred to as module ④, and the display processing module 5 can be referred to as module ⑤.

[0071] See also Figure 2 In some embodiments, module ① includes an SDI Input (SDI input unit), an SDI Output (SDI output unit), an SDI Driver (driver), an FPGA (Field Programmable Gate Array) unit, and a DP (DisplayPort) unit, wherein the FPGA unit of module ① may be referred to as the first FPGA, including a Logic IP Core (Logic Internet Protocol) and an HDR (High Dynamic Range Imaging) Core, and the DP unit includes a DP (DisplayPort) Core.

[0072] The SDI signal input to module ① can be 3G-SDI, 6G-SDI, 12G-SDI, or other SDI signals. After the SDI signal enters module ① via the SDI input unit, it is first identified by the SDI driver. Once the SDI driver recognizes the input signal as an SDI signal, it is processed in two ways: First, the SDI driver sends the unprocessed SDI signal directly to the FPGA unit. Second, the SDI driver outputs the unprocessed SDI signal directly through the SDI terminal, thereby cascading the current monitor to the next-level monitor. The FPGA unit processes the SDI signal through its internal LogicIP Core, HDR Core, and other cores before outputting it to the DP Core to generate a DP signal. The DP Core then outputs the DP signal to the next level. The DP signal can be a 4K 60Hz signal.

[0073] In some embodiments, module ② includes a microprocessor unit, which can be referred to as a first MCU. The first MCU is provided with an SPI (Serial Peripheral Interface) interface and an I2C (Inter-Integrated Circuit) interface.

[0074] The first MCU can communicate with the HDR Core in the FPGA unit through the SPI interface to automatically read the EOTF (Electrical-Optical Transfer Function) in the SPI signal. The value of the EOTF can also be called the GAMMA value.

[0075] The first MCU can communicate with the microprocessor unit of module ③ through the I2C interface to manually set the EOTF parameters and exchange configuration information.

[0076] In some embodiments, module ③ includes a keypad (input key), a second MCU, a scaler unit and a VB1 (display interface) Core, wherein the second MCU is a microprocessor unit of module ③, and the scaler unit includes a scaler chip.

[0077] The keypad is a user operation interface that can receive user operation instructions. The operation instructions are statistically and logically processed by the second MCU, and instructions are sent to read and control the Scaler chip. The second MCU also generates a corresponding output signal based on the EOTF transformation of the input signal; the DP signal output by module ① is received by the Scaler chip, which can perform signal conversion, signal processing, image quality processing and other processes on the DP signal, and send the processed signal to module ④ for processing through the physical interface of VB1Core.

[0078] In some embodiments, module ④ includes a second FPGA unit, which is respectively connected to the second MCU of VB1Core in module ③, receives the image data output by VB1Core, performs backlight calculation based on the output signal of the second MCU, obtains backlight data, and sends the backlight data to module ⑤.

[0079] In some embodiments, module ⑤ includes a BLU (Basic Link Unit, backlight unit) unit, a TCON (timing controller, timing controller) unit and a Panel unit.

[0080] The TCON unit is used to perform logic control on the display timing of the VB1 signal, and the BLU unit is used to control the backlight brightness of the display partition.

[0081] To illustrate the working principle of the monitor provided in the embodiment of the present application, Figure 3 A schematic diagram of the software architecture of a monitor according to some embodiments is shown. Figure 3 In the example, the SDI_IP of module ① is Figure 2 The SDI Input in module ① is the Logic_IP Figure 2 The Logic IP Core in module 1 is HDR_IP. Figure 2 HDR Core in the module ①, DP_out_IP is Figure 2 DP Core in module ②, EOTF_MCU is Figure 2 The first MCU in the module is the Scale_MCU in module ③. Figure 2 The second MCU in module ③ is the Scale_core Figure 2 The Scale chip in module ③ is Display_core. Figure 2 VB1Core in module ④ is the FPGA Figure 2 The second FPGA in the.

[0082] a~o refer to the transmission data at different stages.

[0083] In some embodiments, the input of the SDI_IP of module ① is data a, which can be an SDI signal of different formats. For example, a can be an SDI signal in HD / 3G / 6G / 12G format, that is, a can be an HD-SDI signal or a 3G-SDI signal or a 6G-SDI signal or a 12G-SDI signal, and the mode can be Single or Quadlink. SDI_IP can extract data b from the SDI signal, and data b can include resolution (Resolution), refresh rate (Picture Rate), scan mode (Scan mode), VPID raw data and other signal auxiliary information, and send the SDI signal and signal auxiliary information to Logic_IP (i.e. Figure 2 LogicIP Core in the .

[0084] Exemplarily, the signal auxiliary information extracted by SDI_IP includes: 1. Resolution: 3840*2160; 2. Resolution: 60Hz; 3. Scan mode: Progressive (line-by-line scanning); 4. VPID: CE DB A0 01, where CEDB A0 01 is the VPID original data, and Logic_IP needs to parse the VPID original data to obtain its meaning.

[0085] In some embodiments, the input of the Scale_MCU of module ③ is c, which can be an OSD (On Screen Display) menu control. The OSD menu control can configure VPID AUTO (VPID status) to ON / OFF.

[0086] When VPID AUTO is configured as OFF, the data sent by Scale_MCU to the Logic_IP of module ① is d1. When VPID AUTO is configured as ON, the data sent by Scale_MCU to the Logic_IP of module ① is d2. The parameters in d2 are the same as those in b.

[0087] Exemplarily, d1 is: VPID AUTO: OFF Config Parameter: 1. RGB / YCC range; 2. Color Space; 3. Transfer Matrix; 4. EOTF.

[0088] d2 is: VPID AUTO: ON Config Parameter: 1. Resolution: 3840*2160; 2. Resolution: 60Hz; 3. Scan mode: Progressive (line-by-line scan); 4. VPID (CE DB A0 01).

[0089] When VPID AUTO is configured to ON, the data Scale_MCU sends to the Logic_IP of module ① is d1. When VPID AUTO is configured to ON, the data Scale_MCU sends to the Logic_IP of module ① is d2. The parameters in d2 are the same as those in b.

[0090] For example, d1 is: VPID AUTO: OFF Config Parameters: 1. RGB / YCC range; 2. Color Space; 3. Transfer Matrix; 4. EOTF. d2 is: VPID AUTO: ON Config Parameters: 1. Resolution: 3840*2160; 2. Resolution: 60Hz; 3. Scan mode: Progressive; 4. VPID (CE DB A0 01).

[0091] In some embodiments, Scale_MCU also sends data f to EOTF_MCU of module ②. Data f may be: Config EOTF (Configure EOTF), so that EOTF_MCU configures EOTF.

[0092] In some embodiments, referring to Table 1, Logic_IP and Scale_MCU perform different data processing when the VPID function is on or off, respectively.

[0093] Table 1

[0094]

[0095] For example, the data e can be: VPID OK / NG 1. Color Space OK: (ITU-R BT.2020) NG: (ITU-R BT.709); 2. EOTF OK: (ITU-R BT.2100 (HLG)) NG: EOTF: 2.4 (SDR); 3. GB / YCC angle OK: (YCC-Limited) NG: (Limited); 4-Bit Depth OK: (10-Bit) NG: (10-Bit); 5. Scan mode (Progressive). OK indicates that VPID Auto is on, and NG indicates that VPID Auto is off.

[0096] The data g can be: Get Parameter 1, RGB / YCC Range; 2, Color Space; 3, TansferMatrix; 4, EOTF.

[0097] Data h can be: Config PQ Data.

[0098] Data i can be: Config Parameter 1, RGB / YCC Range; 2, Color Space; 3, TansferMatrix; 4, EOTF.

[0099] In some embodiments, HDR_IP parses the SDI signal and obtains HDR data as data j. For example, j is HDR_IP 1. Color Space (ITU-R BT.2020); 2. EOTF (ITU-R BT.2100 (HLG)); 3. RGB / YCC (YCC-Limited); 4. Bit Depth (10 Bit); 5. Sampling Structure (YCbCr 422); and 6. Color Temp (D65).

[0100] In some embodiments, HDR_IP parses the SDI signal, combines the parsed parameters with the parameters sent by Logic_IP, and sends them to DP_OUT_IP. DP_OUT_IP, based on the front-end signal parsing and the combined parameters, ultimately outputs data k to DP_IN_IP in module ③. DP_IN_IP in module ③ then sends the received data to Scaler_core in module ③. As shown in Table 2, data k can be a combination of the following parameters:

[0101] Table 2

[0102]

[0103] In some embodiments, after receiving the DP signal, the Scaler_core of module ③ will perform operations such as signal format, system Gamma, image quality adjustment, and EOTF adjustment, and will eventually send out the display image signal through the VB1 interface of the Display_core.

[0104] In some embodiments, after receiving the image signal data to be displayed from VB1, the FPGA of module ③ calculates the backlight data using a specific algorithm and sends it to Panel2 (stacked screen). At the same time, it bypasses the image data of VB1 to the TCON end and finally displays it on Panel1 (stacked screen).

[0105] In some embodiments, the Scaler_mcu of module ③ parses the VPID value read from the Logic_IP and, according to the following SMPTE protocol, for SDI signals of different input formats (HD / 3G / 6G / 12G / Single / Quadlink), references different protocol documents, and parses a list of values including EOTF, as shown in Table 3:

[0106] Table 3

[0107]

[0108] The parsed parameters of Scaler_mcu are shown in Table 4:

[0109] Table 4

[0110]

[0111]

[0112] In some embodiments, due to the characteristics of the panel itself, the color temperature of the panel will change at different brightness levels. The Gamma parameter values at different brightness levels will be debugged during the factory production stage. During the signal input process, when the EOTF changes, the Scaler_mcu will call out the parameters set in the factory production stage and set the backlight value corresponding to the new EOTF.

[0113] based on Figure 2 The hardware architecture of the monitor shown and Figure 3 The software architecture of the monitor shown in FIG. 1 is used to display an image of the monitor. Figure 4 As shown, the method may include the following steps:

[0114] Step S101: Receive SDI signal.

[0115] In some embodiments, after the monitor is connected to the device where the SDI video source is located, module ① of the monitor can receive the video signal of the SDI video source, which can be an SDI signal such as a 3G-SDI signal, a 6G-SDI signal, or a 12G-SDI signal.

[0116] Step S102: In response to the SDI signal, obtain parameter information in the SDI signal, and convert the SDI signal into a DP signal, wherein the parameter information includes VPID information.

[0117] In some embodiments, after module ① receives the SDI signal, the SDI input unit can extract information such as resolution, refresh rate, scan mode, VPID, etc. from the SDI signal, and send the parameter information and the SDI signal to the Logic IP Core for processing.

[0118] The Logic IP Core can interact with the first MCU of module ② to obtain the current VPID status. If the VPID status is automatic, the Logic IP Core parses the VPID data and sends the parsed data and previously extracted parameter information to the HDR Core for processing.

[0119] The HDR Core performs HDR processing based on the data sent by the Logic IP Core according to the VPID status of Automatic, obtains the color space, bit depth, sampling standard, color standard and other data of the SDI signal, and sends the newly extracted data and the previously extracted data to the DP Core.

[0120] Step S103: Acquire EOTF parameters in the VPID information.

[0121] In some embodiments, the first MCU of module ② interacts with the HDR Core to obtain data parsed by the HDR Core according to the VPID status being automatic, obtains EOTF parameters based on the data parsed by the HDR Core and performs parameter calculations, and feeds back the data after parameter calculation to the HDR Core, so that the HDR Core sends the data after parameter calculation to the DP Core.

[0122] In some embodiments, the DP Core converts the SDI signal into a DP signal in DP format, and sends the received parameter data and DP signal to the scale chip of module ③.

[0123] Step S104: generating a backlight adjustment signal according to the EOTF parameters, and converting the DP signal into a VB1 signal;

[0124] In some embodiments, the scale chip of module ③ processes the DP signal in signal format, image quality adjustment, EOTF adjustment, etc. to obtain a VB1 signal, and sends the VB1 signal to the second FPGA of module ④.

[0125] In some embodiments, the second MCU of module ③ reads the EOTF parameters from module ②, generates a backlight adjustment signal based on the mapping relationship between the preset EOTF parameter values and the backlight value, and sends the backlight adjustment signal to the second FPGA of module ④, where the backlight adjustment signal includes the backlight value.

[0126] In some embodiments, the method for generating the backlight adjustment signal can also be found in Figure 5 , including steps S201-S202.

[0127] Step S201: generating an interrupt level according to the change of the EOTF parameters.

[0128] In some embodiments, the second MCU of module ③ and the FPGA unit of module ① are also connected via GPIO, and the FPGA unit is configured to set the level of the GPIO connection interface to an interrupt level when a change in the EFTO parameter is detected, thereby notifying the second MCU of module ③ that a change in the EFTO parameter has occurred.

[0129] Step S202: reading the EOTF parameters multiple times in response to the interrupt level, and generating a backlight adjustment signal based on the EOTF parameters read multiple times being consistent and different from the EOTF parameters stored last time.

[0130] In some embodiments, the second MCU of ③ can read the VPID information multiple times according to the interrupt level to obtain the EOTF parameters, generate a backlight adjustment signal based on the EOTF parameters read multiple times being consistent and different from the EOTF parameters stored last time, and store the latest EOTF parameters for calling when the EOTF parameters need to be compared next time.

[0131] Step S105: generating backlight data corresponding to the VB1 signal, and adjusting the backlight data according to the backlight adjustment signal.

[0132] In some embodiments, after the second FPGA of module ④ receives the VB1 signal, it calculates the backlight data according to the VB1 signal, and then adjusts the backlight data according to the backlight adjustment signal to obtain the adjusted backlight data, and sends the adjusted backlight data and the VB1 signal to module ⑤.

[0133] Step S106: generating and displaying an image corresponding to the SDI signal according to the VB1 signal and the adjusted backlight data.

[0134] In some embodiments, module ⑤ superimposes the image data of the VB1 signal and the adjusted backlight data to obtain an image corresponding to the SDI signal. The superposition method can be a stacking method, see Figure 6 The stacked screen 1 is a screen layer for displaying the image data corresponding to the VB1 signal, and the stacked screen 2 is a screen layer for displaying the backlight.

[0135] To further illustrate the VPID automatic identification method provided in the embodiment of the present application, Figure 7 A flow chart of a method for displaying an image on a monitor is also shown. Figure 7 As shown, the method may include the following steps:

[0136] Step S301: SDI signal input.

[0137] In some embodiments, after the SDI Input of the monitor is connected to a video source, it can receive an SDI signal from the video source.

[0138] Step S302: SDI_IP_CORE parses the SDI signal.

[0139] In some embodiments, the SDI Input of module ① is provided with SDI_IP_CORE, which parses the SDI signal to obtain information such as resolution, refresh rate, scan mode, and VPID.

[0140] Step S303: OSD sets SDI channel parameters.

[0141] Step S304: Scale_MCU determines whether to start VPID automatic identification.

[0142] In some embodiments, the monitor is equipped with a VPID switch that the user can turn on or off. If the user turns on the VPID switch, the OSD sets the VPID AUTO state to OFF in response to the user operation. Otherwise, it is set to ON. Based on the VPID AUTO state, the Scale_MCU can determine whether the VPID switch is on.

[0143] Step S305: If yes, Scale_MCU sends a VPID switch status instruction to Logic IP.

[0144] In some embodiments, based on the VPID switch being turned on, the Scale_MCU sends a VPID switch status instruction to the Logic IP, which is a VPID on instruction. The instruction indicates that the VPID switch is turned on and the VPID needs to be automatically identified and configured.

[0145] In some embodiments, based on the VPID switch being turned off, the Scale_MCU sends a VPID switch status instruction to the Logic IP, which is a VPID off instruction. The instruction indicates that the VPID switch is turned off and the VPID needs to be configured according to a preset value.

[0146] Step S306: If not, Scale_MCU sets image parameters.

[0147] In some embodiments, the Scale_MCU sets the image parameters of the monitor to default values or image parameters input by the user according to the VPID switch being turned off.

[0148] Step S307: Scale_MCU sets the preset value parameters of the SDI signal through the OSD menu.

[0149] In some embodiments, the Scale_MCU obtains the preset value parameters of the SDI signal set in the OSD menu based on whether the VPID switch is turned off, and sets the preset value parameters as the preset value parameters of the currently input SDI signal. The preset value parameters of the SDI signal set in the OSD menu can be default values or preset value parameters entered by the user.

[0150] Step S308: Scale_MCU sets EOTF parameters.

[0151] In some embodiments, the Scale_MCU retrieves the EOTF set in the OSD menu based on whether the VPID switch is off and sets it as the EOTF of the currently input SDI signal. The EOTF set in the OSD menu can be a default parameter or a user-entered EOTF. The Scale_MCU notifies the EOTF_MCU of the set EOTF via I2C.

[0152] Step S309: EOTF_MCU configures EOTF parameters.

[0153] In some embodiments, the EOTF_MCU configures EOTF parameters according to the EOTF set by the Scale_MCU.

[0154] Step S310: The Logic IP determines whether the VPID is automatically identified.

[0155] In some embodiments, the Logic IP determines that the VPID of the currently input SDI signal needs to be automatically identified if the VPID switch status instruction sent by the Scale_MCU is a VPID on instruction; otherwise, it determines that the VPID of the currently input SDI signal does not need to be automatically identified.

[0156] Step S311: If yes, the Logic IP parses the VPID information.

[0157] In some embodiments, if the Logic IP determines that automatic VPID identification is required, the VPID in the SDI signal is automatically parsed.

[0158] Step S312: If not, obtain the stored image parameters.

[0159] In some embodiments, if the Logic IP determines that automatic VPID identification is not required, the stored image parameters sent by the Scale_MCU are obtained.

[0160] Step S313: HDR_CORE parses the VPID information.

[0161] In some embodiments, HDR_CORE performs HDR processing on the SDI signal to obtain HDR parameters, combines the HDR parameters with the parameters obtained in the previous step, and sends them to DP_CORE_OUT of module ①.

[0162] Step S314: DP_CORE_OUT outputs the DP signal.

[0163] In some embodiments, the DP_CORE_OUT of module ① transmits all parameters of the received SDI signal to the DP_CORE_IN of module ③.

[0164] Step S315: DP_CORE_IN inputs the DP signal.

[0165] In some embodiments, the DP_CORE_IN of module ③ passes the received data to the Scaler.

[0166] Step S316: Scale_MCU obtains VPID information.

[0167] In some embodiments, the Scale_MCU automatically recognizes the state as on based on the VPID and reads the VPID of the SPI signal.

[0168] Step S317: Scale_MCU parses the VPID information.

[0169] In some embodiments, the Scale_MCU parses the VPID according to the protocol document of the VPID to obtain data as shown in Table 4.

[0170] Step S318: Display backlight.

[0171] In some embodiments, the Scale_MCU may generate corresponding backlight data according to the EOTF value in the parsing result of the VPID, and control the display panel to display backlight according to the backlight data.

[0172] Step S319: Scale_MCU sets GAMMEA parameters.

[0173] In some embodiments, the VPID is also used to enable the Scale_MCU to set the GAMMEA (EOTF) parameters.

[0174] Step S320: Scale the output image data.

[0175] In some embodiments, Scale adjusts the image quality according to the obtained image quality parameters to obtain image data, and outputs the image data to the display panel.

[0176] Step S321: Display the image.

[0177] In some embodiments, the display panel displays a corresponding image according to the received image data.

[0178] In some embodiments, the backlight adjustment method can be found in Figure 8 , including the following steps:

[0179] Step S401: The EOTF parameters of the input signal change.

[0180] In some embodiments, the input signal is an SDI signal from a video source. At different times, the EOTF parameters in the SDI signal may be different.

[0181] Step S402: The Logic Core parses the VPID information.

[0182] In some embodiments, the Logic Core of the first FPGA unit can automatically identify the VPID as being in the on state, analyze the VPID information in the SDI signal, and convert the SDI signal into a DP signal after being processed by the Logic Core, HDR Core, and DP Core and output to the Scale unit.

[0183] Step S403: Scale generates image data according to the parsed VPID information.

[0184] In some embodiments, Scale_MCU can automatically identify the state as on based on VPID, control the Scale unit to read the parsed VPID information, and perform signal format conversion, signal processing, image quality processing and other processes on the DP signal based on the parsed VPID information to obtain image data in VB1 format, that is, VB1 signal.

[0185] Step S404: Scale transmits the image data to the display panel for display.

[0186] In some embodiments, the Scale unit transmits the obtained image data to the second FPGA via the VB1 Core, and the second FPGA transmits the image data to the display panel for display.

[0187] Step S405: Scale controls the display panel to perform backlight display.

[0188] In some embodiments, the second FPGA performs backlight calculation according to the scene to obtain backlight data. If a backlight adjustment signal is received, the backlight data is adjusted according to the backlight adjustment signal and the adjusted backlight data is sent to the display panel for display.

[0189] Step S501: Scale_MCU reads VPID information from the EOTF processing module via I2C.

[0190] In some embodiments, the Scale_MCU automatically identifies the VPID as being in the on state and reads the VPID information of the SDI signal from the EOTF module via I2C at regular intervals. The EOTF module interacts with the HDR Core of the first FPGA to obtain the VPID information, which is information parsed by the Logic Core and the HDR Core.

[0191] Step S502: Scale_MCU determines whether the EOTF parameters have changed.

[0192] In some embodiments, after obtaining the VPID information, the Scale_MCU extracts the EOTF parameters from the VPID information and determines whether the EOTF parameters are consistent with the EOTF parameters read last time.

[0193] Step S503: If yes, Scale_MCU generates a backlight adjustment signal.

[0194] In some embodiments, if Scale_MCU detects that the EOTF parameters read twice are inconsistent, it obtains the backlight value corresponding to the current EOTF parameter according to the mapping relationship table between EOTF parameters and backlight values, and generates a backlight adjustment signal including the backlight value.

[0195] Depend on Figure 8 It can be seen that Scaler_mcu has been obtaining the EOTF parameters of the SDI signal through queries. In the scenario where the EOTF parameters of the SDI signal change rapidly, if the query frequency is too fast, it will occupy a large amount of CPU resources, causing delays in the execution of other processes and affecting the overall performance of the system. If the query frequency is too slow, the backlight adjustment will lag behind the display of the image data, causing the screen to flicker.

[0196] In order to improve the timeliness of backlight adjustment, the embodiment of the present application also provides a backlight adjustment solution. In this solution, a physical GPIO connection line is set between the Scaler_mcu and the Logic Core of the first FPGA, so that the Scaler_mcu can be informed of EOTF changes in a timely manner. The method for the Scaler_mcu to be informed of EOTF changes can be found in Figure 9 , including the following steps:

[0197] Step S601: The EOTF parameters of the input signal change.

[0198] In some embodiments, the input signal is an SDI signal from a video source. At different times, the EOTF parameters in the SDI signal may be different.

[0199] Step S602: The Logic Core parses the VPID information.

[0200] In some embodiments, the Logic Core of the first FPGA unit can automatically identify the VPID as being in the on state, analyze the VPID information in the SDI signal, and convert the SDI signal into a DP signal after being processed by the Logic Core, HDR Core, and DP Core and output to the Scale unit.

[0201] In some embodiments, after the Logic Core detects that the EOTF parameters have changed, it immediately triggers the interrupt level of the GPIO interface of the Logic Core, so that the Scale_MCU receives the GPIO interrupt signal.

[0202] Step S603: Scale generates image data according to the parsed VPID information.

[0203] In some embodiments, Scale_MCU can automatically identify the state as on based on VPID, control the Scale unit to read the parsed VPID information, and perform signal format conversion, signal processing, image quality processing and other processes on the DP signal based on the parsed VPID information to obtain image data in VB1 format, that is, VB1 signal.

[0204] Step S604: Scale controls the display panel to perform backlight display.

[0205] In some embodiments, the second FPGA performs backlight calculation according to the scene to obtain backlight data. If a backlight adjustment signal is received, the backlight data is adjusted according to the backlight adjustment signal and the adjusted backlight data is sent to the display panel for display.

[0206] Step S605: Scale transmits the image data to the display panel for display.

[0207] In some embodiments, the Scale unit transmits the obtained image data to the second FPGA via the VB1 Core, and the second FPGA transmits the image data to the display panel for display.

[0208] Step S701: Scale_MCU detects a GPIO interrupt signal.

[0209] In some embodiments, the Scale_MCU may initiate a backlight adjustment process based on a GPIO interrupt signal received from the Logic Core.

[0210] Step S702: Scale_MCU determines whether multiple readings of VPID information have been completed.

[0211] In some embodiments, upon receiving a GPIO interrupt signal, the Scale_MCU can repeatedly read the VPID information multiple times within a specified time period to prevent incorrect readings that could trigger subsequent actions. For example, the Scale_MCU can read the VPID information three times and determine whether the three read results are consistent.

[0212] Step S703: Scale_MCU reads VPID information via I2C.

[0213] In some embodiments, if Scale_MCU determines that a GPIO interrupt occurs, it immediately reads the VPID information from the EFTO processing module via I2C.

[0214] Step S704: Scale_MCU determines whether the VPID information is the same as the previous one.

[0215] In some embodiments, after reading the VPID information, the Scale_MCU may determine that the VPID information read multiple times in this round is the same. If the multiple reading results are the same, the reading result is valid. If at least one reading result is inconsistent with the other reading results, the reading result is invalid and the current backlight adjustment process ends.

[0216] Step S705: If yes, store the changed data.

[0217] In some embodiments, Scale_MCU stores the changed data in the VPID information to update the VPID information for future use when analyzing the VPID information.

[0218] Step S706: Scale_MCU determines whether the EOTF parameters have changed.

[0219] In some embodiments, when storing the VPID information, it may be determined whether the EOTF parameters in the VPID information are the same as the EOTF parameters in the VPID information stored in the previous backlight adjustment process.

[0220] Step S707: If yes, Scale_MCU generates a backlight adjustment signal.

[0221] In some embodiments, if the EOTF parameters change, the Scale_MCU generates a backlight adjustment signal according to the latest EOTF parameters, and then sends the backlight adjustment signal to the Scale unit for use by the Scale unit in backlight display.

[0222] In some embodiments, if the EOTF parameters do not change, the current round of backlight adjustment ends.

[0223] Depend on Figure 9 It can be seen that when the Logic core of the first FPGA reads the EOTF optimization, it immediately triggers the interrupt level. Scaler_mcu receives the interrupt and immediately reads the EOTF parameters through I2C. It reads multiple times within the specified time to prevent false triggering. This may cause the backlight adjustment to precede the display change of the image data. By setting the delay time, the backlight adjustment can be synchronized with the display of the image data, such as Figure 10As shown, for example, a delay can be set in any step from step S701 to step S707, so that the backlight adjustment signal of step S707 is delayed to reach the Scale unit, and finally step S605 and step S605 are executed simultaneously, thereby improving the synchronization of the image data and the backlight data displayed on the display panel.

[0224] As can be seen from the above embodiments, the monitor of the embodiment of the present application includes an SDI signal processing module, an EOTF processing module, a Scale signal processing module, a backlight control module, and a display processing module. The SDI signal processing module can automatically identify the VPID information in the SDI signal, and the EOTF processing module can parse the EFTO parameter in the VPID information. The Scale signal processing module can obtain the VB1 signal corresponding to the SDI signal based on the VPID information, and obtain the backlight adjustment signal based on the EFTO parameter. The backlight control module can obtain backlight data based on the backlight adjustment signal, and send the VB1 signal and backlight data to the display processing module to display the image corresponding to the SDI signal on the monitor. The embodiment of the present application enables the monitor to automatically identify the VPID information in the SPI signal, and automatically configures itself based on the identified VPID information to generate the image corresponding to the SDI signal. The displayed image restores the image of the video source with high accuracy, and the present application reduces the difficulty of operating the monitor.

[0225] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

[0226] For ease of explanation, the above description has been made with reference to specific embodiments. However, the above exemplary discussion is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations are possible. The above embodiments are selected and described to better explain the principles and practical applications, so that those skilled in the art can better utilize the embodiments and various different variations of the embodiments suitable for specific use considerations.

Claims

1. A monitor, characterized in that: include: An SDI signal processing module is used to obtain parameter information in the SDI signal and convert the SDI signal into a DP signal, wherein the parameter information includes VPID information; An EOTF processing module, connected to the SDI signal processing module, configured to obtain EOTF parameters in the VPID information; A scaler signal processing module is connected to the SDI signal processing module and the EOTF processing module, and is used to control the EOTF processing module to perform EOTF configuration, generate a backlight adjustment signal according to the EOTF parameters, and convert the DP signal into a VB1 signal; a backlight control module connected to the Scaler signal processing module, configured to generate backlight data corresponding to the VB1 signal and adjust the backlight data according to the backlight adjustment signal; The display processing module is used to generate and display an image corresponding to the SDI signal according to the VB1 signal and the adjusted backlight data.

2. The monitor according to claim 1, wherein The SDI signal processing module includes: An SDI input unit, configured to receive the SDI signal and obtain signal auxiliary information in the SDI signal; An SDI driving unit, connected to the SDI input unit, configured to identify the SDI signal and send the SDI signal to the FPGA unit; The FPGA unit is connected to the SDI driving unit and is used to parse the signal auxiliary information, obtain the parameter information, and send the SDI signal to the DP unit; The DP unit is connected to the FPGA unit and is used to convert the SDI signal into a DP signal.

3. The monitor according to claim 2, wherein: The scaler signal processing module is connected to the FPGA unit. The FPGA unit is configured to trigger an interrupt level connected to the scaler signal processing module according to a change in the EOTF parameter. The scaler signal processing module is configured to read the EOTF parameter according to the interrupt level.

4. The monitor according to claim 1, wherein The Scaler signal processing module includes: User operation interface, used to receive user operation instructions; a processor unit connected to the user operation interface, and configured to communicate with the EOTF processing module and the Scale unit respectively according to the user operation interface; The scale unit is connected to the processor unit and the SDI signal processing module, and is used to process the DP signal according to the control instruction of the processor unit to obtain the VB1 signal; The VB1 processing unit is connected to the Scale unit and is used to send the VB1 signal to the backlight control module.

5. The monitor according to claim 4, wherein: The processor unit is configured to: If the operation instruction is to start VPID identification, sending a first EOTF instruction to the EOTF processing module, so that the EOTF processing module parses EOTF parameters in the VPID information and configures a monitor according to the EOTF parameters; If the operation instruction is to turn off VPID identification, obtain the EOTF parameters set in the OSD menu, send a second EOTF instruction to the EOTF processing module, so that the EOTF processing module does not parse the EOTF parameters in the VPID information, and configure the monitor according to the EOTF parameters set in the OSD menu.

6. An image display method, used for the monitor according to any one of claims 1 to 5, characterized in that: include: Receive SDI signal; In response to the SDI signal, acquiring parameter information in the SDI signal, and converting the SDI signal into a DP signal, the parameter information including VPID information; Obtaining EOTF parameters in the VPID information; Generate a backlight adjustment signal according to the EOTF parameter, and convert the DP signal into a VB1 signal; generating backlight data corresponding to the VB1 signal, and adjusting the backlight data according to the backlight adjustment signal; An image corresponding to the SDI signal is generated and displayed according to the VB1 signal and the adjusted backlight data.

7. The image display method according to claim 6, wherein: Obtaining EOTF parameters in the VPID information includes: Get the SMPTE protocol corresponding to the data format of the SDI signal; The VPID information in the SDI signal is parsed according to the SMPTE protocol to obtain EOTF parameters.

8. The image display method according to claim 6, wherein: Converting the DP signal into a VB1 signal includes: performing signal format conversion on the DP signal, and performing image data processing on the converted signal according to the parameter information to obtain the VB1 signal.

9. The image display method according to claim 6, wherein: Generating a backlight adjustment signal according to the EOTF parameter, including: generating an interrupt level according to a change in the EOTF parameters; The EOTF parameters are read multiple times in response to the interrupt level, and a backlight adjustment signal is generated based on the EOTF parameters read multiple times being consistent and different from the EOTF parameters stored last time.

10. The image display method according to claim 6, wherein: The acquiring of parameter information in the SDI signal includes acquiring resolution, refresh rate, scanning mode, color space, EOTF parameters, signal range, bit depth and sampling structure in the SDI signal.

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