Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a substrate, a plurality of sub-pixels, a plurality of data lines, a control signal line, a data test line, a test circuit, and an auxiliary electrode line. The test circuit includes a plurality of test units, each of at least one of the plurality of test units includes a first control line and a plurality of control switches. The auxiliary electrode line and the first control line are connected in parallel with each other, and a part of at least one of the plurality of control switches is located between the orthographic projections of the first control line and the auxiliary electrode line on the surface of the substrate. The display substrate can reduce the impedance of the first control line and improve the transmission efficiency of the first control line.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] For OLED (Organic Light-Emitting Diode) display products, there are many types of circuit units, such as pixel circuits, gate driver circuits (Gate Driver on Array, GOA), data selection circuits (Multiplexer, MUX), and test circuits (Cell Test, CT), etc. Each circuit plays its own role in display. Among them, the test circuit unit, as a test circuit structure, detects whether the pixel units of the display product display normally and plays an important role in the panel test stage of the display product. Summary of the Invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a substrate, a plurality of sub-pixels, a plurality of data lines, control signal lines, a plurality of data test lines, a test circuit, and auxiliary electrode lines. The substrate includes a display area and a peripheral area at least on one side of the display area; the plurality of sub-pixels are located in the display area and are arranged in an array; the plurality of data lines are located in the display area and are configured to provide data signals to the plurality of sub-pixels; the control signal lines are located in the peripheral area and on at least one side of the display area; the plurality of data test lines are located in the peripheral area and on at least one side of the display area; the test circuit is located in the peripheral area and is electrically connected to the plurality of data lines, the control signal lines, and the plurality of data test lines, and is configured to transmit test signals to the plurality of data lines through the plurality of data test lines under the control of the control signal lines. Among them, the test circuit includes a plurality of test units, and each of at least one test unit in the plurality of test units includes a first control line and a plurality of control switches. The plurality of control switches include control ends, and the first control line, the control signal line, and the control ends of the plurality of control switches are connected; the auxiliary electrode line is located in the peripheral area and is connected in parallel with the first control line, and a part of at least one control switch in the plurality of control switches is located between the orthographic projections of the first control line and the auxiliary electrode line on the surface of the substrate.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first control line and the auxiliary electrode line are located in different layers with respect to the substrate, and the first control line and the auxiliary electrode line are respectively located in a first conductive layer and a second conductive layer that are insulated from each other and spaced apart.

[0005] For example, in the display substrate provided by at least one embodiment of the present disclosure, the auxiliary electrode line is located on one side of the test circuit away from the display area or on one side close to the display area.

[0006] For example, the display substrate provided by at least one embodiment of the present disclosure further includes an electrostatic discharge circuit disposed between the test circuit and the display area. The electrostatic discharge circuit is electrically connected to the plurality of data lines, and the auxiliary electrode line is located between the test circuit and the electrostatic discharge circuit.

[0007] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of connection lines. The plurality of connection lines are respectively disposed between the plurality of control switches. The first control line overlaps with the active layers of the plurality of control switches, and the overlapping portion of the first control line and the active layer forms the control terminals of the plurality of control switches. The first ends of the plurality of connection lines are connected to the first control line, and the second ends of the plurality of connection lines are connected to the auxiliary electrode line.

[0008] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of data test lines extend along a first direction and are spaced apart along a second direction on one side of the test circuit away from the display area. The first direction and the second direction intersect. The first ends of the plurality of control switches are respectively connected to the plurality of data test lines and are configured to receive test signals provided by the plurality of data test lines. The second ends of the plurality of control switches are respectively electrically connected to the plurality of data lines.

[0009] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of first lead segments and a plurality of data leads. The plurality of first lead segments and the plurality of data leads extend along the second direction. The plurality of first lead segments are respectively connected to the plurality of data test lines and the first ends of the plurality of control switches. The plurality of data leads are respectively connected to the second ends of the plurality of control switches and the plurality of data lines.

[0010] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of data leads include second lead segments. The plurality of second lead segments are respectively connected to the second ends of the plurality of control switches and the electrostatic discharge circuit. The plurality of first lead segments and the plurality of second lead segments are located in a third conductive layer. The third conductive layer is located between the first conductive layer and the second conductive layer and is insulated from each other. The orthographic projections of the plurality of second lead segments on the surface of the substrate and the orthographic projection of the auxiliary electrode on the surface of the substrate overlap each other.

[0011] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of data leads further include third lead segments, the third lead segments are located in the peripheral region and between the display region and the electrostatic discharge circuit, one ends of the plurality of third lead segments are electrically connected to the control end of the electrostatic discharge circuit, the other ends of the plurality of third lead segments are respectively connected to the plurality of data lines correspondingly, and the third lead segments are located in the third conductive layer.

[0012] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. Among them, the pixel driving circuit includes a semiconductor layer, a first display region metal layer, a second display region metal layer, and a third display region metal layer. The light-emitting element is located on the side of the pixel driving circuit away from the substrate, and is connected to the third display region metal layer of the pixel driving circuit. The first insulating layer is located on the substrate. The semiconductor layer is located on the side of the first display region metal layer close to the substrate. The second display region metal layer is located on the side of the first display region metal layer away from the substrate. The third display region metal layer is located on the side of the second display region metal layer away from the substrate. The first conductive layer is arranged on the same layer as the first display region metal layer. The third conductive layer is arranged on the same layer as the second display region metal layer. The second conductive layer is arranged on the same layer as the third display region metal layer. The active layers of the plurality of control switches are arranged on the same layer as the semiconductor layer. The plurality of connection lines are located in the first conductive layer, and the second ends of the plurality of connection lines are connected to the auxiliary electrode lines.

[0013] For example, in the display substrate provided by at least one embodiment of the present disclosure, the pixel driving circuit further includes a first transistor and a storage capacitor. The first transistor includes a gate, a source electrode, a drain electrode, and an active layer. The storage capacitor includes a first electrode plate and a second electrode plate. The active layer is located in the semiconductor layer. The gate and the first electrode plate are located in the first display region metal layer. The second electrode plate is located in the second display region metal layer. The source electrode and the drain electrode are located in the third display region metal layer.

[0014] For example, in the display substrate provided by at least one embodiment of the present disclosure, the test circuit further includes at least one virtual test unit. The at least one virtual test unit is located on the side of the test circuit away from the plurality of test units. The second conductive layer includes a plurality of first transfer electrodes. Each of the at least one virtual test unit includes a plurality of virtual control switches. The first ends of the plurality of virtual control switches are respectively connected to the plurality of data test lines correspondingly. The control ends of the plurality of virtual control switches are connected to the first control line. The plurality of transfer electrodes respectively connect the first ends and the second ends of the plurality of virtual control switches.

[0015] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a plurality of power supply lines, and the plurality of power supply lines are routed around at least one side of the display area. Among them, the plurality of power supply lines include a first power supply line and a second power supply line. The first power supply line is configured to provide a first power signal, and the second power supply line is configured to provide a second power signal. At least a part of the first power supply line and the second power supply line is located in the second conductive layer. The first power supply line is routed on the side of the electrostatic discharge circuit away from the display area, and the second power supply line is routed on the side of the electrostatic discharge circuit close to the display area. The first power supply line and the second power supply line are respectively connected to the first end and the second end of the electrostatic discharge circuit. The electrostatic discharge circuit includes a plurality of first electrostatic discharge units, and one end of the plurality of second lead segments away from the test circuit is respectively and correspondingly connected to the control ends of the plurality of first electrostatic discharge units.

[0016] For example, in the display substrate provided by at least one embodiment of the present disclosure, the test circuit and the electrostatic discharge circuit are located on the first side of the display area. The second side and the third side of the display area are oppositely arranged and adjacent to the first side. The plurality of data test lines include a first data test line, a second data test line, and a third data test line. At least a part of the first data test line and the second data test line are routed around the second side and the first side of the display area. The second data test line is located on the side of the first data test line close to the display area. At least a part of the third data test line and the control signal line are routed around the third side and the first side of the display area. The control signal line is located on the side of the third data test line close to the display area. On the side of the test circuit away from the display area, the second data test line is located between the first data test line and the third data test line, and the first data test line is located on the side away from the test circuit. The first conductive layer includes a first connection trace, and the first connection trace extends along the second direction. The semiconductor layer includes a plurality of first resistors. The first end of the control signal line is located on the first side of the display area and close to the test circuit. One end of the first connection trace is connected to the first end of the control signal line, and the other end of the first connection trace is connected to one end of the first control line close to the third side of the display area. The first ends of the first data test line and the second data test line are located on the side of the test circuit away from the display area. At least one of the plurality of first resistors connects the first end of the first data test line and the control signal line, and at least another of the plurality of first resistors connects the first end of the second data test line and the control signal line.

[0017] For example, in the display substrate provided by at least one embodiment of the present disclosure, at least one of the first data test line, the second data test line, the third data test line, the control signal line, and the first control line is connected to the electrostatic discharge circuit.

[0018] For example, in the display substrate provided by at least one embodiment of the present disclosure, the electrostatic discharge circuit further includes a second electrostatic discharge unit. The second electrostatic discharge unit is located on at least one side of the plurality of first electrostatic discharge units and on one side close to the third side of the display area. The first conductive layer includes a second connection trace and a third connection trace. The semiconductor layer includes a second resistor. One end of the second connection trace is connected to the control end of the second electrostatic discharge unit, and the other end of the second connection trace is connected to the first end of the control signal line. The second resistor connects the control end of the second electrostatic discharge unit and the first power supply line. The electrostatic discharge circuit further includes a third electrostatic discharge unit. The third electrostatic discharge unit is located on one side close to the third side of the display area of the second electrostatic discharge unit. One end of the third connection trace is connected to the third data test line, and the other end of the third connection trace is connected to the control end of the third electrostatic discharge unit.

[0019] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive layer further includes a fourth connection trace that extends along the second direction. The semiconductor layer includes a third resistor. The second conductive layer includes a second transfer electrode that extends along the first direction. The first end of the fourth connection trace is connected to one end of the first control line close to the second side of the display area, and the second end of the fourth connection trace is connected to the first end of the second transfer electrode. The first end of the third data test line is located on the side of the test circuit away from the display area, and the third resistor connects the second end of the second transfer electrode and the first end of the third data test line.

[0020] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive layer further includes a fifth connection trace. The electrostatic discharge circuit further includes a fourth electrostatic discharge unit. The fourth electrostatic discharge unit is located on one side close to the second side of the display area of the plurality of first electrostatic discharge units. One end of the fifth connection trace is connected to the second end of the fourth connection trace, and the other end of the fifth connection trace is connected to the control end of the fourth electrostatic discharge unit.

[0021] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first conductive layer further includes a sixth connection trace and a seventh connection trace, the electrostatic discharge circuit further includes a fifth electrostatic discharge unit and a sixth electrostatic discharge unit, the sixth electrostatic discharge unit is located on one side of the fourth electrostatic discharge unit close to the second side of the display area, the fifth electrostatic discharge unit is located between the fourth electrostatic discharge unit and the sixth electrostatic discharge unit, one end of the sixth connection trace is connected to the first data test line, the other end of the sixth connection trace is connected to the control end of the fifth electrostatic discharge unit, one end of the seventh connection trace is connected to the second data test line, and the other end of the seventh connection trace is connected to the control end of the sixth electrostatic discharge unit.

[0022] For example, the display substrate provided by at least one embodiment of the present disclosure further includes a bonding area and a signal access unit located on the fourth side of the display area opposite to the first side, the signal access unit is located between the bonding area and the display area, the bonding area includes a plurality of contact pads arranged along the first direction, the plurality of contact pads include a first contact pad and a second contact pad close to the second side of the display area, and a third contact pad and a fourth contact pad close to the third side of the display area, the second end of the first data test line extends to the fourth side of the display area and is connected to the second contact pad, the second end of the second data test line extends to the fourth side of the display area and is connected to the first contact pad, the second end of the control signal line extends to the fourth side of the display area and is connected to the third contact pad, and the second end of the third data test line extends to the fourth side of the display area and is connected to the fourth contact pad.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, portions of the first data test line, the second data test line, the third data test line, and the control signal line are located in the second conductive layer.

[0024] For example, in the display substrate provided by at least one embodiment of the present disclosure, the plurality of power supply lines further include a third power supply line and a fourth power supply line. The third power supply line is configured to provide a third power signal to the plurality of sub-pixels, and the fourth power supply line is configured to provide a fourth power signal to the plurality of sub-pixels. The plurality of contact pads further include a fifth contact pad, a sixth contact pad, a seventh contact pad, and an eighth contact pad. The seventh contact pad is located on one side of the second contact pad close to the second side of the display area, and the eighth contact pad is located on one side of the fourth contact pad close to the third side of the display area. The fifth contact pad is located between the seventh contact pad and the second contact pad, and the sixth contact pad is located between the fourth contact pad and the eighth contact pad. Both ends of the third power supply line are respectively connected to the seventh contact pad and the eighth contact pad and are routed around the display area. The third power supply line is located on a side of the first data test line and the third data test line away from the display area. Both ends of the fourth power supply line are respectively connected to the fifth contact pad and the sixth contact pad, and are routed between the signal access unit and the display area and extend to the display area. The orthographic projection of the fourth power supply line on the surface of the substrate overlaps with the orthographic projections of the first data test line, the second data test line, the third data test line, and the control signal line on the surface of the substrate. In the area where the orthographic projection of the fourth power supply line on the surface of the substrate overlaps with the orthographic projections of the first data test line, the second data test line, the third data test line, and the control signal line, the fourth power supply line is located in the second conductive layer, and the first data test line, the second data test line, the third data test line, and the control signal line are insulated from the second conductive layer at intervals.

[0025] For example, in the display substrate provided by at least one embodiment of the present disclosure, the first data test line includes a first part connected to its first end, a second part connected to its second end, and an eighth connection trace. The first part and the second part of the first data test line are located in the second conductive layer, and the eighth connection trace is located in the first conductive layer. Both ends of the eighth connection trace are respectively connected to the first part and the second part of the first data test line. The second data test line includes a first part connected to its first end, a second part connected to its second end, and a ninth connection trace. The first part and the second part of the second data test line are located in the second conductive layer, and the ninth connection trace is located in the first conductive layer. Both ends of the ninth connection trace are respectively connected to the first part and the second part of the second data test line. The orthographic projections of the eighth connection trace and the ninth connection trace on the surface of the substrate overlap with the orthographic projection of the fourth power supply line on the surface of the substrate.

[0026] For example, in the display substrate provided by at least one embodiment of the present disclosure, the third data test line includes a first part connected to its first end, a second part connected to its second end, and a tenth connection trace. The first part and the second part of the third data test line are located in the second conductive layer, the tenth connection trace is located in the first conductive layer, and both ends of the tenth connection trace are respectively connected to the first part and the second part of the third data test line. The control signal line includes a first part connected to its first end, a second part connected to its second end, and an eleventh connection trace. The first part and the second part of the control signal line are located in the second conductive layer, the eleventh connection trace is located in the first conductive layer, and both ends of the eleventh connection trace are respectively connected to the first part and the second part of the control signal line. The orthographic projections of the tenth connection trace and the eleventh connection trace on the surface of the substrate overlap with the orthographic projection of the fourth power supply line on the surface of the substrate.

[0027] For example, in the display substrate provided by at least one embodiment of the present disclosure, the signal access unit includes a plurality of signal access pads. The first conductive layer further includes a twelfth connection trace. One end of the twelfth connection trace is connected to at least one of the plurality of signal access pads, and the other end of the twelfth connection trace is connected to the control signal line.

[0028] At least one embodiment of the present disclosure provides a display device, including the display substrate described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

[0030] Figure 1A It is a schematic structural diagram of a test circuit unit of a display substrate;

[0031] Figure 1B It is a schematic diagram of the working principle of a test circuit of a display substrate;

[0032] Figure 2 It is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure;

[0033] Figure 3 It is a partial structural schematic diagram of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area;

[0034] Figure 4 For along Figure 3 The cross-sectional view of the center line A - B;

[0035] Figure 5 A cross-sectional schematic diagram of a display area of a display substrate provided by at least one embodiment of the present disclosure;

[0036] Figure 6 Another partial structural schematic diagram of a peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area;

[0037] Figure 7A Another partial structural schematic diagram of a peripheral area of a display substrate provided by at least another embodiment of the present disclosure on the first side of the display area;

[0038] Figure 7B is Figure 7A An enlarged schematic diagram of the virtual test unit in

[0039] Figure 8 Another partial structural schematic diagram of a peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area;

[0040] Figure 9 A partial structural schematic diagram of a peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the fourth side of the display area; and

[0041] Figure 10 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. Detailed implementation manners

[0042] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure.

[0043] Unless otherwise defined, the technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "including" or "comprising" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents. For convenience of description, in some of the drawings, "upper", "lower", "front" and "rear" are given. In the embodiments of this disclosure, the vertical direction is the direction from top to bottom, the vertical direction is the direction of gravity, the horizontal direction is the direction perpendicular to the vertical direction, and the horizontal direction from right to left is the direction from front to back.

[0044] Figure 1A It is a schematic structural diagram of a test circuit unit of a display substrate; Figure 1B It is a schematic diagram of the working principle of a test circuit of a display substrate.

[0045] The basic structure of the test unit CT0 of the test circuit commonly used for the display substrate of wearable products is as Figure 1A shown. For example, the test unit CT0 includes a plurality of test switches CT01. For example, the plurality of test switches CT01 includes three, which are respectively electrically connected to different data test signal lines. In Figure 1A , the first pole (such as one of the source or drain) of the test unit CT0 receives the DR0 data signal, the DG0 data signal, and the DB0 data signal. The DR0 signal, the DG0 signal, and the DB0 signal are respectively data signals and are provided by different data test signal lines. For example, the gate of the test unit CT0 (such as the test switch CT01) receives the CTSW0 switch signal.

[0046] The working principle of the above test circuit is as Figure 1B shown. For example, Figure 1AThe working principle of the shown test circuit is as follows: The test unit CT01 turns on the test switch CT01 switch in response to the received switch signal, that is, the switch signal received through the control signal line CTSW0 connected to the gate of the test switch CT01; and provides the data signal transmitted through the data test signal line CT_D (for example, DR0 data signal, DG0 data signal or DB0 data signal) to the Data_R data line, Data_G data line or Data_B data line. For example, the Data_R data line, Data_G data line and Data_B data line are respectively connected to different column sub-pixels P10. At this time, the voltages of the data signals of all sub-pixels are the same, and only a solid-color picture can be displayed. If there are colored dots, such as black dots, during the detection, it means that there are abnormal points in the display panel detected.

[0047] For example, for a display device, the impedance of the signal line plays an important role in the signal transmission efficiency and display effect. As Figure 1A shown, for the common test unit CT0, the gate of the test switch CT01 is a single-layer trace (for example, located in the first gate electrode layer) and is respectively connected to the control signal line CTSW0. Such a design usually causes the impedance to increase as the trace distance of the signal line increases. For example Figure 1A the distances of the gates of the three test switches CT01 shown in the figure from the control signal line in the vertical direction in the figure are different, and the impedance of the signal received by the test switch CT01 farther from the control signal line is greater. In addition, the increase in the impedance of the signal will also cause uneven signal strengths at the gates of each test switch CT01, thus affecting the test results.

[0048] At least one embodiment of the present disclosure provides a display substrate, which includes: a substrate substrate, a plurality of sub-pixels, a plurality of data lines, a control signal line, a data test line, a test circuit, and an auxiliary electrode line. The substrate substrate includes a display area and a peripheral area at least on one side of the display area; the plurality of sub-pixels are located in the display area and are arranged in an array; the plurality of data lines are located in the display area and are configured to provide data signals to the plurality of sub-pixels; the control signal line is located in the peripheral area and on at least one side of the display area; the plurality of data test lines are located in the peripheral area and on at least one side of the display area; the test circuit is located in the peripheral area and is electrically connected to the plurality of data lines, the control signal line, and the plurality of data test lines, and is configured to transmit test signals to the plurality of data lines through the plurality of data test lines under the control of the control signal line. The test circuit includes a plurality of test units, and each of at least one test unit in the plurality of test units includes a first control line and a plurality of control switches. The plurality of control switches include control ends, and the first control line, the control signal line, and the control ends of the plurality of control switches are connected; the auxiliary electrode line is located in the peripheral area and is connected in parallel with the first control line, and the orthographic projection of at least a part of at least one control switch in the plurality of control switches on the surface of the substrate substrate is located between the orthographic projections of the first control line and the auxiliary electrode line on the surface of the substrate substrate.

[0049] At least one embodiment of the present disclosure further provides a display device including the above display substrate.

[0050] In the display substrate and the display device provided in the above embodiments, the display substrate can reduce the impedance of the first control line, improve the transmission efficiency of the first control line, prevent signal distortion, and provide a more stable control signal for the test circuit.

[0051] The embodiments and examples of the present disclosure will be described in detail below with reference to the drawings.

[0052] Figure 2 It is a schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 3 It is a partial structural schematic diagram of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area.

[0053] For example, in some embodiments, such as Figure 2As shown, the display substrate 1 includes a substrate substrate 100. The substrate substrate 100 includes a display area 10 and a peripheral area 20. For example, the peripheral area 20 surrounds the display area 10. The display substrate 1 includes a plurality of sub-pixels P10. The plurality of sub-pixels P10 are located in the display area 10 and are arranged in an array, for example, arranged in multiple rows and multiple columns along a first direction X and a second direction Y. The display substrate 1 further includes a plurality of data lines D10 and control signal lines CW. The plurality of data lines D10 are located in the display area 10, for example, passing through the display area 10 along the second direction Y (longitudinally). The plurality of data lines D10 are configured to provide data signals to the sub-pixels P10 corresponding to each column respectively. The control signal lines CW are located in the peripheral area 20 and are routed around at least one side of the display area 10, for example, routed around the third side 13 of the display area 10 (for example, Figure 2 the right side of the display area 10 in

[0054] For example, the included angle between the first direction X and the second direction Y involved in the present disclosure is between 70° and 90°, and includes 70° and 90°. For example, the included angle between the first direction X and the second direction Y is 70°, 90° or 80°, etc., which can be set according to actual situations, and the embodiments of the present disclosure do not limit this. For example, the included angle between the first direction X and the second direction Y can also be 75°, 85°, etc.

[0055] For example, the substrate substrate 100 can be a glass plate, a quartz plate, a metal plate or a resin plate, etc. For example, the material of the substrate substrate can include organic materials. For example, the organic material can be resin materials such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate; for example, the substrate substrate 100 can be a flexible substrate or a non-flexible substrate, and the embodiments of the present disclosure do not limit this.

[0056] As Figure 2 and Figure 3 shown, the display substrate 1 further includes a test circuit CT. The test circuit CT is located in the peripheral area 20, for example, located on the first side 11 of the display area 10 (for example, Figure 2 the upper side of the display area 10 in Figure 3As shown). Each of at least one test unit CT1 includes a first control line CT11 and a plurality of control switches CT12. Each of the plurality of control switches CT12 includes a control terminal CT121 (such as a gate), and the first control line CT11, the control signal line CW, and the control terminals CT121 of the plurality of control switches CT12 in the test unit CT1 are connected to provide a control signal to the plurality of control switches CT12. For example, the test circuit CT transmits a test signal to a plurality of data lines D10 under the control of the control signal line CW (for example, through a plurality of data test lines DR / DG / DB). For example, the first control line CT11 and the control terminal CT121 of the control switch CT12 are disposed on the same layer and integrally formed.

[0057] For example, as Figure 2 and Figure 3 shown, the display substrate 1 further includes an auxiliary electrode line SW. The auxiliary electrode line SW is located in the peripheral area 20, for example, on the first side 11 of the display area 10. For example, the routing directions of the auxiliary electrode line SW and the first control line CT11 are substantially the same, for example, both extend along the first direction X. For example, the auxiliary electrode line SW and the first control line CT11 are connected in parallel with each other, and at least a part of at least one control switch CT12 among the plurality of control switches CT12 is located between the orthographic projections of the first control line CT11 and the auxiliary electrode line SW on the plane S of the substrate 100 (as Figure 4 shown). For example, in Figure 3 , each of the plurality of control switches CT12 further includes a first end CT122 (such as the first end away from the auxiliary electrode line SW) and a second end CT123 (such as the first end close to the auxiliary electrode line SW), and the second ends CT123 of the plurality of control switches CT12 are spaced between the first control line CT11 and the auxiliary electrode line SW. That is, the orthographic projection of the second end CT123 of the control switch CT12 on the plane S of the substrate 100 is located between the orthographic projections of the first control line CT11 and the auxiliary electrode line SW on the plane S of the substrate 100.

[0058] For example, for example, the auxiliary electrode line SW and the first control line CT11 may not be parallel to the first direction X, for example, intersect the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0059] For example, while connecting the control terminal CT121 of each of the plurality of control switches CT12 to the first control line CT11, the control terminals CT121 of the plurality of control switches CT12 are connected in series, so that the first control line CT11 and the auxiliary electrode line SW connected to the control terminal CT121 of each control switch CT12 form a parallel structure. According to the parallel resistance formula: R = (R CT11 +R SW) / (R CT11 *R SW ), where R CT11 represents the resistance of the first control line CT11, and R SW represents the resistance of the auxiliary electrode line SW. After the auxiliary electrode line SW and the first control line CT11 are connected in parallel, the impedance of the first control line CT11 will decrease.

[0060] In the above embodiments of the present disclosure, the display substrate 1 can reduce the impedance of the first control line CT11, improve the transmission efficiency of the first control line CT11, prevent signal distortion, and provide a more stable control signal for the test circuit, without changing the structure or working performance of the control switch CT12.

[0061] It should be noted that, taking the control switch CT12 as a P-type transistor as an example. The control switch CT12 can also be an N-type transistor, and the embodiments of the present disclosure are not limited thereto. For example, the control terminal CT121 of the control switch CT12, for example, is the gate of the transistor, and the first terminal CT122 and the second terminal CT123 of the control switch CT12 are the source and drain of the transistor, respectively.

[0062] Figure 4 is a cross-sectional view along Figure 3 the center line A - B.

[0063] For example, in some embodiments, as Figure 3 and Figure 4 shown, the first control line CT11 and the auxiliary electrode line SW are located in different layers with respect to the substrate 100, that is, they are not in the same layer. For example, the first control line CT11 and the auxiliary electrode line SW are respectively located in the first conductive layer 201 and the second conductive layer 203 that are insulated from each other. For example, the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 are provided between the first conductive layer 201 and the second conductive layer 203. For example, the peripheral interlayer insulating layer 2244 is located on the side of the first conductive layer 201 away from the substrate 100, the peripheral interlayer insulating layer 2244 is located on the side of the second peripheral insulating layer 2243 away from the substrate 100, and the second conductive layer 203 is located on the side of the peripheral interlayer insulating layer 2244 away from the substrate 100. Thus, compared with the case where the auxiliary electrode line SW is located in the first conductive layer 201 (for example, in the same layer as the first control line CT11), the resistance value of the auxiliary electrode line SW is increased, thereby further reducing the impedance of the first control line CT11.

[0064] For example, in some embodiments, the auxiliary electrode line SW is located on the side of the test circuit CT away from the display area 10 (for example, Figure 3 on the upper side of the test circuit CT in Figure 3 ) or on the side close to the display area 10 (for example,

[0065] For example, in some embodiments, as Figure 2 and Figure 3 shown, the display substrate 1 further includes an electrostatic discharge circuit ESD disposed between the test circuit CT and the display area 10. The electrostatic discharge circuit ESD is electrically connected to a plurality of data lines D10 to remove electrostatic interference generated during the transmission of the test signal of the test circuit CT. The auxiliary electrode line SW is located between the test circuit CT and the electrostatic discharge circuit ESD and is thus connected in parallel with the first control line CT11.

[0066] For example, in some embodiments, as Figure 3 shown, the display substrate 1 further includes a plurality of connection lines 101. The plurality of connection lines 101 are respectively disposed between a plurality of control switches CT12, that is, arranged in the gaps between the plurality of control switches CT12. The first control line CT11 overlaps with the active layers CT124 of the plurality of control switches CT12, and the overlapping portions of the first control line CT11 and the active layers CT124 form the control terminals CT121 of the plurality of control switches CT12. For example, the first control line and the control terminal CT121 of the control switch CT12 are integrally formed. For example, the first ends 1011 of the plurality of connection lines 101 are connected to the first control line CT11, and the second ends 1012 of the plurality of connection lines 101 are connected to the auxiliary electrode line SW, so that the first control line CT11 and the auxiliary electrode line SW form a parallel connection structure.

[0067] For example, as Figure 4 shown, the plurality of connection lines 101 and the first control line CT11 are disposed on the same layer and are both located in the first conductive layer 201. For example, the plurality of connection lines 101 and the first control line CT11 are integrally formed.

[0068] It should be noted that in the embodiments of the present disclosure, "disposed on the same layer" includes that two functional layers or structural layers are on the same layer and formed of the same material in the hierarchical structure of the display substrate, that is, in the manufacturing process, the two functional layers or structural layers can be formed from the same material layer and the required patterns and structures can be formed through the same patterning process. A patterning process, for example, includes processes such as the formation of photoresist, exposure, development, and etching.

[0069] For example, in some embodiments, as Figure 2 and Figure 3As shown, the display substrate 1 further includes a plurality of data test lines (for example, a first data test line DR, a second data test line DG, and a third data test line DB). The plurality of data test lines are located in the peripheral area 20 and run around at least one side (for example, a first side 11, a second side 12, and a third side 13) of the display area 10. The plurality of data test lines extend along a first direction X and are spaced apart on a side of the test circuit CT away from the display area 10 (above the test circuit CT in the figure). That is, on the first side 11 of the display area 10, the plurality of data test lines run along the first direction X. For example, each of the plurality of control switches CT12 is based on a control signal received on the control terminal CT121. For example, when the control switch CT12 is a P-type transistor, when the control signal is at a low level, the control terminal CT121 of the control switch CT12 is turned on, so that the first terminal CT122 and the second terminal CT123 can transmit a test signal. The first terminals CT122 of the plurality of control switches CT12 are respectively connected to the plurality of data test lines and are configured to receive test signals provided by the plurality of data test lines. The second terminals CT123 of the plurality of control switches CT12 are respectively electrically connected to the plurality of data lines D10 to provide test signals to the sub-pixels P10 of the display area 10.

[0070] For example, in some embodiments, as Figure 3 shown, the display substrate 1 further includes a plurality of first lead segments 102 and a plurality of data leads 103. The plurality of first lead segments 102 and the plurality of data leads 103 extend along a second direction Y. For example, the plurality of first lead segments 102 are respectively connected to the plurality of data test lines (for example, a first data test line DR, a second data test line DG, and a third data test line DB) and the first terminals CT122 of the plurality of control switches CT12. For example, the plurality of data leads 103 are respectively connected to the second terminals CT123 of the plurality of control switches CT12 and the plurality of data lines D10 to provide test signals to the sub-pixels P10 of the display area 10 when the control switches CT12 are turned on.

[0071] For example, the plurality of first lead segments 102 and the plurality of data leads 103 may not be parallel to the second direction Y, for example, intersect the second direction Y at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0072] For example, in some embodiments, as Figure 3 shown, each of the plurality of data leads 103 respectively includes a second lead segment 1031. The plurality of second lead segments 1031 are respectively connected to the second terminals CT123 of the plurality of control switches CT12 and the electrostatic discharge circuit ESD.

[0073] For example, as Figure 4As shown, a plurality of first lead segments 102 and a plurality of second lead segments 1031 are located in the third conductive layer 202. The third conductive layer 202 is located between the first conductive layer 201 and the second conductive layer 203 and is insulated from each other. For example, the third conductive layer 202 is located between the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244. There is a peripheral interlayer insulating layer 2244 between the third conductive layer 202 and the second conductive layer 203. There is a second peripheral insulating layer 2243 between the third conductive layer 202 and the first conductive layer 201. For example, the first lead segment 102 is connected to the first end CT122 of the control switch CT12 through a via hole penetrating the interlayer insulating layer 2244. For example, the second lead segment 1031 is connected to the second end CT123 of the control switch CT12 through a via hole penetrating the interlayer insulating layer 2244. The orthographic projections of the plurality of second lead segments 1031 on the board surface S of the substrate 100 and the orthographic projection of the auxiliary electrode SW on the board surface S of the substrate 100 overlap each other. The plurality of second lead segments 1031 and the auxiliary electrode SW are located in different layers to save wiring space.

[0074] For example, as Figure 3 shown, the plurality of first lead segments 102 do not overlap with the first control line CT11, which can avoid generating parasitic capacitance between the first lead segments 102 and the first control line CT11.

[0075] Figure 6 Another schematic structural diagram of a part of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area.

[0076] For example, in some embodiments, as Figure 2 and Figure 6 shown, each of the plurality of data leads 103 further includes a third lead segment 1032. The third lead segment 1032 is located in the peripheral area 20 and between the display area 10 and the electrostatic discharge circuit ESD. For example, one end (the end close to the electrostatic discharge circuit ESD) of the plurality of third lead segments 1032 is electrically connected to the control end of the electrostatic discharge circuit ESD. The other ends of the plurality of third lead segments 1032 are respectively connected to the plurality of data lines D10 to provide a test signal to the sub-pixels P10 in the display area 10. For example, the third lead segment 1032 is located in the third conductive layer 202.

[0077] Figure 5 A schematic cross-sectional view of a display area of a display substrate provided by at least one embodiment of the present disclosure.

[0078] For example, in some embodiments, as Figure 5As shown, each of a plurality of sub-pixels P10 includes a pixel structure. The pixel structure includes a pixel driving circuit 104 and a light-emitting element 11. The pixel driving circuit 104 includes a semiconductor layer 304, a first display area metal layer 301, a second display area metal layer 302, a third display area metal layer 303, a first insulating layer 1242 (i.e., a first gate insulating layer), a second insulating layer 1243 (i.e., a second gate insulating layer), and an interlayer insulating layer 1244. The light-emitting element 11 is located on a side of the pixel driving circuit 104 away from the substrate 100 and is connected to the third display area metal layer 303 of the pixel driving circuit 104.

[0079] As Figure 5 shown, the first insulating layer 1242 is located on the substrate 100. The semiconductor layer 304 is located on a side of the first insulating layer 1242 close to the substrate 100. The first display area metal layer 301 is located on a side of the first insulating layer 1242 away from the substrate 100. The second insulating layer 1243 is located on a side of the first display area metal layer 301 away from the substrate 100. The second display area metal layer 302 is located on a side of the second insulating layer 1243 away from the substrate 100. The interlayer insulating layer 1244 is located on a side of the second display area metal layer 302 away from the substrate. The third display area metal layer 303 is located on a side of the interlayer insulating layer 1244 away from the substrate 100.

[0080] As Figure 5 shown, the display substrate 1 may further include a buffer layer 1241 and a barrier layer 1240. The buffer layer 1241 is located on a side of the semiconductor layer 304 close to the substrate 100, and the barrier layer 1240 is located on a side of the buffer layer 1241 close to the substrate 100. The buffer layer 1241 serves as a transition layer, which can prevent harmful substances in the substrate from invading the interior of the display substrate and can also increase the adhesion of the film layers in the display substrate to the substrate 100. The barrier layer 1240 can provide a flat surface for forming the pixel driving circuit 104 and can prevent impurities that may exist in the substrate 100 from diffusing into the sub-pixel driving circuit or the pixel driving circuit 104 and adversely affecting the performance of the display substrate.

[0081] For example, the material of one or more of the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. The materials of the first insulating layer 1242, the second insulating layer 1243, and the interlayer insulating layer 1244 may be the same or different.

[0082] For example, the material of the buffer layer 1241 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride. For example, the material of the barrier layer 1240 may include inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, or other suitable materials.

[0083] For example, the material of the semiconductor layer 304 may include polysilicon or an oxide semiconductor (e.g., indium gallium zinc oxide (IGZO)).

[0084] For example, the materials of the first display region metal layer 301, the second display region metal layer 302, and the third display region metal layer 303 may include a metal material or an alloy material, such as a single-layer or multi-layer structure of metals formed by molybdenum, aluminum, titanium, etc. For example, the multi-layer structure is a multi-metal layer stack (such as a three-layer metal stack of titanium, aluminum, and titanium (Ti / Al / Ti)). For example, the materials of the first display region metal layer 301, the second display region metal layer 302, and the third display region metal layer 303 may be the same or different, and the embodiments of the present disclosure are not limited thereto.

[0085] For example, in some embodiments, as Figure 4 and Figure 5 shown, the first conductive layer 201 is disposed on the same layer as the first display region metal layer 301. For example, the third conductive layer 202 is disposed on the same layer as the second display region metal layer 302. For example, the second conductive layer 203 is disposed on the same layer as the third display region metal layer 303. For example, the active layer CT124 of the plurality of control switches CT12 is disposed on the same layer as the semiconductor layer 304. For example, the second peripheral insulating layer 2243 is disposed on the same layer as the second insulating layer 1243, and the peripheral interlayer insulating layer 2244 is disposed on the same layer as the interlayer insulating layer 1244. Thereby, the manufacturing process flow is simplified.

[0086] For example, as Figure 4 shown, a plurality of connection lines 101 are located in the first conductive layer 201, and the second ends 1012 of the plurality of connection lines 101 are connected to the auxiliary electrode line SW through vias GK1 that penetrate through the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244 (e.g., the second insulating layer 1243 and the interlayer insulating layer 1244).

[0087] For example, as Figure 4 shown, in the peripheral region 20, the display substrate 1 further includes a first peripheral insulating layer 2242, a peripheral buffer layer 2241, and a peripheral barrier layer 2240. The first peripheral insulating layer 2242 is located on the side of the first conductive layer 201 close to the substrate 100, the peripheral buffer layer 2241 is located on the side of the first peripheral insulating layer 2242 close to the substrate 100, and the peripheral barrier layer 2240 is located on the side of the peripheral buffer layer 2241 close to the substrate 100. For example, the first peripheral insulating layer 2242 is disposed on the same layer as the first insulating layer 1242, the peripheral buffer layer 2241 is disposed on the same layer as the buffer layer 1241, and the peripheral barrier layer 2240 is disposed on the same layer as the barrier layer 1240.

[0088] For example, as Figure 5As shown, the pixel driving circuit 104 further includes a first transistor 12 and a storage capacitor 13. The first transistor 13 includes a transistor directly electrically connected to the light-emitting element 11, and this transistor is, for example, a switching transistor (such as a light-emitting control transistor) or a driving transistor. The first transistor 12 includes a gate 122, two source-drain electrodes (a source electrode 123 and a drain electrode 124), and an active layer 121. The gate 122 is located in the first display area metal layer 301, the two source-drain electrodes (the source electrode 123 and the drain electrode 124) are located in the third display area metal layer 303, and the active layer 121 is located in the semiconductor layer 304. The storage capacitor 13 includes a first electrode plate 131 and a second electrode plate 132. For example, the first electrode plate 131 is located in the first display area metal layer 301, and the second electrode plate 132 is located in the second display area metal layer 302. The gate 122 and the first electrode plate 131 are arranged in the same layer. The first electrode plate 131 and the second electrode plate 132 are spaced apart by a second insulating layer 1243 to form a capacitance function.

[0089] For example, in other embodiments, the first electrode plate 131 can be arranged to be located in the second display area metal layer 302, and the second electrode plate 132 is arranged to be located in the third display area metal layer 303. At this time, the first electrode plate 131 and the second electrode plate 132 are spaced apart by a side key insulating layer 1244. The embodiments of the present disclosure are not limited to the specific setting manner of the storage capacitor 13.

[0090] For example, as Figure 5 shown, the display substrate 1 further includes a first planarization layer 1245. The first planarization layer 1245 provides a first planarized surface on the side of the source electrode 123 and the drain electrode 124 (that is, the pixel driving circuit 104) away from the substrate 100 to planarize the surface of the pixel driving circuit 104 on the side away from the substrate 100. The first planarization layer 1245 includes a first via 252, and the pixel driving circuit 104 (such as the third display area metal layer 303) is electrically connected to the light-emitting element through the first via 252.

[0091] For example, the material of the first planarization layer 1245 includes inorganic insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride, and can also include organic insulating materials such as polyimide, polyphthalimide, polyamide, acrylic resin, benzocyclobutene, or phenolic resin. The embodiments of the present disclosure do not limit this.

[0092] For example, as Figure 5As shown, the display substrate 1 further includes a pixel defining layer 146. The light-emitting element 11 is disposed on a side of the second planarization layer 1245 away from the substrate 100. The light-emitting element 11 includes a first electrode 113 (e.g., an anode), a light-emitting layer 112, and a second electrode 111 (e.g., a cathode). The first electrode 113 is located on a side of the first planarization layer 1245 away from the substrate 100 and is electrically connected to the pixel driving circuit 104 (e.g., the drain 124 of the first transistor 12) through a via 252. The second electrode 111 is located on a side of the pixel defining layer 146 away from the substrate 100. The pixel defining layer 146 is located on a side of the first electrode 113 away from the substrate 100 and includes a first pixel opening 1461. The first pixel opening 1461 is disposed corresponding to the light-emitting element 11. The light-emitting layer 112 is located in the first pixel opening 1461 and between the first electrode 113 and the second electrode 111. The portion of the light-emitting layer 112 directly sandwiched between the first electrode 113 and the second electrode 111 will emit light after being energized, and thus the region occupied by this portion corresponds to the light-emitting area of the light-emitting element 11.

[0093] For example, the pixel driving circuit 104 generates a light-emitting driving current under the control of a data signal (e.g., a test signal) provided by the data line D10, a gate scanning signal provided by, for example, a shift register, a light-emitting control signal, etc. The light-emitting driving current enables the light-emitting element 11 to emit red light, green light, blue light, or white light, etc.

[0094] For example, the pixel driving circuit 104 includes a conventional 2T1C (i.e., two transistors and one capacitor) pixel circuit, a 7T1C (i.e., seven transistors and one capacitor) pixel circuit, etc. The pixel driving circuit 104 includes at least one switching transistor and one driving transistor (such as Figure 5 the first transistor 12 as mentioned). The gate of the switching transistor receives the gate scanning signal, and the source or drain of the switching transistor is connected to the data line D10 to receive the data signal. In different embodiments, the pixel driving circuit 104 may further include a compensation circuit, which includes an internal compensation circuit or an external compensation circuit. The compensation circuit may include transistors, capacitors, etc. For example, according to needs, the pixel circuit may further include a reset circuit, a light-emitting control circuit, a detection circuit, etc. The embodiments of the present disclosure do not limit the type of the first light-emitting device and the specific structure of the pixel circuit.

[0095] For example, the material of the pixel defining layer 146 may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene, or phenolic resin, or may include inorganic insulating materials such as silicon oxide, silicon nitride, etc. The embodiments of the present disclosure do not limit this.

[0096] For example, the material of the first electrode 113 may include at least one transparent conductive oxide material, including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In addition, the first electrode 113 may include a metal with a high reflectivity as a reflective layer, such as silver (Ag).

[0097] For example, for an OLED, the light-emitting layer 112 may include a small molecule organic material or a polymer molecule organic material, may be a fluorescent light-emitting material or a phosphorescent light-emitting material, may emit red light, green light, blue light, or may emit white light; and, if necessary, the light-emitting layer may further include functional layers such as an electron injection layer, an electron transport layer, a hole injection layer, a hole transport layer, etc.

[0098] For example, for a QLED, the light-emitting layer 112 may include quantum dot materials, such as silicon quantum dots, germanium quantum dots, cadmium sulfide quantum dots, cadmium selenide quantum dots, cadmium telluride quantum dots, zinc selenide quantum dots, lead sulfide quantum dots, lead selenide quantum dots, indium phosphide quantum dots, and indium arsenide quantum dots, etc., and the particle size of the quantum dots is 2-20 nm.

[0099] For example, the second electrode 111 may include various conductive materials. For example, the second electrode 111 may include metal materials such as lithium (Li), aluminum (Al), magnesium (Mg), silver (Ag), etc.

[0100] For example, as Figure 5 shown, the display substrate 1 further includes a packaging layer 147. The packaging layer 147 is located on the side of the second electrode 111 away from the substrate 100. The packaging layer 147 seals the light-emitting element 11 (light-emitting element 11), thereby reducing or preventing the deterioration of the light-emitting element 11 caused by moisture and / or oxygen included in the environment. The packaging layer 147 may be a single-layer structure or a composite layer structure, and the composite layer structure includes a structure in which an inorganic layer and an organic layer are stacked. The packaging layer 147 includes at least one packaging sub-layer. For example, the packaging layer 147 may include a first inorganic packaging layer, a first organic packaging layer, and a second inorganic packaging layer arranged in sequence.

[0101] For example, the material of the packaging layer 147 may include insulating materials such as silicon nitride, silicon oxide, silicon oxynitride, and polymer resins. Inorganic materials such as silicon nitride, silicon oxide, and silicon oxynitride have high density and can prevent the intrusion of water, oxygen, etc.; the material of the organic packaging layer may be a polymer material containing a desiccant or a polymer material that can block water vapor, such as a polymer resin, etc., to planarize the surface of the display substrate, and can relieve the stress between the first inorganic packaging layer and the second inorganic packaging layer, and may also include water-absorbing materials such as desiccants to absorb substances such as water and oxygen that invade the interior.

[0102] Figure 7ASchematic diagram of another part of the peripheral area of a display substrate provided for at least another embodiment of the present disclosure on the first side of the display area; Figure 7B is Figure 7A An enlarged schematic diagram of the virtual test unit in

[0103] For example, in some embodiments, such as Figure 7A and Figure 7B shown, the test circuit CT further includes at least one virtual test unit DCT1, and at least one virtual test unit DCT1 is located on the side of the test circuit CT away from the plurality of test units CT1. For example, the number of at least one virtual test unit DCT1 is at least two and is arranged on both sides of the test circuit CT away from the plurality of test units CT1. The second conductive layer 203 includes a plurality of first transfer electrodes ZL1. For example, each of the at least one virtual test unit DCT1 includes a plurality of virtual control switches DCT11. The first ends DCT13 of the plurality of virtual control switches DCT11 are respectively connected to a plurality of data test lines (for example, the first data test line DR, the second data test line DG, and the third data test line DB). For example, the control ends DCT12 of the plurality of virtual control switches DCT11 are connected to the first control line CT11. For example, the plurality of transfer electrodes ZL1 are arranged in one-to-one correspondence with the plurality of virtual control switches DCT11. The transfer electrode ZL1 connects the first end DCT13 and the second end DCT14 of the virtual control switch DCT11. That is to say, compared with the structure of the control switch CT12, the virtual control switch DCT11 is provided with an additional transfer electrode ZL1. The setting of the virtual test unit DCT1 can increase the uniformity of the wiring in the peripheral area 20 on the first side 11 of the display area 10.

[0104] For example, in some embodiments, such as Figure 2 and Figure 6 shown, the display substrate 1 further includes a plurality of power supply lines (for example, including a first power supply line VGH and a second power supply line VGL). The plurality of power supply lines are routed around at least one side (for example, the first side 11, the second side 12, and the third side 13) of the display area 10. For example, the plurality of power supply lines include a first power supply line VGH and a second power supply line VGL, and the first power supply line VGH is configured to provide a first power signal (for example, a high-level voltage signal), and the second power supply line VGL is configured to provide a second power signal (for example, a low-level voltage signal). At least a part of the first power supply line VGH and the second power supply line VGL is located in the second conductive layer 203. For example, the first power supply line VGH, the second power supply line VGL, and other wirings (for example Figure 2The overlapping portion of the fourth power line VDD) and the first conductive layer 201. For example, on the first side 11 of the display area 10, the first power line VGH runs on the side of the electrostatic discharge circuit ESD away from the display area 10, and the second power line VGL runs on the side of the electrostatic discharge circuit ESD close to the display area 10. The first power line VGH and the second power line VGL are respectively connected to the first end ESD1 and the second end ESD2 of the electrostatic discharge circuit ESD. For example, the electrostatic discharge circuit ESD includes a plurality of first electrostatic discharge units ESD10. For example, one end of the plurality of second lead segments 1031 away from the test circuit CT is respectively connected to the control ends ESD11 of the plurality of first electrostatic discharge units ESD10.

[0105] For example, the first electrostatic discharge unit ESD10 is implemented as a plurality of transistors connected in series. One of the source-drain electrodes (for example, the first end ESD1 and the second end ESD2) of each transistor is short-circuited to the control end (for example, the control end ESD11) to form a diode structure with a one-way conduction characteristic. When the signal transmitted by the second lead segment 1031 connected to the first electrostatic discharge unit ESD10 is a high-level signal, the first electrostatic discharge unit ESD10 conducts, thereby discharging the static electricity on the second lead segment 1031. That is to say, the first electrostatic discharge unit ESD10 is configured to discharge the static electricity on the test signal provided by the data test signal line (for example, the first data test line DR, the second data test line DG, and the third data test line DB) on the transmission path to the data line D10.

[0106] For example, as Figure 2 shown, the test circuit CT and the electrostatic discharge circuit ESD are located on the first side of the display area 10. The second side 12 and the third side 13 of the display area 10 are oppositely arranged and adjacent to the first side 11, and the fourth side 14 of the display area 10 is oppositely arranged to the first side 11. Combining Figure 7A shown, the plurality of data test lines include the first data test line DR, the second data test line DG, and the third data test line DB. The first data test line DR and the second data test line DG (for example, at least part of them) run around the second side 12 and the first side 11 of the display area 10, and the second data test line DG is located on the side of the first data test line DR close to the display area 10. The third data test line DB and the control signal line CW (for example, at least part of them) run around the third side 13 and the first side 11 of the display area 10, and the control signal line CW is located on the side of the third data test line DB close to the display area 10. For example, on the side of the test circuit CT away from the display area 10, the second data test line DG is located between the first data test line DR and the third data test line DB, and the first data test line DR is located on the side away from the test circuit CT. For example, the first data test line DR, the second data test line DG, and the third data test line DB are arranged side by side and spaced apart in the second direction Y.

[0107] For example, as shown in Figure 7A , the first conductive layer 201 includes a first connection trace LL1 that extends along the second direction Y. The semiconductor layer 304 includes a plurality of first resistors R1. The first end CW1 of the control signal line CW is located on the first side 11 of the display area 10 and close to the test circuit CT. For example, the control signal line CW extends to a side of the test circuit CT that is close to the third side 13 of the display area 10. One end of the first connection trace LL1 is connected to the first end CW1 of the control signal line CW (for example, through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244), and the other end of the first connection trace LL1 is connected to one end of the first control line CT11 that is close to the third side 13 of the display area 10. For example, the first control line CT11 and the first connection trace LL1 are provided on the same layer and integrally formed to simplify the manufacturing process. For example, the first end DR1 of the first data test line DR and the first end DG1 of the second data test line DG are located on a side of the test circuit CT that is away from the display area 10, that is, on a side of the virtual test unit DCT1 that is close to the third side 13 of the display area 10 and away from the display area 10. For example, one of the plurality of first resistors R1 (for example, at least one of the first resistors) is connected (for example, through a via penetrating the first peripheral insulating layer 2242, the second peripheral insulating layer 2243, and the peripheral interlayer insulating layer 2244) to the first end DR1 of the first data test line DR and the control signal line CW, and another one of the plurality of first resistors R1 (for example, at least another one of the first resistors) is connected to the first end DG1 of the second data test line DG and the control signal line CW. The first resistor R1 can prevent static electricity from being generated at the first end DR1 of the first data test line DR and the first end DG1 of the second data test line DG.

[0108] For example, for example, the first connection trace LL1 may not be parallel to the second direction Y, for example, intersecting the second direction Y at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0109] Figure 8 Schematic diagram of still another part of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the first side of the display area.

[0110] For example, in some embodiments, as shown in Figure 7A and Figure 8As shown, at least one of the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW, and the first control line CT11 is connected to the electrostatic discharge circuit ESD. For example, the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW, and the first control line CT11 are respectively electrically connected to different electrostatic discharge units in the electrostatic discharge circuit ESD to remove the static electricity generated during the signal transmission of the first data test line DR, the second data test line DG, the third data test line DB, the control signal line CW, and the first control line CT11.

[0111] For example, in some embodiments, as Figure 7A shown, the electrostatic discharge circuit ESD further includes a second electrostatic discharge unit ESD20. The second electrostatic discharge unit ESD20 is located on one side (e.g., the right side of the plurality of first electrostatic discharge units ESD10) of the third side 13 of the plurality of first electrostatic discharge units ESD10 close to the display area 10. For example, the first conductive layer 201 includes a second connection trace LL2, and the semiconductor layer 304 includes a second resistor R2. For example, the second connection trace LL2 overlaps with the first power supply line VGH. For example, the second connection trace LL2 is generally in an "L" - shaped trace. One end of the second connection trace LL2 is connected to the control terminal ESD21 of the second electrostatic discharge unit ESD20 (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244), and the other end of the second connection trace LL2 is connected to the first end CW1 of the control signal line CW to remove the static electricity generated at the first end CW1 of the control signal line CW. The second resistor R2 is located on the side of the second electrostatic discharge unit ESD20 away from the first electrostatic discharge unit ESD10. The second resistor R2 is connected (e.g., through a via penetrating the first peripheral insulating layer 2242, the second peripheral insulating layer 2243, and the peripheral interlayer insulating layer 2244) to the control terminal ESD21 of the second electrostatic discharge unit ESD20 and the first power supply line VGH to prevent static electricity from being generated at the control terminal ESD21 of the second electrostatic discharge unit ESD20.

[0112] For example, in some embodiments, as Figure 7AAs shown, the first conductive layer 201 further includes a third connection trace LL3. For example, the third connection trace LL3 overlaps with the first power line VGH and the control signal line CW, and the third connection trace LL3 is a bent trace. The electrostatic discharge circuit ESD further includes a third electrostatic discharge unit ESD30. The third electrostatic discharge unit ESD30 is located on one side (e.g., the right side in the figure) of the third side 13 of the second electrostatic discharge unit ESD20 close to the display area 10. For example, one end of the third connection trace LL3 is connected to the third data test line DB (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244), and the other end of the third connection trace LL3 is connected to the control terminal ESD31 of the third electrostatic discharge unit ESD30 (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244) to remove the static electricity of the third data test line DB.

[0113] For example, in some embodiments, as Figure 8 shown, the first conductive layer 201 further includes a fourth connection trace LL4. For example, the fourth connection trace LL4 extends along the second direction Y. For example, the fourth connection trace LL4 is symmetrically arranged with the first connection trace LL1 to increase the uniformity of the traces. For example, the first end LL41 of the fourth connection trace LL4 is connected to one end of the first control line CT11 close to the second side 12 of the display area 10. For example, the fourth connection trace LL4 and the first control line CT11 are arranged on the same layer and integrally formed to simplify the manufacturing process. For example, the semiconductor layer 304 includes a third resistor R3. The second conductive layer 203 includes a second transfer electrode ZL2, and the second transfer electrode ZL2 extends along the first direction X. For example, the second end LL42 of the fourth connection trace LL4 is connected to the first end ZL21 of the second transfer electrode ZL2 (e.g., connected through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). For example, the first end DB1 of the third data test line DB is located on the side of the test circuit CT away from the display area 10. For example, the third data test line DB extends in the direction from the first side 11 of the display area 10 towards the second side 12. For example, the third resistor R3 is connected (e.g., through a via penetrating the first peripheral insulating layer 2242, the second peripheral insulating layer 2243, and the peripheral interlayer insulating layer 2244) to the second end ZL22 of the second transfer electrode ZL2 and the first end DB1 of the third data test line DB.

[0114] For example, for example, the fourth connection trace LL4 may also not be parallel to the second direction Y, for example, intersecting the second direction Y at a certain angle. For example, the intersection angle is less than or equal to 20°. The second transfer electrode ZL2 may also not be parallel to the first direction X, for example, intersecting the first direction X at a certain angle. For example, the intersection angle is less than or equal to 20°.

[0115] For example, in some embodiments, as Figure 8 shown, the first conductive layer 201 further includes a fifth connection trace LL5. For example, the electrostatic discharge circuit ESD further includes a fourth electrostatic discharge unit ESD40, and the fourth electrostatic discharge unit ESD40 is located on one side (e.g., the left side) of the second side 12 of the plurality of first electrostatic discharge units ESD10 close to the display area 10. For example, the fifth connection trace LL5 is generally in an "L" shape. For example, one end of the fifth connection trace LL5 is connected to the second end LL42 of the fourth connection trace LL4 (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). The other end of the fifth connection trace LL5 is connected to the control terminal ESD41 of the fourth electrostatic discharge unit ESD40 to remove the static electricity generated by the first control line CT11.

[0116] For example, in some embodiments, as Figure 8 shown, the first conductive layer 201 further includes a sixth connection trace LL6 and a seventh connection trace LL7. The sixth connection trace LL6 and the seventh connection trace LL7 are bent. For example, the electrostatic discharge circuit ESD further includes a fifth electrostatic discharge unit ESD50 and a sixth electrostatic discharge unit ESD60. The sixth electrostatic discharge unit ESD60 is located on one side (e.g., the left side) of the fourth electrostatic discharge unit ESD40 close to the second side 12 of the display area 10. For example, the fifth electrostatic discharge unit ESD50 is located between the fourth electrostatic discharge unit ESD40 and the sixth electrostatic discharge unit ESD60. For example, one end of the sixth connection trace LL6 is connected to the first data test line DR (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244), and the other end of the sixth connection trace LL6 is connected to the control terminal ESD51 of the fifth electrostatic discharge unit ESD50 (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244) to remove the static electricity generated by the first data test line DR. For example, one end of the seventh connection trace LL7 is connected to the second data test line DG (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244), and the other end of the seventh connection trace LL7 is connected to the control terminal ESD61 of the sixth electrostatic discharge unit ESD60 (e.g., through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244) to remove the static electricity generated by the second data test line DG.

[0117] Figure 9 Schematic diagram of a partial structure of the peripheral area of a display substrate provided by at least one embodiment of the present disclosure on the fourth side of the display area.

[0118] For example, in some embodiments, as Figure 2 and Figure 9As shown, the display substrate 1 further includes a bonding area 21 and a signal access unit 22 located on the fourth side 14 of the display area 10. For example, in the second direction Y, the signal access unit 22 is located between the bonding area 21 and the display area 10. The bonding area 21 includes a plurality of contact pads arranged along the first direction X. The plurality of contact pads include a first contact pad 211 and a second contact pad 212 close to the second side 12 of the display area 10 (e.g., located on the left side of the bonding area 21), and a third contact pad 213 and a fourth contact pad 214 close to the third side 13 of the display area 10 (e.g., located on the right side of the bonding area 21). For example, the second end DR2 of the first data test line DR extends to the fourth side 14 of the display area 10 and is connected to the second contact pad 212. The second end DG2 of the second data test line DG extends to the fourth side 14 of the display area 10 and is connected to the first contact pad 211. For example, the second end CW2 of the control signal line CW extends to the fourth side 14 of the display area 10 and is connected to the third contact pad 213. The second end DB2 of the third data test line DB extends to the fourth side 14 of the display area 10 and is connected to the fourth contact pad 214. The plurality of contact pads are configured to be electrically connected to an external test circuit (e.g., bonding, probe contact, etc.) during the test phase to apply a test signal to the sub-pixel P10 through the test circuit CT, thereby testing the performance of the sub-pixel P10 of the display substrate 1 in displaying black and white images, monochromatic images, and grayscale images, etc.

[0119] For example, the signal access unit 22 is configured to be bonded to a signal input element. For example, the signal input element includes an integrated circuit (IC). For another example, the signal input element includes a data driving circuit IC. The signal input element provides a display signal for the display substrate 1 during the display phase to enable the sub-pixel P10 to display an image.

[0120] For example, in some embodiments, a part of the first data test line DR, the second data test line DG, the third data test line DB, and the control signal line CW is located in the second conductive layer 203. For example, other parts of the first data test line DR, the second data test line DG, the third data test line DB, and the control signal line CW are located in the first conductive layer 201.

[0121] For example, in some embodiments, as Figure 2 and Figure 9 shown, the plurality of power lines further include a third power line VSS and a fourth power line VDD. The third power line VSS is configured to provide a third power signal to the plurality of sub-pixels P10. The fourth power line VDD is configured to provide a fourth power signal to the plurality of sub-pixels P10.

[0122] It should be noted that the fourth power supply line VDD is a power supply line that provides a high voltage to multiple sub-pixels P10, and the third power supply line VSS is a power supply line that provides a low voltage (lower than the aforementioned high voltage) to multiple sub-pixels P10. In the embodiments of the present disclosure, the fourth power supply line VDD provides a constant fourth power supply voltage, and the fourth power supply voltage is a positive voltage; the third power supply line VSS provides a constant third power supply voltage, and the third power supply voltage can be a negative voltage or the like. For example, in some examples, the third power supply voltage can be a ground voltage.

[0123] For example, as Figure 2 and Figure 9 shown, for example, the multiple contact pads in the bonding area 21 further include a fifth contact pad 215, a sixth contact pad 216, a seventh contact pad 217, and an eighth contact pad 218. For example, the seventh contact pad 217 is located on one side of the second side 12 of the second contact pad 212 close to the display area 10 (e.g., Figure 9 the left side in Figure 9 ), and the eighth contact pad 218 is located on one side of the third side 13 of the fourth contact pad 214 close to the display area 10 (e.g.,

[0124] the right side in Figure 9 ). For example, the fifth contact pad 215 is located between the seventh contact pad 217 and the second contact pad 212, and the sixth contact pad 216 is located between the fourth contact pad 214 and the eighth contact pad 218. For example, both ends of the third power supply line VSS are respectively connected to the seventh contact pad 217 and the eighth contact pad 218 and are routed around the display area 10 (e.g., the second side 12, the third side 13, and the fourth side 14). The third power supply line VSS is located on the side of the first data test line DR and the third data test line DB away from the display area 10. For example, both ends of the fourth power supply line VDD are respectively connected to the fifth contact pad 215 and the sixth contact pad 216, and are routed between the signal access unit 22 and the display area 10 and extend to the display area 10. For example, the orthographic projection of the fourth power supply line VDD on the board surface S of the substrate 100 overlaps with the orthographic projections of the first data test line DR, the second data test line DG, the third data test line DB, and the control signal line CW on the board surface S of the substrate 100 to reduce the wiring space.

[0125] For example, in some embodiments, as Figure 9 shown, the first data test line DR includes a first portion DR3 connected to its first end DR1, a second portion DR4 connected to its second end DR2, and an eighth connection trace LL8. For example, the first portion DR3 and the second portion DR4 of the first data test line DR are located in the second conductive layer 203, the eighth connection trace LL8 is located in the first conductive layer 201, and both ends of the eighth connection trace LL8 are respectively connected to the first portion DR3 and the second portion DR4 of the first data test line DR (for example, through vias penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). For example, the second data test line DG includes a first portion DG3 connected to its first end DG1, a second portion DG4 connected to its second end DG2, and a ninth connection trace LL9. For example, the first portion DG3 and the second portion DG4 of the second data test line DG are located in the second conductive layer 203, the ninth connection trace LL9 is located in the first conductive layer LL9, and both ends of the ninth connection trace LL9 are respectively connected to the first portion DG3 and the second portion DG4 of the second data test line DG (for example, through vias penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). For example, the eighth connection trace LL8 and the ninth connection trace LL9 are bent traces. For example, the orthographic projections of the eighth connection trace LL8 and the ninth connection trace LL9 on the board surface S of the substrate 100 overlap with the orthographic projection of the fourth power supply line VDD on the board surface S of the substrate 100 (for example Figure 9 on the left side of the signal access unit 22 in

[0126] For example, in some embodiments, as Figure 9As shown, the third data test line DB includes a first portion DB3 connected to its first end DB1, a second portion DB4 connected to its second end DB2, and a tenth connection trace LL10. For example, the first portion DB3 and the second portion DB4 of the third data test line DB are located in the second conductive layer 203, the tenth connection trace LL10 is located in the first conductive layer 201, and both ends of the tenth connection trace LL10 are respectively connected to the first portion DB3 and the second portion DB4 of the third data test line DB (for example, through vias penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). For example, the control signal line CW includes a first portion CW3 connected to its first end CW1, a second portion CW4 connected to its second end CW2, and an eleventh connection trace LL11. For example, the first portion CW3 and the second portion CW4 of the control signal line CW are located in the second conductive layer 203, and the eleventh connection trace LL11 is located in the first conductive layer 201. Both ends of the eleventh connection trace LL11 are respectively connected to the first portion CW3 and the second portion CW4 of the control signal line CW (for example, through vias penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). For example, the tenth connection trace LL10 and the eleventh connection trace LL11 are bent traces. For example, the orthographic projections of the tenth connection trace LL10 and the eleventh connection trace LL11 on the board surface S of the substrate 100 overlap with the orthographic projection of the fourth power supply line VDD on the board surface S of the substrate 100 (for example Figure 9 on the right side of the signal access unit 22 in

[0127] ), to reduce the wiring space. It should be noted that the first power supply line VGH and the second power supply line VGL also extend to the fourth side 14 of the display area 10 and are connected to other contact pads in the bonding area 21. The first power supply line VGH and the second power supply line VGL also overlap with the fourth power supply line VDD on the fourth side 14 of the display area 10, and in the overlapping area, the first power supply line VGH and the second power supply line VGL adopt a way of changing layers for wiring. On the fourth side 14 of the display area 10, the wiring ways of the first power supply line VGH and the second power supply line VGL are similar to those of the first data test line DR, the second data test line DG, the third data test line DB, and the control signal line CW, and will not be elaborated here in detail.

[0128] For example, in some embodiments, such as Figure 9As shown, the signal access unit 22 includes a plurality of signal access pads 221. The first conductive layer 201 further includes a twelfth connection trace LL12. One end of the twelfth connection trace LL12 is connected to at least one of the plurality of signal access pads 221, and the other end of the twelfth connection trace LL12 is connected to the control signal line CW (such as the second part CW4) (for example, through a via penetrating the second peripheral insulating layer 2243 and the peripheral interlayer insulating layer 2244). The twelfth connection trace LL12 can provide a control signal to the test circuit CT through the control signal line CW during the display stage to turn off the test circuit CT, so that the sub-pixel P10 displays an image based on the display signal provided by the signal input unit.

[0129] Figure 10 Schematic diagram of a display device provided by at least one embodiment of the present disclosure.

[0130] At least one embodiment of the present disclosure further provides a display device. Figure 10 Schematic diagram of a display device provided by an embodiment of the present disclosure. As Figure 10 shown, the display device 2 includes the display substrate 1 provided by any embodiment of the present disclosure and a signal input element. For example, the display substrate 1 adopts Figure 2 the display substrate 1 shown in. For example, the signal input element includes a data driving circuit IC. For example, the data driving circuit IC can be bonded to the signal input unit 22 of the display substrate 1. The data driving circuit IC provides a display signal for the display substrate 1 during the display stage, so that the sub-pixel P10 displays an image.

[0131] It should be noted that the display device 2 can be a wearable device. For example, the display device 2 can also be an OLED panel, an OLED TV, a QLED panel, a QLED TV, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any product or component with a display function. The display device 2 can also include other components, such as a data driving circuit, a timing controller, etc., which are not limited in the embodiments of the present disclosure.

[0132] It should be noted that, for clarity and conciseness, the embodiments of the present disclosure do not show all the constituent units of the display device. To implement the substrate function of the display device, those skilled in the art can provide and set other structures not shown according to specific needs, which are not limited in the embodiments of the present disclosure.

[0133] Regarding the technical effects of the display device 2 provided in the above embodiments, reference can be made to the technical effects of the display substrate 1 provided in the embodiments of the present disclosure, which will not be elaborated here.

[0134] The following points need to be explained:

[0135] (1) The accompanying drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure, and other structures can refer to the general design.

[0136] (2) Without conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0137] The above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display substrate, comprising: a substrate substrate, including a display area and a peripheral area at least on one side of the display area; a plurality of sub-pixels, located in the display area and arranged in an array; a plurality of data lines, located in the display area and configured to provide data signals to the plurality of sub-pixels; control signal lines, located in the peripheral area and at least on one side of the display area; a plurality of data test lines, located in the peripheral area and at least on one side of the display area; a test circuit, located in the peripheral area and electrically connected to the plurality of data lines, the control signal lines and the plurality of data test lines, and configured to transmit test signals to the plurality of data lines through the plurality of data test lines under the control of the control signal lines, wherein the test circuit includes a plurality of test units, and each of at least one test unit in the plurality of test units includes a first control line and a plurality of control switches, the plurality of control switches include control ends, first ends and second ends, and the first control line is connected to the control signal lines and the control ends of the plurality of control switches; and auxiliary electrode lines, located in the peripheral area, wherein the control ends of the plurality of control switches are connected in series while being connected to the first control line, so that the auxiliary electrode lines and the first control line are connected in parallel with each other, and the second end of at least one control switch in the plurality of control switches is located between the orthographic projections of the first control line and the auxiliary electrode lines on the surface of the substrate substrate; the first ends of the plurality of control switches are respectively connected to the plurality of data test lines and are configured to receive test signals provided by the plurality of data test lines, and the second ends of the plurality of control switches are respectively electrically connected to the plurality of data lines.

2. The display substrate according to claim 1, wherein, The first control line and the auxiliary electrode line are located on different layers with respect to the substrate substrate, and the first control line and the auxiliary electrode line are respectively located in a first conductive layer and a second conductive layer that are insulated from each other at intervals.

3. The display substrate according to claim 2, wherein, The auxiliary electrode line is located on one side of the test circuit away from the display area or on one side close to the display area.

4. The display substrate according to claim 3, further comprising an electrostatic discharge circuit provided between the test circuit and the display area, the electrostatic discharge circuit being electrically connected to the plurality of data lines, and the auxiliary electrode line is located between the test circuit and the electrostatic discharge circuit.

5. The display substrate according to claim 4, further comprising a plurality of connection lines respectively provided between the plurality of control switches, the first control line overlaps with the active layers of the plurality of control switches, and the overlapping portion of the first control line and the active layer forms the control ends of the plurality of control switches, the first ends of the plurality of connection lines are connected to the first control line, and the second ends of the plurality of connection lines are connected to the auxiliary electrode line.

6. The display substrate according to claim 5, wherein, The plurality of data test lines extend along a first direction on one side of the test circuit away from the display area and are arranged at intervals along a second direction, and the first direction and the second direction intersect.

7. The display substrate according to claim 6 further includes a plurality of first lead segments and a plurality of data leads, and the plurality of first lead segments and the plurality of data leads extend along the second direction. The plurality of first lead segments are respectively connected to the plurality of data test lines and the first ends of the plurality of control switches. The plurality of data leads are respectively connected to the second ends of the plurality of control switches and the plurality of data lines.

8. The display substrate according to claim 7, wherein, The plurality of data leads include a plurality of second lead segments. The plurality of second lead segments are respectively connected to the second ends of the plurality of control switches and the electrostatic discharge circuit. The plurality of first lead segments and the plurality of second lead segments are located in a third conductive layer, and the third conductive layer is located between the first conductive layer and the second conductive layer and is insulated from each other at intervals. The orthographic projection of the plurality of second lead segments on the surface of the substrate and the orthographic projection of the auxiliary electrode line on the surface of the substrate overlap each other.

9. The display substrate according to claim 8, wherein, The plurality of data leads further include a third lead segment, and the third lead segment is located in the peripheral area and between the display area and the electrostatic discharge circuit. One ends of the plurality of third lead segments are electrically connected to the control end of the electrostatic discharge circuit, and the other ends of the plurality of third lead segments are respectively connected to the plurality of data lines. The third lead segment is located in the third conductive layer.

10. The display substrate according to claim 8, wherein, At least one of the plurality of sub-pixels includes a pixel driving circuit and a light-emitting element. Wherein, the pixel driving circuit includes a semiconductor layer, a first display area metal layer, a second display area metal layer, and a third display area metal layer, and the light-emitting element is located on a side of the pixel driving circuit away from the substrate and is connected to the third display area metal layer of the pixel driving circuit. A first insulating layer is located on the substrate, the semiconductor layer is located on a side of the first display area metal layer close to the substrate, the second display area metal layer is located on a side of the first display area metal layer away from the substrate, the third display area metal layer is located on a side of the second display area metal layer away from the substrate, and the first conductive layer is provided on the same layer as the first display area metal layer. The third conductive layer is provided on the same layer as the second display area metal layer. The second conductive layer is provided on the same layer as the third display area metal layer. The active layers of the plurality of control switches are provided on the same layer as the semiconductor layer. The plurality of connection lines are located in the first conductive layer, and the second ends of the plurality of connection lines are connected to the auxiliary electrode line.

11. The display substrate according to claim 10, wherein, The pixel driving circuit further includes a first transistor and a storage capacitor. The first transistor includes a gate, a source electrode, a drain electrode, and an active layer. The storage capacitor includes a first electrode plate and a second electrode plate. The active layer is located in the semiconductor layer, the gate and the first electrode plate are located in the first display area metal layer, the second electrode plate is located in the second display area metal layer, and the source electrode and the drain electrode are located in the third display area metal layer.

12. The display substrate according to claim 10, wherein, The test circuit further includes at least one virtual test unit, the at least one virtual test unit being located on a side of the test circuit away from the plurality of test units, and the second conductive layer includes a plurality of first transfer electrodes. Each of the at least one virtual test unit includes a plurality of virtual control switches, a first end of the plurality of virtual control switches being respectively connected to the plurality of data test lines, a control end of the plurality of virtual control switches being connected to the first control line, and the plurality of first transfer electrodes being respectively connected to the first end and the second end of the plurality of virtual control switches.

13. The display substrate according to claim 10, further comprising a plurality of power lines, the plurality of power lines routing around at least one side of the display area. Among them, The plurality of power lines includes a first power line and a second power line, the first power line being configured to provide a first power signal, and the second power line being configured to provide a second power signal. At least a part of the first power line and the second power line is located in the second conductive layer. The first power line routes on a side of the electrostatic discharge circuit away from the display area, the second power line routes on a side of the electrostatic discharge circuit close to the display area, and the first power line and the second power line are respectively connected to a first end and a second end of the electrostatic discharge circuit. The electrostatic discharge circuit includes a plurality of first electrostatic discharge units. One end of the plurality of second lead segments away from the test circuit is respectively connected to control ends of the plurality of first electrostatic discharge units.

14. The display substrate according to claim 13, wherein, The test circuit and the electrostatic discharge circuit are located on a first side of the display area, a second side and a third side of the display area are oppositely arranged and adjacent to the first side. The plurality of data test lines includes a first data test line, a second data test line and a third data test line, at least a part of the first data test line and the second data test line routes around the second side and the first side of the display area, and the second data test line is located on a side of the first data test line close to the display area. At least a part of the third data test line and the control signal line routes around the third side and the first side of the display area, and the control signal line is located on a side of the third data test line close to the display area. On a side of the test circuit away from the display area, the second data test line is located between the first data test line and the third data test line, the first data test line is located on a side away from the test circuit, the first conductive layer includes a first connection trace, the first connection trace extends along the second direction, and the semiconductor layer includes a plurality of first resistors. A first end of the control signal line is located on the first side of the display area and close to the test circuit, one end of the first connection trace is connected to the first end of the control signal line, and the other end of the first connection trace is connected to one end of the first control line close to the third side of the display area. First ends of the first data test line and the second data test line are located on a side of the test circuit away from the display area. At least one of the plurality of first resistors connects the first end of the first data test line and the control signal line, and at least another one of the plurality of first resistors connects the first end of the second data test line and the control signal line.

15. The display substrate according to claim 14, wherein, At least one of the first data test line, the second data test line, the third data test line, the control signal line, and the first control line is connected to the electrostatic discharge circuit.

16. The display substrate according to claim 15, wherein, The electrostatic discharge circuit further includes a second electrostatic discharge unit, which is located on at least one side of the plurality of first electrostatic discharge units and on one side close to the third side of the display area. The first conductive layer includes a second connection trace and a third connection trace, and the semiconductor layer includes a second resistor. One end of the second connection trace is connected to the control end of the second electrostatic discharge unit, and the other end of the second connection trace is connected to the first end of the control signal line. The second resistor connects the control end of the second electrostatic discharge unit and the first power supply line. The electrostatic discharge circuit further includes a third electrostatic discharge unit, which is located on one side of the second electrostatic discharge unit close to the third side of the display area. One end of the third connection trace is connected to the third data test line, and the other end of the third connection trace is connected to the control end of the third electrostatic discharge unit.

17. The display substrate according to any one of claims 14-16 further includes a bonding area and a signal access unit located on the fourth side of the display area opposite to the first side. The signal access unit is located between the bonding area and the display area. The bonding area includes a plurality of contact pads arranged along the first direction. The plurality of contact pads include a first contact pad and a second contact pad close to the second side of the display area, and a third contact pad and a fourth contact pad close to the third side of the display area. The second end of the first data test line extends to the fourth side of the display area and is connected to the second contact pad, and the second end of the second data test line extends to the fourth side of the display area and is connected to the first contact pad. The second end of the control signal line extends to the fourth side of the display area and is connected to the third contact pad. The second end of the third data test line extends to the fourth side of the display area and is connected to the fourth contact pad.

18. The display substrate according to claim 17, wherein, Parts of the first data test line, the second data test line, the third data test line, and the control signal line are located in the second conductive layer.

19. The display substrate according to claim 17, wherein, The plurality of power supply lines further include a third power supply line and a fourth power supply line. The third power supply line is configured to provide a third power signal to the plurality of sub-pixels. The fourth power supply line is configured to provide a fourth power signal to the plurality of sub-pixels. The plurality of contact pads further include a fifth contact pad, a sixth contact pad, a seventh contact pad, and an eighth contact pad. The seventh contact pad is located on one side of the second contact pad close to the second side of the display area, and the eighth contact pad is located on one side of the fourth contact pad close to the third side of the display area. The fifth contact pad is located between the seventh contact pad and the second contact pad, and the sixth contact pad is located between the fourth contact pad and the eighth contact pad. Both ends of the third power supply line are respectively connected to the seventh contact pad and the eighth contact pad and are routed around the display area. The third power supply line is located on a side of the first data test line and the third data test line away from the display area. Both ends of the fourth power supply line are respectively connected to the fifth contact pad and the sixth contact pad, and are routed between the signal access unit and the display area and extend to the display area. The orthographic projection of the fourth power supply line on the surface of the substrate overlaps with the orthographic projections of the first data test line, the second data test line, the third data test line, and the control signal line on the surface of the substrate. In the area where the orthographic projection of the fourth power supply line on the surface of the substrate overlaps with the orthographic projections of the first data test line, the second data test line, the third data test line, and the control signal line, the fourth power supply line is located in the second conductive layer, and the first data test line, the second data test line, the third data test line, and the control signal line are insulated from the second conductive layer at intervals.

20. A display device, comprising the display substrate according to any one of claims 1-19.

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