Display substrate, manufacturing method thereof, and display device

Abstract

A display substrate and a manufacturing method thereof and a display device. The display substrate includes a plurality of pixels arranged in an array; at least some of the pixels include a plurality of sub-pixels, at least some of the sub-pixels include a light-emitting element and a pixel circuit driving the light-emitting element to emit light, the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, the driving transistor includes an active layer, a gate, a first electrode and a second electrode, the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor receives a first power supply voltage, the second electrode of the driving transistor is connected to the light-emitting device to control the light-emitting device to emit light; at least some of the sub-pixels include a first via hole, the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole, so as to reduce the resistance of the connection position between the first electrode of the data writing transistor and the gate of the driving transistor and the active layer of the data writing transistor, improve the signal transmission efficiency, and simplify the manufacturing process.

Description

Technical Field

[0001] At least one embodiment of the present disclosure relates to a display substrate, a manufacturing method thereof, and a display device. Background Art

[0002] In the display field, organic light-emitting diode (OLED) display panels have the characteristics of self-luminescence, high contrast, low energy consumption, wide viewing angle, fast response speed, can be used for flexible panels, wide operating temperature range, and simple manufacturing, and have broad development prospects. Summary of the invention

[0003] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, which is provided with a plurality of pixels arranged in an array; at least some of the pixels include a plurality of sub-pixels, and at least some of the sub-pixels include a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, and the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, and the driving transistor includes an active layer, a gate, a first electrode and a second electrode, and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; at least some of the sub-pixels include a first via hole, and the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole.

[0004] For example, in the display substrate provided by at least one embodiment of the present disclosure, the gate of the driving transistor includes a main body and an extension portion connected to the main body, the orthographic projection of the main body on the base substrate overlaps with the orthographic projection of the active layer of the driving transistor on the base substrate, and the extension portion extends from the main body, and the extension portion is electrically connected to the first electrode of the data writing transistor and the active layer of the data writing transistor through the first via hole.

[0005] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode of the data write transistor includes a first conductive portion and a second conductive portion stacked on each other in a direction perpendicular to the base substrate, and the second conductive portion is located on a side of the first conductive portion away from the base substrate; the gate of the driving transistor is located on a side of the first conductive portion close to the second conductive portion and is spaced apart from the first conductive portion, and the second conductive portion is in contact with the gate of the driving transistor and the first conductive portion through the first via; the display substrate also includes a connecting portion, for example, in the display substrate provided in at least one embodiment of the present disclosure, which overlaps with the extension portion in a direction perpendicular to the base substrate, and connects the first conductive portion and the active layer of the data write transistor into an integrated structure.

[0006] For example, in the display substrate provided by at least one embodiment of the present disclosure, the material of the second conductive portion and the material of the connecting portion include the same semiconductor material, and the semiconductor material included in the first conductive portion is conductive.

[0007] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first conductive portion includes:

[0008] A first sub-portion located at a first side of the extension portion, wherein the second conductive portion is in direct contact with the first sub-portion through the first via hole at the first side;

[0009] The second conductive portion extends from a first side of the extending portion in the first via hole to the extending portion to contact at least a portion of an upper surface of the extending portion away from the base substrate.

[0010] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first conductive portion further includes:

[0011] A second sub-portion is located on a second side of the extension portion, wherein the second side is opposite to the first side, the second conductive portion extends from the first side of the extension portion in the first via hole across the extension portion to extend to the second side of the extension portion, and the second conductive portion is in direct contact with the second sub-portion through the first via hole on the second side.

[0012] For example, at least one embodiment of the present disclosure provides a display substrate further comprising:

[0013] a gate insulating layer, located between the gate of the driving transistor and the active layer of the driving transistor, wherein the gate of the driving transistor is located on a side of the gate insulating layer away from the substrate;

[0014] A first insulating layer is located on a side of the gate of the driving transistor away from the substrate, wherein the first via hole penetrates the gate insulating layer and the first insulating layer;

[0015] The gate insulating layer comprises an upper surface and a side surface intersecting with the upper surface of the gate insulating layer, the angle between the side surface of the extension portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a first angle, the angle between the side surface of the gate insulating layer and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a second angle, the second conductive portion comprises a middle portion directly contacting the extension portion, the angle between the side surface of the middle portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a third angle;

[0016] The first angle is greater than the second angle, or the first angle is greater than the third angle and the third angle is greater than the second angle.

[0017] For example, in the display substrate provided in at least one embodiment of the present disclosure, the storage capacitor includes:

[0018] A second capacitor electrode, at least part of which is in the same layer as the first electrode of the driving transistor and is an integral structure; and

[0019] The first capacitor electrode is insulated from the second capacitor electrode and is in the same layer as the active layer of the driving transistor and is an integrated structure, wherein the second capacitor electrode and the first capacitor electrode constitute two plates of the first capacitor of the storage capacitor.

[0020] For example, at least one embodiment of the present disclosure provides a display substrate further comprising:

[0021] An opaque shading layer, wherein the active layer of the driving transistor is located within the orthographic projection of the shading layer on the base substrate, the shading layer is electrically connected to the second capacitor electrode of the first capacitor, and the shading layer is insulated from the first capacitor electrode of the first capacitor and at least partially overlaps with the first capacitor electrode in a direction perpendicular to the base substrate to serve as a third capacitor electrode of the storage capacitor, the third capacitor electrode and the first capacitor electrode constitute two plates of the second capacitor of the storage capacitor, and the second capacitor is connected in parallel with the first capacitor.

[0022] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the base substrate, and the shading layer is located on a side of the active layer of the driving transistor close to the base substrate.

[0023] For example, in the display substrate provided by at least one embodiment of the present disclosure, the second conductive portion and the first electrode of the driving transistor are in the same layer and made of the same material.

[0024] For example, at least one embodiment of the present disclosure provides a display substrate further comprising:

[0025] A signal line includes a first layer, a second layer, and a third layer stacked in sequence perpendicular to the substrate and in a direction away from the substrate, wherein the first layer is spaced apart from the second layer, and the signal line also includes a signal line via, and the third layer is electrically connected to the second layer and the first layer through the signal line via.

[0026] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first layer is in the same layer as the active layer of the driving transistor, the second layer is in the same layer as the gate of the driving transistor and has the same material, and the third layer is in the same layer as the first electrode of the driving transistor and has the same material.

[0027] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first layer includes:

[0028] The first conductor portion is located on the first side of the second layer, wherein the third layer is in direct contact with the first conductor portion through the signal line via on the first side of the second layer; the third layer extends from the first side of the first conductor portion in the signal line via to the second side of the first conductor portion to contact at least a portion of the upper surface of the second layer away from the base substrate.

[0029] For example, in the display substrate provided by at least one embodiment of the present disclosure, the third layer is in direct contact with the upper surface of the second layer away from the base substrate and the side surface of the second layer intersecting with its upper surface, and the third layer is in direct contact with the first layer.

[0030] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first layer further includes:

[0031] The second conductor portion is located on the second side of the second layer in the line width direction of the signal line, wherein the second side of the second layer is opposite to the first side of the second layer, and the third layer extends from the first side of the second layer in the signal line via hole along the line width direction of the signal line across the second layer to extend to the second side of the second layer, and the third layer is in direct contact with the second conductor portion through the signal line via hole on the second side of the second layer.

[0032] For example, in the display substrate provided in at least one embodiment of the present disclosure, the first layer further includes:

[0033] The semiconductor portion overlaps with the second layer in a direction perpendicular to the base substrate, is in the same layer as the active layer of the driving transistor, and forms an integral structure with the first conductor portion.

[0034] For example, at least one embodiment of the present disclosure provides a display substrate, further comprising:

[0035] A data line is connected to the second electrode of the data writing transistor and is configured to provide a data signal to the data writing transistor, wherein the signal line includes the data line.

[0036] For example, at least one embodiment of the present disclosure provides a display substrate, further comprising:

[0037] A first power line is configured to provide a first power voltage to a first electrode of the driving transistor, wherein the signal line includes the first power line.

[0038] At least one embodiment of the present disclosure further provides a display device, which includes any one of the display substrates provided in the embodiments of the present disclosure.

[0039] At least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, the manufacturing method comprising: providing a base substrate; forming a plurality of pixels on the base substrate, wherein at least some of the plurality of pixels include a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; and forming a first via hole in at least some of the plurality of sub-pixels, wherein the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole.

[0040] For example, at least one embodiment of the present disclosure further provides a method for manufacturing a display substrate, comprising: forming a semiconductor layer; forming a gate insulating layer covering the semiconductor layer on a side of the semiconductor layer away from the base substrate; forming a gate conductive layer on a side of the gate insulating layer away from the base substrate; patterning the gate conductive layer through a patterning process to form a gate of the driving transistor; performing a patterning process on the gate insulating layer using the gate of the driving transistor as an etching barrier to expose a portion of the semiconductor layer, wherein the semiconductor layer includes a portion blocked by the gate insulating layer and a portion not blocked by the gate insulating layer; and patterning the portion of the semiconductor layer not blocked by the gate insulating layer. The portion of the gate insulating layer is subjected to conductor processing to form a first conductive portion, and the portion blocked by the gate insulating layer is not conductorized to constitute the active layer and the connecting portion of the driving transistor, wherein the gate of the driving transistor includes a main body portion and an extending portion connected to the main body portion, the projection of the main body portion overlaps with the projection of the active layer of the driving transistor, the extending portion extends from the main body portion, and the extending portion is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole; the connecting portion overlaps with the extending portion in a direction perpendicular to the base substrate, and connects the first conductive portion and the active layer of the data writing transistor into an integrated structure.

[0041] For example, at least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, wherein forming the first via includes: after forming the active layer of the driving transistor and the active layer of the data writing transistor, forming a first insulating layer on a side of the gate of the driving transistor away from the base substrate, wherein the first insulating layer covers the gate of the driving transistor, the gate of the data writing transistor and the gate insulating layer; and performing a composition process on the first insulating layer to form the first via, wherein the first via exposes at least a portion of the gate of the driving transistor and at least a portion of the first conductive portion; the manufacturing method also includes: forming a second conductive portion on a side of the gate of the driving transistor away from the base substrate, wherein the second conductive portion is electrically connected to the gate of the driving transistor and the first conductive portion through the first via, and the first conductive portion and the second conductive portion constitute a first pole of the data writing transistor.

[0042] For example, at least one embodiment of the present disclosure also provides a method for manufacturing a display substrate, which also includes: forming a signal line, including a first layer, a second layer, and a third layer formed and stacked in sequence in a direction perpendicular to the base substrate and away from the base substrate, wherein the first layer is spaced apart from the third layer, and the signal line also includes a signal line via, and the third layer is electrically connected to the second layer and the first layer through the signal line via.

[0043] For example, in at least one embodiment of the present disclosure, there is also provided a method for manufacturing a display substrate, wherein the first layer and the active layer of the driving transistor are simultaneously formed by performing the same conductor treatment process on the portion of the semiconductor layer not blocked by the gate insulating layer; the second layer and the gate of the driving transistor are simultaneously formed by performing the same patterning process on the gate conductive layer; and the third layer and the first electrode of the driving transistor are simultaneously formed by performing the same patterning process on the same film layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present invention, but are not intended to limit the present invention.

[0045] Figure 1 A schematic diagram of a display substrate provided for at least one embodiment of the present disclosure;

[0046] Figure 2A A pixel circuit diagram of a display substrate provided in at least one embodiment of the present disclosure;

[0047] Figure 2B-Figure 2D A signal timing diagram of a driving method for a pixel circuit provided by an embodiment of the present disclosure;

[0048] Figure 3A A schematic structural diagram of a sub-pixel of a display substrate provided by at least one embodiment of the present disclosure;

[0049] Figure 3B for Figure 2A A cross-sectional view along section line II';

[0050] Figure 3C for Figure 2A Another cross-sectional view along section line II';

[0051] Figure 4A A schematic plan view of a first conductive layer in a display substrate provided in at least one embodiment of the present disclosure;

[0052] Figure 4B A schematic plan view of a semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0053] Figure 4C A schematic plan view of a second conductive layer in a display substrate provided in at least one embodiment of the present disclosure;

[0054] Figure 4D A schematic plan view of a third conductive layer in a display substrate provided in at least one embodiment of the present disclosure;

[0055] Figure 4EA schematic plan view of a first electrode in a display substrate provided in at least one embodiment of the present disclosure;

[0056] Figure 4F A schematic plan view of a stack of a first conductive layer and a semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure;

[0057] Figure 4G A schematic plan view of a stack of a first conductive layer, a semiconductor layer, and a second conductive layer in a display substrate provided in at least one embodiment of the present disclosure;

[0058] Figure 4H A schematic plan view of a stack of a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer in a display substrate provided in at least one embodiment of the present disclosure;

[0059] Figure 5 for Figure 3A A cross-sectional view along the section line AA';

[0060] Figure 6 A schematic diagram of a display device provided by at least one embodiment of the present disclosure. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. Based on the described embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0062] Unless otherwise defined, the technical or scientific terms used herein shall have the usual meanings understood by persons of ordinary skill in the field to which the invention belongs. The words "first", "second" and similar terms used in the patent application specification and claims of the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Inside", "outside", "upper", "lower" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0063] The drawings in this disclosure are not drawn strictly according to the actual scale, and the number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the number shown in the drawings. The specific size and number of each structure can be determined according to actual needs. The drawings described in this disclosure are only schematic diagrams of the structures.

[0064] At least one embodiment of the present disclosure provides a display substrate, which includes a base substrate, which is provided with a plurality of pixels arranged in an array; at least some of the pixels among the plurality of pixels include a plurality of sub-pixels, and at least some of the sub-pixels among the plurality of sub-pixels include a light-emitting element and a pixel circuit driving the light-emitting element to emit light, and the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, and the driving transistor includes an active layer, a gate, a first electrode and a second electrode, and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; at least some of the sub-pixels among the plurality of sub-pixels include a first via hole, and the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole.

[0065] In the display substrate provided by the embodiment of the present disclosure, the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through only the first via hole. Compared with other connection methods, the contact resistance of the connection position is significantly reduced, the signal transmission efficiency is improved, and at the same time, the display substrate manufacturing process is simplified.

[0066] For example, Figure 1 Schematic diagram of a display substrate provided by at least one embodiment of the present disclosure. Figure 1As shown, the display substrate 10 includes a plurality of pixels 100 arranged in an array, at least some of the pixels 100 in the plurality of pixels 100 include a plurality of sub-pixels, at least some of the sub-pixels in the plurality of sub-pixels include a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, the driving transistor includes an active layer, a gate, a first pole and a second pole, and the data writing transistor includes an active layer, a gate, a first pole and a second pole. The first pole of the driving transistor is configured to receive a first power supply voltage, and the second pole of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light. For example, some of the pixels in the plurality of pixels 100 are dummy pixels (dummy pixel) 101, the dummy pixels 1000 do not participate in the display work, and each dummy pixel 1000 includes a plurality of dummy sub-pixels, but does not include a sub-pixel that plays a display driving role. For example, the display substrate 10 is an organic light-emitting diode (OLED) display substrate, and the light-emitting element is an OLED. The display substrate 10 may also include a plurality of scan lines and a plurality of data lines for providing scan signals (control signals) and data signals to the plurality of sub-pixels, thereby driving the plurality of sub-pixels. As required, the display substrate 10 may further include power lines, detection lines, etc.

[0067] The pixel circuit includes a driving subcircuit for driving the light-emitting element to emit light and a detection subcircuit for detecting the electrical characteristics of the subpixel to achieve external compensation. The embodiment of the present disclosure does not limit the specific structure of the pixel circuit.

[0068] For example, Figure 2A A schematic diagram of a 3T1C pixel circuit for the display substrate is shown. The pixel circuit of the display substrate provided in the embodiment of the present disclosure is not limited to a 3T1C pixel circuit. This embodiment takes the pixel circuit of the display substrate 10 as a 3T1C pixel circuit as an example to illustrate the structure of the display substrate. As required, the pixel circuit may further include a compensation circuit, a reset circuit, etc., which is not limited in the embodiment of the present disclosure.

[0069] Reference Figure 2A, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3 and a storage capacitor Cst. The first transistor T1 is the driving transistor described in the present application, and the second transistor T2 is the data writing transistor described in the present application. The first electrode of the second transistor T2 is electrically connected to the first capacitor electrode Ca of the storage capacitor Cst and the gate of the first transistor T1, the second electrode of the second transistor T2 is configured to receive the data signal DT, and the second transistor T2 is configured to write the data signal DT into the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal G1; the first electrode of the first transistor T1 is electrically connected to the second capacitor electrode Cb of the storage capacitor Cst, and is configured to be electrically connected to the first electrode of the light emitting element, the second electrode of the first transistor T1 is configured to receive the first power supply voltage V1 (for example, the high power supply voltage VDD), the first transistor The body transistor T1 is configured to control the current used to drive the light-emitting element under the control of the voltage of the gate of the first transistor T1; the first electrode of the third transistor T3 is electrically connected to the first electrode of the first transistor T1 and the second capacitor electrode Cb of the storage capacitor Cst, the second electrode of the third transistor T3 is configured to be connected to the detection line 230 to connect to the external detection circuit 21, and the third transistor T3 is configured to detect the electrical characteristics of the sub-pixel to which it belongs in response to the second control signal G2 to achieve external compensation; the electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element. The external detection circuit 21 is, for example, a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., and the embodiments of the present disclosure will not be described in detail.

[0070] For example, Figure 2A The storage capacitor Cst shown in the figure further includes a third capacitor electrode Cc, which is located on a side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is connected to the second capacitor electrode Cb through Figure 3A The vias 7 shown are electrically connected to each other to form a parallel capacitor structure, thereby increasing the capacitance value of the storage capacitor Cst. For example, in a direction perpendicular to the base substrate 101, the third capacitor electrode Cc, the second capacitor electrode Cb, and the first capacitor electrode Ca all overlap with each other.

[0071] The transistors used in the embodiments of the present disclosure can all be thin film transistors or field effect transistors or other switching devices with the same characteristics. The embodiments of the present disclosure are all described by taking thin film transistors as examples. The source and drain of the transistor used here can be symmetrical in structure, so the source and drain can be indistinguishable in structure. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor except the gate, one of the poles is directly described as the first pole and the other pole is the second pole. In addition, transistors can be divided into N-type and P-type transistors according to the characteristics of the transistor. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages), and the turn-off voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (for example, 5V, 10V or other suitable voltages), and the turn-off voltage is a low-level voltage (for example, 0V, -5V, -10V or other suitable voltages). It should be noted that in the following description, Figure 2A The transistor in the figure is an N-type transistor for illustration, but it is not intended to limit the present disclosure.

[0072] Combine the following Figure 2B-Figure 2D The signal timing diagram shown is Figure 2A The working principle of the pixel circuit shown is explained, Figure 2B shows the signal timing diagram of the pixel circuit during the display process, Figure 2C and Figure 2D The signal timing diagram of the pixel circuit during the detection process is shown.

[0073] For example, Figure 2B As shown, the display process of each frame of image includes a data writing and resetting phase 1 and a light emitting phase 2. Figure 2B The timing waveforms of each signal in each stage are shown. A working process of the 3T1C pixel circuit includes: in the data writing and resetting stage 1, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2, the first switch K1 is turned off, the analog-to-digital converter writes a reset signal to the first electrode of the light-emitting element (for example, the anode of the OLED) through the detection line 230 and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode of the light-emitting element to the working voltage; in the light-emitting stage 2, the first control signal G1 and the second control signal G2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in a saturated state and the current remains unchanged, and drives the light-emitting element to emit light.

[0074] For example, Figure 2CThe signal timing diagram of the pixel circuit when detecting the threshold voltage is shown. A working process of the 3T1C pixel circuit includes: the first control signal G1 and the second control signal G2 are both turn-on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; the first switch K1 is closed, the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line 230 and the third transistor T3, the first transistor T1 is turned on and charges the node S until the first transistor is turned off, and the digital-to-analog converter samples the voltage on the detection line 230 to obtain the threshold voltage of the first transistor T1. This process can be performed, for example, when the display device is turned off.

[0075] For example, Figure 2D The signal timing diagram of the pixel circuit when performing the detection of carrier mobility is shown. A working process of the 3T1C pixel circuit includes: in the first stage, the first control signal G1 and the second control signal G2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal DT is transmitted to the gate of the first transistor T1 through the second transistor T2; the first switch K1 is closed, and the analog-to-digital converter writes a reset signal to the first electrode (node ​​S) of the light-emitting element through the detection line 230 and the third transistor T3; in the second stage, the first control signal G1 is a closing signal, the second control signal G1 is an on signal, the second transistor T2 is turned off, the third transistor T3 is turned on, and the first switch K1 and the second switch K2 are disconnected to float the detection line 230; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 works in a saturated state and the current remains unchanged and drives the light-emitting element to emit light, and then the digital-to-analog converter samples the voltage on the detection line 230, and the carrier mobility in the first transistor T1 can be calculated in combination with the magnitude and duration of the light-emitting current. For example, this process can be performed during the blanking phase between display phases.

[0076] Through the above detection, the electrical characteristics of the first transistor T1 can be obtained and a corresponding compensation algorithm can be implemented.

[0077] For example, the display substrate 10 may further include a data driving circuit and a scanning driving circuit (not shown). The data driving circuit is configured to send a data signal, such as the above-mentioned data signal DT, as required (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply the data signal to the gate of the first transistor. The scanning driving circuit is configured to output various scanning signals, such as the above-mentioned first control signal G1 and the second control signal G2, which is, for example, an integrated circuit chip (IC) or a gate driving circuit (GOA) directly prepared on the display substrate.

[0078] For example, the display substrate 10 further includes a control circuit. For example, the control circuit is configured to control the data drive circuit to apply a data signal, and to control the gate drive circuit to apply a scan signal. An example of the control circuit is a timing control circuit (T-con). The control circuit can be in various forms, for example, including a processor and a memory, the memory including an executable code, and the processor runs the executable code to execute the above-mentioned detection method.

[0079] For example, the processor may be a central processing unit (CPU) or other forms of processing devices having data processing capabilities and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0080] For example, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on a computer-readable storage medium, and a processor may run the desired functions of the program instructions. Various applications and various data may also be stored in the computer-readable storage medium, such as electrical characteristic parameters obtained in the above-mentioned detection method, etc.

[0081] Figure 3A A schematic diagram of a sub-pixel of a display substrate 10 provided in at least one embodiment of the present disclosure is shown in FIG. Figure 3A As shown, the display substrate 10 includes a base substrate 101, and a plurality of sub-pixels P1 / P2 / P3 are located on the base substrate 101. The plurality of sub-pixels P1 / P2 / P3 are distributed in a pixel array along a first direction D1 and a second direction D2, and the pixel array includes a plurality of pixel columns and a plurality of pixel rows. The column direction of the pixel array is the first direction D1, and the row direction is the second direction D2. The first direction D1 intersects with the second direction D2, for example, they are orthogonal.

[0082] For example, the sub-pixels of each pixel row are divided into a plurality of pixel units, each of which is configured to emit full-color light. Figure 3A A pixel unit is exemplarily shown in FIG. 1 , and the implementation of the present disclosure is not limited to this layout; Figure 3B Shows Figure 3A A cross-sectional view along the section line II'. Figure 3AAs shown, the pixel unit includes a first sub-pixel P1, a second sub-pixel P2 and a third sub-pixel P3 arranged in sequence along a second direction D2, and the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 are respectively used to emit light of three basic colors (RGB); for example, the first sub-pixel P1 is a red sub-pixel, the second sub-pixel P2 is a blue sub-pixel, and the third sub-pixel P3 is a green sub-pixel.

[0083] Figure 4A A schematic plan view of a first conductive layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4B A schematic plan view of a semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4C A schematic plan view of a second conductive layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4D A schematic plan view of a third conductive layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4E A schematic plan view of a first electrode in a display substrate provided in at least one embodiment of the present disclosure; Figure 4F A schematic plan view of a stack of a first conductive layer and a semiconductor layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4G A schematic plan view of a stack of a first conductive layer, a semiconductor layer, and a second conductive layer in a display substrate provided in at least one embodiment of the present disclosure; Figure 4H A schematic plan view of a stack of a first conductive layer, a semiconductor layer, a second conductive layer, and a third conductive layer in a display substrate provided in at least one embodiment of the present disclosure. Figure 3A-3B as well as Figures 4A-4H The display substrate 10 includes a first conductive layer 501, a second insulating layer 202, a semiconductor layer 104, a gate insulating layer 200, a second conductive layer 502, a first insulating layer 201, a third conductive layer 503 and a fourth conductive layer 504 which are sequentially arranged on a base substrate 101.

[0084] The following will Figure 3A 1. For convenience of description, in the following description, T1g, T1s, T1d, and T1a are used to represent the gate, first electrode, second electrode, and active layer of the first transistor T1, respectively; T2g, T2s, T2d, and T2a are used to represent the gate, first electrode, second electrode, and active layer of the second transistor T2, respectively; T3g, T3s, T3d, and T3a are used to represent the gate, first electrode, second electrode, and active layer of the third transistor T3, respectively; and Ca, Cb, and Cc are used to represent the first capacitor electrode Ca, the second capacitor electrode Cb, and the third capacitor electrode Cc of the storage capacitor Cst, respectively.

[0085] It should be noted that the “same-layer arrangement” referred to in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process, and their materials may be the same or different. The “integrated structure” in the present disclosure refers to a structure in which two (or more) structures are formed by the same deposition process and patterned by the same patterning process and connected to each other, and their materials may be the same or different.

[0086] For example, combined with reference Figure 3A-3B and Figure 4A The first conductive layer 501 includes a light shielding layer 170, and the orthographic projection of the light shielding layer 170 on the base substrate 101 covers the orthographic projection of the active layer T1a of the first transistor T1 on the base substrate 101. The first transistor T1 is a driving transistor of the pixel circuit, and the stability of its electrical characteristics is very important for the light-emitting characteristics of the light-emitting element. The light shielding layer 170 is an opaque layer, which can prevent light from entering the active layer of the first transistor T1 from the back of the base substrate 101 and causing the threshold voltage of the first transistor T1 to drift, thereby avoiding affecting the light-emitting characteristics of the corresponding light-emitting element connected thereto.

[0087] For example, the light shielding layer 170 is a light-proof conductive material, such as a metal or metal alloy material. This configuration can alleviate the back channel phenomenon caused by the trapped charges on the substrate 101 .

[0088] For example, combined with reference Figure 3A-3B and Figure 4B The semiconductor layer 104 includes an active layer T1a of the first transistor T1, an active layer T2a of the second transistor T2, and an active layer T3a of the third transistor T3.

[0089] For example, the semiconductor layer 104 also includes a first

[0090] A capacitor electrode Ca, the first capacitor electrode Ca is obtained by conducting the semiconductor layer 104; that is, the first capacitor electrode Ca is disposed in the same layer as the active layer T1a of the first transistor T1, the active layer T2a of the second transistor, and the active layer T3a of the third transistor.

[0091] For example, combined with reference Figure 3A-3B and Figure 4C The second conductive layer 502 includes a gate T1g of the first transistor T1, a gate T2g of the second transistor T2, and a gate T3g of the third transistor T3.

[0092] For example, the display substrate 10 adopts a self-alignment process and uses the second conductive layer 502 as a mask to perform conductorization treatment (such as doping treatment) on the semiconductor layer 104, so that the portion of the semiconductor layer 104 not covered by the second conductive layer 502 is conductorized, thereby obtaining the first capacitor electrode Ca, and the portion of the active layer of each transistor located on both sides of the channel region is conductorized to form a first pole contact area and a second pole contact area, respectively, and the first pole contact area and the second pole contact area are respectively used to electrically connect to the first pole and the second pole of the transistor.

[0093] For example, combined with reference Figure 3A-3B and Figure 4D The third conductive layer 503 includes a first electrode T1s and a second electrode T1d of the first transistor T1, a first electrode T2s and a second electrode T2d of the second transistor T2, and a first electrode T3s and a second electrode T3d of the third transistor T3.

[0094] For example, the third conductive layer 503 further includes a second capacitor electrode Cb of the storage capacitor Cst. Figure 3B As shown, the second capacitor electrode Cb and the second electrode T1d of the first transistor T1 are arranged in the same layer and connected to each other as an integral structure. Figure 3B As shown, the first capacitor electrode Ca and the second capacitor electrode Cb overlap each other in a direction perpendicular to the base substrate 101 to form a storage capacitor Cst.

[0095] For example, Figure 3B As shown, each sub-pixel further includes a light-emitting element 125, for example, the light-emitting element is an organic light-emitting diode, including a first electrode 123, a light-emitting layer 124, and a second electrode 122 which are sequentially stacked. For example, the light-emitting element 125 is a top emission structure, the first electrode is reflective and the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode 122 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material. Combined with reference Figure 3A-3B and Figure 4E , the fourth conductive layer 504 includes a first electrode 123 .

[0096] For example, refer to Figure 3A-3BEach sub-pixel further includes a light-emitting element 125, for example, the light-emitting element is an organic light-emitting diode, including a first electrode 123, a light-emitting layer 124, and a second electrode 122 stacked in sequence. For example, the light-emitting element 125 is a top emission structure, the first electrode is reflective and the second electrode 122 is transmissive or semi-transmissive. For example, the first electrode is a material with a high work function to act as an anode, such as an ITO / Ag / ITO stacked structure; the second electrode 122 is a material with a low work function to act as a cathode, such as a semi-transmissive metal or metal alloy material, such as an Ag / Mg alloy material.

[0097] For example, Figure 3B As shown, the display substrate 10 further includes a third insulating layer 203 and a fourth insulating layer 204 located between the third conductive layer 503 and the first electrode 123 of the light-emitting element. For example, the third insulating layer 203 is a passivation layer, such as an inorganic insulating layer, such as silicon oxide, silicon nitride, silicon oxynitride, or silicon oxide; the fourth insulating layer 204 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), or other organic insulating materials. For example, the fourth insulating layer 204 is a planarization layer.

[0098] For example, the display substrate 10 further includes a pixel defining layer 206 located on the first electrode 123 of the light emitting element 125, and the pixel defining layer 206 is an organic insulating material, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), etc. The first electrode 123 of the light emitting element 125 is electrically connected to the first electrode T1s of the first transistor T1 and the second capacitor electrode Cb through a No. 8 via hole, and the No. 8 via hole, for example, passes through the third insulating layer 203 and the fourth insulating layer 204.

[0099] For example, the light emitting element OLED in each sub-pixel is configured to emit white light, and the display substrate 10 further includes a color filter layer, and the white light is emitted through the color filter layer to realize full-color display. For example, the light emitting layer 124 can be formed by an open mask combined with an evaporation process, so as to avoid using a fine metal mask (FMM) to pattern the light emitting layer, thereby avoiding the limited precision of the FMM and limiting the resolution of the display substrate.

[0100] For example, the light emitting element of the display substrate 10 provided in some embodiments of the present disclosure may adopt a bottom emission structure. Figure 3A-3BAs shown, the color filter layer is located on the side of the first electrode of the light-emitting element close to the base substrate 101, for example, between the third insulating layer 203 and the fourth insulating layer 204. The color filter layer includes a plurality of color filter portions 190 corresponding to a plurality of sub-pixels except the white sub-pixel, that is, the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 correspond to a color filter portion 190 respectively, and the light emitted by the light-emitting element of the first sub-pixel P1, the second sub-pixel P2 and the third sub-pixel P3 is emitted through the color filter portion 190 to form display light.

[0101] For example Figure 3A The sub-pixels shown are all sub-pixels participating in display, and virtual pixels are not shown. Virtual pixels can be set at appropriate positions on the display substrate according to actual needs. Figure 3A and Figure 3B , each sub-pixel includes a first via hole V0, and the first electrode T2s of the data writing transistor T2 is electrically connected to the gate T1g of the driving transistor T1 and the active layer T2a of the data writing transistor T2 through the first via hole V0. It should be noted that the first via hole V0 is a through hole. Therefore, in the display substrate 10 provided in the embodiment of the present disclosure, the first electrode T2s of the data writing transistor T2 is electrically connected to the gate T1g of the driving transistor T1 and the active layer of the data writing transistor through only the first via hole V0. Compared with other connection methods, the contact resistance of the connection position is significantly reduced, the signal transmission efficiency is improved, and the display substrate manufacturing process is simplified.

[0102] Figure 4B , the first electrode contact area T1a1 and the second electrode contact area T1a2 of the active layer T1a of the first transistor T1, the first electrode contact area T2a1 and the second electrode contact area T2a2 of the active layer T2a of the second transistor T2, and the first electrode contact area T3a1 and the second electrode contact area T3a2 of the active layer T3a of the third transistor T3 are shown. Figure 4B A connection portion 720 is also shown.

[0103] For example, combined with Figure 3A and Figure 3BThe gate T1g of the driving transistor T1 includes a main body 181 and an extension 180 connected to the main body 181. The orthographic projection of the main body 181 on the substrate 101 overlaps with the orthographic projection of the active layer T1a of the driving transistor on the substrate 101. The extension 180 extends from the main body 181. The extension 180 is electrically connected to the first electrode T2s of the data writing transistor T2 and the active layer T2a of the data writing transistor through the first via hole V0. The first via hole V0 includes a first region V1 and a second region V2 that are connected to each other; for example, the first electrode T2s of the data writing transistor T2 is directly in contact with the first electrode T2s of the data writing transistor T2 through the first region V1 and the second region V2 of the first via hole V0 to be electrically connected; the extension 180 is connected to the first electrode contact region T2a1 of the active layer T2a of the second transistor T2 through the first region V1 of the first via hole V0, as shown in FIG. Figure 4B The first electrode contact region T2a1 is in direct contact with the active layer T2a of the second transistor T2 to be electrically connected, so that the extension portion 180 is electrically connected to the active layer T2a of the data writing transistor through the first via hole V0.

[0104] For example, Figure 3B As shown, the first electrode T2s of the data writing transistor T2 includes a first conductive portion 111 and a second conductive portion 112 stacked on each other in a direction perpendicular to the base substrate 101, and the second conductive portion 112 is located on a side of the first conductive portion 111 away from the base substrate 101; the gate T1g of the driving transistor T1 is located on a side of the first conductive portion 111 close to the second conductive portion 112 and is spaced apart from the first conductive portion 111, and the second conductive portion 112 contacts the gate T1g of the driving transistor T1 and the first conductive portion 111 through a first via hole V0 to reduce contact resistance. The display substrate 10 also includes a connecting portion 720, which overlaps with the extension portion 180 in a direction perpendicular to the base substrate 101, and connects the first conductive portion 111 and the active layer T2a of the data writing transistor T2 (for example, the channel region T2a0 of the second transistor T2) into an integrated structure. For example, the connection portion 720 contacts the first conductive portion 111 , and the connection portion 720 contacts the channel region T2 a0 of the second transistor T2 via the first electrode contact region T2 a1 .

[0105] It should be noted that the first conductive portion 111 and the active layer T2a of the data writing transistor T2 are connected as an integral structure, which means that there is no gap between the two and there are no other layers or structures, but the materials of the two are different. For example, as mentioned above, in the process of using the second conductive layer 502 as a mask to conduct the semiconductor layer 104, the first conductive portion 111 and the first pole contact area T2a1 belong to the part of the semiconductor layer 104 that is not covered by the second conductive layer 502 and is conductorized, and the connecting portion 720 and the channel area T2a0 of the second transistor T2 belong to the part covered by the second conductive layer 502 and is not conductorized, so that the first conductive portion 111 and the active layer T2a of the data writing transistor T2 are different in material. In this way, the mask for forming the active layer by the composition process can be saved, and the manufacturing process can be simplified. Thus, the material of the second conductive portion 112 and the material of the connecting portion 180 include the same semiconductor material, and the semiconductor material included in the first conductive portion 111 is conductorized.

[0106] For example, the semiconductorization process may be a plasma treatment process for the semiconductor layer using plasma, or a doping process, etc. The specific process type may refer to conventional techniques in the art, and the present disclosure does not limit this. For example, the semiconductor material is IGZO. For example, the surface of IGZO is treated with a gas containing H+, so that the oxygen in IGZO is combined with H+, and the IGZO not covered by the second conductive layer is made conductive as it continuously reacts with the conductive gas.

[0107] For example, Figure 3B As shown, the first conductive portion 111 includes a first sub-portion S1, which is located on the first side of the extension portion 180; the second conductive portion 112 is directly in contact with the first sub-portion S1 through the first via hole V0 on the first side of the extension portion 180. The second conductive portion 112 extends from the first side of the extension portion 180 to the extension portion 180 in the first via hole V0 to contact at least a portion of the upper surface of the extension portion 180 away from the base substrate 101. For example, the second conductive portion 112 contacts the position of the upper surface of the extension portion 180 over the entire width in the first direction D1. In this way, the contact resistance of the electrical connection between the first conductive portion 111, the extension portion 180 and the second conductive portion 112 can be further reduced, thereby improving the signal transmission efficiency.

[0108] For example, the first conductive portion 111 also includes a second sub-portion S2, which is located on the second side of the extension portion 180, and the second side of the extension portion 180 is opposite to the first side of the extension portion 180; the second conductive portion 112 extends from the first side of the extension portion 180 in the first via hole V0 across the extension portion 180 to extend to the second side of the extension portion 180, and the second conductive portion 112 is directly in contact with the second sub-portion S2 through the first via hole V0 on the second side of the extension portion 180, so as to further reduce the contact resistance of the electrical connection between the first conductive portion 111, the extension portion 180 and the second conductive portion 112, thereby improving the signal transmission efficiency.

[0109] For example, the gate insulating layer 200 is located between the gate T1g of the driving transistor T1 and the active layer T1a of the driving transistor T1, and the gate T1g of the driving transistor T1 is located on the side of the gate insulating layer 200 away from the base substrate 101; the second insulating layer 202 is located on the side of the gate T1g of the driving transistor T1 away from the base substrate 101, and the first via hole V0 penetrates the gate insulating layer 200 and the second insulating layer 202.

[0110] refer to Figure 3B An enlarged schematic diagram of area D in . The extension portion 180 includes a side surface intersecting with the upper surface, and the second conductive portion 112 also covers the side surface of the extension portion and contacts the side surface of the extension portion 180; the gate insulating layer 200 includes an upper surface and a side surface intersecting with the upper surface of the gate insulating layer, and the angle between the side surface of the extension portion 180 and the plane where the upper surface of the extension portion 180 is located, the angle close to the extension portion 180 is a first angle θ1, and the angle between the side surface of the gate insulating layer 200 and the plane where the upper surface of the extension portion 180 is located, the angle close to the extension portion 180 is a second angle θ2; for example, the first angle θ1 is smaller than the second angle θ2, that is, the slope angle of the side surface of the extension portion 180 is smaller than the slope angle of the side surface of the gate insulating layer 200, which is beneficial to increase the reliability of the contact between the second conductive portion 112 and the extension portion 180, thereby ensuring the reliability and stability of the electrical connection between the two. For another example, Figure 3C for Figure 2A Another cross-sectional view along the section line II', Figure 3CIn the illustrated embodiment, the second conductive portion 112 includes a middle portion 800 directly in contact with the extension portion 180, and the angle between the side surface of the middle portion 800 and the plane where the upper surface of the extension portion 180 is located, the angle close to the extension portion 180 is a third angle θ3, the first angle θ1 is greater than the third angle θ3 and the third angle θ3 is greater than the second angle θ2, that is, the second angle θ2 is the smallest, which is conducive to the attachment of the layer above the gate insulating layer 200 above it, and the length of the second conductive portion 112 in the first direction is greater than the length of the extension portion 180 thereunder in the first direction, so that its resistance is greater, and the third angle θ3 is less than the first angle θ1, so that the thickness of the second conductive portion 112 in the direction perpendicular to the substrate can be made larger, which is conducive to reducing the resistance of the second conductive portion 112, and, Figure 3B The angle relationship is more conducive to the stability of the structure.

[0111] For example, schematically, Figure 3B As shown, the second capacitor electrode Cb is at least partially in the same layer as the first electrode T1s of the driving transistor T1 and is an integral structure; the first capacitor electrode Ca is insulated from the second capacitor electrode Cb and is in the same layer as the active layer T1g of the driving transistor T1 and is an integral structure, and the second capacitor electrode Cb and the first capacitor electrode Ca constitute two plates of the first capacitor C1 of the storage capacitor Cst.

[0112] For example, the projection of the active layer of the driving transistor is located within the positive projection of the opaque light-shielding layer 170 on the base substrate 101, the light-shielding layer 170 is electrically connected to the second capacitor electrode Cb of the first capacitor, and the light-shielding layer 170 is insulated from the first capacitor electrode Ca of the first capacitor and at least partially overlaps in a direction perpendicular to the base substrate 101 to serve as the third capacitor electrode Cc of the storage capacitor Cst. The third capacitor electrode Cc and the first capacitor electrode Ca constitute the two plates of the second capacitor C2 of the storage capacitor Cst. The second capacitor is connected in parallel with the first capacitor to increase the charge storage capacity of the capacitor and better realize the compensation effect of the storage capacitor. The third capacitor electrode Cc is located on the side of the first capacitor electrode Ca away from the second capacitor electrode Cb and is connected to the second capacitor electrode Cb through Figure 3A The via holes No. 7 shown are electrically connected to each other to form a parallel capacitor structure, thereby increasing the capacitance value of the storage capacitor Cst.

[0113] For example, the first electrode T1s of the driving transistor T1 is located on a side of the active layer T1a of the driving transistor T1 away from the base substrate 101 , and the light shielding layer 170 is located on a side of the active layer T1a of the driving transistor T1 close to the base substrate 101 .

[0114] For example, the second conductive portion 112 and the first electrode T1s of the driving transistor T1 are in the same layer and made of the same material; both are located in the third conductive layer 503 and can be formed by performing the same patterning process on the same film layer, which is beneficial to simplifying the manufacturing process of the display substrate.

[0115] For example, the display substrate 10 further includes signal lines. Figure 3A As shown, for example, the display substrate 10 further includes a plurality of signal lines extending along the first direction D1, for example, the signal lines may include data lines DL, power lines (for example, a first power line 240 providing a high power voltage VDD or a second power line 250 providing a ground power voltage VSS), a detection line 230 or an auxiliary electrode line, etc. Figure 3A As shown, each second portion 152 intersects with at least one data line in a direction perpendicular to the base substrate 101, thereby defining a plurality of first hollow areas arranged along the second direction D2; each second portion 162 intersects with at least one data line in a direction perpendicular to the base substrate 101, thereby defining a plurality of second hollow areas arranged along the second direction D2.

[0116] By setting the intersection of the scan line and the signal line as a ring structure, that is, a dual-channel structure, the yield of the device can be effectively improved. For example, the intersection of the signal line is prone to short circuit failure due to electrostatic breakdown of the parasitic capacitor. During the detection process, when a short circuit failure is detected in one channel of the ring structure, the channel can be removed (for example, by laser cutting), and the circuit structure can still work normally through the other channel.

[0117] For example, Figure 3A As shown, the plurality of signal lines include a plurality of data lines DL, and the plurality of data lines DL are connected one-to-one with each column of sub-pixels in the sub-pixel array to provide data signals for the sub-pixels. For a pixel row, the plurality of data lines are divided into a plurality of data line groups corresponding one-to-one with a plurality of pixel units in the pixel row, such as Figure 3A As shown, each data line group includes a first data line DL1 connected to the first sub-pixel P1, a second data line DL2 connected to the second sub-pixel P2, and a third data line DL3 connected to the third sub-pixel P3. For each pixel unit, the data lines DL1-DL3 corresponding to the pixel unit are located between the first sub-pixel P1 and the third sub-pixel P3. This arrangement can provide space for the arrangement of detection lines and power lines.

[0118] For example, Figure 3AAs shown, the display substrate 10 further includes a plurality of detection lines 230 extending along the first direction D1, and the detection lines 230 are used to connect to the detection subcircuit (such as the third transistor T3) in the subpixel 100, and connect the detection subcircuit to the external detection circuit. For example, there is at least one column of subpixels between each detection line 230 and any one of the plurality of data lines DL; that is, the detection line 230 is not directly adjacent to any data line DL. For example, Figure 3A As shown, for each pixel unit, the first data line DL1 and the second data line DL2 are located between the first sub-pixel P1 and the second sub-pixel P2, the third data line DL3 is located between the second sub-pixel P2 and the third sub-pixel P3, and the detection line 230 is located on the side of the third sub-pixel P3 away from the second sub-pixel P2 and the first sub-pixel P1.

[0119] This arrangement avoids signal delay on the data line caused by the resistive-capacitive load caused by the data line being directly adjacent to the detection line, further avoiding the display unevenness and other undesirable problems caused by the delay. In addition, since the signal transmitted on the data line DL is usually a high-frequency signal, setting the detection line 230 and the data line DL to be not directly adjacent can avoid the detection line 230 receiving high-frequency signal crosstalk during the external compensation charging sampling process, thereby affecting the sampling accuracy.

[0120] For example, Figure 3A As shown, the three sub-pixels in the pixel unit share a detection line 230, and the detection line 230 is electrically connected to the second electrodes T3d of the third transistors T3 in the three sub-pixels through the detection portion 231 extending along the second direction D2. The detection line 230 is electrically connected to the detection portion 231 through the via 12, and the detection portion 231 is electrically connected to the second electrode T3d of the third transistor T3 through the via No. 10. The first electrode T3s of the third transistor T3 is electrically connected to the first electrode contact area T3a1 of the third transistor T3 through the via No. 6, and the second electrode T3d of the third transistor T3 is electrically connected to the second electrode contact area T3a2 of the third transistor T3 through the via No. 5.

[0121] For example, the third transistor T3 and the second capacitor electrode Cb are disposed in the same layer and connected to form an integrated structure.

[0122] For example, Figure 3A As shown, the display substrate 10 further includes a plurality of first power lines 240 extending along the first direction D1, and the plurality of first power lines 240 are configured to provide a first power voltage for a plurality of sub-pixels, and the power voltage is, for example, a high power voltage VDD. The first power lines 240 are, for example, located in the third conductive layer 503. Figure 3AAs shown, there is at least one pixel column between each of the plurality of first power lines 240 and any one of the plurality of data lines; that is, the first power line 240 is not directly adjacent to any data line DL. This arrangement avoids signal delay on the data line caused by the resistance-capacitance load caused by the data line being directly adjacent to the power line, and further avoids color deviation, uneven display and other undesirable problems caused by the delay.

[0123] For example, any first power line 240 does not overlap with the detection part 231 in a direction perpendicular to the base substrate 101, that is, the first power line 240 is arranged at the interval corresponding to the adjacent detection part 231. This arrangement reduces the overlap of the signal lines and effectively reduces the parasitic capacitance between the signal lines and the signal delay caused thereby.

[0124] For example, Figure 3B As shown, the first power line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the directly adjacent sub-pixel (e.g., the first sub-pixel P1) through via hole No. 3, for example, the power line and the second electrode T1d of the first transistor T1 are an integrated structure. For example, the first power line 240 is electrically connected to the second electrode T1d of the first transistor T1 of the sub-pixel that is not directly adjacent to the first power line 240 through the connecting electrode 241. For example, the connecting electrode 241 is electrically connected to the second electrode T1d of the first transistor T1 of the second sub-pixel or the fourth sub-pixel through via hole No. 11.

[0125] Figure 5 for Figure 3A Sectional view along section line A-A'. Figure 5 As shown, when the signal line is a first power line providing a high power supply voltage VDD, the signal line, i.e., the first power line 240, includes a first layer 2401, a second layer 2402, and a third layer 2403 stacked in sequence perpendicular to the base substrate 101 and in a direction away from the base substrate 101, and the first layer 2401 is spaced apart from the second layer 2402; the first power line 240 also includes a signal line via V3, and the third layer 2403 is electrically connected to the second layer 2402 and the first layer 2401 through the signal line via V3. In this way, in the display substrate provided by the embodiment of the present disclosure, the first layer 2401, the second layer 2402, and the third layer 2403 of the signal line are connected in parallel, which reduces the resistance of the signal line; and the third layer 2403 is electrically connected to the second layer 2402 and the third layer 2403 through only one via, the signal line via V3, which significantly reduces the contact resistance of the connection position compared with other connection methods, improves the transmission efficiency of the signal in the signal line, and simplifies the display substrate manufacturing process.

[0126] For example, the first layer 2401 is in the same layer as the active layer T1a of the driving transistor T1, the second layer 2402 is in the same layer as the gate T1g of the driving transistor T1 and is made of the same material, and the third layer 2403 is in the same layer as the first electrode T1s of the driving transistor T1 and is made of the same material. For example, the first layer 2401 further includes a semiconductor portion A3, which overlaps with the second layer 2402 in a direction perpendicular to the base substrate 101, is in the same layer as the active layer T1a of the driving transistor T1, and forms an integral structure with the first conductor portion 111. For example, in the above-mentioned process of conducting the semiconductor layer using the second conductive layer 502 as a mask, the first layer 2401 and the semiconductor portion A3 blocked by the second layer 2402 are formed at the same time; at the same time, the second layer 2402 and the gate T1g of the driving transistor T1 can be formed using the same patterning process, and the third layer 2403 and the first electrode T1s of the driving transistor T1 can be formed using the same patterning process, so as to simplify the process. For example, the first layer 2401 is located on the semiconductor layer 104, the second layer 2402 is located on the second conductive layer 502, and the third layer 2403 is located on the third conductive layer 503. Thus, in the case of reducing the resistance of the signal line, the structure and manufacturing process of the display substrate are greatly simplified.

[0127] For example, Figure 5 As shown, the first layer 2401 includes a first conductor portion A1, which is located on the first side of the second layer 2402; the third layer 2403 is in direct contact with the first conductor portion A1 through the signal line via V3 on the first side of the second layer 2402; the third layer 2403 extends from the first side of the first conductor portion A1 in the signal line via V3 to the second side of the first conductor portion A1 to contact at least a portion of the upper surface of the second layer 2402 away from the base substrate 101. In this way, the contact resistance of the electrical connection between the first conductor portion A1, the second layer 2402 and the third layer 2403 can be further reduced, thereby improving the signal transmission efficiency.

[0128] For example, Figure 5 As shown, the third layer 2403 is in direct contact with the upper surface of the second layer 2402 away from the base substrate 101 and the side surface of the second layer 2402 intersecting with its upper surface, and the third layer 2403 is in direct contact with the first layer 2401 to further reduce the contact resistance of the electrical connection between the first layer 2401, such as the first conductor portion A1, the second layer 2402 and the third layer 2403, and improve the signal transmission efficiency.

[0129] For example, Figure 5As shown, the first layer 2401 also includes a second conductor portion A2, which is located on the second side of the second layer 2402 in the line width direction of the signal line, and the second side of the second layer 2402 is opposite to the first side of the second layer 2402; the third layer 2403 extends from the first side of the second layer 2402 in the signal line via hole V3 along the line width direction of the signal line across the second layer 2402 to extend to the second side of the second layer 2402, and the third layer 2403 is in direct contact with the second conductor portion A2 through the signal line via hole V3 on the second side of the second layer 2402 to increase the contact area between the third layer 2403 and the second layer 2402 and the first layer 2401, and reduce the contact resistance between the third layer 2403 and the second layer 2402 and the third layer 2403 and the first layer 2401.

[0130] For example, the signal line via V3 includes a first portion V31 and a second portion V32 that are connected to each other. The third layer 2403 is in direct contact with the first conductor portion A1 on the first side of the second layer 2402 through the first portion V31 of the signal line via V3; the third layer 2403 is in direct contact with the second conductor portion A2 on the second side of the second layer 2402 through the second portion V32 of the signal line via V3.

[0131] Figure 3A and Figure 3B Take the signal line as a first power line providing a first power voltage to the first electrode T1s of the driving transistor T1 as an example. In some embodiments, the signal line may further include a data line DT connected to the second electrode T2d of the data writing transistor T2 and configured to provide a data signal to the data writing transistor T2.

[0132] For example, Figure 3A As shown, a signal line may be provided with one or more signal line vias V3. Figure 3A In the example shown, one first power line 240 , for example, four signal line vias V3 may be provided on the first power line 240 .

[0133] For example, in some embodiments, the signal line further includes a detection line 230 , and one detection line 230 may include one or more signal line vias V3 .

[0134] For example, in some embodiments, the signal line further includes a second power line 250, and the second power line 250 provides a low voltage VSS for the light emitting device. One second power line 250 may include one or more signal line vias V3.

[0135] Combination Figure 3A-3B and Figure 4D The second power line 250 is located in the third conductive layer 503 and is connected to the second electrode 122, such as the cathode, through hole No. 13.

[0136] For example, Figure 3A As shown, the second power line 250 is connected to the second electrode layer through hole No. 14 to form a double-layer routing, thereby reducing the resistance of the second power line 250; for example, one second power line 250 includes multiple holes No. 14. Similarly, the detection line 230 is connected to the second electrode layer through hole No. 15 to form a double-layer routing, thereby reducing the resistance of the detection line 230; for example, one detection line 230 includes multiple holes No. 15.

[0137] At least one embodiment of the present disclosure further provides a display panel, including any of the above display substrates 10. It should be noted that the above display substrate 10 provided in at least one embodiment of the present disclosure may include a light-emitting element 125, or may not include the light-emitting element 125, that is, the light-emitting element 125 may be formed in a panel factory after the display substrate 10 is completed. In the case where the display substrate 10 itself does not include the light-emitting element 125, the display panel provided in the embodiment of the present disclosure further includes the light-emitting element 125 in addition to the display substrate 10.

[0138] For example, the display panel is an OLED display panel, and accordingly the display substrate 10 included therein is an OLED display substrate.

[0139] At least one embodiment of the present disclosure further provides a display device 30, such as Figure 6 As shown, the display device 30 includes any of the above-mentioned display substrates 10 or display panels 20. The display device in this embodiment can be: a display, an OLED panel, an OLED TV, an electronic paper, a mobile phone, a tablet computer, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0140] At least one embodiment of the present disclosure also provides a method for manufacturing the above-mentioned display substrate. The manufacturing method includes: providing a base substrate; forming a plurality of pixels on the base substrate, wherein at least some of the plurality of pixels include a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; and forming a first via hole in at least some of the plurality of sub-pixels, wherein the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole.

[0141] For example, a method for manufacturing a display substrate includes: forming a semiconductor layer; forming a gate insulating layer covering the semiconductor layer on a side of the semiconductor layer away from the base substrate; forming a gate conductive layer on a side of the gate insulating layer away from the base substrate; patterning the gate conductive layer through a patterning process to form a gate of the driving transistor; performing a patterning process on the gate insulating layer using the gate of the driving transistor as an etching barrier to expose a portion of the semiconductor layer, wherein the semiconductor layer includes a portion blocked by the gate insulating layer and a portion not blocked by the gate insulating layer; and performing a patterning process on the portion of the semiconductor layer not blocked by the gate insulating layer. The gate insulating layer is subjected to a conductive treatment to form a first conductive portion, and the portion blocked by the gate insulating layer is not conductively treated to constitute the active layer and the connecting portion of the driving transistor, wherein the gate of the driving transistor includes a main body portion and an extending portion connected to the main body portion, the projection of the main body portion overlaps with the projection of the active layer of the driving transistor, the extending portion extends from the main body portion, and the extending portion is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole; the connecting portion overlaps with the extending portion in a direction perpendicular to the base substrate, and connects the first conductive portion and the active layer of the data writing transistor into an integrated structure.

[0142] For example, the formation of the first via hole includes: after forming the active layer of the driving transistor and the active layer of the data writing transistor, forming a first insulating layer on the side of the gate of the driving transistor away from the substrate, wherein the first insulating layer covers the gate of the driving transistor, the gate of the data writing transistor and the gate insulating layer; and performing a composition process on the first insulating layer to form the first via hole, wherein the first via hole exposes at least a portion of the gate of the driving transistor and at least a portion of the first conductive portion; the manufacturing method also includes: forming a second conductive portion on the side of the gate of the driving transistor away from the substrate, wherein the second conductive portion is electrically connected to the gate of the driving transistor and the first conductive portion through the first via hole, and the first conductive portion and the second conductive portion constitute the first pole of the data writing transistor. Thus, the first pole of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole.

[0143] For example, the manufacturing method of the display substrate also includes: forming a signal line, including a first layer, a second layer, and a third layer stacked in sequence perpendicular to the base substrate and in a direction away from the base substrate, wherein the first layer is spaced apart from the third layer, and the signal line also includes a signal line via, and the third layer is electrically connected to the second layer and the first layer through the signal line via.

[0144] For example, the first layer and the active layer of the driving transistor are formed simultaneously by performing the same conductor treatment process on the portion of the semiconductor layer not blocked by the gate insulating layer; the second layer and the gate of the driving transistor are formed simultaneously by performing the same composition process on the gate conductive layer; the third layer and the first electrode of the driving transistor are formed simultaneously by performing the same composition process on the same film layer.

[0145] The following will be combined Figure 3A-3B and Figure 4A-4D , and taking the case of two pixels, each pixel including three sub-pixels as an example, the method for manufacturing the display substrate provided by the embodiment of the present disclosure is exemplified, but the embodiment of the present disclosure is not limited to this. Figure 3A-3B and Figure 4A-4D The following diagram shows two pixels of a display substrate, each pixel including three sub-pixels. Figure 4A-4D The patterns of the first conductive layer, the semiconductor layer, the second conductive layer, and the third conductive layer in a total of six sub-pixels are respectively shown.

[0146] For example, the manufacturing method includes the following steps S1-S5.

[0147] Step S1: forming a first conductive material layer, and patterning the first conductive material layer to form Figure 4A The first conductive layer 501 shown, namely the light shielding layer 170 and the third capacitor electrode Cc of the storage capacitor Cst. The patterning process also forms the detection portion 231 and the connection electrode 241 which are insulated from each other.

[0148] Step S2: forming a second insulating layer 202 on the first conductive layer 501 and forming a semiconductor material layer on the first insulating layer, and patterning the semiconductor material layer to form Figure 4B The semiconductor layer 104 shown in the figure, namely, forms the active layer T1a of the first transistor T1, the active layer T2a of the second transistor T2 and the active layer T3a of the third transistor T3 which are spaced apart from each other. For example, when the semiconductor material layer is patterned, the same patterning process is used to form Figure 5 The first layer 2401 of the signal lines is shown to simplify the manufacturing process of the display substrate.

[0149] Step S3: forming a gate insulating layer 200 on the semiconductor layer 104 and forming a second conductive material layer on the second insulating layer, and performing a patterning process on the second conductive material layer to form a gate insulating layer 200 on the semiconductor layer 104. Figure 4C The second conductive layer 502 shown forms the gate T1g of the first transistor T1, the gate T2g of the second transistor T2 and the gate T3g of the third transistor T3 which are insulated from each other. Figure 4CThe extension 180 is also shown. For example, when the second conductive material layer is patterned, the second conductive layer 502 is formed by the same patterning process. Figure 5 The second layer 2402 of the signal line shown, that is, the second layer and the gate of the driving transistor are formed simultaneously by performing the same patterning process on the gate conductive layer, so as to simplify the manufacturing process of the display substrate.

[0150] For example, Figure 4C As shown, the second conductive layer 502 further includes a first scan line 150 and a second scan line 160 which are insulated from each other.

[0151] For example, the line width of the first scan line 150 and the second scan line 160 is in the range of 5-15 microns.

[0152] For example, the first scan line 150 is integrated with the gate T2g of the second transistor T2 of a corresponding row of sub-pixels, and the second scan line 160 is integrated with the gate T3g of the third transistor T3 of a corresponding row of sub-pixels.

[0153] Step S4: adopt a self-alignment process and use the second conductive layer 502 as a mask to perform conductor treatment on the semiconductor layer 204 (for example, plasma treatment, doping treatment, etc.), so that the portion of the semiconductor layer 204 not covered by the second conductive layer 502 is conductorized, thereby obtaining the first capacitor electrode Ca, and the portion of the active layer of each transistor located on both sides of the channel region is conductorized to form a first pole contact area and a second pole contact area, respectively, and the first pole contact area and the second pole contact area are respectively used to electrically connect to the first pole and the second pole of the transistor. Figure 4B , the first electrode contact area T1a1 and the second electrode contact area T1a2 of the active layer T1a of the first transistor T1, the first electrode contact area T2a1 and the second electrode contact area T2a2 of the active layer T2a of the second transistor T2, and the first electrode contact area T3a1 and the second electrode contact area T3a2 of the active layer T3a of the third transistor T3 are shown. Figure 4B The connecting portion 720 is also shown in FIG. When the semiconductor layer 204 is subjected to conductor processing using the second conductive layer 502 as a mask, a Figure 5 The first conductor portion A1, the second conductor portion A2 and the semiconductor portion A3 shown, that is, the first layer and the active layer of the driving transistor are formed simultaneously through the same conductor processing process through the portion of the semiconductor layer not blocked by the gate insulating layer, so as to simplify the manufacturing process of the display substrate.

[0154] For example, before the semiconductor layer 104 is subjected to the conductorization treatment, the gate insulating layer 200 is subjected to the etching process, so that the area of ​​the gate insulating layer 200 not covered by the second conductive layer 502 is completely etched, that is, the second insulating layer 103 and the second conductive layer 502 overlap in the direction perpendicular to the base substrate 101. In this way, when the area of ​​the semiconductor layer 204 not covered by the second conductive layer 202 is subjected to the conductorization treatment by ion implantation, the implanted ions may not be blocked by the gate insulating layer 200.

[0155] Step S5: forming a first insulating layer 201 on the second conductive layer 502, and forming a third conductive material layer on the first insulating layer 201, and patterning the third conductive material layer to form Figure 4D The third conductive layer 503 shown in the figure forms the first electrode T1s and the second electrode T1d of the first transistor T1, the first electrode T2s and the second electrode T2d of the second transistor T2, and the first electrode T3s and the second electrode T3d of the third transistor T3. When the third conductive material layer is patterned, the same patterning process is used to simultaneously form Figure 5 The third layer 2403 shown, that is, the third layer and the first electrode of the driving transistor are formed simultaneously by performing the same patterning process on the same film layer, so as to simplify the manufacturing process of the display substrate.

[0156] For example, the third conductive layer 503 further includes a data line DL, a detection line 230 and a first power line 240 which are insulated from each other.

[0157] For example, the line width of the data line DL is in the range of 5-15 micrometers, the line width of the detection line 230 is in the range of 5-30 micrometers, and the line width of the first power line 240 is in the range of 5-30 micrometers.

[0158] For example, Figure 4D As shown, the first power line 240 and the second electrode T1d of the first transistor T1 in the directly adjacent (closest) sub-pixel are an integrated structure. For example, each data line 110 and the second electrode T2d of the second transistor T2 in the sub-pixel connected thereto are an integrated structure.

[0159] For example, the material of the semiconductor material layer includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0160] For example, the first conductive material layer is a light-shielding conductive material, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by the combination of the above metals. For example, the first conductive material layer can be a molybdenum-titanium alloy, such as a thickness of 50-100 nanometers.

[0161] For example, the materials of the second conductive material layer and the third conductive material layer may include gold (Au), silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), magnesium (Mg), tungsten (W) and alloy materials formed by combinations of the above metals; or conductive metal oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), aluminum zinc oxide (AZO), etc.

[0162] For example, the second conductive material layer is a stacked structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of the copper is 300-400 nanometers.

[0163] For example, the third conductive material layer is a stacked structure of molybdenum-titanium alloy and copper, for example, the thickness of the molybdenum-titanium alloy is 30-50 nanometers, and the thickness of the copper is 400-700 nanometers.

[0164] For example, the material of the semiconductor material layer includes but is not limited to silicon-based materials (amorphous silicon a-Si, polycrystalline silicon p-Si, etc.), metal oxide semiconductors (IGZO, ZnO, AZO, IZTO, etc.) and organic materials (sixithiophene, polythiophene, etc.).

[0165] For example, the semiconductor material layer is made of indium gallium zinc oxide and has a thickness of 30-50 nanometers.

[0166] For example, the second insulating layer 202, the gate insulating layer 200, and the first insulating layer 201 are, for example, inorganic insulating layers, such as silicon oxide, silicon nitride, silicon oxynitride, and other silicon oxides, silicon nitrides, or silicon oxynitrides, or aluminum oxide, titanium nitride, and other insulating materials including metal oxynitrides. For example, these insulating layers may also be organic materials, such as polyimide (PI), acrylate, epoxy resin, polymethyl methacrylate (PMMA), and the like, which are not limited in the embodiments of the present disclosure.

[0167] For example, the material of the second insulating layer 202 is silicon oxide, and the thickness is 300-500 nanometers. For example, the material of the gate insulating layer 200 is silicon oxide, and the thickness is 100-160 nanometers. For example, the material of the third insulating layer is silicon oxide, and the thickness is 400-600 nanometers.

[0168] For example, refer to Figure 3B A third insulating layer 203, a color filter layer and a fourth insulating layer 204 may be formed on the third conductive layer 503 in sequence, and a first electrode 123 of a light-emitting element may be formed on the fourth insulating layer 204, and then a pixel defining layer 206 may be formed on the first electrode 123, and a light-emitting layer 124 and a second electrode 122 may be formed in sequence, so as to form a Figure 3A The display substrate 10 is shown.

[0169] For example, forming the color filter layer may include first forming a red color filter layer and performing a composition process on the red color filter layer to form a color filter portion corresponding to a red sub-pixel, then forming a green color filter layer and performing a composition process on the green color filter layer to form a color filter portion corresponding to a green sub-pixel, and then forming a blue color filter layer and performing a composition process on the blue color filter layer to form a color filter portion corresponding to a blue sub-pixel.

[0170] For example, the thicknesses of the red color filter layer, the green color filter layer and the blue color filter layer are 2000-3000 nanometers respectively, that is, the thickness of each color filter portion is 2000-3000 nanometers.

[0171] For example, color filter portions may overlap to form a light shielding portion between adjacent sub-pixels to prevent cross-coloring.

[0172] For example, the above-mentioned patterning process may adopt a conventional photolithography process, for example, including the steps of photoresist coating, exposure, development, drying, etching, etc.

[0173] The above description is merely an exemplary embodiment of the present invention and is not intended to limit the protection scope of the present invention. The protection scope of the present invention is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate substrate is provided with a plurality of pixels arranged in an array, wherein at least some of the plurality of pixels include a plurality of sub-pixels, and at least some of the plurality of sub-pixels include a light-emitting element and a pixel circuit driving the light-emitting element to emit light, and the pixel circuit includes a storage capacitor, a driving transistor and a data writing transistor, and the driving transistor includes an active layer, a gate, a first electrode and a second electrode, and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light, wherein, At least some of the sub-pixels in the plurality of sub-pixels include a first via hole, and a first electrode of the data writing transistor is electrically connected to a gate of the driving transistor and an active layer of the data writing transistor through the first via hole; The gate of the driving transistor includes a main body and an extension connected to the main body, the orthographic projection of the main body on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate, the extension extends from the main body, and the extension is electrically connected to the first electrode of the data writing transistor and the active layer of the data writing transistor through the first via hole; The first electrode of the data writing transistor includes a first conductive portion and a second conductive portion stacked on each other in a direction perpendicular to the base substrate, wherein the second conductive portion is located on a side of the first conductive portion away from the base substrate; The display substrate further comprises: a gate insulating layer, located between the gate of the driving transistor and the active layer of the driving transistor, wherein the gate of the driving transistor is located on a side of the gate insulating layer away from the substrate; A first insulating layer is located on a side of the gate of the driving transistor away from the substrate, wherein the first via hole penetrates the gate insulating layer and the first insulating layer; The extension portion includes an upper surface and a side surface intersecting with the upper surface of the extension portion, and the second conductive portion also covers the side surface of the extension portion and contacts with the side surface of the extension portion; The gate insulating layer comprises an upper surface and a side surface intersecting with the upper surface of the gate insulating layer, the angle between the side surface of the extension portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a first angle, the angle between the side surface of the gate insulating layer and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a second angle, the second conductive portion comprises a middle portion directly contacting the extension portion, the angle between the side surface of the middle portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a third angle; The first angle is smaller than the second angle, or the first angle is larger than the third angle and the third angle is larger than the second angle.

2. The display substrate according to claim 1, wherein: The gate of the driving transistor is located on a side of the first conductive portion close to the second conductive portion and is spaced apart from the first conductive portion, and the second conductive portion is in contact with the gate of the driving transistor and the first conductive portion through the first via hole; The display substrate further comprises: The connecting portion overlaps with the extending portion in a direction perpendicular to the base substrate, and connects the first conductive portion and the active layer of the data writing transistor into an integrated structure.

3. The display substrate according to claim 2, wherein: The material of the second conductive portion and the material of the connecting portion include the same semiconductor material, and the semiconductor material included in the first conductive portion is conductorized.

4. The display substrate according to claim 2, wherein: The first conductive portion includes: A first sub-portion located at a first side of the extension portion, wherein the second conductive portion is in direct contact with the first sub-portion through the first via hole at the first side; The second conductive portion extends from a first side of the extending portion in the first via hole to the extending portion to contact at least a portion of an upper surface of the extending portion away from the base substrate.

5. The display substrate according to claim 4, wherein: The first conductive portion further includes: A second sub-portion is located on a second side of the extension portion, wherein the second side is opposite to the first side, the second conductive portion extends from the first side of the extension portion in the first via hole across the extension portion to extend to the second side of the extension portion, and the second conductive portion is in direct contact with the second sub-portion through the first via hole on the second side.

6. The display substrate according to claim 1, wherein: The storage capacitor comprises: A second capacitor electrode, at least part of which is in the same layer as the first electrode of the driving transistor and is an integral structure; and The first capacitor electrode is insulated from the second capacitor electrode and is in the same layer as the active layer of the driving transistor and is an integrated structure, wherein the second capacitor electrode and the first capacitor electrode constitute two plates of the first capacitor of the storage capacitor.

7. The display substrate according to claim 6, further comprising: An opaque shading layer, wherein the active layer of the driving transistor is located within the orthographic projection of the shading layer on the base substrate, the shading layer is electrically connected to the second capacitor electrode of the first capacitor, and the shading layer is insulated from the first capacitor electrode of the first capacitor and at least partially overlaps with the first capacitor electrode in a direction perpendicular to the base substrate to serve as a third capacitor electrode of the storage capacitor, the third capacitor electrode and the first capacitor electrode constitute two plates of the second capacitor of the storage capacitor, and the second capacitor is connected in parallel with the first capacitor.

8. The display substrate according to claim 7, wherein: The first electrode of the driving transistor is located on a side of the active layer of the driving transistor away from the base substrate, and the light shielding layer is located on a side of the active layer of the driving transistor close to the base substrate.

9. The display substrate according to claim 8, wherein: The second conductive portion is in the same layer and made of the same material as the first electrode of the driving transistor.

10. The display substrate according to any one of claims 1 to 9, further comprising: A signal line includes a first layer, a second layer, and a third layer stacked in sequence perpendicular to the substrate and in a direction away from the substrate, wherein the first layer is spaced apart from the second layer, and the signal line also includes a signal line via, and the third layer is electrically connected to the second layer and the first layer through the signal line via.

11. The display substrate according to claim 10, wherein: The first layer is in the same layer as the active layer of the driving transistor, the second layer is in the same layer as the gate electrode of the driving transistor and has the same material, and the third layer is in the same layer as the first electrode of the driving transistor and has the same material.

12. The display substrate according to claim 10, wherein: The first layer includes: The first conductor portion is located on the first side of the second layer, wherein the third layer is in direct contact with the first conductor portion through the signal line via on the first side of the second layer; the third layer extends from the first side of the first conductor portion in the signal line via to the second side of the first conductor portion to contact at least a portion of the upper surface of the second layer away from the base substrate.

13. The display substrate according to claim 12, wherein: The third layer is in direct contact with an upper surface of the second layer away from the base substrate and a side surface of the second layer intersecting with the upper surface thereof, and the third layer is in direct contact with the first layer.

14. The display substrate according to claim 12, wherein: The first layer also includes: The second conductor portion is located on the second side of the second layer in the line width direction of the signal line, wherein the second side of the second layer is opposite to the first side of the second layer, and the third layer extends from the first side of the second layer in the signal line via hole along the line width direction of the signal line across the second layer to extend to the second side of the second layer, and the third layer is in direct contact with the second conductor portion through the signal line via hole on the second side of the second layer.

15. The display substrate according to claim 14, wherein: The first layer also includes: The semiconductor portion overlaps with the second layer in a direction perpendicular to the base substrate, is in the same layer as the active layer of the driving transistor, and forms an integral structure with the first conductor portion.

16. The display substrate according to claim 10, wherein: Also includes: A data line is connected to the second electrode of the data writing transistor and is configured to provide a data signal to the data writing transistor, wherein the signal line includes the data line.

17. The display substrate according to claim 10, wherein: Also includes: A first power line is configured to provide a first power voltage to a first electrode of the driving transistor, wherein the signal line includes the first power line.

18. A display device comprising the display substrate according to any one of claims 1-17.

19. A method for manufacturing a display substrate, for manufacturing the display substrate according to any one of claims 1 to 17, comprising: providing a substrate base plate; A plurality of pixels are formed on the substrate, wherein at least part of the plurality of pixels include a plurality of sub-pixels, each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit for driving the light-emitting element to emit light, the pixel circuit includes a light-emitting device, a storage capacitor, a driving transistor and a data writing transistor, each of the driving transistor and the data writing transistor includes an active layer, a gate, a first electrode and a second electrode; the first electrode of the driving transistor is configured to receive a first power supply voltage, and the second electrode of the driving transistor is connected to the light-emitting device to be configured to control the light-emitting device to emit light; and forming a first via hole in at least part of the plurality of sub-pixels, wherein the first electrode of the data writing transistor is electrically connected to the gate of the driving transistor and the active layer of the data writing transistor through the first via hole; The gate of the driving transistor includes a main body and an extension connected to the main body, the orthographic projection of the main body on the substrate overlaps with the orthographic projection of the active layer of the driving transistor on the substrate, the extension extends from the main body, and the extension is electrically connected to the first electrode of the data writing transistor and the active layer of the data writing transistor through the first via hole; The display substrate further comprises: a gate insulating layer, located between the gate of the driving transistor and the active layer of the driving transistor, wherein the gate of the driving transistor is located on a side of the gate insulating layer away from the substrate; A first insulating layer is located on a side of the gate of the driving transistor away from the substrate, wherein the first via hole penetrates the gate insulating layer and the first insulating layer; The extension portion includes an upper surface and a side surface intersecting with the upper surface of the extension portion, and the second conductive portion also covers the side surface of the extension portion and contacts with the side surface of the extension portion; The gate insulating layer comprises an upper surface and a side surface intersecting with the upper surface of the gate insulating layer, the angle between the side surface of the extension portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a first angle, the angle between the side surface of the gate insulating layer and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a second angle, the second conductive portion comprises a middle portion directly contacting the extension portion, the angle between the side surface of the middle portion and the plane where the upper surface of the extension portion is located, which is close to the extension portion, is a third angle; The first angle is smaller than the second angle, or the first angle is larger than the third angle and the third angle is larger than the second angle.

20. The method for manufacturing a display substrate according to claim 19, comprising: forming a semiconductor layer; forming a gate insulating layer covering the semiconductor layer on a side of the semiconductor layer away from the substrate; forming a gate conductive layer on a side of the gate insulating layer away from the substrate; Patterning the gate conductive layer through a patterning process to form a gate of the driving transistor; Performing a patterning process on the gate insulating layer using the gate of the driving transistor as an etching barrier to expose a portion of the semiconductor layer, wherein the semiconductor layer includes a portion blocked by the gate insulating layer and a portion not blocked by the gate insulating layer; and The portion of the semiconductor layer not blocked by the gate insulating layer is conductorized to form a first conductive portion, and the portion blocked by the gate insulating layer is not conductorized to constitute the active layer and the connecting portion of the driving transistor, wherein the connecting portion overlaps with the extending portion in a direction perpendicular to the base substrate, and the first conductive portion is connected to the active layer of the data writing transistor as an integrated structure.

21. The method for manufacturing a display substrate according to claim 20, wherein: Forming the first via hole includes: After forming the active layer of the driving transistor and the active layer of the data writing transistor, forming a first insulating layer on a side of the gate of the driving transistor away from the base substrate, wherein the first insulating layer covers the gate of the driving transistor, the gate of the data writing transistor and the gate insulating layer; and Performing a patterning process on the first insulating layer to form the first via hole, wherein the first via hole exposes at least a portion of the gate of the driving transistor and at least a portion of the first conductive portion; The production method also includes: A second conductive portion is formed on a side of the gate of the driving transistor away from the base substrate, wherein the second conductive portion is electrically connected to the gate of the driving transistor and the first conductive portion through the first via hole, and the first conductive portion and the second conductive portion constitute a first electrode of the data writing transistor.

22. The method for manufacturing a display substrate according to claim 20 or 21, further comprising: A signal line is formed, including a first layer, a second layer, and a third layer stacked in sequence in a direction perpendicular to the substrate and away from the substrate, wherein the first layer is spaced apart from the third layer, and the signal line further includes a signal line via, and the third layer is electrically connected to the second layer and the first layer through the signal line via.

23. The method for manufacturing a display substrate according to claim 22, wherein: The first layer and the active layer of the driving transistor are simultaneously formed by performing the same conductor treatment process on the portion of the semiconductor layer not blocked by the gate insulating layer; The second layer and the gate of the driving transistor are formed simultaneously by performing the same patterning process on the gate conductive layer; The third layer and the first electrode of the driving transistor are formed simultaneously by performing the same patterning process on the same film layer.

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