Semiconductor structure and method for manufacturing the same

Abstract

The present disclosure provides a method, comprising forming a first metal layer of a sealing structure above a micro-electromechanical system (MEMS) structure of a semiconductor structure and above a channel formed through the MEMS structure of the semiconductor structure to an integrated circuit. The first metal layer is formed at a first temperature. The method also comprises forming a second metal layer above the first metal layer. The second metal layer is formed at a second temperature lower than the first temperature. The method also comprises performing a first cooling process to cool the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Micro-electromechanical systems (MEMS) combine mechanical and electronic components on a semiconductor structure. MEMS structures can be used as sensors, such as pressure sensors. Summary of the Invention

[0003] In one embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes the following steps: forming a first metal layer of a sealing structure above a micro-electromechanical system structure and above a via formed to form an integrated circuit passing through the micro-electromechanical system structure to the semiconductor structure, wherein the first metal layer is formed at a first temperature; forming a second metal layer above the first metal layer, wherein the second metal layer is formed at a second temperature less than the first temperature; and performing a first cooling process to cool the semiconductor structure.

[0004] In one embodiment of the present disclosure, a method for manufacturing a semiconductor structure includes the following steps: performing a first sputtering process at a first sputtering power to form a first metal layer of a sealing structure above a microelectromechanical system structure and above a via formed to form an integrated circuit passing through the microelectromechanical system structure to the semiconductor structure; performing a second sputtering process at a second sputtering power greater than the first sputtering power to form a second metal layer above the first metal layer; and performing a first cooling process to cool the semiconductor structure.

[0005] In one embodiment of the present disclosure, a semiconductor structure includes an integrated circuit, a micro-electromechanical system (MEMS) structure, and a sealing structure. A channel is formed through the MEMS structure to the integrated circuit. The sealing structure is above the channel, wherein the sealing structure includes a first metal layer and a second metal layer above the first metal layer, wherein the first metal layer has a first resistivity different from a second resistivity of the second metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of description.

[0007] Figure 1-8 is a cross-sectional view of a semiconductor structure having a sealing structure at different manufacturing stages according to some embodiments;

[0008] Figure 9is an illustration of a method of forming a semiconductor structure having a sealing structure according to some embodiments.

[0009] Explanation of Figure Numbers

[0010] 100: Semiconductor Structure

[0011] 102: Integrated Circuits

[0012] 104: Cavity

[0013] 106: First floor

[0014] 108: Second floor

[0015] 110: Third floor

[0016] 112: MEMS structure

[0017] 114: Channel

[0018] 116: Top opening

[0019] 202: Physical vapor deposition equipment

[0020] 204: First Metal Materials

[0021] 206: Cooling gas

[0022] 208: First metal layer

[0023] 302: Second metal material

[0024] 304: Second metal layer

[0025] 400: Device

[0026] 402: Cooling gas

[0027] 502: Third metal material

[0028] 504: The third metal layer

[0029] 506: Area

[0030] 602: Fourth Metal Material

[0031] 604: Fourth metal layer

[0032] 702: Sealed structure

[0033] 807: Top surface

[0034] 809: Bottommost surface

[0035] 810: Area

[0036] 811: Surface

[0037] 900: Method

[0038] 902-912: Steps

[0039] H1, H2, H3, H4, 802, 804, 806, 808: Height

[0040] H5, 812: Height of the first area

[0041] H6, 814: Second area height DETAILED DESCRIPTION

[0042] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or above a second feature may include embodiments in which the first and second features are formed to be in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numbers or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not, in itself, specify the relationship between the various embodiments or configurations discussed.

[0043] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0044] One or more semiconductor structures having a sealed structure and / or methods for creating a semiconductor structure having a sealed structure are provided. In some embodiments, the semiconductor structure includes a micro-electromechanical system (MEMS) structure. A channel is formed through the MEMS structure to a cavity between the MEMS structure and an integrated circuit. In some embodiments, the integrated circuit detects a change in the cavity, such as a change in cavity volume or pressure in the cavity. The integrated circuit outputs a signal indicating the detected change.

[0045] During the manufacturing process of a semiconductor structure, a channel is used to remove contents such as air, one or more gases, etc. from a cavity (e.g., by evacuating, creating a pressure differential, etc.), so that the cavity has a specific pressure, volume, etc. Once the contents are removed from the cavity through the channel, a sealing structure is formed on the MEMS structure and the channel. The sealing structure is formed to seal the active area of the MEMS structure, such as sealing the cavity and other parts of the MEMS structure used for active pressure sensing. The active area of the MEMS structure is sealed so that the active area of the MEMS structure can maintain the pressure established in the cavity when the contents are removed from the cavity through the channel. Therefore, sealing the active area of the MEMS structure provides the ability to maintain a certain pressure within the active area of the MEMS structure, such as a pressure that is less than the pressure of the external environment outside the semiconductor structure. Maintaining a relatively low pressure within the active area of the MEMS structure reduces the noise of the MEMS structure and the integrated circuit. Otherwise, the noise can adversely affect the performance and ability of the MEMS structure and the integrated circuit to sense pressure changes.

[0046] In some embodiments, the sealing structure includes one or more metal layers. The one or more metal layers can be formed by at least one of sputtering, deposition, or other suitable processes. The one or more metal layers are formed above the MEMS structure and the channel to form a sealing structure for maintaining pressure in the active area (e.g., the cavity) of the MEMS structure. During the formation of the one or more metal layers, such as during the sputtering process, heat can be utilized. The increased temperature due to the heat energy used to form the sealing structure during the sputtering process can increase the temperature of the integrated circuit. The increased temperature of the integrated circuit causes the integrated circuit (e.g., the complementary metal oxide semiconductor (CMOS) film layer of the integrated circuit) to outgas. When the integrated circuit outgases, gas is discharged from the integrated circuit into the active area (e.g., the cavity) of the MEMS structure and into the channel. The gas flows upward from the integrated circuit through the channel formed above the sealing structure. The higher the temperature, the more gas is generated by the integrated circuit. To escape from the active area of the MEMS structure, such as through the channel, the pressure from the gas can create a leakage path through the sealing structure to the external environment, thereby escaping to the external environment. Therefore, the increased pressure from the gas can break through the sealing structure to form a leakage path.

[0047] When the increased pressure from the integrated circuit exhaust due to increased temperature creates a leakage path through the sealing structure, air can now leak into and out of the channel through the sealing structure. The leakage path through the sealing structure allows air exchange between the active area of the MEMS structure (such as the channel and cavity) and the external environment. The pressure within the active area of the MEMS structure is affected by the air exchange, such as increasing based on the relatively high pressure of the external environment. Changes in pressure can increase the noise of the MEMS structure and the integrated circuit because increases in pressure increase noise. In particular, when a lower pressure is maintained within the active area of the MEMS structure, the ability of the MEMS structure and the integrated circuit to accurately sense pressure changes without noise is improved. Therefore, increased pressure increases noise, which will adversely affect the performance and ability of the MEMS structure and the integrated circuit to correctly sense pressure changes.

[0048] Therefore, as provided herein, a sealing structure is formed using a process utilizing relatively low temperatures to reduce the likelihood of outgassing of the integrated circuit, which could otherwise lead to a leakage path through the sealing structure. In some embodiments, relatively low temperatures include temperatures between approximately 200 degrees Celsius and approximately 300 degrees Celsius. In some embodiments, relatively low temperatures include temperatures below 300 degrees Celsius. In some embodiments, the lower temperatures are achieved by using relatively low sputtering powers in the sputtering process used to form one or more metal layers in the sealing structure. In some embodiments, the metal layers of the sealing structure are formed using a sputtering power between approximately 6,000 watts and approximately 11,500 watts, rather than approximately 20,000 watts. Using relatively low sputtering powers results in lower temperatures when forming the one or more metal layers in the sealing structure. In some embodiments, an additional cooling process is performed during the formation of the metal layers, for example, by flowing a cooling gas, such as argon, over the semiconductor structure during the sputtering process to form the metal layers. In some embodiments, the additional cooling process is performed between the formation of one metal layer and the formation of another metal layer of the sealing structure. In some embodiments, the additional cooling process is performed after the sealing structure is formed. Implementing one or more additional cooling processes can result in lower temperatures during the formation of the sealing structure.

[0049] Reducing the temperature generated during the formation of the sealing structure can reduce the likelihood of outgassing from the integrated circuit. Heat can cause the integrated circuit to release gases. The higher the temperature, the more heat the integrated circuit will experience and the more gases it will release. The more gases released by the integrated circuit, the greater the pressure exerted by the gases on the sealing structure, which can create leak paths. Therefore, reducing the temperature generated during the formation of the sealing structure reduces the likelihood of the integrated circuit releasing gases into the active areas of the MEMS structure (such as the cavity and channels). Reducing outgassing from the integrated circuit so that the integrated circuit does not release gases into the active areas of the MEMS structure reduces or eliminates the possibility of leak paths through the sealing structure. Otherwise, the excess pressure from the outgassing could breach the sealing structure and create a leak path between the active areas of the MEMS structure and the external environment, thereby allowing air to exchange between the MEMS structure and the external environment. Therefore, reducing or eliminating leak paths within the sealing structure allows the active areas of the MEMS structure to maintain proper operating pressure, as there is minimal air exchange between the MEMS structure and the external environment through the leak path, which could otherwise alter the pressure within the active areas of the MEMS structure. The ability to maintain pressure within the active areas of the MEMS structure improves the operation, lifespan, and performance of the MEMS structure, such as its ability to accurately detect pressure changes. The operation, lifetime, and performance of the MEMS structure are improved because the pressure can be maintained within the active region of the MEMS structure, eg, at a pressure less than the external ambient pressure.

[0050] In some embodiments, a sealing structure is formed from one or more metal layers at a processing temperature that reduces or eliminates outgassing that would otherwise result in a leakage path through the sealing structure. A first metal layer in the sealing structure is formed above a MEMS structure and a channel formed through the MEMS structure to the integrated circuit of the semiconductor structure. In some embodiments, the first metal layer is formed at a first temperature. In some embodiments, the first metal layer is formed by a first sputtering process with a first sputtering power. In some embodiments, a cooling gas, such as argon, is used to cool the semiconductor structure during the formation of the first metal layer. A second metal layer of the sealing structure is formed above the first metal layer. In some embodiments, the second metal layer is formed at a second temperature lower than the first temperature used to form the first metal layer. In some embodiments, the second metal layer is formed by a second sputtering process with a second sputtering power greater than the first sputtering power used to form the first metal layer. After forming the second metal layer, a cooling process is performed to cool the semiconductor structure. Forming the first metal layer using a lower first sputtering power and using a cooling gas during the formation of the first metal layer reduces the amount of heat experienced by the integrated circuit, thereby reducing the likelihood of outgassing by the integrated circuit. Furthermore, forming the second metal layer using a lower temperature and performing a cooling process after forming the second metal layer reduces the amount of heat experienced by the integrated circuit, thereby reducing the likelihood of outgassing by the integrated circuit. In some embodiments, one or more additional metal layers of the sealing structure may be formed over the second metal layer of the sealing structure using various temperature cooling processes and sputtering powers to reduce the amount of heat experienced by the integrated circuit.

[0051] Figure 1-8 is a cross-sectional view of the semiconductor structure 100 having the sealing structure 702 at various states of fabrication, in accordance with some embodiments.

[0052] refer to Figure 1 , semiconductor structure 100 includes a MEMS structure 112. MEMS structure 112 includes one or more layers, such as a first layer 106. In some embodiments, first layer 106 includes an oxide material. MEMS structure 112 includes a second layer 108. In some embodiments, second layer 108 includes a semiconductor material, such as polysilicon. In some embodiments, second layer 108 is a pressure port for sensing pressure. MEMS structure 112 includes a third layer 110. In some embodiments, third layer 110 includes an oxide material. It will be appreciated that MEMS structure 112 can be a pressure sensor or any other type of micro-electromechanical system sensor and can include any number of layers including any type of material.

[0053] MEMS structure 112 is located above cavity 104. Cavity 104 initially includes air, gas, vacuum, or other contents. The contents of cavity 104 are subsequently removed via a vacuum process performed through channel 114. Channel 114 (e.g., an air channel or a vacuum channel) is formed through MEMS structure 112 to reach cavity 104. Channel 114 is formed through third layer 110 of MEMS structure 112. Channel 114 is formed through second layer 108 of the MEMS structure so that a top opening 116 of channel 114 is parallel to the position where third layer 110 covers second layer 108. A vacuum process is performed to remove the contents of cavity 104 and channel 114 via top opening 116 of channel 114 so that cavity 104 and channel 114 have a specific pressure. In this way, contents such as air or gas are vacuumed out of cavity 104 via channel 114 and top opening 116. In some embodiments, while the semiconductor structure 100 is in a PVD transfer chamber, the contents are vacuum-evacuated to vent the pressure in the cavity 104 to a specific mTorr pressure.

[0054] The MEMS structure 112 is formed above the integrated circuit 102. In some embodiments, the integrated circuit 102 is configured to detect how the pressure sensed by the MEMS structure 112 affects the cavity 104. When pressure (e.g., pressure from an external or ambient environment relative to the MEMS structure 112) acts on the MEMS structure 112, the MEMS structure 112 (e.g., the first layer 106, the second layer 108, and / or the third layer 110, etc.) deforms based on the applied pressure. When the MEMS structure 112 deforms, the shape of the cavity 104 changes. For example, the pressure may cause the first layer 106 of the MEMS structure 112 to push downward or deflect toward the integrated circuit 102, thereby reducing the volume of the cavity, increasing the pressure within the cavity 104, etc. Depending on the type of MEMS structure 112, when the cavity 104 deforms, the integrated circuit 102 can detect the deformation, such as a pressure change, a voltage change, etc., and output a readout signal based on the deformation of the cavity 104. It will be appreciated that in some embodiments, various types of MEMS structures (e.g., a microelectromechanical system pressure sensor configured to detect light detection and ranging (LIDAR) signals) may be used. Integrated circuit 102 includes a CMOS thin film layer. The CMOS thin film layer of integrated circuit 102 may release gas in response to heat, thereby releasing the gas into cavity 104. Gas outgassing from integrated circuit 102 may travel up channel 114 and be released into the external environment outside semiconductor structure 100. If integrated circuit 102 outgasses during or after the formation of sealing structure 702 due to heat generated during the formation of sealing structure 702, the pressure from the gas attempting to escape through sealing structure 702 may create a leakage path through sealing structure 702. Therefore, as provided herein, sealing structure 702 is formed at a reduced temperature, such as a temperature between about 200 degrees Celsius and about 300 degrees Celsius, to reduce the likelihood of outgassing, thereby creating few or no leakage paths through sealing structure 702 due to the pressure from the gas that would otherwise be created by the release of gas in response to heat.

[0055] refer to Figure 2In some embodiments, first metal layer 208 of seal structure 702 is formed over MEMS structure 112 and over channel 114, which is formed through MEMS structure 112 to cavity 104 and integrated circuit 102. In some embodiments, first metal layer 208 is formed such that first metal layer 208 is formed over top opening 116 of channel 114, but is not formed in top opening 116 and downwardly over channel 114 and integrated circuit 102. First metal layer 208 is formed over third layer 110 of MEMS structure 112. In some embodiments, first metal layer 208 is formed over at least some of second layer 108 of MEMS structure 112, such as portions of second layer 108 of MEMS structure 112 that are not covered by third layer 110 of MEMS structure 112. In some embodiments, semiconductor structure 100 is cooled to room temperature, such as between about 20 degrees Celsius and about 30 degrees Celsius, before forming first metal layer 208. As part of cooling the semiconductor structure 100, degas lamps (used to degas the channel 114 and cavity 104 to draw a vacuum and remove contents, such as air and gas, from the channel and cavity 104) are turned off to reduce heat that could otherwise be generated by the degas lamps and raise the temperature of the semiconductor structure 100 to above room temperature.

[0056] In some embodiments, the first metal layer 208 is formed by at least one of a first sputtering process, a first deposition process, and the like, for example, performed by a physical vapor deposition apparatus 202. The physical vapor deposition apparatus 202 operates to form a first metal material 204 over the MEMS structure 112 and over the channel 114 to form the first metal layer 208. In some embodiments, the first metal layer 208 is formed at a first temperature. In some embodiments, the first temperature is between approximately 200 degrees Celsius and approximately 300 degrees Celsius. In some embodiments, the first sputtering process uses a first sputtering power. In some embodiments, the first sputtering power is between approximately 6,000 watts and approximately 11,500 watts. In some embodiments, the first sputtering power is less than approximately 20,000 watts. In some embodiments, if a higher sputtering power is used, the first sputtering power is less than a threshold value to reduce heat dissipated during the first sputtering process. By utilizing the first sputtering power to reduce heat dissipated during the first sputtering process, the first metal layer 208 can be formed at the first temperature.

[0057] In some embodiments, semiconductor structure 100 is cooled using cooling gas 206 during and / or after formation of first metal layer 208. In some embodiments, cooling gas 206 comprises argon. Due to the relatively large size of argon atoms and / or molecules, argon can be used to sufficiently cool semiconductor structure 100 during and / or after formation of first metal layer 208. Cooling gas 206 can be used to form first metal layer 208 at a first temperature. In some embodiments, first metal layer 208 includes trace amounts of cooling gas, such as argon, for cooling first metal layer 208.

[0058] In some embodiments, first metal layer 208 is formed to have a first resistivity. In some embodiments, the first resistivity of first metal layer 208 is between approximately 2.00E-08 Ω·m and approximately 4.00E-08 Ω·m. In some embodiments, first metal layer 208 comprises an aluminum-copper alloy. In some embodiments, the aluminum-copper alloy comprises approximately 20% to approximately 30% copper material and approximately 80% to approximately 70% aluminum material. In some embodiments, the aluminum-copper alloy comprises approximately 25% copper material and approximately 75% aluminum material. According to some embodiments, at least some of the aforementioned characteristics, features, etc. of first metal layer 208, such as formation at a specific temperature, formation using a specific power, formation with a specific cooling gas, formation with a specific resistivity, formation comprising a specific material, etc., are important for first metal layer 208 to function as desired, such as forming a desired seal, having a desired flexibility (e.g., for movement in response to pressure changes (e.g., pressure changes external to MEMS structure 112) to suppress outgassing of integrated circuit 102), etc.

[0059] refer to Figure 3 In some embodiments, the second metal layer 304 in the sealing structure 702 is formed over the first metal layer 208. In some embodiments, the second metal layer 304 is formed by at least one of a second sputtering process, a second deposition process, and the like, for example, performed by the physical vapor deposition apparatus 202. The physical vapor deposition apparatus 202 operates to form the second metal material 302 over the first metal layer 208 to form the second metal layer 304. In some embodiments, the second metal layer 304 is formed at a second temperature. In some embodiments, the second temperature for forming the second metal layer 304 is lower than the first temperature for forming the first metal layer 208. In some embodiments, the second temperature is between approximately 200 degrees Celsius and approximately 250 degrees Celsius.

[0060] In some embodiments, the second sputtering process uses a second sputtering power. In some embodiments, the second sputtering power is greater than the first sputtering power. In some embodiments, the second sputtering power is greater than about 11,500 watts. In some embodiments, the second sputtering power is about 20,000 watts.

[0061] In some embodiments, the second metal layer 304 is formed to have a second resistivity. In some embodiments, the second resistivity of the second metal layer 304 is different from the first resistivity of the first metal layer 208 .

[0062] In some embodiments, the second resistivity of the second metal layer 304 is between about 1.00E-07 Ω·m and about 1.00E-06 Ω·m. In some embodiments, the second metal layer 304 includes titanium nitride.

[0063] refer to Figure 4 In some embodiments, a first cooling process is performed to cool the semiconductor structure 100. In some embodiments, the first cooling process is performed after the second metal layer 304 is formed over the first metal layer 208. The first cooling process is performed by an apparatus 400 configured to flow a cooling material (e.g., a cooling gas 402) through the semiconductor structure 100. In one embodiment, the apparatus 400 flows the cooling gas 402 through the second metal layer 304 formed over the first metal layer 208. In some embodiments, the cooling gas comprises at least one of nitrogen or argon. In some embodiments, the first cooling process is performed for a time span between about 120 seconds and about 220 seconds. In some embodiments, the first cooling process is performed by the apparatus 400 for about 180 seconds. In some embodiments, the first cooling process is performed to cool the semiconductor structure 100 to between about 15 degrees Celsius and about 30 degrees Celsius. In some embodiments, the first cooling process is performed to cool the semiconductor structure 100 to about room temperature, for example, about 20 degrees Celsius. According to some embodiments, at least some of the above-described properties, characteristics, etc., of the second metal layer 304 (e.g., formation at a specific temperature, formation using a specific power, formation with a specific cooling gas, formation with a specific resistivity, formation with a specific resistivity including a specific material, etc.) are at least important for enabling the second metal layer 304 to function as desired, such as forming a desired seal, having a desired flexibility (e.g., for movement in response to pressure changes (e.g., pressure changes external to the MEMS structure 112) to suppress outgassing of the integrated circuit 102), etc.

[0064] refer to Figure 5In some embodiments, the third metal layer 504 in the sealing structure 702 is formed over the second metal layer 304. In some embodiments, the third metal layer 504 is formed by at least one of a third sputtering process, a third deposition process, and the like, for example, performed by the physical vapor deposition apparatus 202. The physical vapor deposition apparatus 202 operates to form the third metal material 502 over the second metal layer 304 to form the third metal layer 504. In some embodiments, the third metal layer 504 is formed at a third temperature. In some embodiments, the third temperature for forming the third metal layer 504 is similar to the first temperature for forming the first metal layer 208. In some embodiments, the third temperature for forming the third metal layer 504 is higher than the second temperature for forming the second metal layer 304. In some embodiments, the third temperature is between approximately 200 degrees Celsius and approximately 300 degrees Celsius.

[0065] In some embodiments, the third sputtering process uses a third sputtering power. In some embodiments, the third sputtering power is similar to the second sputtering power. In some embodiments, the third sputtering power is greater than the first sputtering power. The third sputtering power is greater than the first sputtering power, forming the third metal layer 504 at a faster rate than the rate at which the first metal layer 208 is formed. In some embodiments, the third sputtering power is greater than approximately 11,500 watts. In some embodiments, the third sputtering power is approximately 20,000 watts.

[0066] In some embodiments, the third metal layer 504 is formed to have a third resistivity. In some embodiments, the third resistivity of the third metal layer 504 is different from the second resistivity of the second metal layer 304 .

[0067] In some embodiments, the third resistivity of the third metal layer 504 is similar to the first resistivity of the first metal layer 208. In some embodiments, the third resistivity of the third metal layer 504 is between about 2.00E-08 Ω·m and about 4.00E-08 Ω·m. In some embodiments, the third metal layer 504 comprises an aluminum-copper alloy.

[0068] In some embodiments, the aluminum-copper alloy comprises about 20% to about 30% copper material and about 80% to about 70% aluminum material. In some embodiments, the aluminum-copper alloy comprises about 25% copper material and about 75% aluminum material.

[0069] The grain size of the metallic material of the metal layer of the sealing structure 702 is a factor (among other factors) associated with the parameters of forming the metallic material, such as the temperature at which the metallic layer is formed from the metallic material. In some embodiments, the metallic material will have a smaller grain size if a lower temperature is used than the grain size (particle size) of the metallic material when a higher temperature is used. The grain size corresponds to the average particle size of the particles (crystals) of the metallic material of the metallic layer. In some embodiments, the third metallic material 502 of the third metallic layer 504 has a grain size that is smaller than the grain size of the first metallic layer 208, for example, in the region 506 above the top opening 116 of the channel 114. In some embodiments, the grain size of the metallic material of the metallic layer of the sealing structure 702 is approximately 2.01 μm. According to some embodiments, at least some of the above-mentioned properties, characteristics, etc. of the third metal layer 504, such as formation at a specific temperature, formation using a specific power, formation with a specific cooling gas, formation with a specific resistivity, formation with a specific resistivity including a specific material, a structure with a specific particle size, etc., are at least important for the third metal layer 504 to function as required, such as forming a required seal, having a required flexibility (for example, for movement in response to pressure changes (for example, pressure changes external to the MEMS structure 112) to suppress outgassing of the integrated circuit 102), etc.

[0070] refer to Figure 6 In some embodiments, the fourth metal layer 604 in the sealing structure 702 is formed over the third metal layer 504. In some embodiments, the fourth metal layer 604 is formed by at least one of a fourth sputtering process, a fourth deposition process, and the like, for example, performed by the physical vapor deposition apparatus 202. The physical vapor deposition apparatus 202 operates to form a fourth metal material 602 over the third metal layer 504 to form the fourth metal layer 604. In some embodiments, the fourth metal layer 604 is formed at a fourth temperature. In some embodiments, the fourth temperature for forming the fourth metal layer 604 is lower than the first temperature for forming the first metal layer 208. In some embodiments, the fourth temperature is between approximately 200 degrees Celsius and approximately 250 degrees Celsius.

[0071] In some embodiments, the fourth sputtering process uses a fourth sputtering power. In some embodiments, the fourth sputtering power is greater than the first sputtering power. In some embodiments, the fourth sputtering power is greater than approximately 11,500 watts. In some embodiments, the fourth sputtering power is approximately 20,000 watts.

[0072] In some embodiments, fourth metal layer 604 is formed to have a fourth resistivity. In some embodiments, the fourth resistivity of fourth metal layer 604 is different from the first resistivity of first metal layer 208. In some embodiments, the fourth resistivity of fourth metal layer 604 is between approximately 1.00E-07 Ω·m and approximately 1.00E-06 Ω·m. In some embodiments, fourth metal layer 604 comprises titanium nitride.

[0073] In some embodiments, a second cooling process is performed to cool the semiconductor structure 100. In some embodiments, the second cooling process is performed after the fourth metal layer 604 is formed. It will be appreciated that the sealing structure 702 can be formed from any number of metal layers, such as four metal layers, fewer than four metal layers, or more than four metal layers. In some embodiments, if the sealing structure 702 has more or fewer than four metal layers, the second cooling process can be performed to cool the semiconductor structure 100 after the final metal layer of the sealing structure 702 has been formed. Various cooling techniques can be performed to cool the semiconductor structure 100, such as flowing a cooling gas, such as at least one of nitrogen or argon, over the semiconductor structure 100. In some embodiments, the second cooling process is performed to cool the semiconductor structure 100 to a temperature between about 20 degrees Celsius and about 30 degrees Celsius. According to some embodiments, at least some of the above-mentioned properties, characteristics, etc. of the fourth metal layer 604, such as formation at a specific temperature, formation using a specific power, formation with a specific cooling gas, formation with a specific resistivity, formation with a specific resistivity including a specific material, etc., are at least important for the fourth metal layer 604 to function as desired, such as forming a desired seal, having a desired flexibility (e.g., for movement in response to pressure changes (e.g., pressure changes external to the MEMS structure 112) to suppress outgassing of the integrated circuit 102), etc.

[0074] refer to Figure 7 In accordance with some embodiments, sealing structure 702 is depicted as including first metal layer 208, second metal layer 304, third metal layer 504, and fourth metal layer 604. In some embodiments, sealing structure 702 includes fewer than four metal layers. In some embodiments, sealing structure 702 includes more than four metal layers.

[0075] refer to Figure 8In some embodiments, the first metal layer 208 of the semiconductor structure 100 has a height (H1) 802 between approximately 10,000 angstroms and approximately 20,000 angstroms. In some embodiments, the height (H1) 802 of the first metal layer 208 is approximately 15,000 angstroms. The height (H1) 802 can be measured from the uppermost surface 803 of the second layer 108 of the MEMS structure 112 to the lowermost surface 805 of the second metal layer 304. The second metal layer 304 has a height (H2) 804 between approximately 1,000 angstroms and approximately 1,500 angstroms. The third metal layer 504 has a height (H3) 806 between approximately 10,000 angstroms and approximately 20,000 angstroms. In some embodiments, the height (H3) 806 of the third metal layer 504 is approximately 15,000 angstroms. The fourth metal layer 604 has a height (H4) 808 between approximately 250 angstroms and approximately 500 angstroms.

[0076] Figure 8 A magnified view of region 810 over channel 114 is illustrated. The magnified view of region 810 illustrates how an uppermost surface 807 of first metal layer 208 overlying channel 114 has a non-uniform or non-planar shape, according to some embodiments. First metal layer 208 has a first region height (H5) 812 extending from a bottommost surface 809 of first metal layer 208 to an overlying uniform or planar surface 811 of first metal layer 208. First metal layer 208 has a second region height (H6) 814 extending from the plane 811 of first metal layer 208 to the vertex of uppermost surface 807 of first metal layer 208. In some embodiments, first metal layer 208 has a ratio of second region height (H6) 814 to first region height (H5) 812 over channel 114 that is less than approximately 0.30, such as approximately 0.25, e.g., due to, for example, a formation process, characteristics, etc. (e.g., temperature, pressure, etc. associated with forming at least one of first metal layer 208, second metal layer 304, etc.). According to some embodiments, the aforementioned features, dimensions, shapes, etc. facilitate desired properties, such as with respect to sealing, flexibility, and the like.

[0077] Figure 9is an illustration of a method 900 for forming a sealing structure for a semiconductor structure, according to some embodiments. Method 900 includes forming a first metal layer of the sealing structure (902) over a microelectromechanical system (MEMS) structure and a via formed to an integrated circuit through the MEMS structure to the semiconductor structure. According to some embodiments, the first metal layer in the sealing structure is formed at a first temperature. According to some embodiments, the first metal layer in the sealing structure is formed using a first sputtering process and a first sputtering power. In one embodiment, a cooling process is performed during and / or after forming the first metal layer of the sealing structure. A second metal layer in the sealing structure is formed over the first metal layer (904). According to some embodiments, the second metal layer in the sealing structure is formed at a second temperature lower than the first temperature. According to some embodiments, the second metal layer of the sealing structure is formed using a second sputtering process, wherein the second sputtering power is greater than the first sputtering power. A first cooling process is performed to cool the semiconductor structure (906). A third metal layer of the sealing structure is formed over the second metal layer of the sealing structure (908). A fourth metal layer of the sealing structure is formed over the third metal layer of the sealing structure (910). A second cooling process is performed to cool the semiconductor structure (912).

[0078] The sealed structure is formed using a process that uses relatively low temperatures. For example, at least some of the metal layers in the sealed structure are formed at a temperature between about 200 degrees Celsius and about 300 degrees Celsius. The lower temperatures are achieved by using relatively low sputtering power and cooling processes during the formation of at least some of the metal layers in the sealed structure, and by performing one or more cooling processes after the metal layers in the sealed structure are formed. Because the sealed structure is formed at relatively low temperatures, the integrated circuits within the semiconductor structure experience less heat than when higher temperatures are used. Reducing the heat experienced by the integrated circuits reduces outgassing of the integrated circuits, which may otherwise result in leakage paths through the sealed structure, thereby allowing air exchange between the external environment and the cavity connected to the channel. Reducing or eliminating leakage paths through the sealed structure allows the cavity to maintain a certain pressure, thereby enabling the MEMS structure and the integrated circuit to better sense pressure changes. In this way, at least one of the operation, lifespan, or performance of the MEMS structure is improved because a desired pressure is maintained within the cavity.

[0079] According to some embodiments, a method includes forming a first metal layer of a sealing structure over a microelectromechanical system (MEMS) structure and over a via formed as an integrated circuit through the MEMS structure to a semiconductor structure, wherein the first metal layer is formed at a first temperature; forming a second metal layer over the first metal layer, wherein the second metal layer is formed at a second temperature less than the first temperature; and performing a first cooling process to cool the semiconductor structure. In one embodiment, forming the first metal layer includes cooling the semiconductor structure with a cooling gas. In one embodiment, the cooling gas includes argon. In one embodiment, forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the second metal layer includes performing a second sputtering process with a second sputtering power; and the first sputtering power is less than the second sputtering power. In one embodiment, the first metal layer has a resistivity between approximately 2.00E-08Ω·m and approximately 4.00E-08Ω·m. In one embodiment, the second metal layer has a resistivity between 1.00E-07Ω·m and 1.00E-06Ω·m. In one embodiment, the method further includes: forming a third metal layer above the second metal layer, wherein the third metal layer is formed at a third temperature greater than the second temperature. In one embodiment, forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the third metal layer includes performing a second sputtering process with a second sputtering power; and the first sputtering power is less than the second sputtering power. In one embodiment, the method further includes: forming a fourth metal layer above the third metal layer. In one embodiment, forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the fourth metal layer includes performing a second sputtering process with a second sputtering power; and the first sputtering power is less than the second sputtering power. In one embodiment, the method further includes: performing a second cooling process to cool the semiconductor structure after forming the fourth metal layer.

[0080] According to some embodiments, a method includes: performing a first sputtering process at a first sputtering power to form a first metal layer of a sealing structure above a microelectromechanical system structure and above a channel formed as an integrated circuit through the microelectromechanical system structure to a semiconductor structure; performing a second sputtering process at a second sputtering power greater than the first sputtering power to form a second metal layer above the first metal layer; and performing a first cooling process to cool the semiconductor structure. In one embodiment, performing the first sputtering process includes performing the first sputtering process at a first temperature between 200 degrees Celsius and 300 degrees Celsius. In one embodiment, performing the second sputtering process includes performing the second sputtering process at a second temperature between 200 degrees Celsius and 250 degrees Celsius. In one embodiment, the method further includes: forming one or more additional metal layers above the second metal layer. In one embodiment, the method further includes: performing a second cooling process to cool the semiconductor structure after forming the one or more additional metal layers.

[0081] According to some embodiments, a semiconductor structure includes an integrated circuit, a micro-electromechanical system structure, and a sealing structure. A channel is formed to pass through the micro-electromechanical system structure to the integrated circuit. A sealing structure is above the channel, wherein the sealing structure includes a first metal layer and a second metal layer above the first metal layer, wherein the first metal layer has a first resistivity different from the second resistivity of the second metal layer. In one embodiment, the sealing structure includes a third metal layer above the second metal layer, and wherein the particles of the first metal layer are larger than the particles of the third metal layer. In one embodiment, the first metal layer has a first region height to second region height ratio of less than 0.25 above the channel. In one embodiment, the first resistivity is between 2.00E-08Ω·m and 4.00E-08Ω·m, and the second resistivity is between 1.00E-07Ω·m and 1.00E-06Ω·m.

[0082] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that various modifications, substitutions, and variations may be made to the present disclosure without departing from the spirit and scope of the present disclosure.

[0083] Although the subject matter has been described in language specific to structural features or methodological acts, it is to be understood that the subject matter of the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing at least some of the claims.

[0084] Various operations of the embodiments are provided herein. The order in which some or all operations are described should not be interpreted as implying that these operations must be dependent on the order. Alternative orderings that benefit from this description will be understood. Furthermore, it should be understood that not all operations must be present in each embodiment provided herein. Furthermore, it will be understood that not all operations are required in some embodiments.

[0085] It should be understood that the layers, features, components, etc. depicted herein are illustrated with specific dimensions relative to each other, such as structural dimensions or orientations, for example, for simplicity and ease of understanding, and that their actual dimensions, in some embodiments, may be substantially different from those illustrated herein.

[0086] In addition, "exemplary" is used in this article to mean used as an example, instance, illustration, etc., and is not necessarily advantageous. As used in this application, "or" is intended to mean an inclusive "or" rather than an exclusive "or". In addition, "one" used in this application and the appended claims is generally interpreted to mean "one or more" unless otherwise specified or clearly pointed to a singular form from the context. In addition, at least one of A and B and / or the like generally refers to A or B or both A and B. In addition, with respect to the use of "including", "having" or their variations, these terms are intended to be inclusive in a manner similar to the term "including". In addition, unless otherwise specified, "first", "second", etc. are not intended to imply a temporal aspect, a spatial aspect, an order, etc. On the contrary, these terms are merely used as identifiers, names, etc. For example, a first element and a second element generally correspond to element A and element B or two different or two identical elements or identical elements.

[0087] In addition, although the present disclosure has been shown and described with respect to one or more embodiments, equivalent changes and modifications will occur to others of ordinary skill in the art based on a reading and understanding of this specification and the drawings. The present disclosure includes all such modifications and changes and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above-mentioned components (e.g., elements, resources, etc.), unless otherwise noted, the terms used to describe such components are intended to correspond to any component that performs the functions specified in this guide. Even if the structure is not identical to the disclosed structure, the described components (e.g., functionally equivalent) may be used. In addition, although a particular feature of the present disclosure may have been disclosed with respect to one of several embodiments, the feature may be combined with one or more other features of other embodiments, as may be necessary and advantageous for any given or particular application.

[0088] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will understand that they can easily use this disclosure as a basis for designing or modifying other processes and structures to implement the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: forming a first metal layer of a sealing structure over a microelectromechanical system structure and over a via formed to form an integrated circuit through the microelectromechanical system structure to a semiconductor structure, wherein the first metal layer is formed at a first temperature, wherein the first temperature is less than 300 degrees Celsius; forming a second metal layer over the first metal layer, wherein the second metal layer is formed at a second temperature less than the first temperature, wherein the first metal layer has a first resistivity different from a second resistivity of the second metal layer; and A first cooling process is performed to cool the semiconductor structure.

2. The method according to claim 1, characterized in that Forming the first metal layer includes: The semiconductor structure is cooled with a cooling gas.

3. The method according to claim 2, characterized in that The cooling gas includes argon.

4. The method according to claim 1, wherein: Forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the second metal layer includes performing a second sputtering process with a second sputtering power; and The first sputtering power is less than the second sputtering power.

5. The method according to claim 1, wherein The first metal layer has a resistivity between 2.00E-08Ω·m and 4.00E-08Ω·m.

6. The method according to claim 1, characterized in that The second metal layer has a resistivity ranging from 1.00E-07Ω·m to 1.00E-06Ω·m.

7. The method according to claim 1, characterized in that include: A third metal layer is formed over the second metal layer, wherein the third metal layer is formed at a third temperature greater than the second temperature.

8. The method according to claim 7, characterized in that in: Forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the third metal layer includes performing a second sputtering process with a second sputtering power; and The first sputtering power is less than the second sputtering power.

9. The method according to claim 7, characterized in that include: A fourth metal layer is formed over the third metal layer.

10. The method according to claim 9, characterized in that in: Forming the first metal layer includes performing a first sputtering process with a first sputtering power; forming the fourth metal layer includes performing a second sputtering process with a second sputtering power; and The first sputtering power is less than the second sputtering power.

11. The method according to claim 9, characterized in that include: A second cooling process is performed to cool the semiconductor structure after forming the fourth metal layer.

12. A method for manufacturing a semiconductor structure, characterized in that: include: performing a first sputtering process at a first sputtering power to form a first metal layer of a sealing structure over the micro-electro-mechanical system structure and over a via formed as an integrated circuit through the micro-electro-mechanical system structure to the semiconductor structure; performing a second sputtering process at a second sputtering power greater than the first sputtering power to form a second metal layer over the first metal layer, wherein the first metal layer has a first resistivity different from a second resistivity of the second metal layer; and A first cooling process is performed to cool the semiconductor structure.

13. The method according to claim 12, characterized in that Performing the first sputtering process includes performing the first sputtering process at a first temperature between 200 degrees Celsius and 300 degrees Celsius.

14. The method according to claim 13, characterized in that Performing the second sputtering process includes performing the second sputtering process at a second temperature between 200 degrees Celsius and 250 degrees Celsius.

15. The method according to claim 12, characterized in that include: One or more additional metal layers are formed over the second metal layer.

16. The method according to claim 15, characterized in that include: A second cooling process is performed to cool the semiconductor structure after forming the one or more additional metal layers.

17. A semiconductor structure, characterized in that include: integrated circuit; a micro-electro-mechanical systems structure, wherein a via is formed through the micro-electro-mechanical systems structure to the integrated circuit; and A sealing structure is above the channel, wherein the sealing structure includes a first metal layer and a second metal layer above the first metal layer, wherein the first metal layer has a first resistivity different from a second resistivity of the second metal layer, and the first metal layer has a first area height to second area height ratio above the channel that is less than 0.

25.

18. The semiconductor structure according to claim 17, wherein: The sealing structure includes a third metal layer over the second metal layer, and wherein grains of the first metal layer are larger than grains of the third metal layer.

19. The semiconductor structure according to claim 17, wherein: The first resistivity is between 2.00E-08Ω·m and 4.00E-08Ω·m, and the second resistivity is between 1.00E-07Ω·m and 1.00E-06Ω·m.

Images