Field Programmable Gate Array

Abstract

The present invention discloses a field programmable logic gate array (FPGA), which includes a plurality of programmable unit blocks arranged in rows and columns to form an array, and a wiring network including segmented routing and direct routing. The connection block is configured to fan in the segmented routing and direct routing from four cardinal directions, receive fan-in signals, and couple to the programmable block; the switch block is configured to drive and send fan-out signals to the segmented routing; one of the segmented routings in each cardinal direction is directly connected to the switch block via a dedicated circuit to drive long-distance outputs in the four cardinal directions, thereby allowing fan-out signals to be sent to each cardinal direction, including the fan-in direction that receives fan-in signals. The field programmable logic gate array provided by the present invention has a field programmable logic gate array wiring architecture that can minimize die size and more efficiently utilize wiring network resources. The wiring architecture can improve the power efficiency of the wiring network structure without affecting routability.

Description

Technical Field

[0001] The present invention relates generally to the field of field programmable gate arrays (FPGAs). Background Art

[0002] A field-programmable gate array (FPGA) is a semi-custom circuit designed as a semiconductor device that can be programmed after manufacturing. A typical FPGA typically contains programmable logic blocks (CLBs), or configurable logic blocks, each of which can be selectively connected to other CLBs via a programmable interconnect structure. This makes FPGAs very powerful and flexible. Compared to application-specific integrated circuits (ASICs), FPGAs have a shorter design cycle and can be designed and programmed more quickly and efficiently, reducing manufacturing time, by using hardware description languages ​​(HDLs); HDLs include but are not limited to Verilog HDL, VHDL, System Verilog, and System C. Compared to microcontrollers, FPGAs offer greater flexibility and high processing speeds.

[0003] Programmable logic blocks provide the functionality of an FPGA. These logic blocks are interconnected via a programmable routing network, which is configured to route connections to the programmable logic blocks and I / O blocks to implement any user-defined circuit. FPGA routing architectures include traditional island-style FPGAs and hierarchical FPGAs. In an island-style FPGA architecture, the die contains vertical and horizontal routing, occupying over 80% of the total die area, with the remaining 10-20% occupied by CLBs. The primary characteristic of island-style FPGA routing is the arrangement of CLBs in a two-dimensional grid, with routing network resources evenly distributed. A hierarchical FPGA is a multi-level routing architecture characterized by hierarchical and grouped management of logic resources, with routing resources subdivided into low-level local interconnects and high-level global interconnects. This hierarchical routing architecture improves circuit speed and reduces the area occupied by routing.

[0004] Due to the large die size and high power consumption of field-programmable gate arrays (FPGAs), various architectural improvements are needed to overcome these drawbacks. This is particularly true for heterogeneous segmented FPGAs, which are composed of fine-grained logic cells or programmable routing elements and programmable segmented routing. Because the connections between programmable routing element arrays are predefined and immutable after fabrication, the design of the FPGA's wiring architecture must consider worst-case routing network congestion to ensure that any circuit design can be implemented within the FPGA. Consequently, a significant portion of the die area is dedicated to routing network construction, particularly to the connection blocks that connect logic blocks to the segmented routing network, as well as the switch blocks that stitch the segmented routing network together to provide longer-distance segmented routing and direction changes. Obviously, die area is a major cost factor in integrated circuit design, impacting production yield and manufacturing costs. Smaller die sizes allow for more chips to be manufactured on a single wafer, and fewer defective cells can be found. When implementing various FPGA wiring architectures, many routing network resources are often left idle.

[0005] Therefore, there is a need in the art for a wiring architecture that can minimize die size and more effectively utilize wiring network resources, and improve the power efficiency of the wiring network structure without reducing routability. Summary of the Invention

[0006] This article provides a field programmable gate array (FPGA). The purpose of the present invention is to provide a wiring architecture that can minimize die size and more efficiently utilize wiring network resources. This wiring architecture is particularly useful for heterogeneous segmented FPGAs to more efficiently utilize wiring network resources and improve the power efficiency of the wiring network structure.

[0007] The field programmable logic gate array includes: a plurality of programmable cell blocks arranged in rows and columns to form an array, wherein each programmable cell block includes a programmable block, one or more switching blocks, and one or more connection blocks, each programmable block being programmable to operate and perform a logic function or a routing function; and a routing network including segmented routing and direct routing. These connection blocks are configured to fan in segmented routing and direct routing from four cardinal directions, receive fan-in signals, and couple to the programmable blocks. As for the switching blocks, they are configured to drive and send fan-out signals to the segmented routing. One of the segmented routings in each cardinal direction is directly connected to the switching block via a dedicated circuit to drive the switching block to output a long-distance output in the four cardinal directions, thereby allowing the fan-out signal to be sent to the cardinal output direction, which includes the fan-in direction that received the fan-in signal.

[0008] According to one embodiment, the switching block includes a plurality of output multiplexers, each having five input edges connected to the output of the programmable block and one segment route of each of the four cardinal directions, and each output multiplexer outputs a long-distance output to one cardinal output direction.

[0009] Preferably, one of the five input edges of each output multiplexer receives a segment route from a base direction that is the same as the base output direction of the long reach output of each output multiplexer.

[0010] Preferably, the switch block comprises a plurality of long-distance drivers, wherein each long-distance driver is configured to drive and send the fan-out signal in one cardinal direction of the respective segment routing of the four cardinal directions.

[0011] According to one embodiment, the connection block includes a plurality of input multiplexers configured to directly receive the fan-in signal from only half of the segment routing and provide input multiplexing to the programmable block.

[0012] According to one embodiment, one segment route of the segment routes in each cardinal direction is a source or a destination that is farthest from the programmable block.

[0013] According to one embodiment, the fan-in signal and the fan-out signal are fanned in through a source and fanned out through a destination, respectively, wherein the source and the destination are adjacent sources and adjacent destinations that are closest to the programmable block.

[0014] According to one embodiment, the fan-in signal and the fan-out signal are fanned in through a source and fanned out through a destination, respectively, wherein the source and the destination extend in the four cardinal directions and are alternately connected to alternate rows and alternate columns.

[0015] Preferably, the source and the destination extend in the X direction and the Y direction and are completely symmetrical.

[0016] Preferably, the source and the destination are only connected to an odd number of rows and an odd number of columns.

[0017] According to one embodiment, the fan-in signal or the fan-out signal can respectively fan in or fan out to alternating rows or columns that are not directly connected. Each programmable cell block is directly connected to an adjacent programmable cell block in an adjacent direction; the adjacent programmable cell block can receive and send the fan-in signal or the fan-out signal from the adjacent direction, thereby making a U-turn at the adjacent programmable cell block and fanning in or fanning out to the alternating rows or columns that are not directly connected.

[0018] Preferably, the adjacent programmable unit block is directly connected to the source and the destination farthest from the programmable block to perform the U-turn.

[0019] Preferably, the programmable block has a structure configurable as a logic function or a wiring function.

[0020] Preferably, the programmable block includes n-input lookup tables with selectable logic modes, characterized in that the n-input lookup tables can be configured to support execution of n-input logic functions, or configured as routing multiplexers to cooperate with local drivers to support execution of the logic function.

[0021] Preferably, the plurality of programmable cell blocks include a segmented hybrid logic wiring cell block, wherein the segmented hybrid logic wiring cell block uses more than one segmented segmented vertical wiring or segmented horizontal wiring.

[0022] Preferably, the field programmable logic gate array is implemented using more than one die stack.

[0023] Preferably, the field programmable logic gate array is implemented in a standalone die or embedded in an integrated circuit as an intellectual property block.

[0024] To reduce die area and power consumption, the present invention adds a new input edge to the output multiplexer. This allows segment routing to send fan-out signals back in the same direction as their original fan-in. Therefore, by utilizing segment routing connections in the opposite direction, the number of input edges of the input multiplexer can be reduced, thereby reducing the size of the input multiplexer. Similarly, because segment routing has a smaller fan-out number, it can utilize higher power efficiency and smaller long-reach drivers, saving die area without compromising performance.

[0025] By removing direct inputs from segment routes to programmable blocks through segment-to-segment route transitions, the size of the connection block is reduced. However, routing options between segment routes in the switch block are increased to more efficiently utilize the remaining connections in the connection block, preserving the combination of routing options. The size reduction from the connection block is more significant than the size gain from the switch block. As a result, the overall die area of ​​the field programmable logic gate array can be reduced.

[0026] This summary is provided to introduce some concepts in a simplified form, which will be further described in the detailed description below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter. As shown in the following examples, other aspects and advantages of the present invention are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings contain figures that further illustrate and clarify the above and other aspects, advantages, and features of the present invention. It should be appreciated that these drawings depict only certain embodiments of the present invention and are not intended to limit its scope. Those skilled in the art will appreciate that these drawings are shown for simplicity and clarity and are not necessarily drawn to scale. The present invention will now be described and explained with additional specificity and detail through the use of the accompanying drawings, in which:

[0028] Figure 1 A block diagram depicting one embodiment of a field programmable logic gate array;

[0029] Figure 2 A block diagram depicting one embodiment of a heterogeneous segmented field programmable logic gate array;

[0030] Figure 3 A circuit diagram depicting an original implementation of SHLRT in a heterogeneous segmented field programmable logic gate array;

[0031] Figure 4 A circuit diagram depicting one embodiment of a SHLRT with U-turn wiring according to the present invention;

[0032] Figure 5 Describes the basis Figure 4 Circuit diagram of heterogeneous input of SHLRT;

[0033] Figure 6 Describes the basis Figure 4 The circuit diagram of the SHLRT output multiplexer;

[0034] Figure 7 depicts an example of a fan-out graph for a heterogeneous segmented field programmable logic gate array according to the present invention; and

[0035] Figure 8 Describes two Figure 7 A fan-out graph is used to connect rows that do not have long-distance destinations. DETAILED DESCRIPTION

[0036] Examples described herein relate to field programmable gate arrays (FPGAs), and more particularly, to a FPGA with U-turn routing. More specifically, but not by way of limitation, the present invention provides a FPGA routing architecture that minimizes die size and more efficiently utilizes routing network resources, thereby improving the power efficiency of the routing network structure without compromising routability.

[0037] The following detailed description is merely exemplary in nature and is not intended to limit the present invention or its application and / or use. It should be understood that a large number of variations exist. The detailed description will enable those skilled in the art to implement the exemplary embodiments of the present invention without unnecessary experimentation, and it should be understood that various changes or modifications may be made to the functions and structures described in the exemplary embodiments without departing from the scope of the present invention.

[0038] Benefits, advantages, solutions to problems, and any elements that make any benefit, advantage, or solution appear or become more apparent should not be construed as key, required, or essential features or elements of the technical solution of the present invention.

[0039] These and other examples described in this disclosure can be implemented in standalone dies. Other examples can be implemented using more than one die stacked together, or as intellectual property blocks embedded in an integrated circuit. Various models can be implemented based on the examples described herein. As will be readily apparent to those skilled in the art after reading this disclosure, additional or other benefits can be realized through various examples.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present invention have the same meaning as commonly understood by a person of ordinary skill in the art to which the present invention belongs. The terms "horizontal" and "vertical" as used herein are relative to each other and to the conventions followed in the drawings and the specification, and do not indicate any particular orientation physically in the chip (or tube core). Similarly, the terms "above", "below", "left", "right", "vertical", "horizontal", "east", "south", "west", "north" and other directional terms as used herein are relative to each other and to the conventions followed in the drawings and the specification, and do not indicate any particular orientation physically in the chip (or tube core). It should also be noted that the terms "column" and "row" are used to specify directions relative to the drawings herein, and a "column" in one embodiment may be a "row" in another embodiment.

[0041] As used herein, "hybrid logic or routing tiles" or "HLRT," short for "hybrid logic or routing tiles," are a type of programmable cell in a field programmable logic gate array. In one embodiment, multiple HLRTs are arranged in an array of rows and columns. Alternatively, when one or more switch blocks are coupled to multiple HLRTs, extending fine-grained logic or routing programmable elements to enable segmented routing, such as segmented vertical routing using more than one segment or segmented horizontal routing using more than one segment, a new type of programmable cell is formed, referred to herein as a "segmented hybrid logic or routing tile" or "SHLRT," which is short for "segmented hybrid logic or routing tiles."

[0042] As used in this article, "hybrid logic or routing function" or "HLR" is an abbreviation for "hybrid logic or routing function" and refers to a programmable block that can be configured as either a logic function or a routing function.

[0043] The main component of a field programmable gate array (FPGA) is an array of multiple programmable cell blocks arranged in rows and columns. Each programmable cell block includes a logic block and an adjacent wiring network. Therefore, each logic block and adjacent wiring network is implemented as a cell. The figures herein depict the layout of a single "programmable cell block." However, a chip may include one or more programmable cell blocks according to the present invention, and other programmable cell block architectures may also be used without departing from the scope and spirit of this disclosure.

[0044] In one embodiment, adjacent programmable cell blocks (HLRT or SHLRT) are directly connected via direct routing. That is, the HLRT and SHLRT are not connected together by segmented routing, and only a direct drive path is used to connect a relatively short distance. In one embodiment, one or more programmable cell blocks are configured as a wiring function and used as a wiring hub. In one embodiment, one or more programmable cell blocks are configured as a logic function, and the logic function is implemented using a lookup table structure programmed as a multiplexer. In one embodiment, in order to connect a programmable cell block configured as a logic function to an external port of the chip, a programmable cell block configured as a wiring function can be used so that the external port is directly connected to the programmable cell block configured as the logic function, thereby, the signal of the external port can be transmitted through the direct connection formed by multiple programmable cell blocks configured as the wiring function.

[0045] Figure 1An embodiment of a field programmable logic gate array architecture is shown, wherein the field programmable logic gate array has one or more HLRTs 100 arrays arranged in rows and columns, each HLRT 100 including a programmable block having an HLR 101 and a connection block 102. In one embodiment, each HLR 101 can be configured as a logic function or a wiring function, and the connection block 102 is coupled to each programmable block to provide input multiplexing. Although in Figure 1 Two connection blocks 102 are shown, but in some embodiments, there may be one or more than two connection blocks 102 that connect HLR 101 to direct routing. In more detail, HLR 101 includes a logic block 111 that has selectable logic modes (e.g., n-input lookup tables) to support any n-input logic function, or the same logic block 111 can be configured as a routing multiplexer (MUX) 112A by programming the contents of the lookup table accordingly, in conjunction with a driver 112B, to support routing functions and expansion.

[0046] For example, in one configuration, for a logic function with n inputs, a lookup table structure is used to implement a logic block in HLR 101. The same lookup table structure can be programmed into a static n-to-1 multiplexer 112A so that HLR 101 can serve as a routing hop for switching between segment routes, similar to the functionality of a switch block in a typical field programmable gate array architecture.

[0047] In one embodiment, the connection block 102 is an input multiplexer 120 configured to connect the direct route 252 to the HLR 101 to provide multiplexing of the direct route 252 input and output to a logic function or wiring function provided by the HLR 101. Figure 1 Only one input multiplexer 120 is shown. Obviously, there may be more than one input multiplexer 120 on each connection block 102, and each input multiplexer 120 may be an m-to-1 multiplexer.

[0048] The above architecture provides fast logic-to-logic connections, effectively reducing the length of critical paths, and is more suitable for implementing smaller programmable arrays in standalone chips or embedded in different dies, because typical nets do not need to be transmitted over long distances. When larger programmable arrays are required, the routing flexibility of this architecture may be limited, and it may not be possible to support both direct routing252 and segment routing crossover connections in the same programmable cell block.

[0049] Figure 2 Shown Figure 1An extension of the direct-driven routing architecture shown in [1], in one embodiment, the programmable logic architecture combines segment routing for driving segment routing and direct routing for driving direct routing. This heterogeneous segment routing architecture features an additional switch block 204 to provide routing hops between long distances. In certain embodiments, the heterogeneous segment routing architecture may have two or more switch blocks 204. This architecture utilizes a new type of HLRT, referred to herein as SHLRT. A field programmable logic gate array (FPGA) includes a routing network with both direct routing 252 and segment routing 251 routing channels. The corresponding HLR 201 within the same programmable logic block can be used to implement other logic or direct routing 252 functions. In one embodiment, the dedicated long-distance switch block 204 also provides a faster routing connection than that through the HLR 201, thereby achieving both high-performance and long-distance routing connectivity in the same manner as the programmable logic architecture. Segment routing can still reach the HLR 201 directly through the connection block 202, and the output can still be segment-routed through the new switch block 204.

[0050] Reference Figure 2 The heterogeneous segmented field programmable logic gate array has a segment routing 251, a direct routing 252, and a plurality of SHLRT 200 programmable gate architectures arranged in rows and columns to form an array. Each SHLRT 200 includes a plurality of HLRs 201 with logic functions or wiring functions, switching blocks 204, and connection blocks 202. The HLR 201 in the SHLRT 200 is based on Figure 1 The HLR 101 described above operates in a similar manner and is a programmable block that can be programmed to operate and perform logic functions or routing functions. In some embodiments, the programmable block can be programmed once or multiple times at different times. Each HLR 201 includes a logic block 211 having a selectable logic mode (e.g., an n-input lookup table) to support the execution of any n-input logic function. Alternatively, the same logic block 211 can be configured as a routing multiplexer 212A by programming the contents of the lookup table accordingly, in conjunction with a local driver 212B, to support the execution of routing functions and extended routing functions.

[0051] In one embodiment, segment routing 251 is connected to each HLR 201 in a vertical or horizontal direction, thereby connecting multiple SHLRTs 200. Connection block 202 is an input multiplexer 220 configured to receive fan-in signals from segment routing 251 and direct routing 252, and coupled to HLR 201, providing input multiplexing to HLR 201 and outputting signals to logic functions or routing functions provided by HLR 201 without multiplexing routing network resources as is typical in conventional segment routing architectures. In this embodiment, input multiplexer 220 in any one of connection blocks 202 has two or more inputs and one output. The two or more inputs are connected to traces of segment routing 251 and traces of direct routing 252, and the one output is directly connected to input 253 of a logic function or routing function of HLR 201.

[0052] Although Figure 2 Although two connection blocks 202 are shown in the figure, it is apparent that the HLR 201 can be connected to more or less than two connection blocks 202 and to different numbers of segment routing 251 traces and direct routing 252 traces without departing from the scope and spirit of the present disclosure. The sources and destinations fanned in through the connection blocks 202 and fanned out through the switching blocks 204 can also be adjusted according to the number of segment routing 251. The fanned-in signals can be direct routing 252 signals or signals connected to the segment routing 251 signals in the vertical or horizontal direction.

[0053] In one embodiment, the switch block 204 of the SHLRT 200 is configured to connect to the HLR 201 and multiple segment routes 251. The switch block 204 includes multiple output multiplexers 244 and multiple long-distance drivers 245. Each output multiplexer 244 has two or more inputs. Depending on the trace design and needs, one input can be connected to the output 254 of the HLR 201, while the other input can be connected to another segment route 251 to perform a transition from one segment route 251 to another. The output of the output multiplexer 244 is connected to the long-distance driver 245, and the long-distance driver 245 generates an output to the long-distance driver 245. The long-distance driver 245 is configured to drive and send a fan-out signal to the segment route 251. In the illustrated embodiment, only one output multiplexer 244 and one long-distance driver 245 are shown to avoid obscuring the present invention.

[0054] Figure 3 The circuit diagram of an original implementation of SHLRT 200 in a heterogeneous segmented field programmable logic gate array is shown. In this implementation, there are 100 heterogeneous direct routing 252 or segment routing 251 connections. According to the fan-in arrangement of this implementation, the source can be up to 19 horizontal distances and 19 vertical distances away. The details of the fan-in diagram will be described in Figure 7 . The heterogeneous direct routes 252 or segment routes 251 are from 100 different source locations, including 24 direct routes 252 and 76 segment routes 251, and are coupled to the HLR 201 via four input multiplexer traces. Furthermore, the HLR 201 is configured with four input lookup tables (LUT4) 311. Obviously, the HLR 201 can be configured with a different number of input lookup tables (e.g., five input lookup tables and six input lookup tables) without departing from the scope and spirit of the present disclosure, and the number of source locations, direct routes, and segment routes can also be different.

[0055] According to one embodiment, four 25-bit input multiplexers (25:1 MUX) 320 are placed between the source location and the input of the lookup table 311. In particular, the output of the first input multiplexer 320 is coupled to the first input port of the lookup table 311. Similarly, the outputs of the second to fourth input multiplexers 320 are coupled to the second to fourth input ports of the lookup table 311, respectively. The lookup table output (LUT_out) 311A ​​directly drives the corresponding 24 direct routes 252 and the local driver 312. In addition, the lookup table output 311A ​​is also connected to four 4-to-1 output multiplexers 344 and long-distance drivers 345 to provide dedicated segment routing resources to drive long-distance destinations, thereby enabling connection to up to four different long-distance destinations. At the same time, the lookup table 311 of the HLR 201 can still drive different direct routes 252.

[0056] In some embodiments, the SHLRT has different numbers of direct routing 252 and segment routing 251 connections, and can be evenly or unevenly distributed to connect multiple input multiplexers 320, where the input multiplexers 320 can have different number of input bits. The wiring network structure of the field programmable logic gate array is connected to the logic blocks arranged in rows and columns by segment routing 251. Therefore, the segment routing 251 network fan-in from the top, bottom, left, or right of each logic block. For ease of understanding in this disclosure, the fan-in direction of the segment routing 251 is defined as fan-in from the four cardinal directions, namely, "east," "south," "west," and "north" of the SHLRT. The above direction definition also applies to the cardinal output directions. In the illustrated embodiment, there are 19 segment routes fanning in for each cardinal direction. However, segment routes fanning in from the same cardinal direction are not necessarily coupled to only the same input multiplexer 320. Instead, one segment route 251 of the segment routes in each cardinal direction, preferably the source farthest away in the SHLRT (i.e., the 19th source in each cardinal direction), is not only connected to the input multiplexer 320 but is also directly connected to the input of the output multiplexer 344 via a dedicated circuit 342. Therefore, each output multiplexer 344 has one input from the lookup table 311 and three inputs from the segment route 251. Since each output multiplexer 344 is configured to drive a long-distance destination in one output direction, the three inputs from the segment routes 251 are segment routes fanning in from three cardinal output directions different from the output direction, thereby achieving a buffering effect. As shown in the figure, the switch block 204 includes four output multiplexers 244 and four long-distance drivers 245, which drive and send fan-out signals to segment routing 251 in four basic output directions.

[0057] The above arrangement is made under the following assumption: the connection of the segment routing 251 will not return to the basic direction of fan-in, but will continue to connect to the other three basic directions. For example, the segment routing from the north can be directly connected and coupled to the output of the east, south or west through the dedicated circuit 342, without going through the HLR 201, and can quickly connect and choose to connect in a straight line forward or change direction to the left or right. Similarly, the segment routing from the east, south and west can also be directly connected and coupled to the output of each of the other three basic directions through the dedicated circuit 342. The effect of this embodiment can be achieved as follows Figure 2 The illustrated switch block 204 performs a segment routing to segment routing transition.

[0058] According to the original SHLRT routing architecture described above, segment routing 251 connects to each logic block 211 in segments to maximize routing flexibility. While this architecture provides high routing capacity, the input multiplexer 320 area is large due to the large number of segment routing 251 inputs from the incoming connections. Furthermore, due to the high fan-out of these segments, the drive strength of the long-reach driver 345 must be increased to maintain timing performance. This also results in a larger die area and increased power consumption.

[0059] To reduce die area and power consumption, such as Figure 4 The circuit diagram shown in the figure describes a SHLRT 400 with U-turn wiring. In the architecture of a heterogeneous segmented field programmable logic gate array, the field programmable logic gate array includes a plurality of programmable unit blocks arranged in rows and columns, wherein at least one of the plurality of programmable unit blocks is a SHLRT 400, and the SHLRT 400 includes a programmable block, a switching block 204, and a connection block 202; the programmable block can be programmed to operate and perform a logic function or a wiring function. In one embodiment, the programmable block is Figure 2 The depicted HLR 201 includes n-input lookup tables 411 with selectable logic modes to support the execution of any n-input logic function. Alternatively, the same lookup table 411 can be configured as a routing multiplexer by programming the contents of the lookup table 411 accordingly, in conjunction with a local driver 412 and a long-distance driver 445 to support the execution of logic functions, routing functions, and extended routing functions. The connection block 202 includes multiple input multiplexers 420, configured to fan in segment routing 251 and direct routing 252 from four cardinal directions. The multiplexers receive fan-in signals, couple to the HLR 201, provide input multiplexing to the HLR 201, and output to the logic functions or routing functions provided by the lookup table 411. In one embodiment, the heterogeneous segmented field programmable logic gate array may also include other unit blocks, including but not limited to input blocks, output blocks, random access memory blocks, digital signal processing blocks, timing logic, and other programmable logic. For simplicity and clarity, these other unit blocks are not shown in the figure.

[0060] Advantageously, the input multiplexer 420 does not need to receive fan-in signals from all segment routes 251. Instead, in a segment route 251 between two SHLRTs 400, the input multiplexer 420 directly receives fan-in signals from only half of the segment routes 251, while the input multiplexer 420 of the adjacent SHLRT 400 directly receives fan-in signals from the other half of the segment route 251. Therefore, when a fan-in signal needs to be received from a segment route 251 trace that is not directly connected, it can be connected via the adjacent SHLRT 400 using the U-turn routing of the present invention.

[0061] In one embodiment, the switching block 204 includes a plurality of output multiplexers 444 and a plurality of long-distance drivers 445, each of which is configured to drive and send a fan-out signal to a segment route 251 in a cardinal direction. Advantageously, each output multiplexer 444 has five input edges, which are respectively connected to the output of the HLR 201, i.e., the lookup table output (LUT_out) 411A, and one segment route 251 in each of the segment routes in the four cardinal directions for performing a segment route 251 to segment route 251 transition. One segment route 251 in each cardinal direction, preferably the source furthest from the programmable block in that cardinal direction (i.e., the tenth source in each cardinal direction), is directly connected to the switch block 204 via a dedicated circuit 442. Since each output multiplexer 444 receives segment route 251 signals from the four cardinal directions and drives a segment route 251 in each cardinal output direction, thereby driving the long-distance outputs of the four cardinal output directions, fan-out signals can be sent to each cardinal direction, particularly including back to the fan-in direction from which the fan-in signal was received. In other words, when the output multiplexer 444 receives a fan-in signal from a fan-in direction, the present invention allows the fan-out signal to be output to that fan-in direction.

[0062] In one embodiment, the output multiplexer 444 is a five-bit output multiplexer (5:1 MUX) with an additional input routing 443 to receive the same fan-in signal as the long-distance output direction, such as Figure 4 and Figure 5 As shown, for the segment route 251 driving the north (L_N_Out), the SHLRT 400 includes an additional north input route 443A, allowing one of the north segment routes 251 (L_N_in_9) to send a fan-out signal back to the north segment route 251. Similarly, for the segment route 251 driving the east (L_E_Out), the SHLRT 400 includes an additional east input route 443C, allowing one of the east segment routes 251 (L_E_in_9) to send a fan-out signal back to the east segment route 251. The south and west segment routes 251 can also send a fan-out signal back to the south and west segment routes 251 via additional south input route 443B and additional west input route 443D, respectively. By utilizing segmented connections in the opposite direction, the number of inputs can be advantageously reduced to 64, including 24 direct routes 252 and 40 segment routes 251, with the number of input edges per input multiplexer 420 being 16. Figure 3The original implementation shown uses a 25-bit input multiplexer (25:1 MUX) 320 to couple 100 direct inputs. The present invention uses a 16-bit input multiplexer (16:1 MUX) 420. Although the addition of one input to output multiplexer 444 increases its area, the increase is negligible compared to the reduced size of input multiplexer 420. Therefore, the present invention significantly improves die area, resulting in a smaller SHLRT area and reduced power consumption. The number of sources fanning in through connection block 202 and the number of destinations fanning out through switch block 204 is approximately half the number of segment routers 251.

[0063] The SHLRT 400 with U-turn routing can be connected to different numbers of direct routing 252 and segment routing 251, wherein the direct routing 252 and segment routing 251 can be evenly distributed or unevenly distributed to connect multiple input multiplexers 420. Figure 5 A wiring distribution arrangement is shown in detail. The fan-in signal can be a direct route 252 signal or a segmented route 251 signal connected to the four cardinal directions in a vertical or horizontal direction. As previously mentioned, the input multiplexers 420 have a relatively small number of input bits. In this example, each input multiplexer 420 has 16 bits of input. The segment routes 251 are segment routes that fan in from four cardinal directions. There are 10 segment routes 251 that fan in from each cardinal direction. However, the segment routes 251 that fan in from the same cardinal direction are not necessarily coupled to the same input multiplexer 420. As a more preferable method, the segment routes 251 that fan in from the four cardinal directions are evenly distributed and connected to the input multiplexer 420. For example, the first group of direct routes 252A and the first group of segment routes 251A are coupled to the first input multiplexer 420A, wherein the first group of segment routes 251A includes segment routes that fan in from the four cardinal directions, from the center (0) to the periphery (9), and are connected to the east, west, north and south in sequence; the second group of direct routes 252A and the first group of segment routes 251A are connected to the first input multiplexer 420A. The direct route 252B and the second group of segment routes 251B are coupled to the second input multiplexer 420B. The second group of segment routes 251B are connected to the west, north, south and east in sequence from the center (0) to the periphery (9). The third group of direct routes 252C and the third group of segment routes 251C are coupled to the third input multiplexer 420C. The third group of segment routes 251C are connected to the north, south, east and west in sequence from the center (0) to the periphery (9). The fourth group of direct routes 252D and the fourth group of segment routes 251D are coupled to the fourth input multiplexer 420D. The fourth group of segment routes 251D are connected to the south, east, west and north in sequence from the center (0) to the periphery (9).

[0064] In one embodiment, one of the segment routers 251 in each cardinal direction, preferably the source of the SHLRT 400 farthest from the programmable block (i.e., the 10th in each cardinal direction), in addition to being connected to the input multiplexer 420, is also directly connected to the switch block 204 via dedicated circuitry 442 and to the input of the output multiplexer 444 via an additional input router 443. Thus, each output multiplexer 344 has one input from the lookup table 411 and four inputs from the segment router 251.

[0065] Since an input edge is added to each output multiplexer 444, it can receive fan-in signals of the segment routing 251 from four basic directions and be configured to drive a long-distance destination in one basic direction of the segment routing in each of the four basic directions, thereby providing output multiplexing and achieving a buffering effect. Figure 6As shown, the switch block 204 includes four output multiplexers 444 and four long-distance drivers 445, which drive and send fan-out signals to the four basic output direction segment routes 251. The input of the northbound output multiplexer 444N includes the north-most distant source 251N (L_N_in_9) input via the north additional input route 443A, as well as the other three cardinal direction farthest distant sources 251S / 251E / 251W and the lookup table output (LUT_out) 411A, providing output multiplexing to the north-most distant driver 445N to drive the north-most segment route 446N (L_N_Out). The inputs to the southbound output multiplexer 444S include the furthest south source 251S (L_S_in_9) input via the southbound additional input route 443B, along with the three further furthest cardinal direction sources 251N / 251E / 251W and the lookup table output (LUT_out) 411A, providing output multiplexing to the southbound long reach driver 445S to drive the southbound segment route 446S (L_S_Out). The inputs to the east output multiplexer 444E include the east's furthest source 251E (L_E_in_9) via the east's additional input route 443C, along with the three other furthest cardinal direction sources 251N / 251S / 251W and the lookup table output (LUT_out) 411A, providing output multiplexing to the east's long reach driver 445E to drive the east's segment route 446E (L_E_Out). The inputs to the west output multiplexer 444W include the west furthest source 251W (L_W_in_9) input via the west additional input route 443D, along with the three other furthest sources in the cardinal directions 251N / 251S / 251E and the lookup table output (LUT_out) 411A, providing output multiplexing to the west long reach driver 445W to drive the west segment route 446W (L_W_Out).

[0066] Figure 7 An example of a fan-out diagram of a heterogeneous segmented field programmable logic gate array according to the present invention is shown. In the fan-out diagram, "S" and "D" represent the source and the destination, respectively, and the fan-in signal and the fan-out signal fan-in and fan-out through multiple sources, respectively. Among them, the central source 701 fans out to 64 destinations 702, and the 24 direct drive destinations 710 are the 24 adjacent destinations closest to the programmable block, which are direct routes 252 in the wiring network, and can be destinations with predefined adjacent distances. In one embodiment, they are output to 2 vertical and horizontal distances. As for the long-distance destination 720, it is a destination extending in four basic directions, up to 19 horizontal distances and 19 vertical distances, which is a segmented route 251 in the wiring network, used for segmented long-distance connection. As shown Figure 3In the SHLRT shown, in order to directly reach the destinations within 19 horizontal distances and 19 vertical distances, both fan-out and fan-in need to be connected to each row and column. Therefore, 19 destinations are required in each basic direction to ensure that the output can directly reach the surrounding routing nets, improving routing flexibility.

[0067] In one embodiment, Figure 7 It can also be a fan-in graph, which is the same as the fan-out graph, except that the middle "S" is replaced by "D", and the "D" is replaced by "S". In the fan-in graph, 64 surrounding source locations can be driven directly to the central destination location. The surrounding sources include the 24 adjacent sources closest to the programmable block and long-distance sources extending in the four cardinal directions up to 19 horizontal distances and 19 vertical distances.

[0068] According to the fan-out arrangement of the SHLRT 400 with U-turn routing, sources and destinations do not need to be connected to every row and column. As shown in the figure, long-distance destinations 720 extending in four cardinal directions are separated from adjacent long-distance destinations. That is, the long-distance destinations 720 of the SHLRT 400 are alternately connected to alternating rows and columns. Since this figure is centered on the source 701 (0,0 coordinates), extends in the X and Y directions, and is completely symmetrical, the long-distance destinations 720 only fan out to odd-numbered rows and columns, or in some embodiments, can only connect to even-numbered rows and columns in the fan-out diagram. The above description of the destinations also applies to the source.

[0069] Figure 8The present invention illustrates fanning in or out to alternate rows or columns not directly connected using two SHLRTs 400 with U-turn routing. For ease of understanding, the first SHLRT 400A outputs signals, while the adjacent second SHLRT 400B performs the U-turn routing. The first SHLRT 400A is directly connected to the adjacent second SHLRT 400B in an adjacent direction. S1 is the source of the first SHLRT 400A, configured to drive the destination furthest south (D1), and is also the source (S2) for the fan-in of the second SHLRT 400B. Because the present invention can receive and transmit fan-in or fan-out signals from the adjacent direction, the fan-in and fan-out signals perform a U-turn at the adjacent second SHLRT 400B and fan in or out to alternate rows or columns not directly connected. Therefore, the second SHLRT 400B can fan out and connect to rows 730 that do not have a long-distance destination to the first SHLRT 400A. Therefore, even though fan-in signals or fan-out signals can fan in or fan out to alternate rows or columns that are not directly connected, respectively, since the first SHLRT 400A and the second SHLRT 400B alternately connect to each segment route 251 therebetween, and the source and destination farthest from the HLR 201 are directly connected to the adjacent programmable cell block (the second SHLRT 400B), the fan-in signals and fan-out signals make a U-turn through the adjacent programmable cell block, allowing the first SHLRT 400A to indirectly connect to the alternate rows or columns that are not directly connected via the adjacent programmable cell block.

[0070] To reduce die area and power consumption, the present invention adds a new input edge to output multiplexer 444. This allows segment routing 251 to send fan-out signals back in the same direction as their original fan-in. Therefore, by utilizing segment routing 251 connections in the opposite direction, the number of input edges of input multiplexer 420 can be reduced, thereby reducing the size of input multiplexer 420. Similarly, because segment routing 251 has a smaller fan-out number, it can utilize higher power efficiency and smaller long-reach drivers 445, saving die area without compromising performance.

[0071] By removing direct inputs from segment router 251 to programmable blocks through segment router 251 transitions, the size of connection block 202 is reduced. However, routing options between segment routers in switch block 204 are increased to more efficiently utilize the remaining connections in connection block 202, preserving the combination of routing options. The size reduction from connection block 202 is more significant than the size gain from switch block 204. Consequently, the overall die area of ​​the field programmable logic gate array can be reduced.

[0072] This shows a field programmable logic gate array with a U-turn wiring architecture according to the present invention, which can reduce die area and power consumption without reducing wiring flexibility. It is obvious that variations or alternative forms of the above-disclosed and other features and functions or alternative forms thereof can be combined into many other different methods or devices. Therefore, the present embodiment should be considered in all respects as illustrative and not restrictive. The scope of the invention is indicated by the appended claims rather than by the foregoing description, and all changes that come within the meaning and range of equivalents of the claims are therefore intended to be included.

Claims

1. A field programmable gate array, comprising: a plurality of programmable cell blocks arranged in rows and columns to form an array, wherein each programmable cell block includes a programmable block, one or more switching blocks, and one or more connection blocks, and each programmable block can be programmed to operate and perform a logic function or a wiring function; and a routing network including segmented routing and direct routing, wherein the connection block is configured to fan in the segmented routing and the direct routing from four basic directions, receive a fan-in signal, and couple to the programmable block; wherein the switch block is configured to drive and send a fan-out signal to the segment routing; and wherein one segment route in each of the segment routes in each basic direction is directly connected to the switch block through a dedicated circuit to drive the switch block to output long-distance outputs to the four basic directions, thereby allowing the fan-out signal to be sent to a basic output direction, wherein the basic output direction includes a fan-in direction for receiving the fan-in signal; It is characterized in that the switching block includes multiple output multiplexers, wherein each output multiplexer has five input edges, which are respectively connected to the output of the programmable block and one segment route of each of the four basic directions, and each output multiplexer outputs a long-distance output to one basic output direction.

2. The field programmable gate array according to claim 1, wherein: One of the five input edges of each output multiplexer receives a segment route from a base direction that is the same as the base output direction of the long reach output of each output multiplexer.

3. The field programmable gate array according to claim 1, wherein: The switch block includes a plurality of long-distance drivers, wherein each long-distance driver is configured to drive and send the fan-out signal in one cardinal direction of the segment routing in each of the four cardinal directions.

4. The field programmable gate array according to claim 1, wherein: The connection block includes a plurality of input multiplexers configured to directly receive the fan-in signals from only half of the segment routes and provide input multiplexing to the programmable block.

5. The field programmable gate array according to claim 1, wherein: One segment route of the segment routes in each cardinal direction is a source or a destination farthest from the programmable block.

6. The field programmable gate array according to claim 1, wherein: The fan-in signal and the fan-out signal are fanned in through a source and fanned out through a destination, respectively, wherein the source and the destination are adjacent sources and adjacent destinations that are closest to the programmable block.

7. The field programmable gate array according to claim 1, wherein: The fan-in signal and the fan-out signal are fanned in through a source and fanned out through a destination, respectively, wherein the source and the destination extend in the four basic directions and are alternately connected to alternate rows and alternate columns.

8. The field programmable gate array according to claim 7, wherein: The source and the destination extend in the X direction and the Y direction and are completely symmetrical.

9. The field programmable gate array according to claim 8, wherein: The source and the destination are only connected to odd-numbered rows and odd-numbered columns.

10. The field programmable gate array according to claim 7, wherein: The fan-in signal or the fan-out signal can fan in or fan out to alternate rows or alternate columns that are not directly connected, respectively, wherein: Each programmable cell block is directly connected to an adjacent programmable cell block in an adjacent direction; and The adjacent programmable cell blocks may receive and send the fan-in signal or the fan-out signal from the adjacent direction, thereby making a U-turn at the adjacent programmable cell blocks and fanning in or out to the alternating rows or columns that are not directly connected.

11. The field programmable gate array according to claim 10, wherein: The adjacent programmable unit block is directly connected to the source and the destination farthest from the programmable block to make the U-turn.

12. The field programmable gate array according to any one of claims 1 to 11, wherein: The programmable blocks have an architecture that can be configured as logic functions or routing functions.

13. The field programmable gate array according to claim 12, wherein: The programmable block includes an n-input lookup table with a selectable logic mode, wherein the n-input lookup table can be configured to support the execution of an n-input logic function, or configured as a routing multiplexer to cooperate with a local driver to support the execution of the logic function.

14. The field programmable gate array according to any one of claims 1 to 11, wherein: The plurality of programmable cell blocks include a segmented hybrid logic wiring cell block, wherein the segmented hybrid logic wiring cell block uses segmented vertical wiring or segmented horizontal wiring of more than one segment.

15. The field programmable gate array according to any one of claims 1 to 11, wherein: The field programmable gate array is implemented using more than one die stack.

16. The field programmable gate array according to any one of claims 1 to 11, wherein: The field programmable gate array is implemented in a standalone die or embedded in an integrated circuit as an intellectual property block.

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