Hardware acceleration method and device for updating summary page of ssd, computer device and storage medium

Abstract

The present application relates to a hardware acceleration method, device, computer equipment and storage medium for updating a summary page of an SSD, the method comprising: writing LPA0 by a host and allocating a physical address for writing LPA0; determining whether the current physical address is a position for writing raidparity; if not, determining whether the current physical address is a position for writing a summary page; if not, updating a mapping table and transferring information required for updating a summary page to hardware; calculating a position for storing LPA in a summary page table by hardware according to bank / page / offset in the physical address and the information required for updating a summary page, and then updating the current summary page table; and writing user data into NAND according to the updated current summary page table. The present application processes the initialization and content update of a summary page by hardware, which can improve the write performance of a system and better meet the requirements.

Description

Technical Field

[0001] This invention relates to the field of hardware acceleration technology for updating summary pages, and in particular to hardware acceleration methods, apparatus, computer devices, and storage media for updating summary pages of SSDs. Background Technology

[0002] In DRAM-based SSDs, to improve GC (Garbage Collection) performance, the last page of each block storing user data can be used to store the logical address information of that user data. During GC data migration, only the last page needs to be read to determine the location of valid data stored on the block, reducing the time spent on invalid reads during GC. This page storing the logical address information of user data is called a summary page. However, since the logical address information on each block needs to be cached before the block is completely written, the required cache space is relatively large, making it difficult to implement in DRAM-less SSDs. Therefore, this approach cannot meet the requirements. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a hardware acceleration method, apparatus, computer device and storage medium for SSD update summary pages.

[0004] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0005] Firstly, this embodiment provides a hardware acceleration method for updating SSD summary pages, including the following steps:

[0006] The host writes to LPA0 and assigns a physical address to LPA0 for the write;

[0007] Determine if the current physical address is the location to write to the RAID parity;

[0008] If the current physical address is not the location to write to raidparity, then determine whether the current physical address is the location to write to digest page;

[0009] If the current physical address is not the location to write the digest page, update the mapping table and pass the information required to update the digest page to the hardware;

[0010] The hardware calculates the location of the LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then updates the current summary page table;

[0011] Write user data to NAND based on the updated current summary page table.

[0012] The further technical solution is as follows: after the step of determining whether the current physical address is the location to write to the RAID parity, it further includes: if the current physical address is the location to write to the RAID parity, then write the relevant information of the RAID parity to the NAND, and return to execute the host writing to LPA0, and allocate the physical address to write to LPA0.

[0013] The further technical solution is as follows: after the step of determining whether the current physical address is the location to write the digest page, it further includes: if the current physical address is the location to write the digest page, then write the current digest page cache to the NAND, allocate a new digest page cache, write the ID corresponding to the new digest page cache to the hardware, and return to execute the host writing LPA0, and allocate the physical address to write to LPA0.

[0014] The further technical solution is as follows: after the steps of writing the current digest page cache into NAND, allocating a new digest page cache, and writing the ID corresponding to the new digest page cache into the hardware, it further includes: the hardware finding the corresponding address based on the ID and writing the dummy LPA pattern into the new digest page cache.

[0015] Secondly, this embodiment provides a hardware acceleration device for updating the summary page of an SSD, including: a write allocation unit, a first judgment unit, a second judgment unit, an update transmission unit, a calculation update unit, and a write unit;

[0016] The write allocation unit is used for the host to write to LPA0 and allocate a physical address for writing to LPA0;

[0017] The first judgment unit is used to determine whether the current physical address is the location to be written to the RAID parity;

[0018] The second determination unit is used to determine whether the current physical address is the location for writing a digest page if the current physical address is not the location for writing a RAID parity.

[0019] The update transmission unit is used to update the mapping table and transmit the information required to update the summary page to the hardware if the current physical address is not the location where the summary page is written.

[0020] The calculation and update unit is used to calculate the location of LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then update the current summary page table.

[0021] The writing unit is used to write user data into the NAND flash memory according to the updated current summary page table.

[0022] The further technical solution includes: a write return unit, which, if the current physical address is the location for writing to RAID parity, writes the relevant information of RAID parity to NAND, returns to execute the host write to LPA0, and allocates the physical address for writing to LPA0.

[0023] The further technical solution includes: a write allocation return unit, which, if the current physical address is the location for writing a digest page, writes the current digest page cache to the NAND, allocates a new digest page cache, writes the ID corresponding to the new digest page cache to the hardware, and returns to execute the host writing LPA0, and allocates the physical address for writing to LPA0.

[0024] Its further technical solution includes: finding the write unit, which is used by the hardware to find the corresponding address according to the ID and write the dummy LPA pattern in the new digest page buffer.

[0025] Thirdly, this embodiment provides a computer device, which includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the hardware acceleration method for updating the SSD summary page as described above.

[0026] Fourthly, this embodiment provides a storage medium storing a computer program, the computer program including program instructions, which, when executed by a processor, can implement the hardware acceleration method for updating the SSD summary page as described above.

[0027] The beneficial effects of this invention compared to the prior art are: by processing the initialization and content update of the summary page through hardware, the write performance of the system can be improved, and the requirements can be better met.

[0028] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1A flowchart illustrating the hardware acceleration method for SSD update summary pages provided in this embodiment of the invention;

[0031] Figure 2 A schematic diagram illustrating the page allocation order provided in an embodiment of the present invention;

[0032] Figure 3 A schematic diagram of the summary page structure provided in an embodiment of the present invention;

[0033] Figure 4 A schematic diagram illustrating the storage location of the summary page according to an embodiment of the present invention;

[0034] Figure 5 A schematic block diagram of a hardware acceleration device for an SSD update summary page provided in an embodiment of the present invention;

[0035] Figure 6 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0038] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0039] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0040] Please see Figure 1 The specific embodiment shown in this invention discloses a hardware acceleration method for updating SSD summary pages, comprising the following steps:

[0041] S1, the host writes to LPA0 and assigns a physical address to LPA0 for writing;

[0042] S2, determine whether the current physical address is the location where the data was written to raidparity (the XOR result of the RAID module);

[0043] Specifically, after step S2, the process also includes: S7, if the current physical address is the location to be written to the RAID parity, then write the relevant information of the RAID parity to the NAND, and return to execute the host write to LPA0, and allocate the physical address to be written to LPA0, i.e., S1.

[0044] Specifically, the information related to RAID parity refers to the result of XORing user data in the RAID module.

[0045] S3, if the current physical address is not the location to write to the RAID parity, then determine whether the current physical address is the location to write to the digest page;

[0046] Specifically, after step S3, the process also includes: S8, if the current physical address is the location to write the digest page, then write the current digest page cache to the NAND, allocate a new digest page cache, write the ID corresponding to the new digest page cache to the hardware, and return to execute the host writing LPA0, and allocate the physical address to write to LPA0, i.e., S1.

[0047] Specifically, ID is a marker used to distinguish when information on a summary page needs to be updated; it can be a number like 1 / 2 / 3.

[0048] Specifically, after step S8, the process further includes: S9, where the hardware finds the corresponding address based on the ID and writes the dummy LPA pattern into the new digest page cache.

[0049] Specifically, the corresponding address is an ISRAM address. When initializing the content at the corresponding address, an initial value is assigned according to a pattern; dummy LPA means invalid LPA.

[0050] S4. If the current physical address is not the location to write the summary page, update the mapping table and pass the information required to update the summary page to the hardware.

[0051] Specifically, if this location is not written to the summary page, then user information needs to be written. Writing user information requires updating the mapping table. The information required to update the summary page and update the mapping table is the same, including logical address information and corresponding physical address information.

[0052] S5, the hardware calculates the location of LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then updates the current summary page table;

[0053] Specifically, the bank field corresponds to the ch / ce / lun / plane information of the particle, page refers to the particle page, and offset means the corresponding offset in 16K physical pages.

[0054] Specifically, the calculation formula is as follows: page*bank*page_cnt+bank*page_cnt+offset, where page_cnt means how many LPAs are contained in a page.

[0055] S6, write user data to NAND based on the updated current summary page table.

[0056] Specifically, LPA0 represents the logical address of the user data.

[0057] Please see Figure 2 As shown, the logical address (LBA) of user data written by the host generally corresponds to a data size of 512B, which is relatively small. On the SSD side, it will be converted into a larger granularity LPA (Logical Page Address) for storage mapping. Taking an LPA size of 4K as an example, the summary page records the corresponding LPA in the order of writing. For bb pages, dummy pages, summary pages, and parity pages that have not been written with valid user data, the corresponding LPA records are all dummy LPAs.

[0058] Specifically, pages on a Bad block are called bb pages, and pages where dummy data is written are called dummy pages; pages written by the RAID module's XOR results are called parity pages, and non-user data is recorded as dummy LPAs.

[0059] The host writes user data LPA0~LPA100, and the location of the user data written to the NAND is as follows: Figure 2 As shown, taking a 32-bank SLC block as an example, the order of writing LPA 0 to LPA100 to NAND is bank 0 / block M / page0, bank 1 / block M / page0 to bank 31 / block M / page0, then bank0 / block M / page1 is written, and so on.

[0060] Please see Figure 3 As shown, according to the order in which user data is written, the storage location of user data in the summary page is as follows: Figure 3 As shown, taking a 32-bank SLC block as an example, the index of the summary page table corresponds to the result of the calculation of bank + page + offset in the physical address. The calculation formula is:

[0061] page*bank*page_cnt+bank*page_cnt+offset

[0062] Here, page_cnt means how many LPAs are contained in a page. Taking LPA m written to the physical address bank1 / page1 / offset0 as an example, LPA m has an index of 132 in the summary page table. If there is a bb blk (bad block) in a block slot (blocks with the same sequence number are called a group of block slots), then the corresponding position in the summary page table is filled with a dummy LPA, as shown at position t1 in the figure.

[0063] Please see Figure 4 As shown, after the summary page buffer is full, the summary page buffer is stored in the NAND flash memory. The summary page and the corresponding user data are stored in the same block. The summary page is located in the last page of the corresponding page slot (a group of pages with the same page number is called a page slot) that can store valid data. Taking a bank with 32 banks, SLC blocks, RAID function disabled, and a summary page table size of 16K as an example.

[0064] Based on the characteristic that DRAM-less SSD SRAM space is relatively small, the present invention modifies the summary page related scheme to change the summary page cache corresponding to each AP (alloc pool) to 16K. When the summary page is full, the summary page is written into NAND.

[0065] This invention processes the initialization and content update of the summary page through hardware, which can improve the system's write performance and better meet the requirements.

[0066] Please see Figure 5 As shown, the present invention also discloses a hardware acceleration device for SSD update summary pages, including: a write allocation unit 10, a first judgment unit 20, a second judgment unit 30, an update transmission unit 40, a calculation update unit 50, and a write unit 60.

[0067] The write allocation unit 10 is used for the host to write to LPA0 and allocate a physical address for writing to LPA0;

[0068] The first judgment unit 20 is used to determine whether the current physical address is the location to be written to the RAID parity;

[0069] The second judgment unit 30 is used to determine whether the current physical address is the location for writing a digest page if the current physical address is not the location for writing a RAID parity.

[0070] The update transmission unit 40 is used to update the mapping table and transmit the information required to update the summary page to the hardware if the current physical address is not the location where the summary page is written.

[0071] The calculation and update unit 50 is used to calculate the location of LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then update the current summary page table.

[0072] The writing unit 60 is used to write user data into the NAND flash memory according to the updated current summary page table.

[0073] The device further includes a write return unit 70, which, if the current physical address is the location for writing to the RAID parity, writes the relevant information of the RAID parity to the NAND, returns to execute the host write to LPA0, and allocates a physical address for writing to LPA0.

[0074] The device further includes a write allocation return unit 80, which, if the current physical address is the location for writing a digest page, writes the current digest page cache to the NAND, allocates a new digest page cache, writes the ID corresponding to the new digest page cache to the hardware, and returns to execute the host write LPA0, and allocates the physical address for writing to LPA0.

[0075] The device also includes a write-find unit 90, which is used to locate the corresponding address based on the ID and write the dummy LPA pattern into a new digest page cache.

[0076] It should be noted that those skilled in the art can clearly understand that the hardware acceleration device and the specific implementation process of each unit of the above-mentioned SSD update summary page can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, they will not be repeated here.

[0077] The hardware acceleration device for the aforementioned SSD update summary page can be implemented as a computer program, which can, for example... Figure 6 It runs on the computer device shown.

[0078] Please see Figure 6 , Figure 6 This is a schematic block diagram of a computer device 500 provided in an embodiment of this application; the computer device 500 can be a terminal or a server, wherein the terminal can be an electronic device with communication functions such as a smartphone, tablet computer, laptop computer, desktop computer, personal digital assistant, and wearable device. The server can be a standalone server or a server cluster composed of multiple servers.

[0079] See Figure 6 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0080] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a hardware-accelerated method for updating SSD summary pages.

[0081] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0082] The internal memory 504 provides an environment for the execution of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a hardware acceleration method for updating the summary page of an SSD.

[0083] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 6 The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0084] The processor 502 is used to run a computer program 5032 stored in the memory to perform the following steps:

[0085] Step S1: The host writes to LPA0 and assigns a physical address to LPA0 for writing;

[0086] Step S2: Determine if the current physical address is the location to write to the RAID parity;

[0087] Step S3: If the current physical address is not the location to write to the RAID parity, then determine whether the current physical address is the location to write to the digest page;

[0088] Step S4: If the current physical address is not the location to write the digest page, update the mapping table and pass the information required to update the digest page to the hardware;

[0089] Step S5: The hardware calculates the location of the LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then updates the current summary page table.

[0090] Step S6: Write the user data into the NAND according to the updated current summary page table.

[0091] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0092] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0093] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions that, when executed by a processor, can implement the above-described hardware acceleration method for updating the SSD summary page. The storage medium stores a computer program, which includes program instructions that, when executed by a processor, can implement the above-described method. The program instructions include the following steps:

[0094] Step S1: The host writes to LPA0 and assigns a physical address to LPA0 for writing;

[0095] Step S2: Determine if the current physical address is the location to write to the RAID parity;

[0096] Step S3: If the current physical address is not the location to write to the RAID parity, then determine whether the current physical address is the location to write to the digest page;

[0097] Step S4: If the current physical address is not the location to write the digest page, update the mapping table and pass the information required to update the digest page to the hardware;

[0098] Step S5: The hardware calculates the location of the LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then updates the current summary page table.

[0099] Step S6: Write the user data into the NAND according to the updated current summary page table.

[0100] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0101] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0102] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative. For example, the division of each unit is merely a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0103] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the device of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0104] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0105] The above embodiments are preferred implementations of the present invention. In addition, the present invention can be implemented in other ways. Any obvious substitutions without departing from the concept of the present technical solution are within the protection scope of the present invention.

Claims

1. A hardware acceleration method for updating SSD summary pages, characterized in that, Includes the following steps: The host writes to LPA0 and assigns a physical address to LPA0 for the write; Determine if the current physical address is the location to write to the RAID parity; If the current physical address is not the location to write to the RAID parity, then determine whether the current physical address is the location to write to the digest page; If the current physical address is not the location to write the digest page, update the mapping table and pass the information required to update the digest page to the hardware; The hardware calculates the location of the LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then updates the current summary page table; Write user data to NAND based on the updated current summary page table.

2. The hardware acceleration method for SSD update summary pages according to claim 1, characterized in that, After determining whether the current physical address is the location to write to the RAID parity, the method further includes: if the current physical address is the location to write to the RAID parity, then write the relevant information of the RAID parity to the NAND, return to execute the host write to LPA0, and allocate the physical address to write to LPA0.

3. The hardware acceleration method for SSD update summary pages according to claim 1, characterized in that, After determining whether the current physical address is the location to write the digest page, the method further includes: if the current physical address is the location to write the digest page, then write the current digest page cache to the NAND, allocate a new digest page cache, write the ID corresponding to the new digest page cache to the hardware, and return to execute the host writing LPA0, and allocate the physical address to LPA0 for writing.

4. The hardware acceleration method for SSD update summary pages according to claim 3, characterized in that, After the steps of writing the current digest page cache to NAND, allocating a new digest page cache, and writing the ID corresponding to the new digest page cache to the hardware, the method further includes: the hardware finding the corresponding address based on the ID and writing the dummyLPA pattern into the new digest page cache.

5. A hardware acceleration device for updating SSD summary pages, characterized in that, include: The system includes a write allocation unit, a first judgment unit, a second judgment unit, an update and transmission unit, a calculation and update unit, and a write unit. The write allocation unit is used for the host to write to LPA0 and allocate a physical address for writing to LPA0; The first judgment unit is used to determine whether the current physical address is the location to be written to the RAID parity; The second determination unit is used to determine whether the current physical address is the location for writing a digest page if the current physical address is not the location for writing a RAID parity. The update transmission unit is used to update the mapping table and transmit the information required to update the summary page to the hardware if the current physical address is not the location where the summary page is written. The calculation and update unit is used to calculate the location of LPA in the summary page table based on the bank / page / offset in the physical address and the information required to update the summary page, and then update the current summary page table. The writing unit is used to write user data into the NAND flash memory according to the updated current summary page table.

6. The hardware acceleration device for SSD update summary pages according to claim 5, characterized in that, Also includes: The write return unit is used to write the relevant information of the RAID parity to the NAND if the current physical address is the location to be written to the RAID parity, and return to execute the host write to LPA0, and allocate the physical address to be written to LPA0.

7. The hardware acceleration device for SSD update summary pages according to claim 5, characterized in that, Also includes: The write allocation return unit is used to write the current digest page cache to NAND if the current physical address is the location to write the digest page, allocate a new digest page cache, write the ID corresponding to the new digest page cache to the hardware, and return to execute the host write LPA0, and allocate the physical address to write to LPA0.

8. The hardware acceleration device for SSD update summary pages according to claim 7, characterized in that, Also includes: The write unit is located, which is used by the hardware to find the corresponding address based on the ID and write the dummy LPA pattern in the new digest page buffer.

9. A computer device, characterized in that, The computer device includes a memory and a processor. The memory stores a computer program, and when the processor executes the computer program, it implements the hardware acceleration method for updating the SSD summary page as described in any one of claims 1-4.

10. A storage medium, characterized in that, The storage medium stores a computer program, which includes program instructions that, when executed by a processor, can implement the hardware acceleration method for updating the SSD summary page as described in any one of claims 1-4.

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